A54SX32A-1BG329A_技术文档

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SX-A Family FPGAs

u

e

L e a d i n g -E d g e P e r f o r m a n c e

• 250 MHz System Performance

• 350 MHz Internal Performance

• 3.8 ns Clock-to-Out (Pad-to-Pad)

• Configurable I/O Support for 3.3V/5V PCI, 5V TTL,

3.3V LVTTL, 2.5V LVCMOS2

• 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input

Tolerance and 5V Drive Strength

S p e c i f i c a t i o n s

• 12,000 to 108,000 Available System Gates

• Up to 360 User-Programmable I/O Pins

• Devices Support Multiple Temperature Grades

• Configurable Weak-Resistor Pull-up or Pull-down for

Outputs at Power-up

• Up to 2,012 Dedicated Flip-Flops

• Individual Output Slew Rate Control

• 0.22µ/0.25µ CMOS Process Technology

• Up to 100% Resource Utilization and 100% Pin Locking

• Deterministic, User-Controllable Timing

F e a t u r e s

• Hot-Swap Compliant I/Os

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• Power-up/down Friendly (No Sequencing Required for

Supply Voltages)

• Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

• 66 MHz PCI Compliant

• Single-Chip Solution

• Nonvolatile

• Actel’s Secure Programming Technology with FuseLock™

Prevents Reverse Engineering and Design Theft

S X -A P r o d u c t P r o f i l e

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

32,000

48,000

72,000

108,000

Logic Modules

Combinatorial Cells

768

512

1,452

924

2,880

1,800

6,036

4,024

Register Cells

Dedicated Flip-Flops

Maximum Flip-Flops

256

512

528

990

1,080

1,980

2,012

4,024

Maximum User I/Os

Global Clocks

130

3

180

3

249

3

360

3

Quadrant Clocks

Boundary Scan Testing

3.3V/5V PCI

0

4

Yes

4.2 ns

0 ns

Yes

4.6 ns

0 ns

Yes

4.7 ns

0 ns

Yes

5.8 ns

0 ns

Clock-to-Out

Input Set-Up (External)

Speed Grades

–F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3

Temperature Grades

C, I, A

C, I, M, A

Package (by pin count)

PQFP

TQFP

PBGA

FBGA

CQFP*

208

100, 144

—

208

100, 144

—

208

100, 144, 176

329

144, 256, 484

208, 256

208

—

144

144, 256

256, 484

208, 256

Note: For more information about the CQFP package options, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf

A p r i l 2 0 0 3

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S X -A F a m i l y F P G A s

O r d e r i n g I n f o r m a t i o n

A54SX16

A

2

PQ

208

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I

M

A

= Industrial (–40 to +85°C)

= Military (–55 to +125°C)

= Automotive (–40 to +125°C)

Package Lead Count

Package Type

BG = 1.27mm Plastic Ball Grid Array

FG = 1.0mm Fine Pitch Ball Grid Array

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4mm) Quad Flat Pack

CQ = Ceramic Quad Flat Pack*

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

–F = Approximately 40% Slower than Standard

A = 0.22µ/0.25µ CMOS Technology

Part Number

A54SX08A = 12,000 System Gates

A54SX16A = 24,000 System Gates

A54SX32A = 48,000 System Gates

A54SX72A = 108,000 System Gates

*For more information about the CQFP package options, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf

P l a s t i c D e v i c e R e s o u r c e s

User I/Os (including clock buffers)

PQFP

208-Pin

TQFP

100-Pin

TQFP

144-Pin

TQFP

176-Pin

PBGA

329-Pin

FBGA

144-Pin

FBGA

256-Pin

FBGA

484-Pin

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

130

175

174

171

81

—

113

—

111

—

180

203

147

—

249

—

249

360

Contact your Actel sales representative for product availability.

Package Definitions

PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = 1.27mm Plastic Ball Grid Array, FBGA = 1.0mm Fine Pitch Ball

Grid Array

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S X -A F a m i l y F P G A s

P r o d u c t P l a n

Speed Grade**

Application

–F

Std

–1

–2

–3

C

I^†

M^•

A

A54SX08A Device

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

144-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX16A Device

✔

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

144-Pin Fine Pitch Ball Grid Array (FBGA)

256-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX32A Device

✔

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Ceramic Quad Flat Pack (CQFP)*

144-Pin Fine Pitch Ball Grid Array (FBGA)

256-Pin Fine Pitch Ball Grid Array (FBGA)

329-Pin Plastic Ball Grid Array (PBGA)

484-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX72A Device

✔

–

✔

–

✔

–

208-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Fine Pitch Ball Grid Array (FBGA)

484-Pin Fine Pitch Ball Grid Array (FBGA)

✔

–

✔

Contact your Actel sales representative for product availability.

*For more information about the CQFP package options, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf

Applications: C = Commercial

= Industrial

Availability: ✔ = Available

**Speed Grade: –1 = Approx. 15% faster than Standard

I

–2 = Approx. 25% faster than Standard

–3 = Approx. 35% faster than Standard

M = Military

A = Automotive

–F = Approx. 40% slower than Standard

†✔Only Std, –1, –2 Speed Grade

• Only Std, –1 Speed Grade

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S X -A F a m i l y F P G A s

G e n e r a l D e s c r i p t i o n

Actel’s SX-A family of FPGAs features a sea-of-modules

utilization, enables concurrent PCB development, reduces

architecture that delivers high device performance. SX-A design time, and allows designers to achieve performance

devices simplify design time, enable dramatic reductions in

design costs and power consumption, and further decrease

time-to-market for performance-intensive applications.

goals with minimum effort.

Further complementing SX-A’s flexible routing structure is a

hardwired, constantly loaded clock network that has been

tuned to provide fast clock propagation with minimal clock

skew. Additionally, the high performance of the internal

logic has eliminated the need to embed latches or flip-flops

in the I/O cells to achieve fast clock-to-out or fast input

set-up times. SX-A devices have easy-to-use I/O cells that do

not require HDL instantiation, facilitating design re-use and

reducing design and verification time.

Actel’s SX-A architecture features two types of logic

modules, the combinatorial cell (C-cell) and the register

cell (R-cell), each optimized for fast and efficient mapping

of synthesized logic functions. The routing and interconnect

resources are in the metal layers above the logic modules,

providing optimal use of silicon. This enables the entire

floor of the device to be spanned with an uninterrupted grid

of fine-grained, synthesis-friendly logic modules (or

“sea-of-modules”), which reduces the distance signals have

to travel between logic modules. To minimize signal

propagation delay, SX-A devices employ both local and

general routing resources. The high-speed local routing

resources (DirectConnect and FastConnect) enable very

fast local signal propagation that is optimal for fast

counters, state machines, and datapath logic. The general

system of segmented routing tracks allows any logic module

in the array to be connected to any other logic or I/O

module. Within this system, propagation delay is minimized

by limiting the number of antifuse interconnect elements to

five (90 percent of connections typically use only three or

fewer antifuses). The unique local and general routing

structure featured in SX-A devices gives fast and predictable

performance, allows 100% pin-locking with full logic

S X -A F a m i l y A r c h i t e c t u r e

The SX-A family architecture was designed to satisfy

performance

and

integration

requirements

for

production-volume designs in a broad range of applications.

P r o g r a m m a b l e I n t e r c o n n e c t E le m e n t

The SX-A family provides efficient use of silicon by locating

the routing interconnect resources between the top two

metal layers (Figure 1). This completely eliminates the

channels of routing and interconnect resources between

logic modules (as implemented on SRAM FPGAs and

previous generations of antifuse FPGAs), and enables the

entire floor of the device to be spanned with an

uninterrupted grid of logic modules.

Routing Tracks

Amorphous Silicon/

Dielectric Antifuse

Tungsten Plug Via

Metal 4

Metal 3

Tungsten Plug Via

Metal 2

Metal 1

Tungsten Plug Contact

Silicon Substrate

Note: A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and

A54SX32A have three layers of metal with antifuse between Metal 2 and Metal 3.

Figure 1 • SX-A Family Interconnect Elements

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S X -A F a m i l y F P G A s

Interconnection between these logic modules is achieved

using Actel’s patented metal-to-metal programmable

antifuse interconnect elements. The antifuses are normally

open circuit and, when programmed, form a permanent

low-impedance connection.

modules, the register cell (R-cell) and the combinatorial

cell (C-cell).

The R-cell contains a flip-flop featuring asynchronous clear,

asynchronous preset, and clock enable (using the S0 and S1

lines) control signals (Figure 2). The R-cell registers

feature programmable clock polarity selectable on a

register-by-register basis. This provides additional flexibility

while allowing mapping of synthesized functions into the

SX-A FPGA. The clock source for the R-cell can be chosen

from either the hardwired clock, the routed clocks, or

internal logic.

The extremely small size of these interconnect elements

gives the SX-A family abundant routing resources and

provides excellent protection against design pirating.

Reverse engineering is virtually impossible because it is

extremely difficult to distinguish between programmed and

unprogrammed antifuses, and since SX-A is a nonvolatile,

single-chip solution, there is no configuration bitstream to

intercept.

The C-cell implements a range of combinatorial functions of

up to five inputs (Figure 3 on page 6). Inclusion of the DB

input and its associated inverter function increases the

number of combinatorial functions that can be implemented

in a single module from 800 options (as in previous

architectures) to more than 4,000 in the SX-A architecture.

An example of the improved flexibility enabled by the

inversion capability is the ability to integrate a 3-input

exclusive-OR function into a single C-cell. This facilitates

construction of 9-bit parity-tree functions with 1.9 ns

propagation delays. At the same time, the C-cell structure is

extremely synthesis friendly, simplifying the overall design

and reducing synthesis time.

Additionally, the interconnect (i.e., the antifuses and metal

tracks) have lower capacitance and lower resistance than

any other device of similar capacity, leading to the fastest

signal propagation in the industry.

L o g i c M o d u l e D e s ig n

The SX-A family architecture is described as a

“sea-of-modules” architecture because the entire floor of

the device is covered with a grid of logic modules with

virtually no chip area lost to interconnect elements or

routing. Actel’s SX-A family provides two types of logic

Routed

Data Input

S0

S1

PRE

DirectConnect

Input

D

Q

Y

HCLK

CLKA,

CLKB,

CLR

Internal Logic

CKS

CKP

Figure 2 • R-Cell

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S X -A F a m i l y F P G A s

D0

D1

Y

D2

D3

Sa

Sb

DB

B1

A1

A0 B0

Figure 3 • C-Cell

C h i p A r c h i t e c t u r e

FastConnect enables horizontal routing between any two

logic modules within a given SuperCluster and vertical

routing with the SuperCluster immediately below it. Only

The SX-A family’s chip architecture provides a unique

approach to module organization and chip routing that

delivers the best register/logic mix for a wide variety of new one programmable connection is used in a FastConnect

and emerging applications.

path, delivering a maximum pin-to-pin propagation time of

0.3 ns.

M o d u le O r g a n i z a t io n

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing between

SuperClusters. The exact combination of track lengths and

antifuses within each path is chosen by the 100% automatic

place-and-route software to minimize signal propagation

delays.

Actel has arranged all C-cell and R-cell logic modules into

horizontal banks called Clusters. There are two types of

Clusters: Type 1 contains two C-cells and one R-cell, while

Type 2 contains one C-cell and two R-cells.

To increase design efficiency and device performance, Actel

has further organized these modules into SuperClusters

(Figure 4 on page 7). SuperCluster 1 is a two-wide grouping

of Type 1 Clusters. SuperCluster 2 is a two-wide group

containing one Type 1 Cluster and one Type 2 Cluster. SX-A

devices feature more SuperCluster 1 modules than

SuperCluster 2 modules because designers typically require

significantly more combinatorial logic than flip-flops.

C lo c k R e s o u r c e s

Actel’s high-drive routing structure provides three clock

networks (Table 1). The first clock, called HCLK, is hardwired

from the HCLK buffer to the clock select MUX in each R-cell.

HCLK cannot be connected to combinatorial logic. This

provides a fast propagation path for the clock signal, enabling

the 3.8 ns clock-to-out (pad-to-pad) performance of the SX-A

devices. The hardwired clock is tuned to provide clock skew

less than 0.3 ns worst case. If not used, this pin must be set as

LOW or HIGH on the board. It must not be left floating.

Figure 7 describes the clock circuit used for the constant load

HCLK. Upon power-up of the SX-A device, four clock pulses

must be detected on HCLK before the clock signal will be

propagated to registers in the design.

R o u t i n g R e s o u r c e s

Clusters and SuperClusters can be connected through the

use of two innovative local routing resources called

FastConnect and DirectConnect, which enable extremely

fast and predictable interconnection of modules within

Clusters and SuperClusters (Figure 5 and Figure 6 on

page 8). This routing architecture also dramatically reduces

the number of antifuses required to complete a circuit,

ensuring the highest possible performance.

DirectConnect is a horizontal routing resource that provides

connections from a C-cell to its neighboring R-cell in a given

SuperCluster. DirectConnect uses a hardwired signal path

requiring no programmable interconnection to achieve its

fast signal propagation time of less than 0.1 ns.

Two additional clocks (CLKA, CLKB) are global clocks that

can be sourced from external pins or from internal logic

signals within the SX-A device. CLKA and CLKB may be

connected to sequential cells or to combinational logic. If

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S X -A F a m i l y F P G A s

R-Cell

C-Cell

D0

D1

Routed

Data Input

S1

S0

PRE

Y

D2

D3

DirectConnect

Input

D

Q

Y

Sa

Sb

HCLK

CLKA,

CLKB,

Internal Logic

CLR

DB

CKS

CKP

A0 B0

A1 B1

Cluster 1

Cluster 2

Cluster 1

Type 1 SuperCluster

Type 2 SuperCluster

Figure 4 • Cluster Organization

DirectConnect

• No antifuses

• 0.1 ns maximum routing delay

FastConnect

• One antifuse

• 0.3 ns maximum routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 1 SuperClusters

Figure 5 • DirectConnect and FastConnect for Type 1 SuperClusters

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S X -A F a m i l y F P G A s

DirectConnect

• No antifuses

• 0.1 ns maximum routing delay

FastConnect

• One antifuse

• 0.3 ns maximum routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 2 SuperClusters

Figure 6 • DirectConnect and FastConnect for Type 2 SuperClusters

CLKA or CLKB pins are not used or sourced from signals, then

or they can be grouped together to drive multiple quadrants.

these pins must be set as LOW or HIGH on the board. They If QCLKs are not used as quadrant clocks, they will behave as

must not be left floating (except in the A54SX72A where these

clocks can be configured as regular I/Os and can float).

regular I/Os. Bidirectional clock buffers are also available on

the A54SX72A. The CLKA, CLKB, and QCLK circuits for

Figure 8 describes the CLKA and CLKB circuit used in SX-A A54SX72A are shown in Figure 9 on page 9. Note that

devices with the exception of A54SX72A.

bidirectional clock buffers are only available in A54SX72A.

For more information, refer to the “Pin Description” section

on page 53.

In addition, the A54SX72A device provides four quadrant

clocks (QCLKA, QCLKB, QCLKC, QCLKD – corresponding to

bottom-left, bottom-right, top-left, and top-right locations on

the die, respectively), which can be sourced from external

pins or from internal logic signals within the device. Each of

these clocks can individually drive up to a quarter of the chip,

For more information on how to use quadrant clocks in the

A54SX72A device, refer to the Global Clock Networks in

Actel’s Antifuse Devices and Using A54SX72A and

RT54SX72S Quadrant Clocks application notes.

Table 1 • SX-A Clock Resources

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Routed Clocks (CLKA, CLKB)

2

1

0

2

1

0

2

1

0

2

1

4

Hardwired Clocks (HCLK)

Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)

Constant Load

Clock Network

HCLKBUF

From Internal Logic

Figure 7 • SX-A HCLK Clock Pad

CLKBUF

CLKBUFI

CLKINT

CLKINTI

Note: This does not include the clock pad for HiRel A54SX72A.

Figure 8 • SX-A Routed Clock Structure

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S X -A F a m i l y F P G A s

OE

From Internal Logic

Clock Network

From Internal Logic

CLKBUF

CLKBUFI

CLKINT

CLKINTI

CLKBIBUF

QCLKBUF

QCLKBUFI

QCLKINT

QCLKINTI

QCLKBIBUF

Figure 9 • A54SX72A Routed Clock and QClock Structure

O t h e r A r c h i t e c t u r a l F e a t u r e s

Look for this symbol to ensure your valuable IP is secure.

T e c h n o lo g y

Actel’s SX-A family is implemented on a high-voltage,

twin-well CMOS process using 0.22µ/0.25µ design rules. The

metal-to-metal antifuse is comprised of a combination of

amorphous silicon and dielectric material with barrier

metals and has a programmed (“on” state) resistance of

25Ω with capacitance of 1.0 fF for low signal impedance.

u

e

For more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

P e r f o r m a n c e

I /O M o d u l e s

The combination of architectural features described above

enables SX-A devices to operate with internal clock

frequencies of 350 MHz, enabling very fast execution of even

complex logic functions. Thus, the SX-A family is an optimal

platform upon which to integrate the functionality

previously contained in multiple CPLDs. In addition,

designs that previously would have required a gate array to

meet performance goals can be integrated into an SX-A

device with dramatic improvements in cost and

time-to-market. Using timing-driven place-and-route tools,

designers can achieve highly deterministic device

performance.

Each user I/O on an SX-A device can be configured as an

input, an output, a tristate output, or a bidirectional pin.

Mixed I/O standards can be set for individual pins, though

this is only allowed with the same voltage as the input. These

I/Os, combined with array registers, can achieve

clock-to-output-pad timing as fast as 3.8 ns even without the

dedicated I/O registers. In most FPGAs, I/O cells that have

embedded latches and flip-flops require instantiation in HDL

code; this is a design complication not encountered in SX-A

FPGAs. Fast pin-to-pin timing ensures that the device is able

to interface with any other device in the system, which in

turn enables parallel design of system components and

reduces overall design time. All unused I/Os are configured as

tristate outputs by Actel’s Designer software, for maximum

flexibility when designing new boards or migrating existing

designs.

U s e r S e c u r it y

The Actel FuseLock advantage ensures that unauthorized

users will not be able to read back the contents of an Actel

antifuse FPGA. In addition to the inherent strengths of the

architecture, special security fuses that prevent internal

probing and overwriting are hidden throughout the fabric of

the device. They are located such that they cannot be

accessed or bypassed without destroying the rest of the

device, making both invasive and more-subtle noninvasive

attacks ineffective against Actel antifuse FPGAs.

SX-A inputs should be driven by high-speed push-pull devices

with a low-resistance pull-up device. If the input voltage is

greater than V_CCIand a fast push-pull device is NOT used, the

high-resistance pull-up of the driver and the internal circuitry

of the SX-A I/O may create a voltage divider. This voltage

divider could pull the input voltage below specification for

some devices connected to the driver. A logic '1' may not be

correctly presented in this case. For example, if an open

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S X -A F a m i l y F P G A s

drain driver is used with a pull-up resistor to 5V to provide the

logic ’1’ input, and V_CCIis set to 3.3V on the SX-A device, the

input signal may be pulled down by the SX-A input.

During power-up/down (or partial up/down), all I/Os are

tristated. V_CCAand V do not have to be stable during

CCI

power-up/down. After the SX-A device is plugged into an

electrically active system, the device will not degrade the

reliability of or cause damage to the host system. The

device’s output pins are driven to a high impedance state

until normal chip operating conditions are reached. Table 4

Each I/O module has an available power-up resistor of

approximately 50kΩ that can configure the I/O in a known

state during power-up. Just slightly before V_CCAreaches 2.5V,

the resistors are disabled, so the I/Os will be controlled by

user logic. See Table 2 and Table 3 for more information

concerning available I/O features.

summarizes the V

voltage at which the I/Os behave

CCA

according to the user’s design for an SX-A device at room

temperature for various ramp-up rates. The data reported

assumes a linear ramp-up profile to 2.5V. For more

information on power-up and hot-swapping, refer to the

application note, Actel SX-A and RT54SX-S Devices in

Hot-Swap and Cold-Sparing Applications.

H o t S w a p p in g

SX-A I/Os can be configured to be hot-swappable in

compliance with the Compact PCI (5.0V) Specification.

However, note that 3.3V PCI device is not hot swappable.

Table 2 • I/O Features

Function

Description

Input Buffer Threshold Selections

•

5V PCI, TTL

3.3V PCI, LVTTL

2.5V LVCMOS2

Flexible Output Driver

Output Buffer

•

5V: PCI, TTL

3.3V: PCI, LVTTL

2.5V: LVCMOS2

“Hot-Swap” Capability (3.3V PCI is not hot swappable)

•

I/O on an unpowered device does not sink current

Can be used for “cold-sparing”

Selectable on an individual I/O basis

Individually selectable slew rate, high slew or low slew (The default is high slew

rate). The slew is only affected on the falling edge of an output. Rising edges of

outputs are not affected.

Power-Up

Individually selectable pull-ups and pull-downs during power-up (default is to

power-up in tristate)

Enables deterministic power-up of device

V_CCAand V_CCIcan be powered in any order

Table 3 • I/O Characteristics for All I/O Configurations

Hot Swappable

Slew Rate Control

Power-up Resistor

TTL, LVTTL, LVCMOS2

3.3V PCI

Yes

No

Yes. Only affects falling edges of outputs pull-up or pull-down

No. High slew rate only

pull-up or pull-down

5V PCI

Yes

Table 4 • Power-up Time at which I/Os Become Active

Supply Ramp Rate 0.25V/µs 0.025V/µs

5V/ms

ms

2.5V/ms

ms

0.5V/ms

ms

0.25V/ms

0.1V/ms 0.025V/ms

Units

µs

10

µs

96

ms

5.4

4.7

5.2

5.0

ms

A54SX08A

A54SX16A

A54SX32A

A54SX72A

0.34

0.36

0.46

0.41

0.65

2.7

12.9

11.0

12.1

50.8

41.6

47.2

100

0.62

2.5

0.74

2.8

0.67

2.6

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S X -A F a m i l y F P G A s

B o u n d a r y -S c a n T e s t i n g ( B S T )

All SX-A devices are IEEE 1149.1 compliant and offer superior

diagnostic and testing capabilities by providing Boundary

Scan Testing (BST) and probing capabilities. The BST

function is controlled through the special JTAG pins (TMS,

TDI, TCK, TDO, and TRST). The functionality of the JTAG

pins is defined by two available modes: Dedicated and

Flexible. TMS cannot be employed as user I/O in either mode.

Dedicated Mode

In Dedicated mode, all JTAG pins are reserved for BST;

designers cannot use them as regular I/Os. An internal

pull-up resistor is automatically enabled on both TMS and

TDI pins, and the TMS pin will function as defined in the

IEEE 1149.1 (JTAG) specification.

Figure 10 • Device Selection Wizard

Designer software. In Flexible mode, TDI, TCK and TDO pins

may function as user I/Os or BST pins. The functionality is

controlled by the BST TAP controller. The TAP controller

receives two control inputs, TMS and TCK. Upon power-up,

the TAP controller enters the Test-Logic-Reset state. In this

state, TDI, TCK and TDO function as user I/Os. The TDI, TCK,

and TDO are transformed from user I/Os into BST pins when

a rising edge on TCK is detected while TMS is at logic low. To

return to Test-Logic Reset state, TMS must be high for at

To select Dedicated mode, users need to reserve the JTAG

pins in Actel’s Designer software. To reserve the JTAG pins,

users can check the "Reserve JTAG" box in "Device Selection

Wizard" (Figure 10).

Flexible Mode

In Flexible mode, TDI, TCK, and TDO may be employed as

either user I/Os or as JTAG input pins. The internal resistors

on the TMS and TDI pins are not present in flexible JTAG

mode.

least five TCK cycles. An external 10K pull-up resistor to V

should be placed on the TMS pin to pull it HIGH by default.

CCI

Table 5 describes the different configuration requirements of

BST pins and their functionality in different modes.

To select the Flexible mode, users need to uncheck the

"Reserve JTAG" box in "Device Selection Wizard" in Actel’s

Table 5 • Boundary-Scan Pin Configurations and Functions

Mode

Designer "Reserve JTAG" Selection

Checked

TAP Controller State

Dedicated (JTAG)

Flexible (User I/O)

Flexible (JTAG)

Any

Unchecked

Test-Logic-Reset

Any EXCEPT Test-Logic-Reset

TRST Pin

observation. Silicon Explorer II automatically places the

device into JTAG mode. However, probing functionality is

only activated when the TRST pin is driven high or left

floating, allowing the internal pull-up resistor to pull TRST

HIGH. If the TRST pin is held LOW, the TAP controller

remains in the Test-Logic-Reset state so no probing can be

performed. However, the user must drive the TRST pin HIGH

or allow the internal pull-up resistor to pull TRST HIGH.

The TRST pin functions as a dedicated Boundary-Scan Reset

pin when the "Reserve JTAG Test Reset" option is selected as

shown in Figure 10. An internal pull-up resistor is

permanently enabled on the TRST pin in this mode. Actel

recommends connecting this pin to ground in normal

operation to keep the JTAG state controller in the

Test-Logic-Reset state. When JTAG is being used, it can be

left floating or be driven high.

When selecting the "Reserve Probe Pin" box as shown in

Figure 10, direct the layout tool to reserve the PRA and PRB

pins as dedicated outputs for probing. This "reserve" option is

merely a guideline. If the designer assigns user I/Os to the

PRA and PRB pins and selects the "Reserve Probe Pin"

option, Designer Layout will override the "Reserve Probe Pin"

option and place the user I/Os on those pins.

When the "Reserve JTAG Test Reset" option is not selected,

this pin will function as a regular I/O. If unused as an I/O in

the design, it will be configured as a tristated output.

P r o b in g C a p a b i li t i e s

SX-A devices also provide an internal probing capability that

is accessed with the JTAG pins. The Silicon Explorer II

Diagnostic Hardware is used to control the TDI, TCK, TMS

and TDO pins to select the desired nets for debugging. The

user assigns the selected internal nets in Actel’s Silicon

Explorer II software to the PRA/PRB output pins for

To allow probing capabilities, the security fuse must not be

programmed. Programming the security fuse disables the

probe circuitry. Table 6 summarizes the possible device

configurations for probing once the device leaves the

"Test-Logic-Reset" JTAG state.

v4 .0

1 1

S X -A F a m i l y F P G A s

Table 6 • Device Configuration Options for Probe Capability (TRST pin reserved)

JTAG Mode

TRST¹

Security Fuse Programmed

PRA, PRB²

TDI, TCK, TDO²

Dedicated

Flexible

Dedicated

Flexible

–

LOW

HIGH

–

No

Yes

User I/O³

Probing Unavailable

User I/O³

Probe Circuit Outputs

Probe Circuit Inputs

Probe Circuit Secured Probe Circuit Secured

Notes:

1. If the TRST pin is not reserved, the device behaves according to TRST=HIGH as described in the table.

2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input

signals will not pass through these pins and may cause contention.

3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the

Designer software.

SX-A Probe Circuit Control Pins

verification. The selected internal nets are assigned to the

PRA/PRB pins for observation. Figure 11 illustrates the

interconnection between Silicon Explorer II and the FPGA

to perform in-circuit verification.

SX-A devices contain internal probing circuitry that provides

built-in access to every node in a design, enabling 100%

real-time observation and analysis of a device’s internal logic

nodes without design iteration. The probe circuitry is

accessed by Silicon Explorer II, an easy to use integrated

verification and logic analysis tool that can sample data at

100 MHz (asynchronous) or 66 MHz (synchronous).

Silicon Explorer II attaches to a PC’s standard COM port,

turning the PC into a fully functional 18 channel logic

analyzer. Silicon Explorer II allows designers to complete the

design verification process at their desks and reduces

verification time from several hours per cycle to a few

seconds.

D e s i g n C o n s i d e r a t io n s

Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input

or bidirectional ports. Since these pins are active during

probing, critical input signals through these pins are not

available. In addition, do not program the Security Fuse.

Programming the Security Fuse disables the Probe Circuit.

Actel recommends that you use a 70Ω series termination

resistor on every probe connector (TDI, TCK, TMS, TDO,

PRA, PRB). The 70Ω series termination is used to prevent

data transmission corruption during probing and reading

back the checksum.

The Silicon Explorer II tool uses the boundary-scan ports

(TDI, TCK, TMS, and TDO) to select the desired nets for

SX-A FPGA

70 Ω

TDI

TCK

Serial Connection

Silicon Explorer II

TMS

70 Ω

TDO

70 Ω

PRA

PRB

Figure 11 • Probe Setup

1 2

v4 .0

S X -A F a m i l y F P G A s

D e v e l o p m e n t T o o l S u p p o r t

Libero IDE provides an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log files,

and passing necessary design data among tools. Libero IDE

includes Synplicity ® Synplify for Actel, Mentor Graphics™

ViewDraw for Actel, Actel's own Designer software, Model

The SX-A family of FPGAs is fully supported by both the

Actel Libero™ Integrated Design Environment and the

Actel Designer FPGA Development Software. Actel's

Designer software provides a comprehensive suite of

back-end development tools for FPGA development. The

Designer software includes timing-driven place and route, a

world-class integrated static timing analyzer and

constraints editor, and a design netlist schematic viewer.

Technology™

ModelSim

HDL

Simulator,

and

SynaptiCAD™ WaveFormer Lite (Figure 12).

TM

Libero IDE Project Manager

Design Creation/Verification

ACTgen

Macro Builder

HDL Editor

User

Testbench

Stimulus Generation

Functional Simulation

Synthesis

Libraries

Design Synthesis and Optimization

Simulator

Schematic Entry

Timing Simulation

Design Implementation

Timer

Compile

SmartPower

Optimization and DRC

Static Timing Analyzer

and Constraints Editor

Power Analysis

Layout

NetlistViewer

PinEdit

I/O Assignments

Schematic Viewer

Timing Driven Place-and-Route

ChipEdit and

ChipViewer

Placement Editor

Back-Annotate

Cross-Probing

Fuse or Bitstream

System Verification

Programming

Silicon Sculptor

Actel

Device

(Antifuse and Flash Families)

Silicon Explorer II

(Antifuse and Flash Families)

FlashPro

(Flash Families)

FlashPro Lite

(ProASIC^PLUSFamily)

BP Microsystems

Programmers

Figure 12 • Design Flow

v4 .0

1 3

S X -A F a m i l y F P G A s

2 . 5 V /3 . 3 V /5 V O p e r a t i n g C o n d i t i o n s

1

A b s o l u t e M a x im u m R a t i n g s

Symbol

Parameter

Limits

Units

V_CCI

V_CCA

V_I

DC Supply Voltage

Input Voltage

–0.3 to +6.0

–0.3 to +3.0

–0.5 to +5.75

–0.5 to +V_CCI

–65 to +150

V

V_O

Output Voltage

V

T_STG

Note:

Storage Temperature

°C

1. Stresses beyond those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may

affect device reliability. Devices should not be operated outside

the Recommended Operating Conditions.

R e c o m m e n d e d O p e r a t i n g C o n d it io n s

Parameter

Commercial

Industrial

Military

Units

Temperature Range¹

2.5V Power Supply Range

3.3V Power Supply Range

5V Power Supply Range

Note:

0 to +70

2.25 to 2.75

3.0 to 3.6

–40 to +85

2.25 to 2.75

3.0 to 3.6

–55 to +125

2.25 to 2.75

3.0 to 3.6

°C

V

4.75 to 5.25

V

1. Ambient temperature (T_A) is used for commercial and industrial; case temperature (T_C) is used

for military.

3 . 3 V LVT T L a n d 5 V T T L E le c t r ic a l S p e c ific a t io n s

Commercial

Industrial

Symbol Parameter

Min.

Max.

Min.

Max.

Units

V_CCI= MIN

(I_OH= -1mA) 0.9 V_CCI

0.9 V_CCI

V

V_I= V_IHor V_IL

V_OH

V_CCI= MIN, V_CCI

(I_OH= -8mA)

(I_OL= 1mA)

(I_OL= 12mA)

2.4

V

V_I= V_IHor V_IL

V_CCI= MIN, V_CCI

V_I= V_IHor V_IL

0.4

V_OL

V_CCI= MIN, V_CCI

V_I= V_IHor V_IL

V_IL

Input Low Voltage

0.8

V

V_IH

Input High Voltage

2.0

–10

V_CCI+ 0.5

2.0

–10

V_CCI+ 0.5

I_IL/ I_IH

I_OZ

Input Leakage Current, V_IN= V_CCIor GND

3-State Output Leakage Current

Input Transition Time t_R, t_F

I/O Capacitance

10

20

µA

ns

pF

mA

t_R, t_F

C_IO

I_CC

Standby Current

IV Curve^*Can be derived from the IBIS model on the web.

Note: *The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

1 4

v4 .0

S X -A F a m i l y F P G A s

2 . 5 V L V C M O S 2 E l e c t r ic a l S p e c if i c a t io n s

Symbol Parameter

Commercial

Min. Max. Min.

(I_OH= -100µA) 2.1

Industrial

Max.

Units

V_DD= MIN,

V_I= V_IHor V_IL

2.1

2.0

1.7

V

V_DD= MIN,

V_OH

(I_OH= -1 mA)

(I_OH= -2 mA)

(I_OL= 100µA)

(I_OL= 1mA)

2.0

1.7

V

V_I= V_IHor V_IL

V_DD= MIN,

V_I= V_IHor V_IL

V_DD= MIN,

V_I= V_IHor V_IL

0.2

0.4

0.7

0.2

0.4

0.7

V_DD= MIN,

V_OL

V_I= V_IHor V_IL

V_DD= MIN,

V_I= V_IHor V_IL

(I_OL= 2 mA)

V_IL

Input Low Voltage, V_OUT≤ V_VOL(max)

Input High Voltage, V_OUT≥ V_VOH(min)

3-State Output Leakage Current, V_OUT= V_CCIor GND

Input Transition Time t_R, t_F

-0.3

V

V_IH

I_OZ

1.7 V_DD+ 0.3 1.7 V_DD+ 0.3

–10

10

–10

10

20

µA

ns

pF

mA

t_R, t_F

C_IO

I_CC

I/O Capacitance

Standby Current

IV Curve¹Can be derived from the IBIS model on the web.

Note:

1. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

P C I C o m p l i a n c e f o r t h e S X -A F a m i l y

The SX-A family supports 3.3V and 5V PCI and is compliant

with the PCI Local Bus Specification Rev. 2.1.

v4 .0

1 5

S X -A F a m i l y F P G A s

D C S p e c if i c a t io n s ( 5 V P C I O p e r a t io n )

Symbol

Parameter

Condition

Min.

Max.

Units

V_CCA

V_CCI

V_IH

Supply Voltage for Array

Supply Voltage for I/Os

Input High Voltage

2.3

4.75

2.0

2.7

5.25

V

V_CCI+ 0.5

0.8

V

V_IL

Input Low Voltage

–0.5

V

I_IH

Input High Leakage Current¹

Input Low Leakage Current¹

Output High Voltage

V_IN= 2.7

70

µA

V

I_IL

V_IN= 0.5

–70

V_OH

V_OL

C_IN

I_OUT= –2 mA

I_OUT= 3 mA, 6 mA

2.4

5

Output Low Voltage²

Input Pin Capacitance³

CLK Pin Capacitance

0.55

10

V

pF

C_CLK

Notes:

12

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes

FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).

1 6

v4 .0

S X -A F a m i l y F P G A s

A C S p e c if i c a t io n s ( 5 V P C I O p e r a t io n )

Symbol

Parameter

Condition

Min.

Max.

Units

0 < V_OUT≤ 1.4 ¹

1.4 ≤ V_OUT< 2.4 ^{1, 2}

–44

mA

Switching Current High

(–44 + (V_OUT– 1.4)/0.024)

I_OH(AC)

Equation A

on page 18

1, 3

3.1 < V_OUT< V_CCI

V_OUT= 3.1 ³

(Test Point)

–142

mA

V

_OUT≥ 2.2 ¹

95

2.2 > V_OUT> 0.55 ¹

(V_OUT/0.023)

Switching Current Low

I_OL(AC)

Equation B

on page 18

0.71 > V_OUT> 0 ^{1, 3}

(Test Point)

V_OUT= 0.71 ³

206

mA

I_CL

Low Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–5 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

slew_R

slew_F

Notes:

0.4V to 2.4V load ⁴

2.4V to 0.4V load ⁴

1

5

V/ns

1. Refer to the V/I curves in Figure 13 on page 18. Switching current characteristics for REQ# and GNT# are permitted to be one half of that

specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are

system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain

outputs.

2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the

voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.

3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)

are provided with the respective diagrams in Figure 13 on page 18. The equation defined maxima should be met by design. In order to

facilitate component testing, a maximum current test point is defined for each side of the output driver.

4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point

within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an

unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is

now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to

revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard

designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity

modeling accounts for this. Rise slew rate does not apply to open drain outputs.

1/2 in. max.

output

buffer

50 pF

v4 .0

1 7

S X -A F a m i l y F P G A s

Figure 13 shows the 5V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.

200.0

150.0

100.0

50.0

I

MAX Spec

OL

I

OL

I

MIN Spec

3.5

OL

0.0

0

0.5

1

1.5

2

2.5

3

4

4.5

I

5

5.5

6

–50.0

–100.0

–150.0

–200.0

I

MIN Spec

OH

MAX Spec

OH

I

OH

Voltage Out (V)

Figure 13 • 5V PCI V/I Curve for SX-A Family

Equation A

Equation B

I_OH= 11.9 * (V_OUT– 5.25) * (V_OUT+ 2.45)

for V_CCI> V_OUT> 3.1V

I

_OL= 78.5 * V

* (4.4 – V

)

OUT

for 0V < V_OUT< 0.71V

DC S p e c ific a t io n s (3 . 3 V P C I O p e r a t io n )

Symbol

Parameter

Condition

Min.

Max.

Units

V_CCA

V_CCI

V_IH

Supply Voltage for Array

Supply Voltage for I/Os

Input High Voltage

2.3

3.0

2.7

3.6

V

0.5V_CCIV_CCI+ 0.5

V

V_IL

Input Low Voltage

–0.5

0.7V_CCI

–10

0.3V_CCI

V

I_IPU

Input Pull-up Voltage¹

Input Leakage Current²

Output High Voltage

Output Low Voltage

Input Pin Capacitance³

CLK Pin Capacitance

V

I_IL

0 < V_IN< V_CCI

I_OUT= –500 µA

I_OUT= 1500 µA

+10

µA

V

V_OH

V_OL

C_IN

0.9V_CCI

0.1V_CCI

10

V

pF

C_CLK

Notes:

5

12

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications sensitive to

static power utilization.

2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).

1 8

v4 .0

S X -A F a m i l y F P G A s

AC S p e c ific a t io n s (3 . 3 V P C I O p e r a t io n )

Symbol

Parameter

Condition

Min.

Max.

Units

1

0 < V_OUT≤ 0.3V_CCI

–12V_CCI

mA

1

Switching Current High

0.3V_CCI≤ V_OUT< 0.9V_CCI

(–17.1(V_CCI– V_OUT))

I_OH(AC)

Equation C

on page 20

1, 2

0.7V_CCI< V_OUT< V_CCI

2

(Test Point)

V_OUT= 0.7V_CC

–32V_CCI

mA

1

V

_CCI> V_OUT≥ 0.6V_CCI

16V_CCI

1

Switching Current Low

0.6V_CCI> V_OUT> 0.1V_CCI

0.18V_CCI> V_OUT> 0 ^{1, 2}

(26.7V_OUT)

I_OL(AC)

Equation D

on page 20

2

(Test Point)

V_OUT= 0.18V_CC

38V_CCI

mA

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

I_CH

V_CCI+ 4 > V_IN≥ V_CCI+ 1

0.2V_CCI- 0.6V_CCIload ³

0.6V_CCI- 0.2V_CCIload ³

25 + (V_IN– V_CCI– 1)/0.015

mA

slew_R

slew_F

Notes:

1

4

V/ns

1. Refer to the V/I curves in Figure 14 on page 20. Switching current characteristics for REQ# and GNT# are permitted to be one half of that

specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are

system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain

outputs.

2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)

are provided with the respective diagrams in Figure 14 on page 20. The equation defined maximum should be met by design. In order to

facilitate component testing, a maximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point

within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an

unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum

parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.

1/2 in. max.

output

buffer

10 pF

1k/25Ω

output

buffer

10 pF

v4 .0

1 9

S X -A F a m i l y F P G A s

Figure 14 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.

150.0

100.0

50.0

I

MAX Spec

OL

I

OL

I

MIN Spec

2.5

OL

0.0

0

0.5

MIN Spec

1

1.5

2

3

3.5

4

–50.0

–100.0

–150.0

I

OH

I

MAX Spec

I

OH

Voltage Out (V)

Figure 14 • 3.3V PCI V/I Curve for SX-A Family

Equation C

Equation D

I_OH= (98.0/V ) * (V_OUT– V ) * (V_OUT+ 0.4V )

I_OL= (256/V ) * V

* (V_CCI– V

)

CCI

OUT

for 0.7 V_CCI< V_OUT< V

for 0V < V_OUT< 0.18 V

CCI

2 0

v4 .0

S X -A F a m i l y F P G A s

J u n c t i o n T e m p e r a t u r e ( T _J)

P = Power

= Junction to ambient of package. θ numbers are

located in the Package Thermal Characteristics table

below.

The temperature variable in the Designer Series software

refers to the junction temperature, not the ambient

temperature. This is an important distinction because the

heat generated from dynamic power consumption is usually

hotter than the ambient temperature. Equation 1, shown

below, can be used to calculate junction temperature.

θ

ja

P a c k a g e T h e r m a l C h a r a c t e r i s t i c s

The device junction-to-case thermal characteristic is θ_jc,

and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different

air flow rates.

Junction Temperature = ∆T + T

(1)

a

Where:

T = Ambient Temperature

a

The maximum junction temperature is 150°C.

∆T = Temperature gradient between junction (silicon) and

ambient

A sample calculation of the absolute maximum power

dissipation allowed for a TQFP 176-pin package at

commercial temperature and still air is as follows:

∆T = θ * P

(2)

ja

Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C

--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------

= 2.86W

Maximum Power Allowed =

=

θ_ja(°C/W)

28°C/W

P a c k a g e T h e r m a l C h a r a c t e r is t ic s

θ_ja

Package Type

Pin Count

θ_jc

Still Air

300 ft/min

Units

Thin Quad Flat Pack (TQFP)

100

144

176

208

329

144

256

484

12

11

8

37.5

32

30

24

°C/W

Thin Quad Flat Pack (TQFP)

28

21

Plastic Quad Flat Pack (PQFP)¹

Plastic Quad Flat Pack (PQFP) with Heat Spreader²

Plastic Ball Grid Array (PBGA)

30

23

3.8

3

20

17

18

13.5

26.7

25

Fine Pitch Ball Grid Array (FBGA)

1. The A54SX08A PQ208 has no heat spreader.

3.8

3.3

3

38.8

30

20

15

2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.

For Power Estimator information, please go to http://www.actel.com/products/tools/index.html.

v4 .0

2 1

S X -A F a m i l y F P G A s

S X -A T i m i n g M o d e l *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

Combinatorial

Cell

t

= 0.3 ns

= 0.4 ns

I/O Module

IRD1

IRD2

t

= 0.5 ns

INYH

t

= 2.0 ns

DHL

t

= 0.8 ns

PD

t

= 0.3 ns

RD1

= 0.7 ns

RD4

= 1.2 ns

RD8

I/O Module

t

= 2.0 ns

Register

Cell

DHL

D

Q

t

RD1

= 0.7 ns

= 0.3 ns

SUD

HD

t

= 0.0 ns

= 1.4 ns

ENZL

Routed

Clock

t

= 1.2 ns

RCKH

t

= 0.6 ns

(100% Load)

RCO

I/O Module

= 2.0 ns

DHL

Register

Cell

I/O Module

t

= 1.0 ns

INYH

D

Q

t

RD1

= 0.7 ns

= 0.0 ns

= 0.3 ns

SUD

HD

= 1.4 ns

ENZL

Hard-Wired

Clock

t

RCO

= 1.1 ns

= 0.6 ns

HCKH

Note: *Values shown for A54SX08A, –3, worst-case commercial conditions at 3.3V PCI with standard place-and-route.

S a m p l e P a t h C a l c u l a t i o n s

H a r d w i r e d C lo c k

R o u t e d C l o c k

External Setup = (t_INYH+ t_IRD2+ t_SUD) – t_HCKH

External Setup = (t_INYH+ t_IRD2+ t_SUD) – t_RCKH

= 0.5 + 0.4 + 0.7– 1.2= 0.4 ns

= 0.5 + 0.4+ 0.7 – 1.1 = 0.5 ns

Clock-to-Out (Pad-to-Pad)

= t_HCKH+ t_RCO+ t_RD1+ t_DHL

= t_RCKH+ t_RCO+ t_RD1+ t_DHL

= 1.1 + 0.6 + 0.3 + 2.0= 4.0 ns

=

1.2+ 0.6 + 0.3 + 2.0 = 4.1 ns

2 2

v4 .0

S X -A F a m i l y F P G A s

O u t p u t B u f f e r D e l a y s

E

D

To AC test loads (shown below)

PAD

TRIBUFF

V_CC

In

GND

50%

V_OH

En

Out

GND

10%

50%

En

GND

90%

50%

V_CC

50%

V_OH

50%

1.5V

V_OL

Out

V_OL

Out

GND

1.5V

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_ENHZ

A C T e s t L o a d s

Load 3

Load 2

Load 1

(Used to measure

propagation delay)

(Used to measure disable delays)

(Used to measure enable delays)

V_CC

GND

To the output

under test

35 pF

R to V_CCfor t_PLZ

R to GND for t_PHZ

R = 1 kΩ

R to V_CCfor t_PZL

R to GND for t_PZH

R = 1 kΩ

To the output

under test

To the output

under test

5 pF

35 pF

I n p u t B u f f e r D e l a y s

C -C e l l D e l a y s

S

A

B

Y

PAD

INBUF

V_CC

GND

S, A, or B

50% 50%

V_CC

3V

In

0V

50%

1.5V

V_CC

1.5V

50%

Out

50%

GND

t_PD

Out

GND

50%

V_CC

50%

Out

GND

t_PD

50%

t_PD

v4 .0

2 3

S X -A F a m i l y F P G A s

C e l l T i m i n g C h a r a c t e r i s t i c s

F l ip -F lo p s

D

Q

PRESET

CLR

CLK

(Positive edge triggered)

t_HD

D

t_SUD

CLK

t_HP

t_HPWH

t_RPWH

,

t_HPWL

,

t_RPWL

t_RCO

Q

t_CLR

t_PRESET

CLR

t_WASYN

PRESET

L o n g T r a c k s

T i m i n g C h a r a c t e r i s t i c s

Some nets in the design use long tracks. Long tracks are special

routing resources that span multiple rows, columns, or modules.

Long tracks employ three to five antifuse connections. This

increases capacitance and resistance, resulting in longer net

delays for macros connected to long tracks. Typically, up to

6 percent of nets in a fully utilized device require long tracks.

Long tracks contribute approximately 4 ns to 8.4 ns delay. This

additional delay is represented statistically in higher fanout

routing delays.

Timing characteristics for SX-A devices fall into three

categories: family-dependent, device-dependent, and

design-dependent. The input and output buffer characteristics

are common to all SX-A family members. Internal routing

delays are device-dependent. Design dependency means actual

delays are not determined until after placement and routing of

the user’s design are complete. Delay values may then be

determined by using the Timer utility or performing simulation

with post-layout delays.

T im i n g D e r a t in g

C r it ic a l N e t s a n d T y p i c a l N e t s

SX-A devices are manufactured with a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum timing

parameters reflect maximum operating voltage, minimum

operating temperature, and best-case processing. Maximum

timing parameters reflect minimum operating voltage,

maximum operating temperature, and worst-case processing.

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most timing

critical paths. Critical nets are determined by net property

assignment prior to placement and routing. Up to 6 percent

of the nets in a design may be designated as critical, while

90 percent of the nets in a design are typical.

T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

( N o r m a li z e d t o W o r s t -C a s e C o m m e r c i a l, T _J= 7 0 °C , V _{C C A}= 2 . 3 V )

Junction Temperature (T_J)

V_CCA

2.3V

2.5V

2.7V

–55°C

0.75

–40°C

0.79

0°C

0.88

0.82

0.79

25°C

0.89

0.83

0.79

70°C

1.00

0.93

0.88

85°C

1.04

0.97

0.92

125°C

1.16

0.70

0.74

1.08

0.66

0.69

1.02

2 4

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s , V _{C C A}= 2 . 3 V_,V _{C C I}= 3 . 0 V, T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.8

1.0

1.1

1.3

1.8

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.4

0.5

0.7

1.2

1.7

0.1

0.3

0.5

0.6

0.8

1.4

2.0

0.1

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.1

0.4

0.5

0.6

0.8

1.0

1.8

2.6

0.1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.7

0.8

0.9

1.1

1.3

1.6

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Hold Time

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

0.8

0.0

1.5

0.4

0.3

0.9

0.0

1.7

0.4

0.3

1.1

0.0

2.0

0.5

0.4

1.6

0.0

2.8

0.7

0.6

t_HD

t_WASYN

t_RECASYN

t_HASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.5

0.8

0.6

1.0

0.7

1.0

0.8

1.3

1.1

1.8

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2.0

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1.0

1.8

2.6

0.6

0.8

1.1

1.4

2.5

3.6

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v4 .0

2 5

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.1

1.3

1.2

1.5

1.4

1.8

1.6

2.4

2.2

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.2

0.3

0.4

Minimum Period

2.8

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.1

1.3

1.2

1.4

1.3

1.5

1.2

1.4

1.6

1.5

1.7

1.3

1.6

1.9

1.7

2.0

1.6

1.9

2.2

2.0

2.3

2.2

2.6

3.0

2.8

3.1

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.3

0.4

0.3

0.4

0.7

2 6

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.1

1.0

1.2

1.4

1.3

1.6

1.5

2.4

2.3

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.2

0.3

0.4

Minimum Period

2.8

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.0

1.3

1.1

1.4

1.2

1.5

1.2

1.4

1.3

1.5

1.4

1.6

1.3

1.7

1.5

1.9

1.6

2.0

1.6

2.0

1.8

2.2

1.9

2.3

2.2

2.8

2.5

3.1

2.6

3.4

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.2

0.3

0.4

0.7

v4 .0

2 7

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.0

1.2

1.1

1.4

1.3

1.5

2.3

2.2

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.2

0.3

0.4

Minimum Period

2.8

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.0

1.2

1.1

1.3

1.2

1.4

1.1

1.4

1.3

1.6

1.4

1.7

1.2

1.6

1.5

1.9

1.6

2.0

1.5

1.8

2.1

1.9

2.2

2.0

2.6

2.5

3.1

2.6

3.2

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.2

0.3

0.4

0.7

2 8

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

2.5V LVTTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

3.2

2.6

3.8

3.0

4.3

3.4

5.0

4.0

7.0

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

11.3

2.4

13.0

2.8

14.8

3.2

17.4

3.7

24.4

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.4

13.7

4.0

15.5

4.5

18.2

5.3

25.5

7.5

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.4

4.0

4.5

5.3

7.5

Delta LOW to HIGH

0.031

0.017

0.057

0.037

0.017

0.060

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Note:

Delta HIGH to LOW—low slew

1. Delays based on 35 pF loading.

v4 .0

2 9

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

3.3V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta LOW to HIGH

2.0

2.3

2.6

3.0

4.3

3.1

5.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

1.4

1.7

1.9

2.2

1.4

1.7

1.9

2.2

2.5

2.8

3.2

3.8

2.5

2.8

3.2

3.8

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

Delta HIGH to LOW

3.3V LVTTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.7

2.5

3.2

2.8

3.6

3.2

4.2

3.8

5.9

5.3

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

9.0

10.4

2.6

11.8

2.9

13.8

3.4

19.4

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.9

18.9

3.3

21.3

3.7

25.4

4.4

34.9

6.2

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.5

2.8

3.2

3.8

5.3

Delta LOW to HIGH

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 10 pF loading and 25Ω resistance.

2. Delays based on 35 pF loading.

3 0

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 0 8 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5.0V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.1

2.7

2.5

3.1

2.8

3.5

3.3

4.2

4.6

5.8

15.9

2.8

9.7

2.8

6.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

7.4

8.5

9.6

11.3

2.0

1.3

1.5

1.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

3.5

5.1

5.9

6.9

1.3

1.5

1.7

2.0

Enable-to-Pad, L to Z

3.0

3.5

3.9

4.6

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

Delta LOW to HIGH

0.016

0.026

0.04

0.016

0.03

0.052

0.02

0.032

0.06

0.022

0.04

0.07

0.032 ns/pF

0.052 ns/pF

0.096 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Delta HIGH to LOW—low slew

5.0V TTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

1.9

2.5

2.2

2.9

2.5

3.3

3.0

3.9

4.2

5.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

6.6

7.6

8.6

10.2

3.2

14.2

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

3.6

15.4

5.0

2.3

2.7

3.1

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

6.4

Delta LOW to HIGH

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 50 pF loading.

2. Delays based on 35 pF loading

v4 .0

3 1

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s , V _{C C A}= 2 . 3 V _,V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.8

1.0

1.1

1.3

1.8

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.4

0.5

0.7

1.2

1.7

0.1

0.3

0.5

0.6

0.8

1.4

2.0

0.1

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.1

0.4

0.5

0.6

0.8

1.0

1.8

2.6

0.1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.7

0.8

0.9

1.1

1.3

1.6

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

0.8

0.0

1.5

0.4

0.3

0.9

0.0

1.7

0.4

0.3

1.1

0.0

2.0

0.5

0.4

1.6

0.0

2.8

0.7

0.6

t_HD

t_WASYN

t_RECASYN

t_HASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.5

0.8

0.6

1.0

0.7

1.0

0.8

1.3

1.1

1.8

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2.0

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1.0

0.8

2.6

0.6

0.8

1.1

1.4

2.5

3.6

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3 2

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.2

1.1

1.5

1.4

1.6

1.5

1.9

1.8

2.9

2.8

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.1

0.2

Minimum Period

2.7

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.2

1.3

1.5

1.6

1.7

1.8

1.3

1.4

1.7

1.8

1.9

2.0

1.5

1.6

2.0

2.1

2.2

2.3

1.8

1.9

2.3

2.4

2.6

2.7

2.5

2.7

3.3

3.4

3.6

3.8

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.3

0.5

0.4

0.6

0.4

0.7

0.4

0.8

0.6

1.3

v4 .0

3 3

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.2

1.1

1.5

1.4

1.6

1.5

1.9

1.8

2.9

2.8

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.1

0.2

Minimum Period

2.7

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.2

1.3

1.5

1.6

1.7

1.8

1.3

1.4

1.7

1.8

1.9

2.0

1.5

1.7

2.0

2.1

2.2

2.3

1.8

2.0

2.3

2.4

2.6

2.7

2.4

2.8

3.3

3.4

3.6

3.8

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.3

0.5

0.4

0.6

0.4

0.7

0.4

0.8

0.6

1.3

3 4

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.2

1.1

1.4

1.3

1.6

1.5

1.8

1.7

2.8

2.7

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

3.0

0.1

0.2

Minimum Period

2.7

3.2

3.6

4.2

6.0

f_HMAX

Maximum Frequency

350

310

277

238

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.1

1.2

1.4

1.5

1.6

1.7

1.2

1.4

1.6

1.7

1.9

2.0

1.4

1.6

1.8

1.9

2.1

2.2

1.7

1.8

2.2

2.3

2.5

2.6

2.3

2.6

3.1

3.4

3.5

4.0

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

ns

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.3

0.5

0.4

0.6

0.4

0.7

0.4

0.8

0.6

1.3

v4 .0

3 5

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5V LVTTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

3.2

2.6

3.8

3.0

4.3

3.4

5.0

4.0

7.0

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

11.3

2.4

13.0

2.8

14.8

3.2

17.4

3.7

24.4

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.4

13.7

4.0

15.5

4.5

18.2

5.3

25.5

7.5

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.4

4.0

4.5

5.3

7.5

Delta LOW to HIGH

0.031

0.017

0.057

0.037

0.017

0.060

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Note:

Delta HIGH to LOW—low slew

1. Delays based on 35 pF loading.

3 6

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

3.3V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta LOW to HIGH

2.0

2.3

2.6

3.0

4.3

3.1

5.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

1.4

1.7

1.9

2.2

1.4

1.7

1.9

2.2

2.5

2.8

3.2

3.8

2.5

2.8

3.2

3.8

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

Delta HIGH to LOW

3.3V LVTTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.7

2.5

3.2

2.8

3.6

3.2

4.2

3.8

5.9

5.3

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

9.0

10.4

2.6

11.8

2.9

13.8

3.4

19.4

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.9

18.9

3.3

21.3

3.7

25.4

4.4

34.9

6.2

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.5

2.8

3.2

3.8

5.3

Delta LOW to HIGH

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 10 pF loading and 25Ω resistance.

2. Delays based on 35 pF loading.

v4 .0

3 7

S X -A F a m i l y F P G A s

A 5 4 S X 1 6 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5.0V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.1

2.73

7.4

2.5

3.1

2.8

3.5

3.3

4.2

4.6

5.8

15.9

2.8

9.7

2.8

6.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

8.5

9.6

11.3

2.0

1.3

1.5

1.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

3.5

5.1

5.9

6.9

1.3

1.5

1.7

2.0

Enable-to-Pad, L to Z

3.0

3.5

3.9

4.6

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

Delta LOW to HIGH

0.016

0.026

0.04

0.016

0.03

0.052

0.02

0.032

0.06

0.022

0.04

0.07

0.032 ns/pF

0.052 ns/pF

0.096 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Delta HIGH to LOW—low slew

5.0V TTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

1.9

2.5

2.2

2.9

2.5

3.3

3.0

3.9

4.2

5.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

6.6

7.6

8.6

10.2

3.2

14.2

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

3.6

15.4

5.0

2.3

2.7

3.1

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

6.4

Delta LOW to HIGH

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 50 pF loading.

2. Delays based on 35 pF loading.

3 8

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s , V _{C C A}= 2 . 3 V_,V _{C C I}= 3 . 0 V, T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.8

1.0

1.1

1.3

1.8

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.4

0.5

0.7

1.2

1.7

0.1

0.3

0.5

0.6

0.8

1.4

2.0

0.1

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.1

0.4

0.5

0.6

0.8

1.0

1.8

2.6

0.1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.7

0.8

0.9

1.1

1.3

1.6

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

0.8

0.0

1.5

0.4

0.3

0.9

0.0

1.7

0.4

0.3

1.1

0.0

2.0

0.5

0.4

1.6

0.0

2.8

0.7

0.6

t_HD

t_WASYN

t_RECASYN

t_HASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.5

0.8

0.6

1.0

0.7

1.0

0.8

1.3

1.1

1.8

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2.0

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1.0

1.8

2.6

0.6

0.8

1.1

1.4

2.5

3.6

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v4 .0

3 9

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.7

1.5

2.0

1.7

2.3

1.9

2.7

2.3

4.1

3.5

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.3

0.4

0.5

0.8

Minimum Period

2.7

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.7

2.1

2.3

2.5

2.0

2.4

2.5

2.9

2.2

2.7

2.8

2.9

3.2

2.6

3.2

3.4

3.8

3.7

4.5

5.0

6.4

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.9

1.2

1.3

1.0

1.4

1.5

1.1

1.6

1.7

1.3

1.9

2.0

2.2

3.2

3.4

4 0

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.7

1.5

2.0

1.7

2.3

1.9

2.7

2.3

4.1

3.5

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.3

0.4

0.5

0.8

Minimum Period

2.7

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.7

2.1

2.3

2.5

2.0

2.4

2.5

2.9

2.2

2.8

2.9

3.2

2.6

3.3

3.2

3.4

3.8

3.7

4.6

4.5

5.0

6.4

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.9

1.2

1.3

1.0

1.4

1.5

1.1

1.6

1.7

1.3

1.9

2.0

2.2

3.2

3.4

v4 .0

4 1

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.7

1.5

1.9

1.7

2.3

1.9

2.6

2.2

4.0

3.5

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.3

0.4

0.5

0.8

Minimum Period

2.7

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

1.6

2.0

2.2

2.5

1.9

2.4

2.5

2.9

2.1

2.7

2.8

3.2

2.5

3.1

3.3

3.8

3.5

4.4

2.5

5.5

6.4

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.9

1.2

1.3

1.0

1.4

1.5

1.1

1.6

1.7

1.3

1.9

2.0

3.2

3.4

4 2

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5V LVTTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

3.2

2.6

3.8

3.0

4.3

3.4

5.0

4.0

7.0

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

11.3

2.4

13.0

2.8

14.8

3.2

17.4

3.7

24.4

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.4

13.7

4.0

15.5

4.5

18.2

5.3

25.5

7.5

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.4

4.0

4.5

5.3

7.5

Delta LOW to HIGH

0.031

0.017

0.057

0.037

0.017

0.060

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Note:

Delta HIGH to LOW—low slew

1. Delays based on 35 pF loading.

v4 .0

4 3

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

3.3V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta LOW to HIGH

2.0

2.3

2.6

3.0

4.3

3.1

5.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

1.4

1.7

1.9

2.2

1.4

1.7

1.9

2.2

2.5

2.8

3.2

3.8

2.5

2.8

3.2

3.8

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

Delta HIGH to LOW

3.3V LVTTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.7

2.5

3.2

2.8

3.6

3.2

4.2

3.8

5.9

5.3

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

9.0

10.4

2.6

11.8

2.9

13.8

3.4

19.4

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.9

18.9

3.3

21.3

3.7

25.4

4.4

34.9

6.2

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.5

2.8

3.2

3.8

5.3

Delta LOW to HIGH

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 10 pF loading and 25Ω resistance.

2. Delays based on 35 pF loading.

4 4

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 3 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5.0V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.1

2.7

2.5

3.1

2.8

3.5

3.3

4.2

4.6

5.8

15.9

2.8

9.7

2.8

6.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

7.4

8.5

9.6

11.3

2.0

1.3

1.5

1.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

3.5

5.1

5.9

6.9

1.3

1.5

1.7

2.0

Enable-to-Pad, L to Z

3.0

3.5

3.9

4.6

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

Delta LOW to HIGH

0.016

0.026

0.04

0.016

0.03

0.052

0.02

0.032

0.06

0.022

0.04

0.07

0.032 ns/pF

0.052 ns/pF

0.096 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Delta HIGH to LOW—low slew

5.0V TTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

1.9

2.5

2.2

2.9

2.5

3.3

3.0

3.9

4.2

5.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

6.6

7.6

8.6

10.2

3.2

14.2

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

3.6

15.4

5.0

2.3

2.7

3.1

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

6.4

Delta LOW to HIGH

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 50 pF loading.

2. Delays based on 35 pF loading.

v4 .0

4 5

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s , V _{C C A}= 2 . 3 V _,V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.8

1.0

1.1

1.3

1.8

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.4

0.5

0.7

1.2

1.7

0.1

0.3

0.5

0.7

0.9

1.5

2.2

0.1

0.3

0.4

0.6

0.8

1.0

1.7

2.5

0.1

0.4

0.5

0.7

0.9

1.1

2.1

3.0

0.1

0.6

0.7

1.0

1.3

1.5

2.9

4.2

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.7

0.8

0.9

1.1

1.3

1.6

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

0.8

0.0

1.5

0.4

0.3

0.9

0.0

1.7

0.4

0.3

1.1

0.0

2.0

0.5

0.4

1.6

0.0

2.8

0.7

0.6

t_HD

t_WASYN

t_RECASYNAsynchronous Recovery Time

t_HASYNAsynchronous Hold Time

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.5

0.8

0.6

1.0

0.7

1.0

0.8

1.3

1.1

1.8

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1.0

1.7

2.5

0.5

0.7

0.9

1.1

2.1

3.0

0.7

1.0

1.3

1.5

2.9

4.2

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

4 6

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.3

1.1

1.5

1.3

1.7

1.5

2.1

1.9

3.1

2.9

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.7

0.8

0.9

1.0

1.6

Minimum Period

2.8

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

2.3

2.6

3.0

3.3

3.7

4.0

2.6

3.1

3.5

3.8

4.3

4.6

2.9

3.4

3.9

4.2

4.8

5.1

3.5

4.0

4.6

4.9

5.7

6.0

4.8

5.6

6.5

7.1

8.0

8.6

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.8

1.2

1.4

2.1

1.4

1.5

2.4

1.6

1.7

2.7

1.9

2.0

3.8

3.2

3.4

v4 .0

4 7

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 3 . 0 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.3

1.1

1.5

1.3

1.7

1.5

2.1

1.9

3.1

2.9

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.7

0.8

0.9

1.0

1.6

Minimum Period

2.8

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

2.2

2.7

3.0

3.3

3.7

4.0

2.6

3.1

3.5

3.8

4.3

4.6

2.9

3.5

3.9

4.2

4.8

5.1

3.5

4.1

4.6

4.9

5.7

6.0

4.8

5.7

6.5

7.1

8.0

8.6

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.8

1.2

1.4

2.1

1.4

1.5

2.4

1.6

1.7

2.7

1.9

2.0

3.8

3.2

3.4

4 8

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

Dedicated (Hardwired) Array Clock Networks

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.3

1.1

1.4

1.2

1.7

1.5

2.0

1.8

3.0

2.8

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.2

3.0

ns

0.7

0.8

0.9

1.0

1.6

Minimum Period

2.8

3.2

3.6

4.4

6.0

f_HMAX

Maximum Frequency

350

310

277

227

166 MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

2.2

2.6

3.0

3.3

3.7

4.0

2.5

3.0

3.5

3.8

4.3

4.6

2.8

3.4

3.9

4.2

4.8

5.1

3.4

3.9

4.6

4.9

5.7

6.0

4.6

5.5

6.5

7.1

8.0

8.6

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

1.4

1.6

1.8

2.2

3.0

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.8

2.1

1.4

1.5

2.4

1.6

1.7

2.7

1.9

2.0

3.8

3.2

3.4

v4 .0

4 9

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 2 . 3 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5V LVTTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

3.3

2.6

3.9

3.0

4.4

3.4

5.2

4.0

7.2

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

11.7

2.4

13.5

2.8

15.3

3.2

18.0

3.7

25.9

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.4

13.7

4.0

15.5

4.5

18.2

5.3

25.5

7.5

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.4

4.0

4.5

5.3

7.5

Delta LOW to HIGH

0.031

0.017

0.057

0.037

0.017

0.060

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Note:

Delta HIGH to LOW—low slew

1. Delays based on 35 pF loading.

5 0

v4 .0

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s V_{C C A}= 2 . 3 V, V_{C C I}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter Description

3.3V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta LOW to HIGH

2.0

2.3

2.6

3.0

4.3

3.1

5.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

1.4

1.7

1.9

2.2

1.4

1.7

1.9

2.2

2.5

2.8

3.2

3.8

2.5

2.8

3.2

3.8

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

Delta HIGH to LOW

3.3V LVTTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.7

2.5

3.2

2.8

3.6

3.2

4.2

3.8

5.9

5.3

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

9.0

10.4

2.6

11.8

2.9

13.8

3.4

19.4

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.9

18.9

3.3

21.3

3.7

25.4

4.4

34.9

6.2

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.5

2.8

3.2

3.8

5.3

Delta LOW to HIGH

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 10 pF loading and 25Ω resistance.

2. Delays based on 35 pF loading.

v4 .0

5 1

S X -A F a m i l y F P G A s

A 5 4 S X 7 2 A T i m i n g C h a r a c t e r i s t i c s (C o n t in u e d )

( W o r s t -C a s e C o m m e r c ia l C o n d it io n s V _{C C A}= 2 . 3 V , V _{C C I}= 4 . 7 5 V , T _J= 7 0 °C )

‘Std’

Speed

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘–F’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5.0V PCI Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

2.1

2.7

2.5

3.1

2.8

3.5

3.3

4.2

4.6

5.8

15.9

2.8

9.7

2.8

6.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

7.4

8.5

9.6

11.3

2.0

1.3

1.5

1.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

3.5

5.1

5.9

6.9

1.3

1.5

1.7

2.0

Enable-to-Pad, L to Z

3.0

3.5

3.9

4.6

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

Delta LOW to HIGH

0.016

0.026

0.04

0.016

0.03

0.052

0.02

0.032

0.06

0.022

0.04

0.07

0.032 ns/pF

0.052 ns/pF

0.096 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Delta HIGH to LOW—low slew

5.0V TTL Output Module Timing²

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—low slew

Enable-to-Pad, Z to L

1.9

2.5

2.2

2.9

2.5

3.3

3.0

3.9

4.2

5.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

6.6

7.6

8.6

10.2

3.2

14.2

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

3.6

15.4

5.0

2.3

2.7

3.1

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.0

3.5

3.9

4.6

6.4

Delta LOW to HIGH

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

d_THL

Delta HIGH to LOW

d_THLS

Notes:

Delta HIGH to LOW—low slew

1. Delays based on 50 pF loading.

2. Delays based on 35 pF loading.

5 2

v4 .0

S X -A F a m i l y F P G A s

P i n D e s c r i p t i o n

capabilities can be permanently disabled to protect

programmed design confidentiality.

C LK A/B

C lo c k A a n d B

T C K , I/O

Te s t C lo c k

These pins are clock inputs for clock distribution networks.

Input levels are compatible with standard TTL, LVTTL, 3.3V

PCI or 5V PCI specifications. The clock input is buffered

prior to clocking the R-cells. If not used, this pin must be set

LOW or HIGH on the board except A54SX72A. In A54SX72A

these clocks can be configured as user I/O.

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active when

the TMS pin is set LOW (refer to Table 5 on page 11). This

pin functions as an I/O when the boundary scan state

machine reaches the “logic reset” state.

Q C LK A/B /C /D, Q u a d r a n t C lo c k A, B , C , a n d D

I/O

T D I, I/O

Te s t D a t a In p u t

Serial input for boundary scan testing and diagnostic probe.

In flexible mode, TDI is active when the TMS pin is set LOW

(refer to Table 5 on page 11). This pin functions as an I/O

when the boundary scan state machine reaches the “logic

reset” state.

These four pins are the quadrant clock inputs and are only

for A54SX72A with A, B, C, and D corresponding to

bottom-left, bottom-right, top-left, and top-right quadrants,

respectively. They are clock inputs for clock distribution

networks. Input levels are compatible with standard TTL,

LVTTL, 3.3V PCI or 5V PCI specifications. Each of these

clock inputs can drive up to a quarter of the chip, or they

can be grouped together to drive multiple quadrants. The

clock input is buffered prior to clocking the R-cells. If not

used as a clock it will behave as a regular I/O.

T DO , I/O

Te s t Da t a O u t p u t

Serial output for boundary scan testing. In flexible mode,

TDO is active when the TMS pin is set LOW (refer to Table 5

on page 11). This pin functions as an I/O when the boundary

scan state machine reaches the "logic reset" state. When

Silicon Explorer II is being used, TDO will act as an output

when the "checksum" command is run. It will return to user

IO when "checksum" is complete.

G N D

G r o u n d

LOW supply voltage.

H C LK

De d ic a t e d (H a r d w ir e d )

Ar r a y C lo c k

T M S

Te s t M o d e S e le c t

The TMS pin controls the use of the IEEE 1149.1 Boundary

Scan pins (TCK, TDI, TDO, TRST). In flexible mode when

the TMS pin is set LOW, the TCK, TDI, and TDO pins are

boundary scan pins (refer to Table 5 on page 11). Once the

boundary scan pins are in test mode, they will remain in

that mode until the internal boundary scan state machine

reaches the “logic reset” state. At this point, the boundary

scan pins will be released and will function as regular I/O

pins. The “logic reset” state is reached 5 TCK cycles after

the TMS pin is set HIGH. In dedicated test mode, TMS

functions as specified in the IEEE 1149.1 specifications.

This pin is the clock input for sequential modules. Input

levels are compatible with standard TTL, LVTTL, 3.3V PCI

or 5V PCI specifications. This input is directly wired to each

R-cell and offers clock speeds independent of the number of

R-cells being driven. If not used, this pin must be set LOW

or HIGH on the board. It must not be left floating.

I/O

In p u t /O u t p u t

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Based on certain configurations, input

and output levels are compatible with standard TTL, LVTTL,

3.3V PCI or 5V PCI specifications. Unused I/O pins are

automatically tristated by the Designer Series software.

T R S T, I/O

B o u n d a r y S c a n R e s e t P in

Once it is configured as the JTAG Reset pin, the TRST pin

functions as an active-low input to asynchronously initialize

or reset the boundary scan circuit. The TRST pin is

equipped with an internal pull-up resistor. This pin

functions as an I/O when the “Reserve JTAG Reset Pin” is

not selected in Designer.

N C

N o C o n n e c t io n

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device. The

only exception is for the A54SX32A FG-484, where the NC

pins must be left floating.

V_{C C I}

S u p p ly Vo lt a g e

Supply voltage for I/Os. See “Recommended Operating

P R A, I/O

P R B , I/O

P ro b e A/B

Conditions” table on page 14. All V power pins in the

CCI

device should be connected.

The Probe pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the other probe pin to

allow real-time diagnostic output of any signal path within

the device. The Probe pin can be used as a user-defined I/O

when verification has been completed. The pin’s probe

V_{C C A}

S u p p ly Vo lt a g e

Supply voltage for Array. See “Recommended Operating

Conditions” table on page 14. All V_CCApower pins in the

device should be connected.

v4 .0

5 3

P a c k a g e P i n A s s i g n m e n t s

2 0 8 -P in P Q F P ( T o p V i e w )

208

1

208-Pin PQFP

5 4

v4 .0

2 0 8 -P in P Q F P

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

2

3

4

NC

I/O

5

I/O

6

NC

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

NC

I/O

NC

I/O

GND

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

TRST, I/O

NC

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

NC

I/O

NC

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

v4 .0

5 5

2 0 8 -P in P Q F P ( C o n t in u e d )

A54SX08A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

Function

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

QCLKA

I/O

NC

PRB, I/O

GND

V_CCA

GND

NC

I/O

PRB, I/O

GND

V_CCA

GND

NC

I/O

PRB, I/O

GND

V_CCA

GND

NC

I/O

PRB,I/O

GND

V_CCA

GND

NC

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

HCLK

V_CCI

QCLKB

I/O

NC

I/O

NC

I/O

NC

I/O

5 6

v4 .0

2 0 8 -P in P Q F P ( C o n t in u e d )

A54SX08A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

Function

93

I/O

NC

I/O

94

95

I/O

96

I/O

97

NC

V_CCI

I/O

98

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

NC

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

V_CCA

V_CCI

NC

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

GND

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

I/O

NC

I/O

NC

I/O

v4 .0

5 7

2 0 8 -P in P Q F P ( C o n t in u e d )

A54SX08A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

Function

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

I/O

NC

I/O

NC

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

QCLKD

I/O

CLKA

CLKB

NC

GND

V_CCA

CLKA

CLKB

NC

GND

V_CCA

CLKA

CLKB

NC

GND

V_CCA

CLKA

CLKB

NC

GND

V_CCA

5 8

v4 .0

2 0 8 -P in P Q F P ( C o n t in u e d )

A54SX08A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

Function

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

GND

PRA, I/O

I/O

GND

PRA, I/O

I/O

GND

PRA, I/O

I/O

GND

PRA, I/O

V_CCI

I/O

NC

I/O

QCLKC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

NC

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

TCK, I/O

v4 .0

5 9

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

1 0 0 -P in T Q F P ( T o p V i e w )

100

1

100-Pin

TQFP

6 0

v4 .0

1 0 0 -T Q F P

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

GND

I/O

GND

I/O

GND

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

PRB, I/O

V_CCA

GND

NC

PRB, I/O

V_CCA

GND

NC

PRB, I/O

V_CCA

GND

NC

I/O

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TCK, I/O

v4 .0

6 1

P a c k a g e P i n A s s i g n m e n t s ( c o n t i n u e d )

1 4 4 -P in T Q F P ( T o p V i e w )

144

1

144-Pin

TQFP

6 2

v4 .0

1 4 4 -P in T Q F P

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

7

I/O

8

I/O

9

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

GND

NC

V_CCA

GND

NC

V_CCA

GND

NC

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

v4 .0

6 3

1 4 4 -P in T Q F P ( C o n t in u e d )

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

77

78

I/O

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

I/O

79

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

80

I/O

81

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

82

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

I/O

89

V_CCA

NC

V_CCA

NC

V_CCA

NC

I/O

90

I/O

91

I/O

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

92

I/O

93

I/O

94

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

95

I/O

96

I/O

97

I/O

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

98

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

TCK, I/O

6 4

v4 .0

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

1 7 6 -P in T Q F P (T o p Vie w )

176

1

176-Pin

TQFP

v4 .0

6 5

1 7 6 -P in T Q F P

Number

A54SX32A

Function

Number

A54SX32A

Function

Number

A54SX32A

Function

Number

A54SX32A

Function

1

GND

TDI, I/O

I/O

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

I/O

91

I/O

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

I/O

2

92

3

I/O

93

I/O

4

I/O

94

I/O

5

I/O

95

I/O

V_CCI

I/O

6

I/O

96

I/O

7

I/O

V_CCI

I/O

97

I/O

8

I/O

98

V_CCA

V_CCI

I/O

9

I/O

99

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

TMS

V_CCI

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

I/O

CLKA

CLKB

NC

I/O

GND

V_CCA

GND

I/O

PRB, I/O

GND

V_CCA

NC

I/O

GND

V_CCA

PRA, I/O

I/O

GND

V_CCA

GND

I/O

HCLK

I/O

TRST, I/O

I/O

V_CCI

V_CCA

I/O

V_CCA

GND

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TCK, I/O

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

6 6

v4 .0

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

3 2 9 -P in P B G A ( T o p V i e w )

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

v4 .0

6 7

3 2 9 -P in P B G A

A54SX32A

Pin Number Function

A54SX32A

Pin Number Function

A54SX32A

Pin Number Function

A1

A2

GND

V_CCI

NC

AA23

AB1

V_CCI

I/O

AC22

AC23

B1

V_CCI

GND

V_CCI

GND

I/O

C21

C22

C23

D1

V_CCI

GND

NC

I/O

A3

AB2

GND

I/O

A4

AB3

B2

A5

I/O

AB4

I/O

B3

D2

I/O

A6

I/O

AB5

I/O

B4

I/O

D3

I/O

A7

V_CCI

NC

AB6

I/O

B5

I/O

D4

TCK, I/O

I/O

A8

AB7

I/O

B6

I/O

D5

A9

I/O

AB8

I/O

B7

I/O

D6

I/O

A10

A11

I/O

AB9

I/O

B8

I/O

D7

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

I/O

B9

I/O

D8

I/O

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

I/O

PRB, I/O

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

I/O

D9

I/O

CLKB

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

E1

I/O

HCLK

I/O

PRA, I/O

CLKA

I/O

V_CCA

NC

I/O

NC

I/O

V_CCI

GND

V_CCI

I/O

GND

I/O

GND

V_CCI

NC

I/O

GND

V_CCI

NC

I/O

GND

I/O

AC2

I/O

AC3

C2

TDI, I/O

GND

I/O

V_CCI

I/O

AC4

C3

E2

I/O

AC5

I/O

C4

E3

I/O

AC6

I/O

C5

I/O

E4

I/O

AC7

I/O

C6

I/O

E20

E21

E22

E23

F1

I/O

AC8

I/O

C7

I/O

AC9

V_CCI

I/O

C8

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

I/O

F2

TMS

I/O

F3

I/O

F4

I/O

NC

I/O

F20

F21

F22

F23

G1

I/O

TDO, I/O

V_CCI

I/O

G2

I/O

NC

I/O

G3

I/O

6 8

v4 .0

3 2 9 -P in P B G A ( C o n t in u e d )

A54SX32A

Pin Number Function

A54SX32A

Pin Number Function

A54SX32A

Pin Number Function

A54SX32A

Pin Number Function

G4

G20

G21

G22

G23

H1

I/O

L20

L21

L22

L23

M1

NC

I/O

R1

R2

I/O

V_CCA

I/O

V_CCA

I/O

V_CCI

I/O

NC

I/O

Y4

Y5

GND

I/O

R3

Y6

I/O

NC

R4

Y7

I/O

GND

I/O

R20

R21

R22

R23

T1

Y8

I/O

M2

I/O

Y9

I/O

H2

I/O

M3

I/O

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

I/O

H3

I/O

M4

V_CCA

GND

V_CCA

I/O

H4

I/O

M10

M11

M12

M13

M14

M20

M21

M22

M23

N1

V_CCA

NC

I/O

H20

H21

H22

H23

J1

V_CCA

I/O

T2

T3

I/O

T4

I/O

T20

T21

T22

T23

U1

I/O

NC

I/O

J2

I/O

J3

I/O

J4

I/O

V_CCI

I/O

GND

I/O

J20

J21

J22

J23

K1

I/O

U2

I/O

N2

TRST, I/O

I/O

U3

I/O

N3

U4

I/O

N4

I/O

U20

U21

U22

U23

V1

I/O

N10

N11

N12

N13

N14

N20

N21

N22

N23

P1

GND

NC

K2

I/O

K3

I/O

K4

I/O

K10

K11

K12

K13

K14

K20

K21

K22

K23

L1

GND

I/O

V2

V3

I/O

V4

I/O

V20

V21

V22

V23

W1

W2

W3

W4

W20

W21

W22

W23

Y1

I/O

P2

I/O

P3

I/O

P4

I/O

P10

P11

P12

P13

P14

P20

P21

P22

P23

GND

I/O

L2

I/O

L3

I/O

L4

NC

L10

L11

L12

L13

L14

GND

I/O

Y2

I/O

Y3

v4 .0

6 9

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

1 4 4 -P in F B G A (To p Vie w )

4

1

2

3

5

6

7

8

10 11 12

9

A

B

C

D

E

F

G

H

J

K

L

M

7 0

v4 .0

1 4 4 -P in F B G A

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

A1

A2

I/O

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

E1

TDI, I/O

I/O

TDI, I/O

I/O

TDI, I/O

I/O

A3

I/O

A4

I/O

A5

V_CCA

GND

CLKA

I/O

V_CCA

GND

CLKA

I/O

V_CCA

GND

CLKA

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

A11

A12

B1

I/O

E2

I/O

E3

I/O

B2

GND

I/O

GND

I/O

GND

I/O

E4

I/O

B3

E5

TMS

V_CCI

V_CCA

I/O

TMS

V_CCI

V_CCA

I/O

TMS

V_CCI

V_CCA

I/O

B4

I/O

E6

B5

I/O

E7

B6

I/O

E8

B7

CLKB

I/O

CLKB

I/O

CLKB

I/O

E9

B8

E10

E11

E12

F1

B9

I/O

GND

I/O

GND

I/O

GND

I/O

B10

B11

B12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

D1

D2

I/O

GND

I/O

GND

I/O

GND

I/O

F2

I/O

F3

NC

I/O

F4

I/O

TCK, I/O

I/O

TCK, I/O

I/O

TCK, I/O

I/O

F5

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

F6

I/O

F7

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

F8

F9

I/O

F10

F11

F12

G1

G2

G3

G4

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

v4 .0

7 1

1 4 4 -P in F B G A ( C o n t i n u e d )

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

G5

G6

G7

G8

G9

G10

G11

G12

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

J1

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

K3

K4

I/O

K5

I/O

K6

I/O

K7

GND

I/O

GND

I/O

GND

I/O

K8

I/O

K9

I/O

K10

K11

K12

L1

GND

I/O

GND

I/O

GND

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

L2

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

L3

I/O

L4

I/O

L5

I/O

L6

I/O

L7

HCLK

I/O

HCLK

I/O

HCLK

I/O

L8

I/O

L9

I/O

NC

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

I/O

J2

I/O

J3

I/O

J4

I/O

J5

I/O

J6

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

J7

I/O

J8

I/O

J9

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

J10

J11

J12

K1

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

K2

I/O

7 2

v4 .0

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

2 5 6 -P in F B G A (To p Vie w )

1

2

3

4

6

7

8

9 10 11 12

13 14

5

15 16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

v4 .0

7 3

2 5 6 -P in F B G A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

A1

A2

GND

TCK, I/O

I/O

GND

TCK, I/O

I/O

GND

TCK, I/O

I/O

C14

C15

C16

D1

I/O

A3

I/O

A4

I/O

A5

I/O

D2

I/O

A6

I/O

D3

I/O

A7

I/O

D4

I/O

A8

I/O

D5

I/O

A9

CLKB

I/O

CLKB

I/O

CLKB

I/O

D6

I/O

A10

A11

A12

A13

A14

A15

A16

B1

D7

I/O

D8

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

QCLKD

I/O

NC

I/O

D9

I/O

D10

D11

D12

D13

D14

D15

D16

E1

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

B2

GND

I/O

GND

I/O

GND

I/O

B3

I/O

B4

I/O

B5

I/O

E2

I/O

B6

NC

I/O

E3

I/O

B7

I/O

E4

I/O

B8

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

E5

I/O

B9

E6

I/O

B10

B11

B12

B13

B14

B15

B16

C1

I/O

E7

I/O

QCLKC

I/O

NC

I/O

E8

I/O

E9

I/O

E10

E11

E12

E13

E14

E15

E16

F1

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

C2

TDI, I/O

GND

I/O

TDI, I/O

GND

I/O

TDI, I/O

GND

I/O

C3

I/O

C4

I/O

C5

NC

I/O

F2

I/O

C6

I/O

F3

I/O

C7

I/O

F4

TMS

I/O

TMS

I/O

TMS

I/O

C8

I/O

F5

C9

CLKA

I/O

CLKA

I/O

CLKA

I/O

F6

I/O

C10

C11

C12

C13

F7

V_CCI

I/O

F8

I/O

F9

I/O

F10

7 4

v4 .0

2 5 6 -P in F B G A ( C o n t i n u e d )

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

F11

F12

F13

F14

F15

F16

G1

I/O

VCCA

I/O

VCCA

I/O

VCCA

I/O

J8

J9

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

J10

J11

J12

J13

J14

J15

J16

K1

I/O

NC

I/O

G2

I/O

G3

NC

I/O

G4

I/O

G5

I/O

K2

I/O

G6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

K3

NC

I/O

G7

K4

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

G8

K5

G9

K6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

G10

G11

G12

G13

G14

G15

G16

H1

K7

K8

K9

GND

NC

GND

I/O

GND

I/O

K10

K11

K12

K13

K14

K15

K16

L1

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

H2

I/O

NC

I/O

H3

V_CCA

TRST, I/O

I/O

V_CCA

TRST, I/O

I/O

V_CCA

TRST, I/O

I/O

H4

I/O

H5

L2

I/O

H6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

L3

I/O

H7

L4

I/O

H8

L5

I/O

H9

L6

I/O

H10

H11

H12

H13

H14

H15

H16

J1

L7

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

L8

L9

I/O

L10

L11

L12

L13

L14

L15

L16

M1

M2

M3

M4

I/O

NC

I/O

NC

I/O

J2

NC

I/O

J3

NC

I/O

NC

I/O

J4

I/O

J5

I/O

J6

V_CCI

GND

V_CCI

GND

V_CCI

GND

I/O

J7

I/O

v4 .0

7 5

2 5 6 -P in F B G A ( C o n t i n u e d )

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

N1

I/O

PRB, I/O

I/O

GND

I/O

P11

P12

P13

P14

P15

P16

R1

I/O

QCLKA

PRB, I/O

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

PRB, I/O

I/O

NC

I/O

R2

GND

I/O

GND

I/O

GND

I/O

R3

NC

I/O

R4

NC

I/O

R5

I/O

R6

I/O

R7

I/O

N2

I/O

R8

I/O

N3

I/O

R9

HCLK

I/O

HCLK

I/O

HCLK

QCLKB

I/O

N4

I/O

R10

R11

R12

R13

R14

R15

R16

T1

N5

I/O

N6

I/O

N7

I/O

N8

I/O

N9

I/O

GND

I/O

GND

I/O

GND

I/O

N10

N11

N12

N13

N14

N15

N16

P1

I/O

T2

I/O

T3

I/O

T4

NC

I/O

T5

I/O

T6

I/O

T7

I/O

P2

GND

I/O

GND

I/O

T8

I/O

P3

T9

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

P4

I/O

T10

T11

T12

T13

T14

T15

T16

P5

NC

I/O

P6

I/O

NC

I/O

P7

I/O

P8

I/O

P9

I/O

TDO, I/O

GND

TDO, I/O

GND

TDO, I/O

GND

P10

NC

I/O

7 6

v4 .0

P a c k a g e P i n A s s i g n m e n t s (C o n t in u e d )

4 8 4 -P in F B G A ( T o p V ie w )

1

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

2

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

v4 .0

7 7

4 8 4 -P in F B G A

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Function

A1

A2

NC*

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

I/O

NC

V_CCI

I/O

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

I/O

PRB, I/O

V_CCA

I/O

PRB, I/O

V_CCA

I/O

AD5

AD6

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

A3

AD7

I/O

A4

AD8

I/O

A5

I/O

AD9

V_CCI

I/O

A6

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

A7

I/O

A8

I/O

A9

I/O

V_CCI

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

AA1

AA2

AA3

AA4

AA5

AA22

AA23

AA24

AA25

AA26

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

I/O

TDO, I/O

GND

NC*

I/O

TDO, I/O

GND

I/O

NC*

I/O

V_CCI

I/O

NC*

I/O

NC*

I/O

AC2

I/O

AC3

I/O

V_CCI

NC*

I/O

AC4

NC*

V_CCI

I/O

NC*

V_CCA

I/O

AC5

V_CCI

I/O

AC6

AC7

V_CCI

I/O

V_CCI

I/O

AC8

AE2

AC9

I/O

AE3

NC*

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

I/O

AE4

I/O

AE5

I/O

QCLKA

I/O

AE6

I/O

AE7

I/O

AE8

I/O

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

I/O

NC*

I/O

NC*

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC*

I/O

NC*

I/O

NC*

I/O

NC*

I/O

NC*

I/O

AD2

I/O

AD3

GND

I/O

GND

I/O

AD4

Note: *These pins must be left floating on the A54SX32A device.

7 8

v4 .0

4 8 4 -P in F B G A ( C o n t i n u e d )

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Function

AE25

AE26

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

B1

NC*

NC

I/O

B19

B20

B21

B22

B23

B24

B25

B26

C1

I/O

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

I/O

NC*

I/O

NC*

I/O

NC*

I/O

NC

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

C2

I/O

C3

I/O

C4

I/O

NC*

HCLK

I/O

C5

I/O

NC*

I/O

NC

HCLK

QCLKB

I/O

C6

V_CCI

I/O

V_CCI

I/O

C7

I/O

C8

I/O

E2

I/O

NC*

I/O

C9

V_CCI

I/O

V_CCI

I/O

E3

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

E4

I/O

E5

GND

TDI, IO

I/O

GND

TDI, IO

I/O

E6

I/O

PRA, I/O

I/O

PRA, I/O

I/O

E7

NC*

I/O

E8

I/O

QCLKD

I/O

E9

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

I/O

NC

I/O

V_CCA

CLKB

I/O

V_CCA

CLKB

I/O

V_CCI

I/O

V_CCI

I/O

B2

I/O

B3

I/O

B4

I/O

B5

I/O

NC*

TMS

I/O

B6

I/O

B7

I/O

B8

I/O

D2

TMS

I/O

B9

I/O

D3

I/O

B10

B11

I/O

D4

V_CCI

NC*

TCK, I/O

I/O

V_CCI

I/O

NC*

V_CCI

CLKA

NC*

I/O

D5

V_CCI

GND

V_CCI

NC*

I/O

V_CCI

GND

V_CCI

I/O

B12

B13

B14

B15

B16

B17

B18

I/O

D6

TCK, I/O

I/O

V_CCI

CLKA

I/O

D7

D8

I/O

F2

D9

I/O

F3

I/O

D10

D11

D12

I/O

F4

I/O

F5

I/O

V_CCI

I/O

QCLKC

F22

I/O

Note: *These pins must be left floating on the A54SX32A device.

v4 .0

7 9

4 8 4 -P in F B G A ( C o n t i n u e d )

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Function

F23

F24

F25

F26

G1

I/O

K17

K22

K23

K24

K25

K26

L1

GND

I/O

GND

I/O

N5

N10

N11

N12

N13

N14

N15

N16

N17

N22

N23

N24

N25

N26

P1

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

NC*

I/O

NC*

I/O

NC

I/O

G2

I/O

G3

I/O

G4

I/O

L2

I/O

G5

I/O

L3

I/O

G22

G23

G24

G25

G26

H1

I/O

L4

I/O

V_CCA

I/O

V_CCA

I/O

L5

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L22

L23

L24

L25

L26

M1

GND

I/O

GND

I/O

NC*

I/O

NC*

I/O

NC

I/O

H2

I/O

P2

I/O

H3

I/O

P3

I/O

H4

I/O

P4

I/O

H5

I/O

P5

V_CCA

GND

I/O

V_CCA

GND

I/O

H22

H23

H24

H25

H26

J1

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P22

P23

P24

P25

P26

R1

I/O

NC*

I/O

NC*

I/O

NC

J2

I/O

M2

I/O

J3

I/O

M3

I/O

J4

I/O

M4

I/O

J5

I/O

M5

I/O

J22

J23

J24

J25

J26

K1

I/O

M10

M11

M12

M13

M14

M15

M16

M17

M22

M23

M24

M25

M26

N1

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

NC*

I/O

V_CCI

I/O

NC*

I/O

R2

NC*

I/O

R3

I/O

K2

V_CCI

I/O

V_CCI

I/O

R4

I/O

K3

R5

TRST, I/O

GND

I/O

TRST, I/O

GND

I/O

K4

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R22

K5

V_CCA

GND

V_CCA

GND

I/O

K10

K11

K12

K13

K14

K15

K16

I/O

NC*

I/O

N2

V_CCI

I/O

V_CCI

I/O

N3

N4

I/O

Note: *These pins must be left floating on the A54SX32A device.

8 0

v4 .0

4 8 4 -P in F B G A ( C o n t i n u e d )

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Number

A54SX32A A54SX72A

Function

R23

R24

R25

R26

T1

I/O

U3

U4

I/O

V25

V26

W1

NC*

I/O

V_CCA

I/O

V_CCI

I/O

NC*

I/O

U5

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U22

U23

U24

U25

U26

V1

GND

I/O

GND

I/O

W2

I/O

W3

I/O

T2

I/O

W4

I/O

T3

I/O

W5

I/O

T4

I/O

W22

W23

W24

W25

W26

Y1

I/O

T5

I/O

V_CCA

I/O

T10

T11

T12

T13

T14

T15

T16

T17

T22

T23

T24

T25

T26

U1

GND

I/O

GND

I/O

NC*

I/O

Y2

V_CCI

I/O

V_CCI

I/O

Y3

Y4

I/O

NC*

I/O

Y5

NC*

I/O

V2

I/O

Y22

Y23

Y24

Y25

Y26

I/O

V3

I/O

V4

I/O

V_CCI

I/O

NC*

I/O

V5

I/O

V22

V23

V24

V_CCA

I/O

V_CCA

I/O

U2

V_CCI

I/O

Note: *These pins must be left floating on the A54SX32A device.

v4 .0

8 1

L i s t o f C h a n g e s

The following table lists critical changes that were made in the current version of the document.

Previous version Changes in current version (v3.0)

Page

The “SX-A Product Profile” table on page 1 was updated.

The “Ordering Information” section on page 2 was updated.

The “Product Plan” section on page 3 was updated.

Figure 1 on page 4 was updated.

page 1

page 2

page 3

page 4

page 6

page 8

page 9

page 10

page 11

The ““Clock Resources” section on page 6“ was updated

The “SX-A Clock Resources” table on page 8 is new.

The “User Security” section on page 9 is new.

The “I/O Modules” section on page 9 was updated.

The “I/O Features” table on page 10 was updated.

The “I/O Characteristics for All I/O Configurations” table on page 10 is new.

The “Power-up Time at which I/Os Become Active” table on page 10 is new

Figure 10 on page 11 is new.

The “Boundary-Scan Pin Configurations and Functions” table on page 11 is new.

v4.0

The “Device Configuration Options for Probe Capability (TRST pin reserved)” table

page 12

on page 12 is new.

The “SX-A Probe Circuit Control Pins” section on page 12 was updated.

The “Design Considerations” section on page 12 was updated.

Figure 11 on page 12 was updated.

page 12

page 13

page 14

The “Development Tool Support” section on page 13 was updated.

Figure 12 on page 13 is new.

The “Absolute Maximum Ratings1” table on page 14 was updated.

The “Recommended Operating Conditions” table on page 14 was updated.

The “3.3V LVTTL and 5V TTL Electrical Specifications” table on page 14 was

updated.

page 14

The “2.5V LVCMOS2 Electrical Specifications” table on page 15 was updated.

The SX-A Timing Model* and Sample Path Calculations equations were updated.

The “Pin Description” section on page 53 was updated.

page 15

page 22

page 53

page 10

The section, “Development Tool Support” section on page 13 has been updated.

The section, “I/O Modules” section on page 9, and the table, I/O Features, Table 2 on

page 10 have been updated.

page 9

v2.0.1

The “SX-A Timing Model*” section on page 22 and several timing tables on pages

22-49 have new timing numbers.

pages 19,

22-49

D a t a S h e e t C a t e g o r i e s

In order to provide the latest information to designers, some data sheets are published before data has been fully

characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories

are as follows:

A d v a n c e d

The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This

information can be used as estimates, but not for production.

8 2

v4 .0

P r e l im i n a r y

The data sheet contains information based on simulation and/or initial characterization. The information is believed to be

correct, but changes are possible.

U n m a r k e d ( p r o d u c t io n )

The data sheet contains information that is considered to be final.

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

USA

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

39th Floor

One Pacific Place

88 Queensway

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: (408) 739-1010

Fax: (408) 739-1540

Tel: +44 (0)1276 401450

Fax: +44 (0)1276 401490

Tel: +81 03-3445-7671

Fax: +81 03-3445-7668

Admiralty, Hong Kong

Tel: 852-22735712

5172147-6/4.03


型号：	A54SX32A-1BG329A
厂家：	Microsemi
描述：	Field Programmable Gate Array, 2880-Cell, CMOS, PBGA329, 栅
文件：	总83页 (文件大小：2107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A54SX32A-1BG329A [MICROSEMI]

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