AGLE3000V2-FGG484C [MICROSEMI]
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484;
| 型号： | AGLE3000V2-FGG484C |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484 栅 可编程逻辑 |
| 文件： | 总156页 (文件大小：5023K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v1.2
®
IGLOOe Low-Power Flash FPGAs
with Flash*Freeze Technology
Pro (Professional) I/O
Features and Benefits
• 700 Mbps DDR, LVDS-Capable I/Os
Low Power
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-
Power Flash*Freeze Mode
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
• I/O Registers on Input, Output, and Enable Paths
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
®
• Pin-Compatible Packages across the IGLOO e Family
• Retains Programmed Design when Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
®
to Secure FPGA Contents
H•ighFla-PsheLrofcokrmance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
A•RMTruPerDoucael-sPsoortrSSRAuMpp(eoxrctepitn×I1G8)LOOe FPGAs
• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available
with or without Debug
IGLOOe Product Family
IGLOOe Devices
AGLE600
AGLE3000
ARM-Enabled IGLOOe Devices
System Gates
M1AGLE3000
600 k
13,824
49
3 M
75,264
137
504
112
1 k
VersaTiles (D-flip-flops)
Quiescent Current (typical) in Flash*Freeze Mode (µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
108
24
FlashROM Bits
1 k
Yes
6
Secure (AES) ISP
Yes
6
CCCs with Integrated PLLs
1
VersaNet Globals
18
18
I/O Banks
8
8
Maximum User I/Os
270
620
Package Pins
FBGA
FG256, FG484
FG484, FG896
Notes:
1. Refer to the Cortex-M1 Handbook for more information.
2. Six chip (main) and twelve quadrant global networks are available.
3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook.
October 2008
I
© 2008 Actel Corporation
1
I/Os Per Package
IGLOOe Devices
AGLE600
AGLE3000
ARM-Enabled IGLOOe Devices
M1AGLE3000
I/O Types
Single-Ended
I/O1
Differential
I/O Pairs
Single-Ended
Differential
I/O Pairs
Package
FG256
FG484
FG896
Notes:
I/O1
–
165
270
–
79
135
–
–
341
620
168
310
1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe Low-Power Flash
FPGAs with Flash*Freeze Technology handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os). When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular
I/O, the number of single-ended user I/Os available is reduced by one.
6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
7. "G" indicates RoHS-compliant packages. Refer to "IGLOOe Ordering Information" on page III for the location of the
"G" in the part number.
IGLOOe FPGAs Package Sizes Dimensions
Package
FG256
17 × 17
289
FG484
23 × 23
529
FG896
31 × 31
961
Length × Width (mm × mm)
Nominal Area (mm2)
Pitch (mm)
1
1
1
Height (mm)
1.6
2.23
2.23
II
v1.2
IGLOOe Low-Power Flash FPGAs
IGLOOe Ordering Information
_
AGLE3000
FG
896
I
V2
G
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant Packaging
Package Type
=
FG
Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOOe Devices
AGLE600 = 600,000 System Gates
AGLE3000 = 3,000,000 System Gates
IGLOOe Devices with Cortex-M1
M1AGLE3000 =
3,000,000 System Gates
Notes:
1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics
provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be
added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
v1.2
III
Temperature Grade Offerings
AGLE600
AGLE3000
Package
FG256
FG484
FG896
M1AGLPE3000
C, I
C, I
–
–
C, I
C, I
Note: C = Commercial temperature range: 0°C to 70°C ambient temperature.
I = Industrial temperature range: –40°C to 85°C ambient temperature.
Speed Grade and Temperature Grade Matrix
Temperature Grade
–F 1
Std.
✓
C 2
✓
3
I
–
✓
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.
IV
v1.2
1 – IGLOOe Device Family Overview
General Description
The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA,
a single-chip solution, small footprint packages, reprogrammability, and an abundance of
advanced features.
The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low-
power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power
management through I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the
IGLOOe device is completely functional in the system. This allows the IGLOOe device to control
system power management based on external inputs (e.g., scanning for keyboard stimulus) while
consuming minimal power.
Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power,
single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have
up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620
user I/Os.
M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM
for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA
fabric. It has a three-stage pipeline that offers a good balance between low-power consumption
and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M
instruction set, has a configurable nested interrupt controller, and can be implemented with or
without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not
support AES decryption.
Flash*Freeze Technology
The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn
off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction
in power consumption, thus achieving the lowest total system power.
When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and
data is retained.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe
devices the best fit for portable electronics.
v1.2
1-1
IGLOOe Device Family Overview
Flash Advantages
Low Power
Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
IGLOOe devices also have low dynamic power consumption to further maximize power savings;
power is even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOOe device the lowest total system power offered by any FPGA.
Security
The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead,
advantages that only an FPGA with nonvolatile flash programming can offer.
IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in IGLOOe devices can
be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. AES was adopted by the National Institute of Standards and Technology
(NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a built-in AES decryption
engine and a flash-based AES key that make them the most comprehensive programmable logic
device security solution available today. IGLOOe devices with AES-based security allow for secure,
remote field updates over public networks such as the Internet, and ensure that valuable IP
remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a
programmed IGLOOe device cannot be read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been
used to make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES
security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable
IP is protected and secure, making remote ISP possible. An IGLOOe device provides the most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
IGLOOe FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
The Actel flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system
design and reduces total system cost, often eliminating the need for CPLDs and clock generation
PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOOe device's
flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB
design. Flash-based IGLOOe devices simplify total system design and reduce cost and design risk
while increasing system reliability and improving system initialization time.
1-2
v1.2
IGLOOe Low-Power Flash FPGAs
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device
architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe
family a cost-effective ASIC replacement solution, especially for applications in the consumer,
networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-
based FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot
be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error
detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through
an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS
design techniques are used to implement logic and control functions. The combination of fine
granularity, enhanced flexible routing resources, and abundant flash switches allows for very high
logic utilization without compromising device routability or performance. Logic functions within
the device are interconnected through a four-level routing hierarchy.
IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The
IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on
page 4):
•
•
•
•
•
•
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup
table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.
The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture
flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
v1.2
1-3
IGLOOe Device Family Overview
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of IGLOOe devices via an IEEE 1532 JTAG interface.
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Pro I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Figure 1-1 • IGLOOe Device Architecture Overview
Flash*Freeze Technology
The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating
the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and
global I/Os can still be driven and can be toggling without impact on power consumption, clocks
can still be driven or can be toggling without impact on power consumption, and the device retains
all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode
or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No
power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the
power management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to
decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a
regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the
1-4
v1.2
IGLOOe Low-Power Flash FPGAs
inherent low power static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an
illustration of entering/exiting Flash*Freeze mode.
Actel IGLOOe
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-2 • IGLOOe Flash*Freeze Mode
VersaTiles
The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The IGLOOe VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
User Nonvolatile FlashROM
Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for
a user design.
v1.2
1-5
IGLOOe Device Family Overview
The FlashROM can be programmed via the JTAG programming interface, and its contents can be
read back either through the JTAG programming interface or via direct FPGA core addressing. Note
that the FlashROM can only be programmed from the JTAG interface and cannot be programmed
from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-
byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8
banks and which of the 16 bytes within that bank are being read. The three most significant bits
(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of
the FlashROM address define the byte.
The Actel IGLOOe development software solutions, Libero® Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part.
Another feature allows the inclusion of static data for system version control. Data for the
FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.
Comprehensive programming file support is also included to allow for easy programming of large
numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit
port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the
SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The
FIFO width and depth are programmable. The FIFO also features programmable Almost Empty
(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters necessary for generation of the read and write
address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member
of the IGLOOe family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One
CCC (center west side) has a PLL.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration.
•
•
Output duty cycle = 50% 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used
•
•
•
Maximum acquisition time is 300 µs
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC
1-6
v1.2
IGLOOe Low-Power Flash FPGAs
Global Clocking
IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
Pro I/Os with Advanced I/O Standards
The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including single-
ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks
per device (two per side). The configuration of these banks determines the I/O standards
supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced
I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.
Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that
minibank will be able to use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
IGLOOe banks support M-LVDS with 20 multi-drop points.
v1.2
1-7
IGLOOe Device Family Overview
Part Number and Revision Date
Part Number 51700096-001-3
Revised October 2008
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
Changes in Current Version (v1.2)
Page
v1.1
(June 2008)
The Quiescent Current values in the "IGLOOe Product Family" table were
updated.
I
v1.0
(April 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of
core voltage support. The document was updated to change 1.2 V / 1.5 V to
1.2 V to 1.5 V.
N/A
N/A
51700096-001-1
(March 2008)
This document was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The
second section is a device family overview.
51700096-001-0
(January 2008)
The "Low Power" section was updated to change "1.2 V and 1.5 V Core
Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 µW)"
was removed from "Low-Power Active FPGA Operation."
I
1.2_V was added to the list of core and I/O voltages in the "Pro (Professional)
I/O" and "Pro I/Os with Advanced I/O Standards" sections.
I, 1-7
N/A
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers.
The new version number is 51700096-001-0.
Advance v0.3
(September 2007)
Table 1 • IGLOOe Product Family was updated to change the maximum
number of user I/Os for AGLE3000.
i
Table 2 • IGLOOe FPGAs Package Sizes Dimensions is new. Package
dimensions were removed from the "I/Os Per Package1" table. The number
of I/Os was updated for FG896.
ii
A note regarding marking information was added to "IGLOOe Ordering
Information".
iii
Advance v0.2
(July 2007)
Cortex-M1 device information was added to Cortex-M1 device information i, ii, iii, iv
was added to Table 1 • IGLOOe Product Family, the "I/Os Per Package1"
table, "IGLOOe Ordering Information", and Temperature Grade Offerings.
Advance v0.1
The words "ambient temperature" were added to the temperature range in
the "IGLOOe Ordering Information", "Temperature Grade Offerings", and
"Speed Grade and Temperature Grade Matrix" sections.
iii, iv
1-8
v1.2
IGLOOe Low-Power Flash FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data
has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"
"Preliminary," and "Production." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains
general product information. This document gives an overview of specific device and family
information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or
speed grades. This information can be used as estimates, but not for production. This label only
applies to the DC and Switching Characteristics chapter of the datasheet and will only be used
when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The
information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations
(EAR). They could require an approved export license prior to export from the United States. An
export includes release of product or disclosure of technology to a foreign national inside or
outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
v1.2
1-9
2 – IGLOOe DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this
document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or
any other conditions beyond those listed under the Recommended Operating Conditions specified
in Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
V
V
V
V
V
VJTAG
VPUMP Programming voltage
VCCPLL Analog power supply (PLL)
VCCI
DC I/O buffer supply voltage
I/O input voltage
and
VMV 3
VI
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
V
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+125
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input
signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for
recommended operating limits, refer to Table 2-2 on page 2-2.
3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.
Advance v0.3
2-1
IGLOOe DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 4
Symbol
TA
Parameter
Commercial
0 to +70 6
0 to + 85
Industrial
Units
7
Ambient Temperature
Junction Temperature 8
–40 to +85
°C
TJ
–40 to +100
VCC
1.5
V
DC core supply
1.425 to 1.575 1.425 to 1.575
V
V
voltage1
1.2 V–1.5 V wide range core
voltage2
1.14 to 1.575
1.14 to 1.575
VJTAG
JTAG DC voltage
1.4 to 3.6
3.15 to 3.45
0 to 3.45
1.4 to 3.6
3.15 to 3.45
0 to 3.45
V
V
V
V
V
5
VPUMP
Programming voltage
Programming Mode
Operation3
Analog power supply (PLL) 1.5 V DC core supply voltage1
1.4 to 1.6
1.4 to 1.6
9
VCCPLL
1.2 V–1.5 V wide range core 1.14 to 1.575
voltage2
1.14 to 1.575
V
CCI and 1.2 V DC supply voltage2
1.14 to 1.26
1.14 to 1.26
V
VMV 10
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
LVDS differential I/O
1.425 to 1.575 1.425 to 1.575
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
V
V
V
V
V
2.375 to 2.625 2.375 to 2.625
3.0 to 3.6 3.0 to 3.6
LVPECL differential I/O
Notes:
1. For IGLOOe V5 devices
2. For IGLOOe V2 devices only, operating at VCCI ≥ VCC
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each
I/O standard are given in Table 2-20 on page 2-20. VCCI should be at the same voltage within a given I/O
bank.
4. All parameters representing voltages are measured with respect to GND unless otherwise specified.
5. VPUMP can be left floating during operation (not programming mode).
6. Maximum TJ = 85 °C.
7. Maximum TJ = 100 °C.
8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel
recommends that the user follow best design practices using Actel’s timing and power simulation tools.
9. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.
10. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1
Programming Program Retention
Maximum Storage
Maximum Operating Junction
Temperature TJ (°C) 2
Product Grade
Commercial
Industrial
Cycles
(biased/unbiased) Temperature TSTG (°C) 2
500
20 years
20 years
110
110
100
100
500
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device
operating conditions and absolute limits.
2-2
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or Undershoot Duration
as a Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot2
VCCI
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at junction temperature at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two
cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
3. The device meets overshoot/undershoot specification requirements for PCI inputs with VCCI = 3.45 V at 85°C
maximum, whereas the average toggling of inputs at one-sixth of PCI frequency is considered.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOOe device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.
There are five regions to consider during power-up.
IGLOOe I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and
Figure 2-2 on page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Advance v0.3
2-3
IGLOOe DC and Switching Characteristics
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper
powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed
brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1
and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information
on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
V
a = 0.85 V 0.25 V
Deactivation trip point:
d = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
V
VCCI
Activation trip point:
Min VCCI datasheet specification
Va = 0.9 V 0.3 V
Deactivation trip point:
Vd = 0.8 V 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
Figure 2-1 • V5 – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Advance v0.3
IGLOOe DC and Switching Characteristics
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
V
CC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
Va = 0.85 V 0.2 V
Deactivation trip point:
Region 1: I/O buffers are OFF
Vd = 0.75 V 0.2 V
VCCI
Activation trip point:
Va = 0.9 V 0.15 V
Deactivation trip point:
Vd = 0.8 V 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in Actel Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power
consumption cause the chip junction to be higher than the ambient temperature.
EQ 2-1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
EQ 2-1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.
P = Power dissipation
Advance v0.3
2-5
IGLOOe DC and Switching Characteristics
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal
resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute
maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute
maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and
in still air.
Max. junction temp. (°C) – Max. ambient temp. (°C)
100°C – 70°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 2. 20 6 W
θja(°C/W) 13.6°C/W
EQ 2-2
Table 2-5 • Package Thermal Resistivities
θja
200 ft./min.
22.5
Package Type
Pin Count
θjc
8.0
3.8
Still Air
26.1
500 ft./min.
Units
C/W
C/W
Plastic Quad Flat Package (PQFP)
208
208
20.8
11.9
Plastic Quad Flat Package (PQFP) with
embedded heat spreader
16.2
13.3
Fine Pitch Ball Grid Array (FBGA)
256
484
676
896
3.8
3.2
3.2
2.4
26.9
20.5
16.4
13.6
22.8
17.0
13.0
10.4
21.5
15.9
12.0
9.4
C/W
C/W
C/W
C/W
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C,VCC = 1.425 V)
For IGLOOe V2 or V5 devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.425
1.5
–40°C
0.95
0.88
0.82
0°C
0.96
0.89
0.84
25°C
0.98
0.91
0.85
70°C
1.00
0.93
0.87
85°C
1.01
0.93
0.88
110°C
1.02
0.94
0.89
1.575
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.14 V)
For IGLOOe V2, 1.2 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.14
1.2
–40°C
0.97
0.84
0.76
0°C
0.98
0.85
0.77
25°C
0.99
0.86
0.78
70°C
1.00
0.87
0.79
85°C
1.01
0.88
0.79
110°C
1.01
0.88
0.80
1.26
2-6
Advance v0.3
IGLOOe DC and Switching Characteristics
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating
voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power
modes usage. Actel recommends using the PowerCalculator and SmartPower software
estimation tools to evaluate the projected static and active power based on the user design,
power mode usage, operating voltage, and temperature.
Table 2-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode*
Core Voltage
1.2 V
AGLE600
AGLE3000
95
Units
µA
Typical (25°C)
34
72
1.5 V
310
µA
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6
and PDC7).
Table 2-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)*
Core Voltage
AGLE600
AGLE3000
Units
VCCI/VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V
1.7
1.7
µA
VCCI/VJTAG = 1.5 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.8
1.9
2.2
2.5
1.8
1.9
2.2
2.5
µA
µA
µA
µA
VCCI/VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI/VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI/VJTAG= 3.3 V (per bank)
Typical (25°C)
* IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).
Table 2-10 • Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)*
Core Voltage
AGLE600
AGLE3000
Units
Typical (25°C)
1.2 V / 1.5 V
0
0
µA
* IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6
and PDC7).
Advance v0.3
2-7
IGLOOe DC and Switching Characteristics
Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode*
Core Voltage
AGLE600
AGLE3000
Units
ICCA Current2
Typical (25°C)
1.2 V
1.5 V
28
82
89
µA
µA
320
ICCI or IJTAG Current3, 4
VCCI/VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI/VJTAG = 1.5 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
VCCI/VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI/VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI/VJTAG= 3.3 V (per bank)
Typical (25°C)
Notes:
1. To calculate total device IDD, multiply the number of banks used in ICCI and add ICCA contribution.
2. Includes VCC, VCCPLL, and VPUMP currents.
3. Per VCCI or VJTAG bank
4. Values do not include I/O static contribution (PDC6 and PDC7).
2-8
Advance v0.3
IGLOOe DC and Switching Characteristics
Power per I/O Pin
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VCCI
(V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
2.5 V LVCMOS
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
3.3
3.3
3.3
3.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16.34
24.49
4.71
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
6.13
1.66
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.2 V LVCMOS 3
1.2 V LVCMOS – Schmitt trigger 3
3.3 V PCI
1.78
1.01
0.97
0.60
0.53
17.76
19.10
17.76
19.10
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
2.90
2.13
2.81
2.57
0.17
0.17
1.38
1.38
3.21
3.21
7.07
3.62
2.97
2.55
0.85
0.85
3.30
3.30
8.08
8.08
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
2.5
3.3
2.26
5.71
0.95
1.62
LVPECL
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI
.
2. PAC9 is the total dynamic power measured on VCCI
3. Applicable for IGLOOe V2 devices only.
.
Advance v0.3
2-9
IGLOOe DC and Switching Characteristics
Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD
(pF)
VCCI
(V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS 4
3.3 V PCI
5
5
3.3
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
–
148.00
83.23
54.58
37.05
17.94
204.61
204.61
5
5
5
10
10
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
10
10
10
10
20
20
30
30
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
–
24.08
13.52
2.5 V GTL
–
3.3 V GTL+
2.5 V GTL+
HSTL (I)
–
24.10
–
13.54
7.08
13.88
16.69
25.91
26.02
42.21
26.22
27.22
HSTL (II)
SSTL2 (I)
105.56
116.60
114.87
131.76
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
–
–
2.5
3.3
7.70
89.62
LVPECL
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2. PDC7 is the static power (where applicable) measured on VCCI
.
3. PAC10 is the total dynamic power measured on VCCI
.
4. Applicable for IGLOOe V2 devices only.
2-10
Advance v0.3
IGLOOe DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-14 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device-Specific Dynamic
Contributions (µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLE600
19.7
AGLE3000
12.77
PAC2
Clock contribution of a Global Spine
4.16
1.85
PAC3
Clock contribution of a VersaTile row
0.88
0.11
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
PAC5
0.057
0.207
0.207
0.7
PAC6
PAC7
PAC8
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
See Table 2-12 on page 2-9.
PAC10
PAC11
PAC12
PAC13
See Table 2-13 on page 2-10.
25.00
30.00
2.70
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or
SmartPower in Actel Libero® Integrated Design Environment (IDE) software.
Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device Specific Static Power (mW)
Parameter
PDC1
Definition
AGLE600
AGLE3000
Array static power in Active mode
See Table 2-11 on page 2-8.
See Table 2-10 on page 2-7.
See Table 2-8 on page 2-7.
1.84
PDC2
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
PDC3
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
I/O input pin static power (standard-dependent)
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-8.
See Table 2-12 on page 2-9.
See Table 2-13 on page 2-10.
PDC6
PDC7
Advance v0.3
2-11
IGLOOe DC and Switching Characteristics
Table 2-16 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Device-Specific Dynamic
Contributions (µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLE600
12.61
AGLE3000
8.17
PAC2
Clock contribution of a Global Spine
2.66
1.18
PAC3
Clock contribution of a VersaTile row
0.56
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
0.071
0.045
0.186
0.109
0.449
PAC5
PAC6
PAC7
PAC8
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
See Table 2-8 on page 2-7.
PAC10
See Table 2-9 on page 2-7
and Table 2-10 on page 2-7.
PAC11
PAC12
PAC13
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic PLL contribution
25.00
30.00
2.10
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or
SmartPower in Actel Libero IDE software.
Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Device Specific Static Power (mW)
Parameter
PDC1
Definition
AGLE600
AGLE3000
Array static power in Active mode
See Table 2-11 on page 2-8.
See Table 2-10 on page 2-7.
See Table 2-8 on page 2-7.
0.90
PDC2
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
PDC3
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
I/O input pin static power (standard-dependent)
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-8.
See Table 2-12 on page 2-9.
See Table 2-13 on page 2-10.
PDC6
PDC7
2-12
Advance v0.3
IGLOOe DC and Switching Characteristics
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE
software.
The power calculation methodology described below uses the following variables:
•
The number of PLLs as well as the number and the frequency of each output clock
generated
•
•
•
•
•
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-18 on
page 2-15.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-19 on page 2-15.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-19 on page 2-15. The calculation should be repeated for each clock domain defined
in the design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7
NINPUTS is the number of I/O input buffers used in the design.
N
OUTPUTS is the number of I/O output buffers used in the design.
BANKS is the number of I/O banks powered in the design.
N
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided
in Table 2-18 on page 2-15.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-18 on page 2-15.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
F
N
P
Sequential Cells Contribution—P
S-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15.
FCLK is the global clock signal frequency.
Advance v0.3
2-13
IGLOOe DC and Switching Characteristics
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-15.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-19
on page 2-15.
F
WRITE-CLOCK is the memory write clock frequency.
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19
on page 2-15.
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 * FCLKOUT
FCLKOUT is the output clock frequency.1
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
2-14
Advance v0.3
IGLOOe DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.
If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.
Below are some examples:
•
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of
the clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled.
When nontristate output buffers are used, the enable rate should be 100%.
Table 2-18 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 2-19 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
β1
β2
β3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
Advance v0.3
2-15
IGLOOe DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL
tPD = 1.19 ns
tPD = 1.04 ns
t
DP = 1.75 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL/LVCMOS 3.3 V
Output drive strength = 12 mA
High slew rate
tDP = 3.13 ns
tPD = 1.77 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
LVTTL/LVCMOS 3.3 V
Output drive strength = 24 mA
High slew rate
tDP = 2.76 ns
tPY = 1.45 ns
tPD = 1.33 ns
LVPECL
D
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
tICLKQ = 0.43 ns
ISUD = 0.47 ns
t
DP = 3.30 ns
t
tPD = 0.85 ns
Input LVTTL/LVCMOS 3.3 V
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
Y
tPY = 1.10 ns
D
Q
D
Q
D
Q
GTL+ 3.3V
DP = 1.85 ns
I/O Module
(Non-Registered)
tPD = 0.90 ns
t
t
CLKQ = 0.90 ns
SUD = 0.82 ns
tCLKQ = 0.90 ns
SUD = 0.82 ns
t
t
OCLKQ = 1.02 ns
OSUD = 0.52 ns
LVDS,
BLVDS,
M-LVDS
t
t
Input LVTTL/LVCMOS 3.3 V
Clock
Input LVTTL/LVCMOS 3.3 V
Clock
tPY = 1.62 ns
tPY = 1.10 ns
tPY = 1.10 ns
Figure 2-3 • Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices
2-16
Advance v0.3
IGLOOe DC and Switching Characteristics
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
tPY
(R)
tPY
(F)
GND
tPYS
(F)
tPYS
(R)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
Advance v0.3
2-17
IGLOOe DC and Switching Characteristics
tDOUT
tDP
D Q
CLK
PAD
DOUT
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
tDOUT
(F)
VCC
(R)
50%
50%
VCC
D
0 V
50%
50%
0 V
DOUT
PAD
VOH
Vtrip
Vtrip
VOL
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
2-18
Advance v0.3
IGLOOe DC and Switching Characteristics
t
EOUT
D
Q
CLK
t , t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
t
CLK
D
= MAX(t
(r), t
(f))
V
I/O Interface
EOUT
EOUT
EOUT
V
CC
D
E
CC
50%
t
50%
t
EOUT (F)
EOUT (R)
V
CC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
V
HZ
CCI
90% V
CCI
V
V
trip
trip
V
10% V
OL
CCI
V
CC
D
E
V
CC
50%
50%
t
t
EOUT (F)
EOUT (R)
V
CC
50%
50%
EOUT
PAD
50%
t
ZHS
t
V
ZLS
OH
V
V
trip
trip
V
OL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
Advance v0.3
2-19
IGLOOe DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions
1
1
VIL
Strength Slew Rate Min., V Max., V
VIH
VOL
VOH
IOL IOH
Drive
I/O Standard
Min., V Max., V Max., V
Min., V mA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
1.7
12 12
12 12
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS4
3.3 V PCI
12 mA
12 mA
12 mA
2 mA
High
High
High
High
–0.3
0.7
1.7
2.7
1.9
0.7
–0.3 0.35 * VCCI 0.65*VCCI
0.45
VCCI – 0.45 12 12
–0.3 0.35 * VCCI 0.65*VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
Per PCI Specification
2
2
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
Per PCI-X Specification
25 mA2
25 mA2
35 mA
33 mA
8 mA
15 mA2
15 mA
18 mA
14 mA
21 mA
High
High
High
High
High
High
High
High
High
High
–0.3 VREF – 0.05 VREF + 0.05
3.6
0.4
0.4
–
25 25
25 25
35 35
33 33
–0.3 VREF – 0.05 VREF + 0.05 2.7
–
–0.3
V
REF – 0.1 VREF + 0.1
3.6
2.7
0.6
–
–
–0.3 VREF – 0.1 VREF + 0.1
0.6
–0.3 VREF – 0.1 VREF + 0.1 1.575
–0.3 VREF – 0.1 VREF + 0.1 1.575
0.4
0.4
0.54
0.35
0.7
0.5
VCCI – 0.4
8
8
HSTL (II)
VCCI – 0.4 15 15
VCCI – 0.62 15 15
VCCI – 0.43 18 18
VCCI – 1.1 14 14
VCCI – 0.9 21 21
SSTL2 (I)
–0.3 VREF – 0.2 VREF + 0.2
–0.3 VREF – 0.2 VREF + 0.2
2.7
2.7
3.6
3.6
SSTL2 (II)
SSTL3 (I)
–0.3
VREF – 0.2 VREF + 0.2
SSTL3 (II)
–0.3 VREF – 0.2 VREF + 0.2
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output drive strength is below JEDEC specification.
3. Output Slew Rates can be extracted from IBIS Models, located at
http://www.actel.com/download/ibis/default.aspx.
4. Applicable to V2 Devices ONLY, operating in the 1.2 V core range.
2-20
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL
IIH
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IIL
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
IIH
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS3
3.3 V PCI
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Commercial range (0°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
3. Applicable to V2 Devices ONLY, operating in the 1.2 V core range.
Advance v0.3
2-21
IGLOOe DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 • Summary of AC Measuring Points
Input Reference
Board Termination
Measuring Trip
Standard
Voltage (VREF_TYP
)
Voltage (VTT_REF
)
Point (Vtrip
)
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
–
–
1.4 V
–
–
–
1.2 V
–
–
0.90 V
0.75 V
0.6 V
–
–
–
–
–
0.285*VCCI (RR)
0.615*VCCI (FF))
0.285*VCCI (RR)
0.615*VCCI (FF)
VREF
–
–
3.3 V PCI-X
–
–
–
–
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
VREF
VREF
VREF
VREF
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
LVPECL
–
–
Table 2-23 • I/O AC Parameter Definitions
Parameter
Definition
Data to Pad delay through the Output Buffer
tDP
tPY
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
tDOUT
tEOUT
tDIN
tPYS
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
tZH
tLZ
tZL
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
2-22
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
I/O Standard
3.3 V LVTTL /
12 mA
High
5
–
0.98 2.18 0.19 1.10 1.37 0.67 2.22 1.72 2.78 3.17 5.85 5.35 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High
High
High
5
5
5
–
–
–
0.98 2.21 0.19 1.34 1.45 0.67 2.25 1.89 2.86 3.06 5.88 5.52 ns
0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11 5.70 ns
0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98 ns
Per PCI High 10 25 2 0.98 2.44 0.19 0.98 1.45 0.67 2.49 1.84 2.79 3.17 6.12 5.47 ns
spec
3.3 V PCI-X
Per PCI-X High 10 25 2 0.98 2.44 0.19 0.94 1.37 0.67 2.49 1.84 2.79 3.17 6.12 5.47 ns
spec
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA
25 mA
35 mA
33 mA
8 mA
High 10
High 10
High 10
High 10
High 20
High 20
High 30
High 30
High 30
High 30
25 0.98 1.83 0.19 2.41
25 0.98 1.90 0.19 2.04
25 0.98 1.85 0.19 1.35
25 0.98 1.97 0.19 1.29
50 0.98 2.74 0.19 1.77
25 0.98 2.62 0.19 1.77
50 0.98 1.91 0.19 1.15
25 0.98 1.94 0.19 1.15
50 0.98 2.05 0.19 1.09
25 0.98 1.86 0.19 1.09
–
–
–
–
–
–
–
–
–
–
–
0.67 1.84 1.83 0.00 0.00 5.47 5.46 ns
0.67 1.94 1.87 0.00 0.00 5.57 5.50 ns
0.67 1.88 1.81 0.00 0.00 5.51 5.44 ns
0.67 2.00 1.84 0.00 0.00 5.63 5.47 ns
0.67 2.79 2.73 0.00 0.00 6.42 6.36 ns
0.67 2.66 2.40 0.00 0.00 6.29 6.03 ns
0.67 1.94 1.72 0.00 0.00 5.57 5.35 ns
0.67 1.97 1.66 0.00 0.00 5.60 5.29 ns
0.67 2.09 1.71 0.00 0.00 5.72 5.34 ns
0.67 1.89 1.58 0.00 0.00 5.52 5.21 ns
HSTL (II)
15 mA
15 mA
18 mA
14 mA
21 mA
24 mA
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS/B-LVDS/
M-LVDS
High
–
–
0.98 1.77 0.19 1.62
–
–
–
–
–
–
–
ns
LVPECL
24 mA
High
–
–
0.98 1.75 0.19 1.45
–
–
–
–
–
–
–
–
ns
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on
page 2-42 for connectivity. This resistor is not required during normal operation.
Advance v0.3
2-23
IGLOOe DC and Switching Characteristics
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V
I/O Standard
3.3 V LVTTL /
12 mA High
5
–
1.55 2.46 0.26 1.31 1.57 1.10 2.51 2.04 3.27 3.96 8.32 7.85 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High
1.8 V LVCMOS 12 mA High
1.5 V LVCMOS 12 mA High
5
5
5
5
–
–
–
–
1.55 2.50 0.26 1.55 1.76 1.10 2.54 2.22 3.34 3.83 8.35 8.03 ns
1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21 ns
1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96 8.51 ns
1.55 4.07 0.26 2.06 2.96 1.10 3.90 3.43 3.80 4.02 9.49 9.03 ns
1.2 V LVCMOS
3.3 V PCI
2mA
High
Per PCI High 10 25 2 1.55 2.74 0.26 1.19 1.63 1.10 2.80 2.16 3.28 3.96 8.60 7.97 ns
spec
3.3 V PCI-X
Per PCI-X High 10 25 2 1.55 2.74 0.26 1.21 1.57 1.10 2.80 2.16 3.28 3.96 8.60 7.97 ns
spec
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA High 10
25 mA High 10
35 mA High 10
33 mA High 10
25 1.55 2.09 0.26 2.75
25 1.55 2.16 0.26 2.35
25 1.55 2.11 0.26 1.61
25 1.55 2.23 0.26 1.55
50 1.55 3.10 0.26 1.94
25 1.55 2.93 0.26 1.94
50 1.55 2.17 0.26 1.39
25 1.55 2.20 0.26 1.39
50 1.55 2.32 0.26 1.32
25 1.55 2.12 0.26 1.32
–
–
–
–
–
–
–
–
–
–
–
1.10 2.10 2.09
1.10 2.20 2.13
1.10 2.15 2.07
1.10 2.28 2.11
1.10 3.12 3.10
1.10 2.98 2.75
1.10 2.21 2.04
1.10 2.24 1.97
1.10 2.37 2.02
1.10 2.16 1.89
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7.91 7.89 ns
8.01 7.94 ns
7.95 7.88 ns
8.08 7.91 ns
8.93 8.91 ns
8.79 8.55 ns
8.02 7.84 ns
8.05 7.78 ns
8.17 7.83 ns
7.97 7.70 ns
8 mA
High 20
HSTL (II)
15 mA High 20
15 mA High 30
18 mA High 30
14 mA High 30
21 mA High 30
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS/B-LVDS/
M-LVDS
24 mA High
–
–
1.55 2.19 0.26 1.88
–
–
–
–
–
ns
LVPECL
24 mA High
–
–
1.55 2.16 0.26 1.70
–
–
–
–
–
–
–
–
ns
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on
page 2-42 for connectivity. This resistor is not required during normal operation.
2-24
Advance v0.3
IGLOOe DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-26 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min.
Max.
Units
pF
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
Table 2-27 • I/O Output Buffer Maximum Resistances1
Standard
Drive Strength
4 mA
R
PULL-DOWN (Ω)2
RPULL-UP (Ω)3
300
150
75
3.3 V LVTTL / 3.3 V LVCMOS
100
50
8 mA
12 mA
16 mA
24 mA
4 mA
25
17
50
11
33
2.5 V LVCMOS
1.8 V LVCMOS
100
50
200
100
50
8 mA
12 mA
16 mA
24 mA
2 mA
25
20
40
11
22
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
12 mA
16 mA
2 mA
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
2 mA
33
37
1.2 V LVCMOS
3.3 V PCI/PCI-X
TBD
25
TBD
75
Per PCI/PCI-X
specification
3.3 V GTL
2.5 V GTL
3.3 V GTL+
Notes:
25 mA
25 mA
35 mA
11
14
12
–
–
–
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design considerations
and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at
http://www.actel.com/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
Advance v0.3
2-25
IGLOOe DC and Switching Characteristics
Table 2-27 • I/O Output Buffer Maximum Resistances1 (continued)
Standard
2.5 V GTL+
HSTL (I)
Drive Strength
33 mA
R
PULL-DOWN (Ω)2
RPULL-UP (Ω)3
15
50
25
27
13
44
18
–
8 mA
50
25
31
15
69
32
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
15 mA
15 mA
18 mA
14 mA
21 mA
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design considerations
and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at
http://www.actel.com/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R((WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 k
11 k
18 k
19 k
TBD
Max.
45 k
55 k
70 k
90 k
TBD
Min.
Max.
45 k
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
Notes:
10 k
12 k
17 k
19 k
TBD
74 k
110 k
140 k
TBD
1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN
2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN
2-26
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-29 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSH (mA)*
IOSL (mA)*
27
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
8 mA
25
51
54
12 mA
16 mA
24 mA
4 mA
103
132
268
16
109
127
181
18
2.5 V LVCMOS
8 mA
32
37
12 mA
16 mA
24 mA
2 mA
65
74
83
87
169
9
124
11
1.8 V LVCMOS
4 mA
17
22
6 mA
35
44
8 mA
45
51
12 mA
16 mA
2 mA
91
74
91
74
1.5 V LVCMOS
13
16
4 mA
25
33
6 mA
32
39
8 mA
66
55
12 mA
2 mA
66
55
1.2 V LVCMOS
3.3 V PCI/PCIX
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
TBD
TBD
Per PCI/PCI-X Specification
25 mA
25 mA
35 mA
33 mA
8 mA
Per PCI Curves
268
169
268
169
32
181
124
181
124
39
HSTL (II)
15 mA
15 mA
18 mA
14 mA
21 mA
66
55
SSTL2 (I)
83
87
SSTL2 (II)
169
51
124
54
SSTL3 (I)
SSTL3 (II)
103
109
* TJ = 100°C
Advance v0.3
2-27
IGLOOe DC and Switching Characteristics
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection,
but such protection would only be needed in extremely prolonged stress conditions.
Table 2-30 • Duration of Short Circuit Event before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
110°C
6 months
3 months
Table 2-31 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
240 mV
140 mV
80 mV
60 mV
40 mV
Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
10 ns*
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
20 years (110°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but input noise 20 years (110°C)
voltage cannot exceed Schmitt
hysteresis.
HSTL/SSTL/GTL
No requirement
No requirement
10 ns*
10 ns*
10 years (100°C)
10 years (100°C)
LVDS/B-LVDS/M-LVDS/LVPECL
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,
then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity
evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
2-28
Advance v0.3
IGLOOe DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS
standard is supported as part of the 3.3 V LVTTL support.
Table 2-33 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
4
8
4
8
25
51
27
54
10 10
10 10
10 10
10 10
10 10
8 mA
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
103
132
268
109
127
181
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-7 • AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
VREF (typ.) (V)
CLOAD (pF)
0
3.3
1.4
–
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Advance v0.3
2-29
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
0.98 5.04 0.19 1.10 1.37 0.67 5.13 4.10 2.33 2.22 8.76 7.73
0.98 4.16 0.19 1.10 1.37 0.67 4.23 3.54 2.60 2.72 7.86 7.17
0.98 3.53 0.19 1.10 1.37 0.67 3.60 3.12 2.78 3.03 7.23 6.75
0.98 3.36 0.19 1.10 1.37 0.67 3.42 3.03 2.82 3.12 7.05 6.66
0.98 3.26 0.19 1.10 1.37 0.67 3.32 3.04 2.87 3.45 6.95 6.67
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
0.98 2.93 0.19 1.10 1.37 0.67 2.99 2.33 0.00 2.34 6.62 5.96 ns
0.98 2.45 0.19 1.10 1.37 0.67 2.50 1.92 2.60 2.84 6.13 5.55 ns
0.98 2.18 0.19 1.10 1.37 0.67 2.22 1.72 2.78 3.17 5.85 5.35 ns
0.98 2.13 0.19 1.10 1.37 0.67 2.17 1.69 2.83 3.26 5.80 5.32 ns
0.98 2.15 0.19 1.10 1.37 0.67 2.19 1.64 2.88 3.58 5.82 5.27 ns
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-30
Advance v0.3
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
1.55 5.53 0.26 1.31 1.57 1.10 5.63 4.53 2.78 2.85 11.44 10.34 ns
8 mA
1.55 4.58 0.26 1.31 1.57 1.10 4.67 3.95 3.07 3.44 10.48 9.76
1.55 3.92 0.26 1.31 1.57 1.10 3.99 3.51 3.27 3.80 9.80 9.32
1.55 3.73 0.26 1.31 1.57 1.10 3.79 3.41 3.31 3.90 9.60 9.22
1.55 3.62 0.26 1.31 1.57 1.10 3.69 3.42 3.36 4.28 9.50 9.23
ns
ns
ns
ns
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
1.55 3.27 0.26 1.31 1.57 1.10 3.33 2.67 2.78 2.99 9.14 8.48
1.55 2.75 0.26 1.31 1.57 1.10 2.81 2.24 3.07 3.58 8.61 8.05
1.55 2.46 0.26 1.31 1.57 1.10 2.51 2.04 3.27 3.96 8.32 7.85
1.55 2.41 0.26 1.31 1.57 1.10 2.46 2.00 3.32 4.06 8.27 7.81
1.55 2.43 0.26 1.31 1.57 1.10 2.48 1.95 3.37 4.44 8.29 7.76
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-31
IGLOOe DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 2-39 • Minimum and Maximum DC Input and Output Levels
2.5 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSH
IOSL
IIL IIH
Drive
Strength
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
4
8
4
8
16
32
18
37
10 10
10 10
10 10
10 10
10 10
8 mA
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
65
74
83
87
169
124
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-8 • AC Loading
Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
VREF (typ.) (V)
CLOAD (pF)
0
2.5
1.2
–
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-32
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-41 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
0.98 5.70 0.19 1.34 1.45 0.67 5.81 4.87 2.34 2.01 9.44 8.50
0.98 4.71 0.19 1.34 1.45 0.67 4.79 4.17 2.65 2.60 8.42 7.80
0.98 4.00 0.19 1.34 1.45 0.67 4.07 3.67 2.86 2.99 7.70 7.30
0.98 3.78 0.19 1.34 1.45 0.67 3.85 3.56 2.90 3.09 7.48 7.19
0.98 3.69 0.19 1.34 1.45 0.67 3.75 3.57 2.96 3.46 7.38 7.20
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-42 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
0.98 3.02 0.19 1.34 1.45 0.67 3.08 2.74 2.34 2.08 6.71 6.37
0.98 2.51 0.19 1.34 1.45 0.67 2.56 2.17 2.65 2.69 6.19 5.80
0.98 2.21 0.19 1.34 1.45 0.67 2.25 1.89 2.86 3.06 5.88 5.52
0.98 2.16 0.19 1.34 1.45 0.67 2.20 1.84 2.90 3.17 5.83 5.47
0.98 2.17 0.19 1.34 1.45 0.67 2.21 1.77 2.96 3.57 5.84 5.40
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-33
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-43 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
1.55 6.24 0.26 1.55 1.76 1.10 6.36 5.34 2.80 2.61 12.17 11.15
1.55 5.17 0.26 1.55 1.76 1.10 5.27 4.61 3.12 3.30 11.08 10.42
1.55 4.41 0.26 1.55 1.76 1.10 4.49 4.08 3.34 3.75 10.30 9.89
1.55 4.18 0.26 1.55 1.76 1.10 4.26 3.96 3.39 3.87 10.06 9.77
1.55 4.08 0.26 1.55 1.76 1.10 4.15 3.98 3.45 4.30 9.96 9.79
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Table 2-44 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
1.55 3.36 0.26 1.55 1.76 1.10 3.43 3.11 2.80 2.70 9.23
1.55 2.82 0.26 1.55 1.76 1.10 2.87 2.51 3.12 3.40 8.68
1.55 2.50 0.26 1.55 1.76 1.10 2.54 2.22 3.34 3.83 8.35
1.55 2.44 0.26 1.55 1.76 1.10 2.49 2.16 3.39 3.95 8.29
1.55 2.45 0.26 1.55 1.76 1.10 2.50 2.09 3.45 4.42 8.31
8.92
8.32
8.03
7.97
7.90
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-34
Advance v0.3
IGLOOe DC and Switching Characteristics
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-45 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive
Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
1.9
1.9
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
9
11
22
44
51
74
74
10 10
10 10
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
17
35
45
91
91
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-9 • AC Loading
Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
VREF (typ.) (V)
CLOAD (pF)
0
1.8
0.9
–
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Advance v0.3
2-35
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-47 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.98 7.53 0.19 1.30 1.63 0.67 7.67 6.34 2.40 1.21 11.30 9.97
0.98 6.24 0.19 1.30 1.63 0.67 6.36 5.38 2.77 2.48 9.99 9.01
0.98 5.33 0.19 1.30 1.63 0.67 5.43 4.73 3.01 2.96 9.06 8.36
0.98 5.02 0.19 1.30 1.63 0.67 5.11 4.60 3.07 3.09 8.74 8.23
0.98 4.93 0.19 1.30 1.63 0.67 5.02 4.61 3.15 3.57 8.65 8.24
0.98 4.93 0.19 1.30 1.63 0.67 5.02 4.61 3.15 3.57 8.65 8.24
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-48 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
Std.
Std.
Std.
Std.
Std.
Std.
0.98 3.53 0.19 1.30 1.63 0.67 3.59 3.47 2.39 1.23 7.22
0.98 2.90 0.19 1.30 1.63 0.67 2.96 2.65 2.76 2.56 6.59
0.98 2.52 0.19 1.30 1.63 0.67 2.57 2.24 3.01 3.03 6.20
0.98 2.45 0.19 1.30 1.63 0.67 2.49 2.17 3.07 3.17 6.12
0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11
0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11
7.10
6.28
5.87
5.80
5.70
5.70
ns
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-36
Advance v0.3
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-49 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 8.20 0.26 1.53 1.95 1.10 8.35 6.89 2.86 1.68 14.16 12.69
1.55 6.82 0.26 1.53 1.95 1.10 6.95 5.88 3.25 3.16 12.75 11.69
1.55 5.84 0.26 1.53 1.95 1.10 5.95 5.20 3.51 3.71 11.75 11.00
1.55 5.51 0.26 1.53 1.95 1.10 5.61 5.06 3.58 3.87 11.42 10.87
1.55 5.41 0.26 1.53 1.95 1.10 5.51 5.07 3.66 4.42 11.32 10.88
1.55 5.41 0.26 1.53 1.95 1.10 5.51 5.07 3.66 4.42 11.32 10.88
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Table 2-50 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Speed
Drive Strength Grade tDOUT tDP
tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
Std.
Std.
Std.
Std.
Std.
Std.
1.55 3.91 0.26 1.53 1.95 1.10 3.98 3.88 2.85 1.70 9.79 9.68
1.55 3.24 0.26 1.53 1.95 1.10 3.30 3.01 3.24 3.25 9.11 8.82
1.55 2.83 0.26 1.53 1.95 1.10 2.88 2.58 3.51 3.80 8.69 8.39
1.55 2.75 0.26 1.53 1.95 1.10 2.80 2.51 3.57 3.95 8.61 8.31
1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21
1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21
ns
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-37
IGLOOe DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-51 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive
Strength Min., V Max., V
Min., V Max., V Max., V
Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
6
8
13
25
32
66
66
16
33
39
55
55
10 10
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-10 • AC Loading
Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
VREF (typ.) (V)
CLOAD (pF)
0
1.5
0.75
–
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-38
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-53 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
Std.
0.98 7.82 0.19 1.50 1.82 0.67 7.97 6.49 2.89 2.41 11.60 10.12
0.98 6.72 0.19 1.50 1.82 0.67 6.84 5.71 3.17 2.96 10.47 9.34
0.98 6.32 0.19 1.50 1.82 0.67 6.44 5.56 3.24 3.11 10.07 9.19
0.98 6.24 0.19 1.50 1.82 0.67 6.36 5.56 3.33 3.66 9.99 9.19
0.98 6.24 0.19 1.50 1.82 0.67 6.36 5.56 3.33 3.66 9.99 9.19
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-54 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
Std.
0.98 3.34 0.19 1.50 1.82 0.67 3.41 3.07 2.88 2.50 7.04 6.70
0.98 2.88 0.19 1.50 1.82 0.67 2.94 2.57 3.17 3.05 6.57 6.20
0.98 3.90 0.19 1.50 1.82 0.67 3.97 3.79 3.17 3.20 7.60 7.42
0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98
0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-39
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-55 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
Std.
1.55 8.51 0.26 1.72 2.15 1.10 8.67 7.05 3.38 3.07 14.48 12.86
1.55 7.33 0.26 1.72 2.15 1.10 7.47 6.22 3.69 3.71 13.27 12.03
1.55 6.90 0.26 1.72 2.15 1.10 7.03 6.07 3.75 3.88 12.84 11.88
1.55 6.82 0.26 1.72 2.15 1.10 6.95 6.07 3.86 4.52 12.75 11.88
1.55 6.82 0.26 1.72 2.15 1.10 6.95 6.07 3.86 4.52 12.75 11.88
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Table 2-56 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
Std.
1.55 3.71 0.26 1.72 2.15 1.10 3.78 3.46 3.37 3.18 9.59
1.55 3.22 0.26 1.72 2.15 1.10 3.28 2.92 3.68 3.81 9.09
9.26
8.73
ns
ns
ns
ns
ns
1.55 4.30 0.26 1.72 2.15 1.10 4.38 4.21 3.69 4.00 10.19 10.02
1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96
1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96
8.51
8.51
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-40
Advance v0.3
IGLOOe DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose
1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.2 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive
Strength Min., V Max., V
Min., V Max., V Max., V
Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
TBD
TBD
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
5 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-11 • AC Loading
Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Timing Characteristics
1.2 V DC Core Voltage
Table 2-59 • 1.2 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ
tHZ
tZLS tZHS Units
2 mA
Std. 1.55
9.93 0.26 2.06 2.96 1.10 9.50 7.45 3.68 4.03 15.10 13.05 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
Table 2-60 • 1.2 LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Speed
Drive Strength Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ
tHZ
tZLS tZHS Units
ns
2 mA
Std. 1.55
4.07 0.26 2.06 2.96 1.10 3.90 3.43 3.80 4.02 9.49 9.03
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
Advance v0.3
2-41
IGLOOe DC and Switching Characteristics
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI
Bus applications.
Table 2-61 • Minimum and Maximum DC Input and Output Levels
IO
3.3 V PCI/PCI-X
VIL
VIH
Max.,
VOL
VOH IOL
IOSH
IOSL
IIL IIH
H
Min.,
V
Max.,
V
Min.,
V
Max.,
V
Min.,
V
m
A
m
A
µA µA
2
2
Drive Strength
V
Max., mA1 Max., mA1
Per PCI
Per PCI curves
10 10
specification
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable
path characterization are described in Figure 2-12.
R to VCCI for tDP (F)
R to GND for tDP (R)
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH /tZHS/tZL/tZLS
5 pF for tHZ /tLZ
Figure 2-12 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in Table 2-62.
Table 2-62 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
VREF (typ.) (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–
10
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-42
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-63 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS tEOUT
0.67
tZL
tZH
tLZ
tHZ
tZLS tZHS Units
ns
Std.
0.98
2.44 0.19 0.98 1.45
2.49 1.84 2.79 3.17 6.12 5.47
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-64 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS tEOUT
1.10
tZL
tZH
tLZ
tHZ
tZLS tZHS Units
ns
Std.
1.55
2.74 0.26 1.19 1.63
2.80 2.16 3.28 3.96 8.60 7.97
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-43
IGLOOe DC and Switching Characteristics
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
3.3 V.
Table 2-65 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength Min., V Max., V
25 mA3
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25 268 181 10 10
–
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-13 • AC Loading
Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-44
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-67 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.83
0.19
2.41
0.67
1.84
1.83
5.47
5.46
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-68 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.09
0.26
2.75
1.10
2.10
2.09
7.91
7.89
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-45
IGLOOe DC and Switching Characteristics
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
2.5 V.
Table 2-69 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 μA2 μA2
–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25 169 124 10 10
VOL
VOH IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
25 mA3
–
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-14 • AC Loading
Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
V
REF (typ.) (V) VTT (typ.) (V)
0.8 1.2
CLOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-46
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-71 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.90
0.19
2.04
0.67
1.94
1.87
5.57
5.50
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-72 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.16
0.26
2.35
1.10
2.20
2.13
8.01
7.94
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-47
IGLOOe DC and Switching Characteristics
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
3.3 V
Table 2-73 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
–0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 35 35 268 181 10 10
VOL
VOH IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
35 mA
–
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-15 • AC Loading
Table 2-74 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.1
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
10
V
VREF + 0.1
1.0
1.0
1.5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-48
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-75 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.85
0.19
1.35
0.67
1.88
1.81
5.51
5.44
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-76 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.11
0.26
1.61
1.10
2.15
2.07
7.95
7.88
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-49
IGLOOe DC and Switching Characteristics
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
2.5 V.
Table 2-77 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
–0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 33 33 169 124 10 10
VOL
VOH IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
33 mA
–
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-16 • AC Loading
Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
10
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-50
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-79 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.97
0.19
1.29
0.67
2.00
1.84
5.63
5.47
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-80 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.23
0.26
1.55
1.10
2.28
2.11
8.08
7.91
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-51
IGLOOe DC and Switching Characteristics
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-81 • Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
8 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.4
VCCI – 0.4
8
8
32
39
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
HSTL
Class I
50
Test Point
20 pF
Figure 2-17 • AC Loading
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input LOW (V)
Input HIGH (V)
(V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
20
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-52
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-83 • HSTL Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
2.74
0.19
1.77
0.67
2.79
2.73
6.42
6.36
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-84 • HSTL Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
3.10
0.26
1.94
1.10
3.12
3.10
8.93
8.91
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-53
IGLOOe DC and Switching Characteristics
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-85 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
15 mA3
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.4 VCCI – 0.4 15 15
66
55
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
HSTL
Class II
25
Test Point
20 pF
Figure 2-18 • AC Loading
Table 2-86 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.1
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
20
V
VREF + 0.1
0.75
0.75
0.75
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-54
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-87 • HSTL Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
2.62
0.19
1.77
0.67
2.66
2.40
6.29
6.03
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-88 • HSTL Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.93
0.26
1.94
1.10
2.98
2.75
8.79
8.55
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-55
IGLOOe DC and Switching Characteristics
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-89 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
15 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.54 VCCI – 0.62 15 15
83
87
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class I
50
Test Point
25
30 pF
Figure 2-19 • AC Loading
Table 2-90 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.2
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
30
V
VREF + 0.2
1.25
1.25
1.25
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
2-56
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-91 • SSTL 2 Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.91
0.19
1.15
0.67
1.94
1.72
5.57
5.35
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-92 • SSTL 2 Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.17
0.26
1.39
1.10
2.21
2.04
8.02
7.84
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-57
IGLOOe DC and Switching Characteristics
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-93 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
18 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.35 VCCI – 0.43 18 18
169
124
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class II
25
Test Point
25
30 pF
Figure 2-20 • AC Loading
Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.2
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
30
V
VREF + 0.2
1.25
1.25
1.25
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-95 • SSTL 2 Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.94
0.19
1.15
0.67
1.97
1.66
5.60
5.29
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-96 • SSTL 2 Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.20
0.26
1.39
1.10
2.24
1.97
8.05
7.78
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-58
Advance v0.3
IGLOOe DC and Switching Characteristics
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-97 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
14 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.7 VCCI – 1.1 14 14
54
51
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class I
50
Test Point
25
30 pF
Figure 2-21 • AC Loading
Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.2
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
30
V
VREF + 0.2
1.5
1.5
1.485
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Advance v0.3
2-59
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-99 • SSTL 3 Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
2.05
0.19
1.09
0.67
2.09
1.71
5.72
5.34
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-100 • SSTL 3 Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.32
0.26
1.32
1.10
2.37
2.02
8.17
7.83
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-60
Advance v0.3
IGLOOe DC and Switching Characteristics
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-101 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
21 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.5 VCCI - 0.9 21 21
103
109
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class II
25
Test Point
25
30 pF
Figure 2-22 • AC Loading
Table 2-102 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input LOW (V)
REF – 0.2
Input HIGH (V)
Point* (V)
V
REF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
30
V
VREF + 0.2
1.5
1.5
1.485
Note: Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Advance v0.3
2-61
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-103 • SSTL 3 Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
0.98
1.86
0.19
1.09
0.67
1.89
1.58
5.52
5.21
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-104 • SSTL 3 Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ tHZ
tZLS
tZHS
Units
Std.
1.55
2.12
0.26
1.32
1.10
2.16
1.89
7.97
7.70
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-62
Advance v0.3
IGLOOe DC and Switching Characteristics
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Actel Designer software
when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for
bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also
requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVPECL
implementation because the output standard specifications are different.
Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
165 Ω
165 Ω
Z0 = 50 Ω
140 Ω
Z0 = 50 Ω
INBUF_LVDS
+
–
100 Ω
N
N
Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation
Advance v0.3
2-63
IGLOOe DC and Switching Characteristics
Table 2-105 • Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
2.375
0.9
Typ.
2.5
Max.
2.625
1.25
1.6
Units
V
VCCI
VOL
VOH
Supply Voltage
Output LOW Voltage
1.075
1.425
0.91
0.91
V
Output HIGH Voltage
1.25
0.65
0.65
0
V
4
IOL
Output Lower Current
1.16
1.16
2.925
10
mA
mA
V
4
IOH
Output HIGH Current
VI
Input Voltage
3
IIH
Input HIGH Leakage Current
Input LOW Leakage Current
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
µA
µA
mV
V
3
IIL
10
VODIFF
VOCM
VICM
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
V
VIDIFF
Notes:
mV
1.
5%
2. Differential input voltage = 350 mV
3. Currents are measured at 85°C junction temperature.
4. IOL/IOH is defined by VODIFF/(resistor network).
Table 2-106 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
VREF (typ.) (V)
1.075
1.325
Cross point
–
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-107 • LVDS – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.98
1.77
0.19
1.62
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-108 • LVDS – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
1.55
2.19
0.26
1.88
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-64
Advance v0.3
IGLOOe DC and Switching Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard
to high-performance multipoint bus applications. Multidrop and multipoint bus configurations
may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the
higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers
require series terminations for better signal quality and to control voltage swing. Termination is
also required at both ends of the bus since the driver can be located anywhere on the bus. These
configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with
appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz
with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output
buffer delays are available in the LVDS section in Table 2-107 on page 2-64 and Table 2-108 on
page 2-64.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the
required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:
RS = 60 Ω and RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
OUTBUF_LVPECL
100 Ω
100 Ω
Z0 = 50 Ω
187 W
Z0 = 50 Ω
INBUF_LVPECL
+
–
100 Ω
N
N
Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation
Advance v0.3
2-65
IGLOOe DC and Switching Characteristics
Table 2-109 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min. Max. Min. Max. Min. Max. Units
3.0
3.3
3.6
V
V
VOL
Output LOW Voltage
0.96
1.8
0
1.27
2.11
3.3
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.9
VOH
Output HIGH Voltage
V
VIL, VIH
VODIFF
VOCM
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
V
0.625 0.97 0.625 0.97 0.625 0.97
1.762 1.98 1.762 1.98 1.762 1.98
V
V
VICM
1.01
300
2.57
1.01
300
2.57
1.01
300
2.57
V
VIDIFF
mV
Table 2-110 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
VREF (typ.) (V)
1.64
1.94
Cross point
–
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-111 • LVPECL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.98
1.75
0.19
1.45
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-112 • LVPECL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
1.55
2.16
0.26
1.70
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-66
Advance v0.3
IGLOOe DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous
Preset
Preset
L
D
DOUT
Data_out
PRE
DFN1E1P1
F
PRE
DFN1E1P1
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
G
E
E
EOUT
B
H
I
A
PRE
DFN1E1P1
J
D
Q
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
CLKBUF
INBUF
INBUF
Postive-Edge Triggered
Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Advance v0.3
2-67
IGLOOe DC and Switching Characteristics
Table 2-113 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
G, H
G, H
L, DOUT
L, H
tOHE
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
J, H
tOESUE
tOEHE
K, H
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
* See Figure 2-26 on page 2-67 for more information.
2-68
Advance v0.3
IGLOOe DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous
Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
CLR
LL
HH
AA
DD
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Advance v0.3
2-69
IGLOOe DC and Switching Characteristics
Table 2-114 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
II, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
* See Figure 2-27 on page 2-69 for more information.
2-70
Advance v0.3
IGLOOe DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
tIHD
50%
50%
1
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-28 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-115 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Std. Units
Clock-to-Q of the Input Data Register
0.42
0.47
0.00
0.67
0.00
0.79
0.79
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
tIHE
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-71
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-116 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
Std. Units
0.68
0.97
0.00
1.02
0.00
1.19
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-72
Advance v0.3
IGLOOe DC and Switching Characteristics
Output Register
t
t
OCKMPWH OCKMPWL
50%
t
50%
50%
50%
50%
50%
50%
CLK
t
OSUD OHD
50%
50%
1
0
Data_out
t
OREMPRE
Enable
Preset
50%
t
t
OWPRE
ORECPRE
t
OHE
50%
50%
50%
t
OSUE
t
t
OREMCLR
50%
t
ORECCLR
OWCLR
50%
50%
Clear
t
OPRE2Q
50%
50%
50%
DOUT
t
OCLR2Q
t
OCLKQ
Figure 2-29 • Output Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-117 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Std. Units
Clock-to-Q of the Output Data Register
1.00
0.51
0.00
0.70
0.00
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
tOHE
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
tOCKMPWH
tOCKMPWL
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-73
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-118 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Output Data Register
Parameter
tOCLKQ
Std. Units
1.52
1.15
0.00
1.11
0.00
1.96
1.96
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
tOCKMPWH
tOCKMPWL
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-74
Advance v0.3
IGLOOe DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD tOEHD
50%
50%
0
1
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
50%
tOERECPRE
50%
tOESUE OEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
EOUT
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
Figure 2-30 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-119 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
Std. Units
Clock-to-Q of the Output Enable Register
0.75
0.51
0.00
0.73
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOESUE
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-75
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-120 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Output Enable Register
Parameter
tOECLKQ
tOESUD
Std. Units
1.10
1.15
0.00
1.22
0.00
1.65
1.65
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOESUE
Enable Setup Time for the Output Enable Register
tOEHE
Enable Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-76
Advance v0.3
IGLOOe DC and Switching Characteristics
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLR
CLKBUF
FF2
C
INBUF
DDR_IN
Figure 2-31 • Input DDR Timing Model
Table 2-121 • Parameter Definitions
Parameter Name
Parameter Definition
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Measuring Nodes (from, to)
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
Advance v0.3
2-77
IGLOOe DC and Switching Characteristics
CLK
t
t
DDRISUD
DDRIHD
Data
CLR
1
2
3
4
5
6
7
8
9
t
DDRIRECCLR
t
DDRIREMCLR
t
DDRICLKQ1
t
t
DDRICLR2Q1
Out_QF
Out_QR
6
2
4
t
DDRICLKQ2
DDRICLR2Q2
7
3
5
Figure 2-32 • Input DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-122 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Description
Std.
0.48
0.65
0.50
0.40
0.00
0.00
0.82
0.98
0.00
0.23
0.19
0.31
0.28
Units
Clock-to-Out Out_QR for Input DDR
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-78
Advance v0.3
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-123 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out Out_QR for Input DDR
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Std.
0.76
0.94
0.93
0.84
0.00
0.00
1.23
1.42
0.00
0.24
0.19
0.31
0.28
Units
ns
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-79
IGLOOe DC and Switching Characteristics
Output DDR Module
Output DDR
A
Data_F
XX
(from core)
FF1
Out
B
C
0
1
CLK
X
X
X
E
CLKBUF
X
OUTBUF
D
Data_R
(from core)
FF2
B
C
X
X
CLR
INBUF
DDR_OUT
Figure 2-33 • Output DDR Timing Model
Table 2-124 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (from, to)
tDDROCLKQ
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
tDDROSUD2
tDDROHD1
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROHD2
2-80
Advance v0.3
IGLOOe DC and Switching Characteristics
CLK
tDDROHD2
tDDROSUD2
3
4
9
5
Data_F
1
2
tDDROHD1
tDDROREMCLR
Data_R 6
CLR
7
8
10
11
tDDRORECCLR
tDDROREMCLR
tDDROCLR2Q
tDDROCLKQ
Out
7
2
8
3
9
4
10
Figure 2-34 • Output DDR Timing Diagram
Advance v0.3
2-81
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-125 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Std.
1.07
0.67
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.31
0.28
Units
ns
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-126 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
Clock-to-Out of DDR for Output DDR
Std.
1.60
1.09
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
Units
ns
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-82
Advance v0.3
IGLOOe DC and Switching Characteristics
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOOe library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the IGLOO,
Fusion, and ProASIC3 Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-35 • Sample of Combinatorial Cells
Advance v0.3
2-83
IGLOOe DC and Switching Characteristics
t
PD
Fanout = 4
A
B
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
t
= MAX(t
, t
,
PD
PD(RR) PD(RF)
t
, t
) where edges are
PD(FF) PD(FR)
A
applicable for a particular
combinatorial cell
Net
Y
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
VCC
50%
50%
A, B, C
GND
VCC
50%
50%
OUT
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-36 • Timing Model and Waveforms
2-84
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-127 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
0.80
0.84
0.90
1.19
1.10
1.37
1.33
1.79
1.48
1.21
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A , B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
AND3
tPD
ns
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-128 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
1.35
1.42
1.58
2.10
1.94
2.33
2.34
3.05
2.64
2.10
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A , B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
AND3
tPD
ns
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-85
IGLOOe DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOOe library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are
presented for a representative sample from the library. For more details, refer to the IGLOO,
Fusion, and ProASIC3 Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Out
Data
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-37 • Sample of Sequential Cells
2-86
Advance v0.3
IGLOOe DC and Switching Characteristics
t
t
CKMPWH CKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
HD
t
SUD
50%
50%
t
Data
EN
0
50%
t
RECPRE
WPRE
t
REMPRE
t
HE
50%
50%
50%
t
PRE
CLR
Out
SUE
t
t
t
REMCLR
RECCLR
WCLR
50%
50%
50%
t
PRE2Q
t
CLR2Q
50%
50%
50%
t
CLKQ
Figure 2-38 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-129 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-87
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-130 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
1.61
1.17
0.00
1.29
0.00
0.87
0.89
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-88
Advance v0.3
IGLOOe DC and Switching Characteristics
Global Resource Characteristics
AGLE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing.
The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the AGLE600
device. It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-39 • Example of Global Tree Use in an AGLE600 Device for Clock Routing
Advance v0.3
2-89
IGLOOe DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
capabilities, refer to the "Clock Conditioning Circuits" section on page 2-92. Table 2-131 and
Table 2-133 present minimum and maximum global clock delays within the device. Minimum and
maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-131 • AGLE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.48
Units
ns
1.82
1.94
tRCKH
Input HIGH Delay for Global Clock
1.52
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-132 • AGLE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
2.00
Max.2
Units
ns
2.34
tRCKH
Input HIGH Delay for Global Clock
2.09
2.51
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-90
Advance v0.3
IGLOOe DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-133 • AGLE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
2.22
Max.2
Units
ns
2.67
tRCKH
Input HIGH Delay for Global Clock
2.32
2.93
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
Table 2-134 • AGLE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
2.83
Max.2
Units
ns
3.27
tRCKH
Input HIGH Delay for Global Clock
3.00
3.61
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
Advance v0.3
2-91
IGLOOe DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-135 • IGLOOe CCC/PLL Specification
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Serial Clock (SCLK) for Dynamic PLL3
0.75
250
100
Delay Increments in Programmable Delay Blocks1, 2
360
Number of Programmable Values in Each Programmable Delay
Block
32
1
ns
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
External
FB Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.50%
1.00%
2.50%
0.75%
1.50%
3.75%
0.70%
1.20%
2.75%
100 MHz to 250 MHz
Acquisition Time
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter
LockControl = 0
2.5
1.5
ns
ns
%
ns
ns
ns
LockControl = 1
Output Duty Cycle
48.5
1.25
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1, 2, 4
Delay Range in Block: Programmable Delay 2 1, 2, 4
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
3.5
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6
for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions.For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices chapter of the handbook.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
2-92
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-136 • IGLOOe CCC/PLL Specification
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
160
160
60
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Serial Clock (SCLK) for Dynamic PLL4
0.75
Delay Increments in Programmable Delay Blocks1, 2
580
ps
Number of Programmable Values in Each Programmable Delay
Block
32
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
0.25
ns
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
External
FB Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.50%
1.00%
2.50%
0.75%
1.50%
3.75%
0.70%
1.20%
2.75%
100 MHz to 160 MHz
Acquisition Time
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter
LockControl = 0
4
ns
ns
%
ns
ns
ns
LockControl = 1
3
Output Duty Cycle
48.5
2.3
51.5
20.86
20.86
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
5.7
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6
for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-40 • Peak-to-Peak Jitter Definition
Advance v0.3
2-93
IGLOOe DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8 RD17
ADDRA11 DOUTA8
RADDR7
RD16
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WCLK
RESET
RESET
Figure 2-41 • RAM Models
2-94
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
tBKS
A1
A2
ADD
BLK_B
WEN_B
DO
tBKH
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 2-42 • RAM Read for Pass-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 2-43 • RAM Read for Pipelined Output
Advance v0.3
2-95
IGLOOe DC and Switching Characteristics
tCYC
tCKH
tAH
tCKL
CLK
tAS
A0
A1
A2
ADD
BLK_B
WEN_B
DI
tBKS
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 2-44 • RAM Write, Output Retained (WMODE = 0)
t
CYC
t
t
CKH
CKL
CLK
ADD
t
t
AH
AS
A
A
A
2
0
1
t
BKS
t
BKH
BLK_B
WEN_B
DI
t
ENS
t
t
DH
DS
DI
DI
DI
2
0
1
DO
D
DI
DI
1
n
0
(pass-through)
DO
DI
D
DI
1
0
n
(pipelined)
Figure 2-45 • RAM Write, Output as Write Data (WMODE = 1)
2-96
Advance v0.3
IGLOOe DC and Switching Characteristics
CLK1
ADD1
DI1
tAS tAH
A0
tDS tDH
A1
D2
A3
D3
D1
tCCKH
CLK2
WEN_B1
WEN_B2
tAS tAH
A0
A0
D0
A4
D4
ADD2
DI2
tCKQ1
DO2
(pass-through)
Dn
Dn
D0
tCKQ2
DO2
(pipelined)
D0
Figure 2-46 • Write Access after Write onto Same Address
Advance v0.3
2-97
IGLOOe DC and Switching Characteristics
CLK1
tAS tAH
A0
tDS tDH
A2
D2
A3
D3
ADD1
DI1
D0
tWRO
CLK2
WEN_B1
WEN_B2
ADD2
tAS tAH
A1
A0
tCKQ1
A4
DO2
(pass-through)
Dn
D0
D1
D0
tCKQ2
DO2
(pipelined)
Dn
Figure 2-47 • Read Access after Write onto Same Address
2-98
Advance v0.3
IGLOOe DC and Switching Characteristics
CLK1
t
t
AS
AH
A0
A1
A0
ADD1
WEN_B1
t
t
CKQ1
CKQ1
DO1
(pass-through)
D
D
D
n
0
1
t
CKQ2
DO1
(pipelined)
D
D
n
0
t
CCKH
CLK2
t
t
AH
AS
ADD2
A0
D1
A1
A3
D3
D2
DI2
WEN_B2
Figure 2-48 • Write Access after Read onto Same Address
tCYC
tCKH
tCKL
CLK
RESET_B
DO
tRSTBQ
Dm
Dn
Figure 2-49 • RAM Reset
Advance v0.3
2-99
IGLOOe DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-137 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std.
0.83
0.16
0.81
0.16
1.65
0.16
0.71
0.36
3.53
3.06
1.81
TBD
Units
ns
Address Setup Time
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
ns
tENH
tBKS
tBKH
tDS
ns
ns
BLK_B Hold Time
ns
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pass-through, WMODE = 1)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
tCKQ2
tWRO
ns
Address collision clk-to-clk delay for reliable read access after write on
same address
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after
write/read on same address
TBD
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
2.06
2.06
0.61
3.21
0.68
6.24
160
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-100
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-138 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std.
0.83
0.16
0.73
0.08
0.71
0.36
4.21
1.71
TBD
Units
ns
Address Setup Time
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REB_B, WEN_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tENH
tDS
ns
ns
tDH
ns
tCKQ1
tCKQ2
tWRO
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
Address collision clk-to-clk delay for reliable read access after write on
same address
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after
write/read on same address
TBD
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
2.06
2.06
0.61
3.21
0.68
6.24
160
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-101
IGLOOe DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-139 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std.
1.53
0.29
1.50
0.29
3.05
0.29
1.33
0.66
6.61
5.72
3.38
TBD
Units
ns
Address Setup Time
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
ns
tENH
tBKS
tBKH
tDS
ns
ns
BLK_B Hold Time
ns
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pass-through, WMODE = 1)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
tCKQ2
tWRO
ns
Address collision clk-to-clk delay for reliable read access after write on
same address
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after
write/read on same address
TBD
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-102
Advance v0.3
IGLOOe DC and Switching Characteristics
Table 2-140 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std.
1.53
0.29
1.36
0.15
1.33
0.66
7.88
3.20
TBD
Units
ns
Address Setup Time
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REB_B, WEN_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tENH
tDS
ns
ns
tDH
ns
tCKQ1
tCKQ2
tWRO
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
Address collision clk-to-clk delay for reliable read access after write on
same address
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after
write/read on same address
TBD
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Advance v0.3
2-103
IGLOOe DC and Switching Characteristics
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-50 • FIFO Model
2-104
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
tRSTFG
EMPTY
AEMPTY
FULL
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
(Address Counter)
MATCH (A0)
Figure 2-51 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Advance v0.3
2-105
IGLOOe DC and Switching Characteristics
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
(EMPTY)
WA/RA
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
1st Rising
2nd Rising
Edge
After 1st
Write
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-54 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
NO MATCH
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 1st
Read
Edge
After 2nd
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-55 • FIFO FULL Flag and AFULL Flag Deassertion
2-106
Advance v0.3
IGLOOe DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-141 • FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
Std.
1.99
0.16
0.30
0.00
0.76
0.25
3.33
1.80
3.53
3.35
12.85
3.48
12.72
2.02
2.02
0.61
3.21
0.68
6.24
160
Units
ns
REN_B, WEN_B Setup Time
tENH
REN_B, WEN_B Hold Time
ns
tBKS
BLK_B Setup Time
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
ns
tDH
Input Data (DI) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (pass-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
WCLK HIGH to Full Flag Valid
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.3
2-107
IGLOOe DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-142 • FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
Std.
4.13
0.31
0.47
0.00
1.56
0.49
6.80
3.62
7.23
6.85
26.61
7.12
26.33
4.09
4.09
1.23
6.58
1.18
10.90
92
Units
ns
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
tENH
ns
tBKS
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (pass-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
ns
ns
ns
WCLK HIGH to Full Flag Valid
ns
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (pass-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
2-108
Advance v0.3
IGLOOe DC and Switching Characteristics
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
D0
tCKQ2
D1
Data
Figure 2-56 • Timing Diagram
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-143 • Embedded FlashROM Access Time
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tSU
Description
Std.
0.58
0.00
34.14
15
Units
ns
Address Setup Time
tHOLD
tCK2Q
FMAX
Address Hold Time
ns
Clock-to-Out
ns
Maximum Clock Frequency
MHz
Applies to 1.2 V DC Core Voltage
Table 2-144 • Embedded FlashROM Access Time
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tSU
Description
Std.
0.59
0.00
52.90
10
Units
ns
Address Setup Time
Address Hold Time
Clock-to-Out
tHOLD
tCK2Q
FMAX
ns
ns
Maximum Clock Frequency
MHz
Advance v0.3
2-109
IGLOOe DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer
delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User
I/O Characteristics" section on page 2-16 for more details.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-145 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tDISU
Description
Std.
1.50
3.00
1.50
3.00
11.00
30.00
9.00
1.18
0.00
TBD
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
tDIHD
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
Applies to 1.5 V DC Core Voltage
Table 2-146 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
Std.
1.00
2.00
1.00
2.00
8.00
25.00
15.00
0.58
0.00
TBD
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-110
Advance v0.3
IGLOOe DC and Switching Characteristics
Part Number and Revision Date
Part Number 51700096-002-2
Revised July 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (Advance v0.3)
Page
Advance v0.2
(June 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of
core voltage support. The document was updated to change 1.2 V / 1.5 V to
1.2 V to 1.5 V.
2-2
Advance v0.1
(January 2008)
Tables have been updated to reflect default values in the software. The
default I/O capacitance is 5 pF. Tables have been updated to include the
LVCMOS 1.2 V I/O set.
N/A
DDR Tables have two additional data points added to reflect both edges for
Input DDR setup and hold time.
The power data table has been updated to match SmartPower data rather
then simulation values.
Table 2-1 · Absolute Maximum Ratings was updated to add VMV to the VCCI
parameter row and remove the word "output" from the parameter
description for VCCI. Table note 3 was added.
2-1
Table 2-2 · Recommended Operating Conditions 4 was updated to include the
TJ parameter. Table note 9 is new.
2-2
2-2
In Table 2-3 · Flash Programming Limits – Retention, Storage, and Operating
Temperature1, the maximum operating junction temperature was changed
from 110° to 100°.
VMV was removed fromTable 2-4 · Overshoot and Undershoot Limits 1. The
title of the table was revised to remove "as measured on quiet I/Os." Table
note 2 was revised to remove "estimated SSO density over cycles." Table note
3 was deleted.
2-3
The "PLL Behavior at Brownout Condition" section is new.
2-4
2-5
Figure 2-2 · V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
is new.
EQ 2-2 was updated. The temperature was changed to 100°C, and therefore
the end result changed.
2-6
2-7
The table notes for Table 2-8 · Quiescent Supply Current (IDD), IGLOOe
Flash*Freeze Mode*, Table 2-9 · Quiescent Supply Current (IDD), IGLOOe Sleep
Mode (VCC = 0 V)*, and Table 2-10 · Quiescent Supply Current (IDD), IGLOOe
Shutdown Mode (VCC, VCCI = 0 V)* were updated to remove VMV and include
PDC6 and PDC7. VCCI and VJTAG were removed from the statement about IDD in
the table note for Table 2-9 · Quiescent Supply Current (IDD), IGLOOe Sleep
Mode (VCC = 0 V)*.
Note 2 of Table 2-11 · Quiescent Supply Current, No IGLOOe Flash*Freeze
Mode* was updated to include VCCPLL. Note 4 was updated to include PDC6
2-8
2-9
and PDC7
.
Table note 3 was added to Table 2-12 · Summary of I/O Input Buffer Power
(per pin) – Default I/O Software Settings and referenced for 1.2 V LVCMOS.
Advance v0.3
2-111
IGLOOe DC and Switching Characteristics
Previous Version
Changes in Current Version (Advance v0.3)
Page
Advance v0.1
(continued)
Table 2-13 · Summary of I/O Output Buffer Power (per pin) – Default I/O
Software Settings1 was updated to change PDC3 to PDC7. The table notes were
updated to reflect that power was measured on VCCI. Table note 4 is new.
2-10
Table 2-15 · Different Components Contributing to the Static Power
Consumption in IGLOO Devices and Table 2-17 · Different Components
Contributing to the Static Power Consumption in IGLOO Devices were
updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank
quiescent power.
2-11,
2-12
A
table subtitle was added for Table 2-17 · Different Components
2-12
2-13
2-14
Contributing to the Static Power Consumption in IGLOO Devices
The "Total Static Power Consumption—PSTAT" section was updated to revise
the calculation of PSTAT, including PDC6 and PDC7
.
Footnote 1 was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL
= PDC4 + PAC13 * FCLKOUT
.
The "Timing Model" was updated to be consistent with the revised timing
numbers.
2-16
2-21
2-28
N/A
In Table 2-21 · Summary of Maximum and Minimum DC Input Levels, TJ was
changed to TA in notes 1 and 2.
Table 2-31 · Schmitt Trigger Input Hysteresis was updated to included a
hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-41
N/A
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers. The
new version number is Advance v0.1.
Advance v0.3
(September 2007)
Table 2-4 • IGLOOe CCC/PLL Specification and Table 2-5 • IGLOOe CCC/PLL
Specification were updated.
2-18,
2-19
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core.
2-60
2-56
2-64
2-58
3-6
Figure 2-38 • Flash*Freeze Mode Type 1 – Timing Diagram was updated to
modify the LSICC signal.
Table 2-32 • Flash*Freeze Pin Location in IGLOOe Family Packages (device-
independent) was updated for the FG896 package.
Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
Information regarding calculation of the quiescent supply current was added
to the "Quiescent Supply Current" section.
Table 3-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode† was
updated.
3-6
Table 3-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)†
was updated.
3-6
Table 3-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was
updated.
3-6
2-112
Advance v0.3
IGLOOe DC and Switching Characteristics
Previous Version
Changes in Current Version (Advance v0.3)
Page
Advance v0.3
(continued)
Table 3-99 • Minimum and Maximum DC Input and Output Levels was
updated.
3-51
Table 3-136 • JTAG 1532 and Table 3-135 • JTAG 1532 were updated.
3-95
3-2
Advance v0.1
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 6–8 were added.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
Advance v0.3
2-113
IGLOO®e Packaging
3 – Package Pin Assignments
256-Pin FBGA
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v1.1
3-1
Package Pin Assignments
256-Pin FBGA
Pin Number AGLE600 Function
256-Pin FBGA
256-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
A1
A2
GND
C4
C5
VCCPLA
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
E8
E9
IO13NDB0V2
IO21NDB1V0
VCCIB1
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO05PDB0V0
A3
C6
E10
E11
E12
E13
E14
E15
E16
F1
A4
C7
VCCIB1
A5
C8
VMV1
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
IO41PDB2V0
IO124PDB7V0
IO125PDB7V0
IO126PDB7V0
IO130NDB7V1
VCCIB7
A6
IO10PDB0V1
C9
A7
IO12PDB0V2
C10
C11
C12
C13
C14
C15
C16
D1
A8
IO16NDB0V2
A9
IO23NDB1V0
A10
A11
A12
A13
A14
A15
A16
B1
IO23PDB1V0
IO28NDB1V1
VMV2
F2
IO28PDB1V1
IO36NDB2V0
IO42PDB2V0
IO128PDB7V1
IO129PDB7V1
GAC2/IO132PDB7V1
VCOMPLA
F3
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
F4
F5
D2
F6
GND
D3
F7
VCC
GAB2/IO133PDB7V1
D4
F8
VCC
B2
GAA2/IO134PDB7V
1
D5
GNDQ
F9
VCC
D6
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO25PDB1V0
IO27NDB1V0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
VCC
B3
B4
GNDQ
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
IO16PDB0V2
IO20NDB1V0
IO24NDB1V0
IO24PDB1V0
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
D7
GND
D8
VCCIB2
B5
D9
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PSB2V1
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
VCCIB7
B6
D10
D11
D12
D13
D14
D15
D16
E1
B7
B8
B9
VCOMPLB
B10
B11
B12
B13
B14
B15
B16
C1
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
E2
VCC
GBA2/IO36PDB2V0
IO42NDB2V0
IO133NDB7V1
IO134NDB7V1
VMV7
E3
GND
E4
GND
E5
GND
C2
E6
VCCIB0
GND
C3
E7
V
CCIB0
VCC
3-2
v1.1
IGLOOe Packaging
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
Pin Number AGLE600 Function
G12
G13
G14
G15
G16
H1
VCCIB2
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
IO49NSB2V1
GFB0/IO119NPB7V0
GFA0/IO118NDB6V1
GFB1/IO119PPB7V0
VCOMPLF
J16
K1
GCA2/IO53PSB3V0
GFC2/IO115PSB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
VCCIB6
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
GEC0/IO104NPB6V0
VMV5
K2
VCCIB5
K3
VCCIB5
K4
IO84NDB5V0
IO84PDB5V0
VCCIB4
K5
H2
K6
VCC
H3
K7
GND
VCCIB4
H4
K8
GND
VMV3
H5
GFC0/IO120NPB7V0
VCC
K9
GND
VCCPLD
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
H7
GND
VCC
H8
GND
VCCIB3
H9
GND
IO54NPB3V0
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
N4
N5
GNDQ
L2
N6
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
L3
N7
GCB0/IO51NPB2V1
GFA2/IO117PSB6V1
GFA1/IO118PDB6V1
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
L8
VCC
J5
L9
VCC
VCOMPLD
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
VCC
VJTAG
J7
GND
GND
GDC0/IO65NDB3V1
GDA1/IO67PDB3V1
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
VMV6
J8
GND
VCCIB3
J9
GND
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
IO109NPB6V0
IO106NDB6V0
IO106PDB6V0
J10
J11
J12
J13
J14
J15
GND
P2
VCC
P3
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
P4
VCCPLE
P5
IO101NPB5V2
IO95PPB5V1
IO92PDB5V1
P6
P7
v1.1
3-3
Package Pin Assignments
256-Pin FBGA
Pin Number AGLE600 Function
256-Pin FBGA
Pin Number AGLE600 Function
P8
P9
IO90PDB5V1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
T10
T11
T12
T13
T14
T15
T16
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
P10
P11
P12
P13
P14
P15
P16
R1
TCK
VPUMP
GND
TRST
GDA0/IO67NDB3V1
GEA1/IO102PDB6V0
R2
GEA0/IO102NDB6V
0
R3
R4
GNDQ
GEC2/IO99PDB5V2
IO95NPB5V1
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO100NDB5V2
T3
FF/GEB2/IO100PDB5
V2
T4
T5
T6
T7
T8
T9
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NSB5V0
IO80NSB4V1
IO81NDB4V1
3-4
v1.1
IGLOOe Packaging
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v1.1
3-5
Package Pin Assignments
484-Pin FBGA
Pin Number AGLE600 Function
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
IO71NDB4V0
IO71PDB4V0
NC
B7
B8
IO07PDB0V1
IO11NDB0V1
IO17NDB0V2
IO14PDB0V2
IO19PDB0V2
IO22NDB1V0
IO26NDB1V0
NC
GND
A3
VCCIB0
B9
A4
IO06NDB0V1
IO06PDB0V1
IO08NDB0V1
IO08PDB0V1
IO11PDB0V1
IO17PDB0V2
IO18NDB0V2
IO18PDB0V2
IO22PDB1V0
IO26PDB1V0
IO29NDB1V1
IO29PDB1V1
IO31NDB1V1
IO31PDB1V1
IO32NDB1V1
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
NC
A6
NC
A7
VCCIB3
A8
GND
GND
A9
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
IO30NDB1V1
IO30PDB1V1
IO32PDB1V1
NC
AB3
VCCIB5
AB4
IO97NDB5V2
IO97PDB5V2
IO93NDB5V1
IO93PDB5V1
IO87NDB5V0
IO87PDB5V0
NC
AB5
AB6
NC
AB7
VCCIB2
GND
AB8
AB9
VCCIB7
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
C3
NC
VCCIB1
IO75NDB4V1
IO75PDB4V1
IO72NDB4V0
IO72PDB4V0
IO73NDB4V0
IO73PDB4V0
NC
C4
NC
GND
C5
GND
GND
C6
IO04NDB0V0
IO04PDB0V0
VCC
GND
C7
VCCIB6
C8
NC
C9
VCC
IO98PDB5V2
IO96NDB5V2
IO96PDB5V2
IO86NDB5V0
IO86PDB5V0
IO85PDB5V0
IO85NDB5V0
IO78PPB4V1
IO79NDB4V1
IO79PDB4V1
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO14NDB0V2
IO19NDB0V2
NC
NC
VCCIB4
GND
NC
GND
VCC
GND
VCC
B2
VCCIB7
NC
B3
NC
NC
B4
IO03NDB0V0
IO03PDB0V0
IO07NDB0V1
GND
B5
NC
B6
NC
3-6
v1.1
IGLOOe Packaging
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
Pin Number AGLE600 Function
C21
C22
D1
NC
CCIB2
NC
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO16PDB0V2
IO20NDB1V0
IO24NDB1V0
IO24PDB1V0
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
G3
G4
G5
G6
NC
V
IO128PDB7V1
IO129PDB7V1
D2
NC
GAC2/IO132PDB7V
1
D3
NC
G7
G8
VCOMPLA
GNDQ
D4
GND
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO05PDB0V0
IO10PDB0V1
IO12PDB0V2
IO16NDB0V2
IO23NDB1V0
IO23PDB1V0
IO28NDB1V1
IO28PDB1V1
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
D5
G9
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO25PDB1V0
IO27NDB1V0
GNDQ
D6
GBA2/IO36PDB2V0
IO42NDB2V0
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D7
D8
D9
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
NC
NC
F2
IO131NDB7V1
IO131PDB7V1
IO133NDB7V1
IO134NDB7V1
VMV7
VCOMPLB
F3
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO43PDB2V0
IO43NDB2V0
NC
F4
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
F9
NC
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
NC
H3
VCC
NC
H4
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
NC
H5
E2
NC
H6
E3
GND
H7
E4
GAB2/IO133PDB7V
1
H8
VMV2
E5
GAA2/IO134PDB7V
1
H9
VCCIB0
IO36NDB2V0
IO42PDB2V0
NC
H10
H11
H12
H13
H14
H15
VCCIB0
E6
E7
GNDQ
IO13NDB0V2
IO21NDB1V0
VCCIB1
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
NC
E8
NC
E9
VCCIB1
IO127NDB7V1
IO127PDB7V1
E10
VMV1
G2
v1.1
3-7
Package Pin Assignments
484-Pin FBGA
Pin Number AGLE600 Function
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
H16
H17
H18
H19
H20
H21
H22
J1
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
IO41PDB2V0
VCC
K8
K9
VCCIB7
VCC
L21
L22
M1
IO47NDB2V1
IO47PDB2V1
NC
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M2
IO114NPB6V1
IO117NDB6V1
GFA2/IO117PDB6V1
GFA1/IO118PDB6V1
VCCPLF
GND
M3
NC
GND
M4
NC
VCC
M5
IO123NDB7V0
IO123PDB7V0
NC
VCCIB2
M6
J2
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
IO49NPB2V1
IO45NPB2V1
IO48NDB2V1
IO46NDB2V1
NC
M7
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
J3
M8
J4
IO124PDB7V0
IO125PDB7V0
IO126PDB7V0
IO130NDB7V1
VCCIB7
M9
J5
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J6
GND
J7
GND
J8
GND
J9
GND
VCC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO122PDB7V0
IO122NDB7V0
GFB0/IO119NPB7V0
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
VCC
L3
VCC
L4
VCC
L5
GFA0/IO118NDB6V
1
GND
GCA2/IO53PDB3V0
IO53NDB3V0
IO56PDB3V0
NC
L6
GFB1/IO119PPB7V0
VCOMPLF
V
CCIB2
L7
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PPB2V1
NC
L8
GFC0/IO120NPB7V0
VCC
L9
IO114PPB6V1
IO111NDB6V1
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
GND
N2
GND
N3
GND
IO48PDB2V1
IO46PDB2V1
IO121NDB7V0
IO121PDB7V0
NC
N4
GFC2/IO115PPB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
VCCIB6
GND
N5
VCC
N6
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
K2
N7
K3
N8
K4
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
N9
VCC
K5
N10
N11
N12
GND
GCB0/IO51NPB2V1
IO49PPB2V1
K6
GND
K7
GND
3-8
v1.1
IGLOOe Packaging
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE600 Function
Pin Number AGLE600 Function
Pin Number AGLE600 Function
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
VCC
R5
R6
IO106NDB6V0
IO106PDB6V0
GEC0/IO104NPB6V0
VMV5
T19
T20
T21
T22
U1
GDA1/IO67PDB3V1
NC
VCCIB3
R7
IO64PDB3V1
IO62NDB3V1
NC
IO54NPB3V0
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
NC
R8
R9
VCCIB5
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
IO84NDB5V0
IO84PDB5V0
VCCIB4
U2
IO107PDB6V0
IO107NDB6V0
GEB1/IO103PDB6V0
U3
U4
IO56NDB3V0
IO58PDB3V0
NC
U5
GEB0/IO103NDB6V
0
V
CCIB4
U6
U7
VMV6
VCCPLE
VMV3
VCCPLD
P2
IO111PDB6V1
IO115NPB6V1
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
U8
IO101NPB5V2
IO95PPB5V1
IO92PDB5V1
IO90PDB5V1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
P3
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
VCC
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO59NDB3V0
IO62PDB3V1
NC
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
IO110NDB6V0
NC
TCK
VCC
T3
VPUMP
VCC
T4
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
TRST
VCC
T5
GDA0/IO67NDB3V1
NC
GND
T6
V
CCIB3
T7
IO64NDB3V1
IO63PDB3V1
NC
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
NC
T8
GNDQ
T9
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
V2
NC
V3
GND
V4
GEA1/IO102PDB6V
0
IO59PDB3V0
IO58NDB3V0
NC
V5
GEA0/IO102NDB6V
0
V6
V7
V8
GNDQ
R2
IO110PDB6V0
VCC
VCOMPLD
GEC2/IO99PDB5V2
IO95NPB5V1
R3
VJTAG
R4
IO109NPB6V0
GDC0/IO65NDB3V1
v1.1
3-9
Package Pin Assignments
484-Pin FBGA
Pin Number AGLE600 Function
484-Pin FBGA
Pin Number AGLE600 Function
V9
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
W22
Y1
NC
CCIB6
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
W2
W3
W4
W5
W6
V
Y2
Y3
NC
Y4
IO98NDB5V2
Y5
GND
Y6
IO94NDB5V1
Y7
IO94PDB5V1
Y8
VCC
GNDQ
Y9
VCC
TDO
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO89PDB5V0
GND
IO80PDB4V1
NC
IO78NPB4V1
NC
IO63NDB3V1
NC
VCC
NC
VCC
NC
NC
GND
NC
IO100NDB5V2
GND
NC
FF/GEB2/IO100PDB5
V2
NC
W7
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NDB5V0
IO80NDB4V1
IO81NDB4V1
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
NC
W8
VCCIB3
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
GND
NC
NC
3-10
v1.1
IGLOOe Packaging
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
IO170PDB4V2
IO166NDB4V1
IO166PDB4V1
IO160NDB4V0
IO160PDB4V0
IO158NPB4V0
B7
B8
IO14PDB0V1
IO18NDB0V2
IO24NDB0V2
IO34PDB0V4
IO40PDB0V4
IO46NDB1V0
IO54NDB1V1
IO62NDB1V2
IO62PDB1V2
IO68NDB1V3
IO68PDB1V3
IO72PDB1V3
IO74PDB1V4
IO76NPB1V4
VCCIB2
GND
A3
VCCIB0
B9
A4
IO10NDB0V1
IO10PDB0V1
IO16NDB0V1
IO16PDB0V1
IO18PDB0V2
IO24PDB0V2
IO28NDB0V3
IO28PDB0V3
IO46PDB1V0
IO54PDB1V1
IO56NDB1V1
IO56PDB1V1
IO64NDB1V2
IO64PDB1V2
IO72NDB1V3
IO74NDB1V4
VCCIB1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
A6
A7
VCCIB3
A8
GND
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
AB3
VCCIB5
AB4
IO216NDB5V2
IO216PDB5V2
IO210NDB5V2
IO210PDB5V2
IO208NDB5V1
IO208PDB5V1
IO197NDB5V0
IO197PDB5V0
IO174NDB4V2
IO174PDB4V2
IO172NDB4V2
IO172PDB4V2
IO168NDB4V1
IO168PDB4V1
IO162NDB4V1
IO162PDB4V1
VCCIB4
AB5
AB6
AB7
AB8
GND
AB9
VCCIB7
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
IO303PDB7V3
IO305PDB7V3
IO06NPB0V0
GND
C3
C4
GND
C5
GND
C6
IO12NDB0V1
IO12PDB0V1
VCC
GND
C7
VCCIB6
C8
IO228PDB5V4
IO224PDB5V3
IO218NDB5V3
IO218PDB5V3
IO212NDB5V2
IO212PDB5V2
IO198PDB5V0
IO198NDB5V0
IO188PPB4V4
IO180NDB4V3
IO180PDB4V3
IO170NDB4V2
C9
VCC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO34NDB0V4
IO40NDB0V4
IO48NDB1V0
IO48PDB1V0
VCC
GND
GND
GND
VCC
B2
VCCIB7
IO70NDB1V3
IO70PDB1V3
GND
B3
IO06PPB0V0
IO08NDB0V0
IO08PDB0V0
IO14NDB0V1
B4
B5
IO76PPB1V4
IO88NDB2V0
B6
v1.1
3-11
Package Pin Assignments
484-Pin FBGA
Pin Number AGLE3000 Function
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
C21
C22
D1
IO94PPB2V1
CCIB2
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO58NDB1V2
IO58PDB1V2
GBC1/IO79PDB1V4
GBB0/IO80NDB1V4
GNDQ
G5
G6
IO297PDB7V2
GAC2/IO307PDB7V4
VCOMPLA
V
IO293PDB7V2
IO303NDB7V3
IO305NDB7V3
GND
G7
D2
G8
GNDQ
D3
G9
IO26NDB0V3
IO26PDB0V3
IO36PDB0V4
IO42PDB1V0
IO50PDB1V1
IO60NDB1V2
GNDQ
D4
GBA2/IO82PDB2V0
IO86NDB2V0
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO20PDB0V2
IO22PDB0V2
IO30PDB0V3
IO38NDB0V4
IO52NDB1V1
IO52PDB1V1
IO66NDB1V3
IO66PDB1V3
GBB1/IO80PDB1V4
GBA0/IO81NDB1V4
GBA1/IO81PDB1V4
GND
D6
D7
IO90NDB2V1
IO98PDB2V2
IO299NPB7V3
IO301NDB7V3
IO301PDB7V3
IO308NDB7V4
IO309NDB7V4
VMV7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
VCOMPLB
F3
GBB2/IO83PDB2V0
IO92PDB2V1
IO92NDB2V1
IO102PDB2V2
IO102NDB2V2
IO105NDB2V2
IO286PSB7V1
IO291NPB7V2
VCC
F4
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO32NDB0V3
IO32PDB0V3
IO44PDB1V0
IO50NDB1V1
IO60PDB1V2
GBC0/IO79NDB1V4
VCCPLB
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
H3
IO88PDB2V0
IO90PDB2V1
IO94NPB2V1
IO293NDB7V2
IO299PPB7V3
GND
H4
IO295NDB7V2
IO297NDB7V2
IO307NDB7V4
IO287PDB7V1
VMV0
H5
H6
H7
E2
H8
E3
VMV2
H9
VCCIB0
E4
GAB2/IO308PDB7V4
GAA2/IO309PDB7V4
GNDQ
IO82NDB2V0
IO86PDB2V0
IO96PDB2V1
IO96NDB2V1
IO98NDB2V2
IO289NDB7V1
IO289PDB7V1
IO291PPB7V2
IO295PDB7V2
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO36NDB0V4
IO42NDB1V0
VCCIB1
E6
E7
GAB1/IO01PDB0V0
IO20NDB0V2
IO22NDB0V2
IO30NDB0V3
IO38PDB0V4
IO44NDB1V0
E8
VCCIB1
E9
VMV1
E10
E11
E12
G2
GBC2/IO84PDB2V0
IO83NDB2V0
IO100NDB2V2
G3
G4
3-12
v1.1
IGLOOe Packaging
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
H19
H20
H21
H22
J1
IO100PDB2V2
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO272NDB6V4
GFA2/IO272PDB6V4
GFA1/IO273PDB6V4
VCCPLF
VMV2
GND
M5
IO105PDB2V2
IO285NDB7V1
IO285PDB7V1
VMV7
VCC
M6
VCCIB2
M7
IO271NDB6V4
GFB2/IO271PDB6V4
VCC
J2
GCC1/IO112PPB2V3
IO108NDB2V3
IO108PDB2V3
IO110NPB2V3
IO106NPB2V3
IO109NDB2V3
IO107NDB2V3
IO257PSB6V2
IO276PDB7V0
IO276NDB7V0
GFB0/IO274NPB7V0
GFA0/IO273NDB6V4
GFB1/IO274PPB7V0
VCOMPLF
M8
J3
M9
J4
IO279PDB7V0
IO283PDB7V1
IO281PDB7V0
IO287NDB7V1
VCCIB7
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GND
GCB2/IO116PPB3V0
GCA1/IO114PPB3V0
GCC2/IO117PPB3V0
VCCPLC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
VCC
L2
VCC
L3
VCC
L4
VCC
L5
GCA2/IO115PDB3V0
IO115NDB3V0
IO126PDB3V1
IO124PSB3V1
IO255PPB6V2
IO253NDB6V2
VMV6
GND
L6
VCCIB2
L7
IO84NDB2V0
IO104NDB2V2
IO104PDB2V2
IO106PPB2V3
GNDQ
L8
GFC0/IO275NPB7V0
VCC
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
GND
N2
GND
N3
GND
N4
GFC2/IO270PPB6V4
IO261PPB6V3
IO263PDB6V3
IO263NDB6V3
VCCIB6
IO109PDB2V3
IO107PDB2V3
IO277NDB7V0
IO277PDB7V0
GNDQ
GND
N5
VCC
N6
GCC0/IO112NPB2V3
GCB1/IO113PPB2V3
GCA0/IO114NPB3V0
VCOMPLC
N7
N8
N9
VCC
IO279NDB7V0
IO283NDB7V1
IO281NDB7V0
GFC1/IO275PPB7V0
VCCIB7
N10
N11
N12
N13
N14
N15
N16
GND
GCB0/IO113NPB2V3
IO110PPB2V3
IO111NDB2V3
IO111PDB2V3
GNDQ
GND
GND
GND
VCC
VCC
VCCIB3
GND
IO255NPB6V2
IO116NPB3V0
v1.1
3-13
Package Pin Assignments
484-Pin FBGA
Pin Number AGLE3000 Function
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
N17
N18
N19
N20
N21
N22
P1
IO132NPB3V2
IO117NPB3V0
IO132PPB3V2
GNDQ
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
CCIB5
U1
U2
IO240PPB6V0
IO238PDB6V0
IO238NDB6V0
GEB1/IO235PDB6V0
GEB0/IO235NDB6V0
VMV6
V
IO196NDB5V0
IO196PDB5V0
VCCIB4
U3
U4
IO126NDB3V1
IO128PDB3V1
IO247PDB6V1
IO253PDB6V2
IO270NPB6V4
IO261NPB6V3
IO249PPB6V1
IO259PDB6V3
IO259NDB6V3
VCCIB6
U5
VCCIB4
U6
VMV3
U7
VCCPLE
P2
VCCPLD
U8
IO233NPB5V4
IO222PPB5V3
IO206PDB5V1
IO202PDB5V1
IO194PDB5V0
IO176NDB4V2
IO176PDB4V2
VMV4
P3
GDB1/IO152PPB3V4
GDC1/IO151PDB3V4
IO138NDB3V3
VCC
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO130NDB3V2
IO134PDB3V2
IO243PPB6V1
IO245NDB6V1
IO243NPB6V1
IO241PDB6V0
IO241NDB6V0
GEC1/IO236PPB6V0
VCOMPLE
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
TRST
VCC
T5
GDA0/IO153NDB3V4
IO144NDB3V3
IO140NDB3V3
IO142PDB3V3
IO239PDB6V0
IO240NPB6V0
GND
GND
T6
VCCIB3
T7
GDB0/IO152NPB3V4
IO136NDB3V2
IO136PDB3V2
IO138PDB3V3
VMV3
T8
GNDQ
T9
GEA2/IO233PPB5V4
IO206NDB5V1
IO202NDB5V1
IO194NDB5V0
IO186NDB4V4
IO186PDB4V4
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
V3
V4
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
GNDQ
IO130PDB3V2
IO128NDB3V1
IO247NDB6V1
IO245PDB6V1
VCC
V5
V6
V7
GEC2/IO231PDB5V4
IO222NPB5V3
IO204NDB5V1
IO204PDB5V1
IO195NDB5V0
IO195PDB5V0
IO178NDB4V3
IO178PDB4V3
R2
VCOMPLD
V8
R3
VJTAG
V9
R4
IO249NPB6V1
IO251NDB6V2
IO251PDB6V2
GEC0/IO236NPB6V0
VMV5
GDC0/IO151NDB3V4
GDA1/IO153PDB3V4
IO144PDB3V3
IO140PDB3V3
IO134NDB3V2
V10
V11
V12
V13
V14
R5
R6
R7
R8
3-14
v1.1
IGLOOe Packaging
484-Pin FBGA
484-Pin FBGA
Pin Number AGLE3000 Function
Pin Number AGLE3000 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
W2
W3
W4
W5
W6
IO155NDB4V0
GDB2/IO155PDB4V0
TDI
Y6
IO220NDB5V3
IO220PDB5V3
VCC
Y7
Y8
GNDQ
Y9
VCC
TDO
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO200PDB5V0
IO192PDB4V4
IO188NPB4V4
IO187PSB4V4
VCC
GND
IO146PDB3V4
IO142NDB3V3
IO239NDB6V0
IO237PDB6V0
IO230PSB5V4
GND
VCC
IO164NDB4V1
IO164PDB4V1
GND
IO232NDB5V4
FF/GEB2/IO232PDB5V
4
IO158PPB4V0
IO150PDB3V4
IO148NPB3V4
VCCIB3
W7
W8
IO231NDB5V4
IO214NDB5V2
IO214PDB5V2
IO200NDB5V0
IO192NDB4V4
IO184NDB4V3
IO184PDB4V3
IO156NDB4V0
GDC2/IO156PDB4V0
IO154NDB4V0
GDA2/IO154PDB4V0
TMS
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
IO150NDB3V4
IO146NDB3V4
IO148PPB3V4
VCCIB6
Y2
IO237NDB6V0
IO228NDB5V4
IO224NDB5V3
GND
Y3
Y4
Y5
v1.1
3-15
Package Pin Assignments
896-Pin FBGA
A1 Ball Pad Corner
30 29 28 27 26 2524 23 22 21 20 1918 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
3-16
v1.1
IGLOOe Packaging
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Function
Pin Number
Function
Pin Number
Function
IO245NDB6V1
GEB1/IO235PPB6V0
VCC
Pin Number
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
A2
GND
AA8
IO206PDB5V1
IO198NDB5V0
IO198PDB5V0
IO192NDB4V4
IO192PDB4V4
IO178NDB4V3
IO178PDB4V3
IO174NDB4V2
IO162NPB4V1
VCC
A3
GND
AA9
A4
IO14NPB0V1
GND
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
A5
IO226PPB5V4
VCCIB5
A6
IO07NPB0V0
GND
A7
VCCIB5
A8
IO09NDB0V1
IO17NDB0V2
IO17PDB0V2
IO21NDB0V2
IO21PDB0V2
IO33NDB0V4
IO33PDB0V4
IO35NDB0V4
IO35PDB0V4
IO41NDB1V0
IO43NDB1V0
IO43PDB1V0
IO45NDB1V0
IO45PDB1V0
IO57NDB1V2
IO57PDB1V2
GND
VCCIB5
VCCIB5
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
VCCIB4
VCCIB4
VCCIB4
VCCPLD
V
CCIB4
VCCIB3
IO174PDB4V2
VCC
IO150PDB3V4
IO148PDB3V4
IO147NDB3V4
IO145PDB3V3
IO143PDB3V3
IO137PDB3V2
IO254PDB6V2
IO254NDB6V2
IO240PDB6V0
GEC1/IO236PDB6V0
IO237PDB6V0
IO237NDB6V0
VCOMPLE
IO142NPB3V3
IO144NDB3V3
IO144PDB3V3
IO146NDB3V4
IO146PDB3V4
IO147PDB3V4
IO139NDB3V3
IO139PDB3V3
IO133NDB3V2
IO256NDB6V2
IO244PDB6V1
IO244NDB6V1
IO241PDB6V0
IO241NDB6V0
IO243NPB6V1
VCCIB6
AC2
AC3
AC4
AC5
IO69PPB1V3
GND
AC6
AB2
AC7
GBC1/IO79PPB1V4
GND
AB3
AC8
GND
AB4
AC9
IO226NPB5V4
IO222NDB5V3
IO216NPB5V2
IO210NPB5V2
IO204NDB5V1
IO204PDB5V1
IO194NDB5V0
IO188NDB4V4
IO188PDB4V4
GND
AB5
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
IO256PDB6V2
IO248PDB6V1
IO248NDB6V1
IO246NDB6V1
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
IO243PPB6V1
AB6
AB7
AB8
VCCPLE
AB9
VCC
AB10
AB11
AB12
IO222PDB5V3
IO218PPB5V3
IO206NDB5V1
v1.1
3-17
Package Pin Assignments
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Pin Number
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
Function
IO182PPB4V3
IO170NPB4V2
IO164NDB4V1
IO164PDB4V1
IO162PPB4V1
GND
Pin Number
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE1
Function
Pin Number
AE26
AE27
AE28
AE28
AE29
AE30
AF1
Function
GDB0/IO152NDB3V4
GDB1/IO152PDB3V4
VMV3
VCCIB4
TCK
VCC
TRST
VMV3
VCCIB3
VCC
GDA0/IO153NDB3V4
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
GND
IO149PDB3V4
GND
VCOMPLD
IO150NDB3V4
IO148NDB3V4
GDA1/IO153PDB3V4
IO145NDB3V3
IO143NDB3V3
IO137NDB3V2
GND
AF2
IO238PPB6V0
VCCIB6
AF3
IO242PPB6V1
VCC
AF4
IO220NPB5V3
VCC
AE2
AF5
AE3
IO239PDB6V0
IO239NDB6V0
VMV6
AF6
IO228NDB5V4
VCCIB5
AE4
AF7
AE5
AF8
IO230PDB5V4
IO229NDB5V4
IO229PDB5V4
IO214PPB5V2
IO208NDB5V1
IO208PDB5V1
IO200PDB5V0
IO196NDB5V0
IO186NDB4V4
IO186PDB4V4
IO180NDB4V3
IO180PDB4V3
IO168NDB4V1
IO168PDB4V1
IO160NDB4V0
IO158NPB4V0
VCCIB4
AD2
IO242NPB6V1
IO240NDB6V0
GEC0/IO236NDB6V0
VCCIB6
AE5
VMV6
AF9
AD3
AE6
GND
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AD4
AE7
GNDQ
AD5
AE8
IO230NDB5V4
IO224NPB5V3
IO214NPB5V2
IO212NDB5V2
IO212PDB5V2
IO202NPB5V1
IO200NDB5V0
IO196PDB5V0
IO190NDB4V4
IO184PDB4V3
IO184NDB4V3
IO172PDB4V2
IO172NDB4V2
IO166NDB4V1
IO160PDB4V0
GNDQ
AD6
GNDQ
AE9
AD6
GNDQ
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AD7
VCC
AD8
VMV5
AD9
VCCIB5
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
IO224PPB5V3
IO218NPB5V3
IO216PPB5V2
IO210PPB5V2
IO202PPB5V1
IO194PDB5V0
IO190PDB4V4
IO182NPB4V3
IO176NDB4V2
IO176PDB4V2
IO170PPB4V2
IO166PDB4V1
IO154NPB4V0
VCC
TDO
VMV4
VCCIB3
GND
GNDQ
3-18
v1.1
IGLOOe Packaging
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Function
Pin Number
AF29
AF30
AG1
Function
Pin Number
Function
Pin Number
AJ8
GNDQ
AH4
FF/GEB2/IO232PPB5V
4
IO213NDB5V2
IO213PDB5V2
IO209NDB5V1
IO209PDB5V1
IO203NDB5V1
IO203PDB5V1
IO197NDB5V0
IO195PDB5V0
IO183NDB4V3
IO183PDB4V3
IO179NPB4V3
IO177PDB4V2
IO173NDB4V2
IO173PDB4V2
IO163NDB4V1
IO163PDB4V1
IO167NPB4V1
VCC
GND
AJ9
AH5
AH6
VCCIB5
IO238NPB6V0
VCC
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK2
IO219NDB5V3
IO219PDB5V3
IO227NDB5V4
IO227PDB5V4
IO225PPB5V3
IO223PPB5V3
IO211NDB5V2
IO211PDB5V2
IO205PPB5V1
IO195NDB5V0
IO185NDB4V3
IO185PDB4V3
IO181PDB4V3
IO177NDB4V2
IO171NPB4V2
IO165PPB4V1
IO161PPB4V0
IO157NDB4V0
IO157PDB4V0
IO155NDB4V0
VCCIB4
AG2
AH7
AG3
IO232NPB5V4
GND
AH8
AG4
AH9
AG5
IO220PPB5V3
IO228PDB5V4
IO231NDB5V4
GEC2/IO231PDB5V4
IO225NPB5V3
IO223NPB5V3
IO221PDB5V3
IO221NDB5V3
IO205NPB5V1
IO199NDB5V0
IO199PDB5V0
IO187NDB4V4
IO187PDB4V4
IO181NDB4V3
IO171PPB4V2
IO165NPB4V1
IO161NPB4V0
IO159NDB4V0
IO159PDB4V0
IO158PPB4V0
GDB2/IO155PDB4V0
GDA2/IO154PPB4V0
GND
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AJ1
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
IO156NPB4V0
VCC
TMS
GND
GND
GND
TDI
AK3
GND
VCC
AK4
IO217PPB5V2
GND
VPUMP
AK5
GND
AK6
IO215PPB5V2
GND
GND
AK7
AJ2
GND
VJTAG
AK8
IO207NDB5V1
IO207PDB5V1
IO201NDB5V0
IO201PDB5V0
IO193NDB4V4
IO193PDB4V4
AJ3
GEA2/IO233PPB5V4
VCC
VCC
AK9
AJ4
IO149NDB3V4
GND
AK10
AK11
AK12
AK13
AJ5
IO217NPB5V2
VCC
AJ6
AH2
IO233NPB5V4
VCC
AJ7
IO215NPB5V2
AH3
v1.1
3-19
Package Pin Assignments
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Pin Number
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
B1
Function
IO197PDB5V0
IO191NDB4V4
IO191PDB4V4
IO189NDB4V4
IO189PDB4V4
IO179PPB4V3
IO175NDB4V2
IO175PDB4V2
IO169NDB4V1
IO169PDB4V1
GND
Pin Number
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
Function
IO53PDB1V1
IO53NDB1V1
IO61NDB1V2
IO61PDB1V2
IO69NPB1V3
VCC
Pin Number
C25
C26
C27
C28
C29
C30
D1
Function
IO75PDB1V4
VCCIB1
IO64PPB1V2
VCC
GBA1/IO81PPB1V4
GND
GBC0/IO79NPB1V4
VCC
IO303PPB7V3
VCC
D2
IO64NPB1V2
GND
D3
IO305NPB7V3
GND
D4
GND
D5
GAA1/IO00PPB0V0
GAC1/IO02PDB0V0
IO06NPB0V0
GAB0/IO01NDB0V0
IO05NDB0V0
IO11NDB0V1
IO11PDB0V1
IO23NDB0V2
IO23PDB0V2
IO27PDB0V3
IO40PDB0V4
IO47NDB1V0
IO47PDB1V0
IO55NPB1V1
IO65NDB1V3
IO65PDB1V3
IO71NDB1V3
IO71PDB1V3
IO73NDB1V4
IO73PDB1V4
IO74NDB1V4
GBB0/IO80NPB1V4
GND
IO167PPB4V1
GND
GND
D6
C2
IO309NPB7V4
VCC
D7
GDC2/IO156PPB4V0
GND
C3
D8
C4
GAA0/IO00NPB0V0
VCCIB0
D9
GND
C5
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
GND
C6
IO03PDB0V0
IO03NDB0V0
GAB1/IO01PDB0V0
IO05PDB0V0
IO15NPB0V1
IO25NDB0V3
IO25PDB0V3
IO31NPB0V3
IO27NDB0V3
IO39NDB0V4
IO39PDB0V4
IO55PPB1V1
IO51PDB1V1
IO59NDB1V2
IO63NDB1V2
IO63PDB1V2
IO67NDB1V3
IO67PDB1V3
IO75NDB1V4
B2
GND
C7
B3
GAA2/IO309PPB7V4
VCC
C8
B4
C9
B5
IO14PPB0V1
VCC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
B6
B7
IO07PPB0V0
IO09PDB0V1
IO15PPB0V1
IO19NDB0V2
IO19PDB0V2
IO29NDB0V3
IO29PDB0V3
IO31PPB0V3
IO37NDB0V4
IO37PDB0V4
IO41PDB1V0
IO51NDB1V1
IO59PDB1V2
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
GBA0/IO81NPB1V4
VCC
B19
3-20
v1.1
IGLOOe Packaging
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Function
Pin Number
D30
E1
Function
GBA2/IO82PPB2V0
GND
Pin Number
Function
Pin Number
G7
F5
VMV7
VCC
F5
VMV7
G8
VMV0
E2
IO303NPB7V3
VCCIB7
F6
GND
G9
VCCIB0
E3
F7
GNDQ
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G25
G26
G27
G28
G29
G30
H1
IO10NDB0V1
IO16NDB0V1
IO22PDB0V2
IO26PPB0V3
IO38NPB0V4
IO36NDB0V4
IO46NDB1V0
IO46PDB1V0
IO56NDB1V1
IO56PDB1V1
IO66NDB1V3
IO66PDB1V3
VCCIB1
E4
IO305PPB7V3
VCC
F8
IO12NDB0V1
IO12PDB0V1
IO10PDB0V1
IO16PDB0V1
IO22NDB0V2
IO30NDB0V3
IO30PDB0V3
IO36PDB0V4
IO48NDB1V0
IO48PDB1V0
IO50NDB1V1
IO58NDB1V2
IO60PDB1V2
IO77NDB1V4
IO72NDB1V3
IO72PDB1V3
GNDQ
E5
F9
E6
GAC0/IO02NDB0V0
VCCIB0
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F26
F27
F28
F29
F30
G1
E7
E8
IO06PPB0V0
IO24NDB0V2
IO24PDB0V2
IO13NDB0V1
IO13PDB0V1
IO34NDB0V4
IO34PDB0V4
IO40NDB0V4
IO49NDB1V1
IO49PDB1V1
IO50PDB1V1
IO58PDB1V2
IO60NDB1V2
IO77PDB1V4
IO68NDB1V3
IO68PDB1V3
VCCIB1
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
F1
VMV1
VCC
GNDQ
GNDQ
VCCIB2
GND
IO86NDB2V0
IO92NDB2V1
IO100PPB2V2
GND
VMV2
VMV2
IO86PDB2V0
IO92PDB2V1
VCC
IO74PDB1V4
VCC
IO294PDB7V2
IO294NDB7V2
IO300NDB7V3
IO300PDB7V3
IO295PDB7V2
IO299PDB7V3
VCOMPLA
H2
GBB1/IO80PPB1V4
VCCIB2
IO100NPB2V2
GND
H3
H4
IO82NPB2V0
GND
G2
IO296NPB7V2
IO306NDB7V4
IO297NDB7V2
VCCIB7
H5
G3
H6
IO296PPB7V2
VCC
G4
H7
F2
G5
H8
GND
F3
IO306PDB7V4
IO297PDB7V2
G6
GNDQ
H9
IO08NDB0V0
IO08PDB0V0
F4
G6
GNDQ
H10
v1.1
3-21
Package Pin Assignments
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Pin Number
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
J1
Function
IO18PDB0V2
IO26NPB0V3
IO28NDB0V3
IO28PDB0V3
IO38PPB0V4
IO42NDB1V0
IO52NDB1V1
IO52PDB1V1
IO62NDB1V2
IO62PDB1V2
IO70NDB1V3
IO70PDB1V3
GND
Pin Number
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
Function
IO42PDB1V0
IO44NDB1V0
IO44PDB1V0
IO54NDB1V1
IO54PDB1V1
IO76NPB1V4
VCC
Pin Number
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
L1
Function
VCC
IO78PPB1V4
IO88NDB2V0
IO88PDB2V0
IO94PDB2V1
IO94NDB2V1
IO85PDB2V0
IO85NDB2V0
IO93PDB2V1
IO93NDB2V1
IO286NDB7V1
IO286PDB7V1
IO298NDB7V3
IO298PDB7V3
IO283PDB7V1
IO291NDB7V2
IO291PDB7V2
IO293PDB7V2
IO293NDB7V2
IO307NPB7V4
VCC
VCCPLB
VCCIB2
IO90PDB2V1
IO90NDB2V1
GBB2/IO83PDB2V0
IO83NDB2V0
IO91PDB2V1
IO91NDB2V1
IO288NDB7V1
IO288PDB7V1
IO304NDB7V3
IO304PDB7V3
GAB2/IO308PDB7V4
IO308NDB7V4
IO301PDB7V3
IO301NDB7V3
GAC2/IO307PPB7V4
VCC
L2
L3
VCOMPLB
L4
GBC2/IO84PDB2V0
IO84NDB2V0
IO96PDB2V1
IO96NDB2V1
IO89PDB2V0
IO89NDB2V0
IO290NDB7V2
IO290PDB7V2
IO302NDB7V3
IO302PDB7V3
IO295NDB7V2
IO299NDB7V3
VCCIB7
L5
L6
K2
L7
K3
L8
K4
L9
K5
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
K6
J2
K7
VCC
J3
K8
VCC
J4
K9
VCC
J5
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
VCC
J6
IO04PPB0V0
VCC
J7
VCCIB0
VCC
J8
VCCPLA
VCCIB0
VCCIB0
VCC
J9
VCC
VCC
J10
IO04NPB0V0
IO18NDB0V2
IO20NDB0V2
IO20PDB0V2
IO32NDB0V3
IO32PDB0V3
V
CCIB0
VCCIB1
CCIB1
VCC
J11
IO78NPB1V4
IO104NPB2V2
IO98NDB2V2
IO98PDB2V2
IO87PDB2V0
J12
V
J13
VCCIB1
VCCIB1
J14
J15
IO76PPB1V4
3-22
v1.1
IGLOOe Packaging
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Function
Pin Number
Function
IO87NDB2V0
IO97PDB2V1
IO101PDB2V2
IO103PDB2V2
IO119NDB3V0
IO282NDB7V1
IO282PDB7V1
IO292NDB7V2
IO292PDB7V2
IO283NDB7V1
IO285PDB7V1
IO287PDB7V1
IO289PDB7V1
IO289NDB7V1
VCCIB7
Pin Number
Function
IO276PDB7V0
IO278PDB7V0
IO280PDB7V0
IO284PDB7V1
IO279PDB7V0
IO285NDB7V1
IO287NDB7V1
IO281NDB7V0
IO281PDB7V0
VCCIB7
Pin Number
P6
L26
N1
GFC1/IO275PDB7V0
GFC0/IO275NDB7V0
IO277PDB7V0
IO277NDB7V0
VCCIB7
L27
N2
P7
L28
N3
P8
L29
N4
P9
L30
N5
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
R1
M1
N6
VCC
M2
N7
GND
M3
N8
GND
M4
N9
GND
M5
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
P1
GND
M6
VCC
GND
M7
GND
GND
M8
GND
GND
M9
GND
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
GND
VCC
VCC
GND
VCCIB2
GND
GND
GCC1/IO112PDB2V3
IO110PDB2V3
IO110NDB2V3
IO109PPB2V3
IO111NPB2V3
IO105PDB2V2
IO105NDB2V2
GCC2/IO117PDB3V0
IO117NDB3V0
GFC2/IO270PDB6V4
GFB1/IO274PPB7V0
VCOMPLF
GND
GND
GND
GND
GND
VCC
GND
VCCIB2
GND
IO106NDB2V3
IO106PDB2V3
IO108PDB2V3
IO108NDB2V3
IO95NDB2V1
IO99NDB2V2
IO99PDB2V2
IO107PDB2V3
IO107NDB2V3
IO276NDB7V0
IO278NDB7V0
IO280NDB7V0
IO284NDB7V1
IO279NDB7V0
GND
GND
VCC
VCCIB2
NC
R2
IO104PPB2V2
IO102PDB2V2
IO102NDB2V2
IO95PDB2V1
IO97NDB2V1
IO101NDB2V2
IO103NDB2V2
IO119PDB3V0
R3
R4
GFA0/IO273NDB6V4
GFB0/IO274NPB7V0
IO271NDB6V4
GFB2/IO271PDB6V4
IO269PDB6V4
IO269NDB6V4
VCCIB7
R5
R6
P2
R7
P3
R8
P4
R9
P5
R10
v1.1
3-23
Package Pin Assignments
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Pin Number
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
T1
Function
Pin Number
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
U1
Function
Pin Number
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
V1
Function
VCC
GND
VCCIB3
GND
GND
IO120PDB3V0
IO128PDB3V1
IO124PDB3V1
IO124NDB3V1
IO126PDB3V1
IO129PDB3V1
IO127PDB3V1
IO125PDB3V1
IO121NDB3V0
IO268NDB6V4
IO262PDB6V3
IO260PDB6V3
IO252PDB6V2
IO257NPB6V2
IO261NPB6V3
IO255PDB6V2
IO259PDB6V3
IO259NDB6V3
VCCIB6
GND
GND
GND
GND
GND
VCC
GND
VCCIB3
GND
IO109NPB2V3
IO116NDB3V0
IO118NDB3V0
IO122NPB3V1
GCA1/IO114PPB3V0
GCB0/IO113NPB2V3
GCA2/IO115PPB3V0
VCCPLC
GND
GND
VCC
VCCIB2
GCC0/IO112NDB2V3
GCB2/IO116PDB3V0
IO118PDB3V0
IO111PPB2V3
IO122PPB3V1
GCA0/IO114NPB3V0
VCOMPLC
V2
V3
V4
IO121PDB3V0
IO268PDB6V4
IO264NDB6V3
IO264PDB6V3
IO258PDB6V3
IO258NDB6V3
IO257PPB6V2
IO261PPB6V3
IO265NDB6V3
IO263NDB6V3
VCCIB6
V5
V6
U2
V7
U3
V8
GCB1/IO113PPB2V3
IO115NPB3V0
IO270NDB6V4
VCCPLF
U4
V9
U5
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
U6
VCC
T2
U7
GND
T3
GFA2/IO272PPB6V4
GFA1/IO273PDB6V4
IO272NPB6V4
IO267NDB6V4
IO267PDB6V4
IO265PDB6V3
IO263PDB6V3
VCCIB6
U8
GND
T4
U9
GND
T5
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
GND
T6
VCC
GND
T7
GND
GND
T8
GND
GND
T9
GND
GND
T10
T11
T12
T13
T14
T15
GND
VCC
VCC
GND
VCCIB3
GND
GND
IO120NDB3V0
IO128NDB3V1
IO132PDB3V2
IO130PPB3V2
GND
GND
GND
GND
GND
VCC
3-24
v1.1
IGLOOe Packaging
896-Pin FBGA
AGLE3000
896-Pin FBGA
AGLE3000
Pin Number
Function
IO126NDB3V1
IO129NDB3V1
IO127NDB3V1
IO125NDB3V1
IO123PDB3V1
IO266NDB6V4
IO262NDB6V3
IO260NDB6V3
IO252NDB6V2
IO251NDB6V2
IO251PDB6V2
IO255NDB6V2
IO249PPB6V1
IO253PDB6V2
VCCIB6
Pin Number
Function
IO266PDB6V4
IO250PDB6V2
IO250NDB6V2
IO246PDB6V1
IO247NDB6V1
IO247PDB6V1
IO249NPB6V1
IO245PDB6V1
IO253NDB6V2
GEB0/IO235NPB6V0
VCC
V26
Y1
V27
Y2
V28
Y3
V29
Y4
V30
Y5
W1
Y6
W2
Y7
W3
Y8
W4
Y9
W5
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
W6
W7
VCC
W8
VCC
W9
VCC
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
VCC
VCC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
IO142PPB3V3
IO134NDB3V2
IO138NDB3V3
IO140NDB3V3
IO140PDB3V3
IO136PPB3V2
IO141NDB3V3
IO135NDB3V2
IO131NDB3V2
IO133PDB3V2
GND
GND
GND
VCC
VCCIB3
IO134PDB3V2
IO138PDB3V3
IO132NDB3V2
IO136NPB3V2
IO130NPB3V2
IO141PDB3V3
IO135PDB3V2
IO131PDB3V2
IO123NDB3V1
v1.1
3-25
Package Pin Assignments
Part Number and Revision Date
Part Number 51700096-003-1
Revised June 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.1)
Page
v1.0
The naming conventions changed for the following pins in the "484-Pin
FBGA" for the A3GLE600:
3-6
(January 2008)
Pin Number
New Function Name
IO45PPB2V1
J19
K20
M2
N1
IO45NPB2V1
IO114NPB6V1
IO114PPB6V1
N4
GFC2/IO115PPB6V1
IO115NPB6V1
P3
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers. The
new version number is v1.0.
N/A
Advance v0.3
(September 2007)
The "484-Pin FBGA" table for AGLE3000 is new.
4-11
4-16
The "896-Pin FBGA" package and table for AGLE3000 is new.
3-26
v1.1
IGLOOe Packaging
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data
has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"
"Preliminary," and "Production." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains
general product information. This document gives an overview of specific device and family
information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or
speed grades. This information can be used as estimates, but not for production. This label only
applies to the DC and Switching Characteristics chapter of the datasheet and will only be used
when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The
information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations
(EAR). They could require an approved export license prior to export from the United States. An
export includes release of product or disclosure of technology to a foreign national inside or
outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
v1.1
3-27
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
River Court,Meadows Business Park EXOS Ebisu Buillding 4F
Room 2107, China Resources Building
26 Harbour Road
Wanchai, Hong Kong
Station Approach, Blackwater
Camberley Surrey GU17 9AB
United Kingdom
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Phone 650.318.4200
Fax 650.318.4600
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Phone +852 2185 6460
Fax +852 2185 6488
Phone +44 (0) 1276 609 300
Fax +44 (0) 1276 607 540
http://jp.actel.com
www.actel.com.cn
51700096-005-5/10.08
相关型号：
AGLE3000V2-FGG896C
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA896, 31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
MICROSEMI
AGLE3000V5-FFG484C
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
MICROSEMI
AGLE3000V5-FFG484I
Field Programmable Gate Array, 3000000 Gates, 250MHz, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FBGA-484
ACTEL
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