AGLN020V2-VQ81 [MICROSEMI]
IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology; IGLOO纳米低功耗快闪FPGA和Flash * Freeze技术型号: | AGLN020V2-VQ81 |
厂家: | Microsemi |
描述: | IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology |
文件: | 总150页 (文件大小:7699K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 17
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
High-Performance Routing Hierarchy
Features and Benefits
•
Segmented, Hierarchical Routing and Clock Structure
Low Power
Advanced I/Os
•
•
•
•
•
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
•
•
•
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
•
•
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Selectable Schmitt Trigger Inputs
•
Small Footprint Packages
•
•
•
•
•
•
•
•
As Small as 3x3 mm in Size
Wide Range of Features
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
•
•
•
10,000 to 250,000 System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 71 User I/Os
IEEE 1149.1 (JTAG) Boundary Scan Test
®
Pin-Compatible Packages across the IGLOO Family
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL†
•
•
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Up to Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
In-System Programming (ISP) and Security
•
•
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except × 18 organization)
†
®
•
•
•
FlashLock Designed to Secure FPGA Contents
1.2 V Programming
Enhanced Commercial Temperature Range
•
Tj = -20°C to +85°C
AGLN010 AGLN0151 AGLN020
AGLN060
AGLN125
AGLN250
IGLOO nano Devices
IGLOO nano-Z Devices
System Gates
1
AGLN030Z1 AGLN060Z1 AGLN125Z1 AGLN250Z1
10,000
15,000
20,000
30,000
60,000
512
1,536
10
125,000
250,000
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
86
260
2
128
384
4
172
520
4
256
768
5
1,024
3,072
16
36
8
2,048
6,144
24
36
8
Flash*Freeze Mode (typical, µW)
2
RAM Kbits (1,024 bits)
–
–
–
–
18
2
4,608-Bit Blocks
–
–
–
–
4
FlashROM Kbits (1,024 bits)
1
1
1
1
1
1
1
2
Secure (AES) ISP
–
–
–
–
Yes
1
Yes
1
Yes
1
2,3
Integrated PLL in CCCs
–
–
–
–
VersaNet Globals
4
4
4
6
18
18
2
18
4
I/O Banks
2
3
3
2
2
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
34
34
49
–
52
52
77
83
71
71
71
68
68
71
Package Pins
UC/CS
UC36
QN48
UC81,
CS81
QN68
UC81, CS81
QN48, QN68
VQ100
CS81
CS81
CS81
QFN
VQFP
QN68
VQ100
VQ100
VQ100
Notes:
1. Not recommended for new designs.
2. AGLN030 and smaller devices do not support this feature.
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets.
† AGLN030 and smaller devices do not support this feature.
June 2013
I
© 2013 Microsemi Corporation
I/Os Per Package
IGLOO nano Devices
AGLN010
AGLN0151 AGLN020
AGLN060
AGLN125
AGLN250
IGLOO nano-Z Devices1
AGLN030Z1 AGLN060Z1 AGLN125Z1 AGLN250Z1
Known Good Die
UC36
34
23
34
–
–
–
52
–
83
–
71
–
71
–
68
–
QN48
–
–
34
49
66
66
77
–
–
–
QN68
49
–
49
52
52
–
–
–
–
UC81
–
–
–
–
CS81
–
–
60
71
60
71
60
68
VQ100
Notes:
–
–
1. Not recommended for new designs.
2. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO datasheet and IGLOO FPGA
Fabric User’s Guide to ensure compliance with design and board migration requirements.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. "G" indicates RoHS-compliant packages. Refer to "IGLOO nano Ordering Information" on page III for the location of the "G" in
the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other
packages are RoHS-compliant only.
Table 1 • IGLOO nano FPGAs Package Sizes Dimensions
Packages
UC36
3 x 3
9
UC81
4 x 4
16
CS81
5 x 5
36
QN48
6 x 6
36
QN68
8 x 8
64
VQ100
14 x 14
196
Length × Width (mm\mm)
Nominal Area (mm2)
Pitch (mm)
0.4
0.4
0.5
0.4
0.4
0.5
Height (mm)
0.80
0.80
0.80
0.90
0.90
1.20
IGLOO nano Device Status
IGLOO nano Devices
Status
IGLOO nano-Z Devices
Status
AGLN010
Production
AGLN015
AGLN020
Not recommended for new designs.
Production
AGLN030Z
AGLN060Z
AGLN125Z
AGLN250Z
Not recommended for new designs.
Not recommended for new designs.
Not recommended for new designs.
Not recommended for new designs.
AGLN060
AGLN125
AGLN250
Production
Production
Production
II
Revision 17
IGLOO nano Low Power Flash FPGAs
IGLOO nano Ordering Information
_
AGLN250
V2
Z
VQ
G
100
Y
I
Application (Temperature Range)
Blank = Enhanced Commercial (–20°C to +85°C Junction Temperature)
I = Industrial (–40°C to +100°C Junction Temperature)
PP= Pre-Production
ES= Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
=
=
=
=
UC
CS
QN
VQ
Micro Chip Scale Package (0.4 mm pitch)
Chip Scale Package (0.5 mm pitch)
Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
Very Thin Quad Flat Pack (0.5 mm pitch)
=
DIELOT Known Good Die
Z = nano devices without enhanced features1
Blank = Standard
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO nano Devices
AGLN010 = 10,000 System Gates
AGLN015 = 15,000 System Gates (AGLN015 is not recommended for new designs)
AGLN020 = 20,000 System Gates
AGLN030 = 30,000 System Gates
AGLN060 = 60,000 System Gates
AGLN125 = 125,000 System Gates
AGLN250 = 250,000 System Gates
Notes:
1. Z-feature grade devices AGLN060Z, AGLN125Z, and AGLN250Z do not support the enhanced nano features of Schmitt Trigger
input, bus hold (hold previous I/O state in Flash*Freeze mode), cold-sparing, hot-swap I/O capability and 1.2 V programming.
The AGLN030 Z feature grade does not support Schmitt trigger input, bus hold and 1.2 V programming. For the VQ100, CS81,
UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device. Z feature grade
devices are not recommended for new designs.
2. AGLN030 is available in the Z feature grade only.
3. Marking Information: IGLOO nano V2 devices do not have a V2 marking, but IGLOO nano V5 devices are marked with a V5
designator.
Devices Not Recommended For New Designs
AGLN015, AGLN030Z, AGLN060Z, AGLN125Z, and AGLN250Z are not recommended for new designs.
Device Marking
Microsemi normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of
the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages
that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of
the device marking will be used that includes the required legal information and as much of the part number as allowed by character
limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such
as the I designator for Industrial Devices or the ES designator for Engineering Samples.
Revision 17
III
Figure 1 shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the device/package
combination ordered.
Country of Origin
ACTELXXX
Device Name
(six characters)
Date Code
AGL030YWW
Package
UCG81XXXX
XXXXXXXX
Customer Mark
(if applicable)
Wafer Lot #
Figure 1 •
Example of Device Marking for Small Form Factor Packages
IGLOO nano Products Available in the Z Feature Grade
IGLOO nano-Z Devices
AGLN030Z*
QN48
AGLN060Z*
AGLN125Z*
AGLN250Z*
–
–
–
–
–
–
QN68
UC81
–
–
–
CS81
CS81
VQ100
CS81
VQ100
CS81
VQ100
Packages
VQ100
Note: *Not recommended for new designs.
Temperature Grade Offerings
AGLN010
AGLN015*
AGLN020
AGLN060
AGLN125
AGLN250
Package
UC36
AGLN030Z*
AGLN060Z*
AGLN125Z*
AGLN250Z*
C, I
C, I
–
–
–
–
–
–
–
–
–
–
–
–
QN48
QN68
UC81
C, I
C, I
C, I
C, I
C, I
C, I
–
C, I
C, I
C, I
–
–
–
–
–
–
–
–
CS81
–
–
C, I
C, I
C, I
C, I
C, I
C, I
VQ100
–
–
Note: * Not recommended for new designs.
C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature
I = Industrial temperature range: –40°C to +100°C junction temperature
Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx.
IV
Revision 17
IGLOO nano Low Power Flash FPGAs
Table of Contents
IGLOO nano Device Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO nano DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Package Pin Assignments
UC36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Revision 17
V
1 – IGLOO nano Device Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low
power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze
technology simplifies power management through I/O and clock management with rapid recovery to
operation mode.
The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO
nano device is completely functional in the system. This allows the IGLOO nano device to control system
power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming
minimal power.
Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low power,
single-chip solution that is Instant On. The IGLOO nano device is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller
devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates, supported
with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.
IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and
packages for greater customer value in high volume consumer, portable, and battery-backed markets.
Features such as smaller footprint packages designed with two-layer PCBs in mind, power consumption
measured in nanoPower, Schmitt trigger, and bus hold (hold previous I/O state in Flash*Freeze mode)
functionality make these devices ideal for deployment in applications that require high levels of flexibility
and low cost.
Flash*Freeze Technology
The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low power Flash*Freeze mode. IGLOO nano devices do not need additional components to turn off
I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO
nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in
power consumption, thus achieving the lowest total system power.
During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,
tristate, HIGH, or LOW.
The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage
solution, and small-footprint packages make IGLOO nano devices the best fit for portable electronics.
Revision 17
1-1
IGLOO nano Device Overview
Flash Advantages
Low Power
Flash-based IGLOO nano devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. IGLOO nano devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO nano devices also have low dynamic power consumption to further maximize power savings;
power is reduced even further by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO nano device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead, advantages
that only an FPGA with nonvolatile flash programming can offer.
IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest
level of security in the FPGA industry for programmed intellectual property and configuration data. In
addition, all FlashROM data in IGLOO nano devices can be encrypted prior to loading, using the
industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the
National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.
IGLOO nano devices have a built-in AES decryption engine and a flash-based AES key that make them
the most comprehensive programmable logic device security solution available today. IGLOO nano
devices with AES-based security provide a high level of protection for remote field updates over public
networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES security, are
unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
with industry-standard security, making remote ISP possible. An IGLOO nano device provides the best
available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO nano
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and
system reliability.
Instant On
Microsemi flash-based IGLOO nano devices support Level 0 of the Instant On classification standard.
This feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.
The Instant On feature of flash-based IGLOO nano devices greatly simplifies total system design and
reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition,
glitches and brownouts in system power will not corrupt the IGLOO nano device's flash configuration,
and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.
This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor,
brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO nano
devices simplify total system design and reduce cost and design risk while increasing system reliability
and improving system initialization time.
IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done
almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike
SRAM-based FPGAs, the device does not need to reload configuration and design state from external
memory components; instead it retains all necessary information to resume operation immediately.
1-2
Revision 17
IGLOO nano Low Power Flash FPGAs
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be Instant On; no
external boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO nano device
architecture mitigates the need for ASIC migration at higher user volumes. This makes IGLOO nano
devices cost-effective ASIC replacement solutions, especially for applications in the consumer,
networking/communications, computing, and avionics markets.
With a variety of devices under $1, IGLOO nano FPGAs enable cost-effective implementation of
programmable logic and quick time to market.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of IGLOO nano flash-based
FPGAs. Once it is programmed, the flash cell configuration element of IGLOO nano FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO nano device offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
IGLOO nano FPGAs utilize design and process techniques to minimize power consumption in all modes
of operation.
Advanced Architecture
The proprietary IGLOO nano architecture provides granularity comparable to standard-cell ASICs. The
IGLOO nano device consists of five distinct and programmable architectural features (Figure 1-3 on
page 1-5 to Figure 1-4 on page 1-5):
•
•
•
•
•
•
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory†
Extensive CCCs and PLLs†
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the IGLOO nano core tile as either a three-input lookup table (LUT)
equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs. VersaTiles are
connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
† The AGLN030 and smaller devices do not support PLL or SRAM.
Revision 17
1-3
IGLOO nano Device Overview
Bank 1*
I/Os
VersaTile
CCC-GL
User Nonvolatile
FlashROM
Flash*Freeze
Technology
Charge
Pumps
Bank 1
Note: *Bank 0 for the AGLN030 device
Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030)
Bank 1
I/Os
VersaTile
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
CCC-GL
Bank 1
Figure 1-2 • IGLOO Device Architecture Overview with Three I/O Banks and No RAM (AGLN015 and
AGLN020)
1-4
Revision 17
IGLOO nano Low Power Flash FPGAs
.
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 1
Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125)
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 2
Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250)
Revision 17
1-5
IGLOO nano Device Overview
Flash*Freeze Technology
The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks
can still be driven and can be toggling without impact on power consumption, and the device retains all
core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their
previous state or be tristated during Flash*Freeze mode.
Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 2 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of entering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
IGLOO nano
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-5 • IGLOO nano Flash*Freeze Mode
VersaTiles
The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®
core tiles. The IGLOO nano VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-6 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-6 • VersaTile Configurations
1-6
Revision 17
IGLOO nano Low Power Flash FPGAs
User Nonvolatile FlashROM
IGLOO nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO nano IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the AGLN030 and smaller devices), as
in security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The IGLOO nano development software solutions, Libero® System-on-Chip (SoC) and Designer, have
extensive support for the FlashROM. One such feature is auto-generation of sequential programming
files for applications requiring a unique serial number in each part. Another feature enables the inclusion
of static data for system version control. Data for the FlashROM can be generated quickly and easily
using Microsemi Libero SoC and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOO nano devices (except the AGLN030 and smaller devices) have embedded SRAM blocks along
their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have
independent read and write ports that can be configured with different bit widths on each port. For
example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM
blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro
(except in the AGLN030 and smaller devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures provide
designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and AGLN250 contain
six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices use different
CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not have any PLLs
or programmable delays.
For devices using the six CCC block architecture, these are located at the four corners and the centers of
the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow
simple clock delay operations as well as clock spine access.
Revision 17
1-7
IGLOO nano Device Overview
The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to
the CCC block, which are located near the CCC.
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
•
•
•
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
OUT_CCC (for PLL only)
Global Clocking
IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.2 V wide
range, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V).
The I/Os are organized into banks with two, three, or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of various single-data-rate applications for all versions of nano devices and double-data-
rate applications for the AGLN060, AGLN125, and AGLN250 devices.
IGLOO nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support cold-
sparing and Schmitt trigger.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
IGLOO nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support
both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of
2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to
1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
1-8
Revision 17
IGLOO nano Low Power Flash FPGAs
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-7 on page 1-9).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
Figure 1-7 • I/O States During Programming Window
Revision 17
1-9
IGLOO nano Device Overview
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
1-10
Revision 17
2 – IGLOO nano DC and Switching Characteristics
General Specifications
The Z feature grade does not support the enhanced nano features of Schmitt trigger input, Flash*Freeze
bus hold (hold previous I/O state in Flash*Freeze mode), cold-sparing, and hot-swap I/O capability. Refer
to "IGLOO nano Ordering Information" on page III for more information.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
Limits
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
–0.3 V to 3.6 V
–65 to +150
+125
Units
V
VJTAG
VPUMP
VCCPLL
VCCI
JTAG DC voltage
V
Programming voltage
Analog power supply (PLL)
DC I/O buffer supply voltage
I/O input voltage
V
V
V
VI1
V
2
TSTG
Storage temperature
Junction temperature
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 17
2-1
IGLOO nano DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 1
Extended
Symbol
TJ
Parameter
Commercial
Industrial
–40 to +1002
1.425 to 1.575
1.14 to 1.575
1.4 to 3.6
Units
°C
V
Junction temperature
–20 to + 852
1.425 to 1.575
1.14 to 1.575
1.4 to 3.6
VCC
1.5 V DC core supply voltage3
1.2 V–1.5 V wide range core voltage4,5
JTAG DC voltage
V
VJTAG
V
VPUMP 6 Programming voltage Programming mode
3.15 to 3.45
0 to 3.6
3.15 to 3.45
0 to 3.6
V
Operation
V
VCCPLL7 Analog power supply 1.5 V DC core supply voltage3
1.425 to 1.575
1.14 to 1.575
1.425 to 1.575
1.14 to 1.575
V
(PLL)
1.2 V–1.5 V wide range core
V
supply voltage4
VCCI and 1.2 V DC supply voltage 4
1.14 to 1.26
1.14 to 1.575
1.425 to 1.575
1.7 to 1.9
1.14 to 1.26
1.14 to 1.575
1.425 to 1.575
1.7 to 1.9
V
V
V
V
V
V
V
VMV 8,9
1.2 V DC wide range supply voltage 4
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
3.3 V DC wide range supply voltage 10
Notes:
2.3 to 2.7
2.3 to 2.7
3.0 to 3.6
3.0 to 3.6
2.7 to 3.6
2.7 to 3.6
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to
+85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures,
Microsemi recommends using custom settings for temperature range before running timing and power analysis tools.
For more information regarding custom settings, refer to the New Project Dialog Box in the Libero Online Help.
®
3. For IGLOO nano V5 devices
4. For IGLOO nano V2 devices only, operating at VCCI VCC
5. IGLOO nano V5 devices can be programmed with the VCC core voltage at 1.5 V only. IGLOO nano V2 devices can be
programmed with the VCC core voltage at 1.2 V (with FlashPro4 only) or 1.5 V. If you are using FlashPro3 and want to
do in-system programming using 1.2 V, please contact the factory.
6.
V
can be left floating during operation (not programming mode).
PUMP
7. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter for further information.
8. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter of the IGLOO nano
FPGA Fabric User’s Guide for further information.
9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank.
10. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
Maximum Storage
Maximum Operating Junction
Temperature TJ (°C) 2
(biased/unbiased) Temperature TSTG (°C) 2
Commercial
Industrial
Notes:
500
500
20 years
20 years
110
110
100
100
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 17
IGLOO nano Low Power Flash FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or
Undershoot Duration
Maximum Overshoot/
Undershoot2
VCCI
as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO nano device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4.
There are five regions to consider during power-up.
IGLOO nano I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on
page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
VCC Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Revision 17
2-3
IGLOO nano DC and Switching Characteristics
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes LOW and/or the
output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the IGLOO nano FPGA Fabric User’s Guide for information on clock
and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 4: I/O
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 1: I/O Buffers are OFF
buffers are ON.
I/Os are functional
I/Os meet the entire datasheet
but slower because VCCI
and timer specifications for
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
speed, VIH / VIL , VOH / VOL , etc.
buffers do not meet VOH/VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
I/Os are functional but slower because
VCCI / VCC are below specification. For the
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
same reason, input buffers do not meet
VIH/VIL levels, and output buffers to not
meet VOH / VOL levels.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
VCCI
Activation trip point:
Min VCCI datasheet specification
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Revision 17
IGLOO nano Low Power Flash FPGAs
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
V
= 1.575 V
CC
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
Region 1: I/O Buffers are OFF
buffers are ON.
I/Os are functional
I/Os meet the entire datasheet
but slower because VCCI
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
I/Os are functional but slower because
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCCI / VCC are below specification. For the
same reason, input buffers do not meet
VIH / VIL levels, and output buffers do not
meet VOH/VOL levels.
Activation trip point:
V = 0.85 V ± 0.2 V
a
Deactivation trip point:
Region 1: I/O buffers are OFF
V
= 0.75 V ± 0.2 V
d
VCCI
Min VCCI datasheet specification
Activation trip point:
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
V = 0.9 V ± 0.15 V
Deactivation trip point:
a
V
= 0.8 V ± 0.15 V
d
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Revision 17
2-5
IGLOO nano DC and Switching Characteristics
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction temperature to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction
temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C
------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------
Maximum Power Allowed =
=
= 1.46 W
EQ 2
ja(C/W)
20.5°C/W
Table 2-5 • Package Thermal Resistivities
ja
Pin
Count
200 ft./
min.
500 ft./
Package Type
jc
Still Air
TBD
min.
TBD
TBD
TBD
TBD
TBD
27.1
Units
Chip Scale Package (CSP)
36
81
TBD
TBD
TBD
TBD
TBD
10.0
TBD
TBD
TBD
TBD
TBD
29.4
C/W
C/W
C/W
C/W
C/W
C/W
TBD
Quad Flat No Lead (QFN)
48
TBD
68
TBD
100
100
TBD
Very Thin Quad Flat Pack (VQFP)
35.3
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.425 V)
For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.425
1.5
–40°C
0.947
0.875
0.821
–20°C
0.956
0.883
0.829
0°C
25°C
0.978
0.904
0.848
70°C
1.000
0.925
0.868
85°C
1.009
0.932
0.875
100°C
1.013
0.937
0.879
0.965
0.892
0.837
1.575
2-6
Revision 17
IGLOO nano Low Power Flash FPGAs
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.14 V)
For IGLOO nano V2, 1.2 V DC Core Supply Voltage
Junction Temperature (°C)
0°C 25°C 70°C
Array Voltage
VCC (V)
–40°C
0.968
0.863
0.792
–20°C
0.974
0.868
0.797
85°C
1.006
0.898
0.824
100°C
1.009
0.901
0.827
1.14
0.979
0.873
0.801
0.991
0.884
0.811
1.000
0.892
0.819
1.2
1.26
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages
(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage.
Microsemi recommends using the Power Calculator and SmartPower software estimation tools to
evaluate the projected static and active power based on the user design, power mode usage, operating
voltage, and temperature.
Table 2-8 • Power Supply State per Mode
Power Supply Configurations
Modes/Power Supplies
Flash*Freeze
VCC
On
VCCPLL
VCCI
On
VJTAG
VPUMP
On/off/floating
Off
On
Off
Off
On
On
Off
Off
On
Sleep
Off
On
Shutdown
Off
Off
Off
No Flash*Freeze
Note: Off: Power Supply level = 0 V
On
On
On/off/floating
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*
Core
Voltage
AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units
Typical (25°C)
1.2 V
1.9
5.8
3.3
6
3.3
6
8
13
18
20
34
µA
µA
1.5 V
10
Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution,
which is shown in Table 2-13 on page 2-9 through Table 2-14 on page 2-9 and Table 2-15 on page 2-10
through Table 2-18 on page 2-11 (PDC6 and PDC7).
Revision 17
2-7
IGLOO nano DC and Switching Characteristics
Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*
Core
Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units
VCCI= 1.2 V (per bank) 1.2 V
Typical (25°C)
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI
Typical (25°C)
=
1.5 V (per bank) 1.2 V /
1.5 V
VCCI = 1.8 V (per bank) 1.2 V /
Typical (25°C) 1.5 V
VCCI = 2.5 V (per bank) 1.2 V /
Typical (25°C) 1.5 V
VCCI = 3.3 V (per bank) 1.2 V /
Typical (25°C)
1.5 V
Note: *IDD = NBANKS * ICCI
.
Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode
Core Voltage AGLN010 AGLN015 AGLN020 AGLN060
1.2 V / 1.5 V
AGLN125
AGLN250
Units
Typical
(25°C)
0
0
0
0
0
0
µA
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1
Core
Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units
ICCA Current2
Typical (25°C)
1.2 V
1.5 V
3.7
8
5
5
10
20
13
28
18
44
µA
µA
14
14
ICCI or IJTAG Current
VCCI / VJTAG = 1.2 V (per
bank) Typical (25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI / VJTAG = 1.5 V (per 1.2 V / 1.5 V
bank) Typical (25°C)
VCCI / VJTAG = 1.8 V (per 1.2 V / 1.5 V
bank) Typical (25°C)
VCCI / VJTAG = 2.5 V (per 1.2 V / 1.5 V
bank) Typical (25°C)
VCCI / VJTAG = 3.3 V (per 1.2 V / 1.5 V
bank) Typical (25°C)
Notes:
1. IDD = N
* ICCI + ICCA. JTAG counts as one bank when powered.
BANKS
2. Includes VCC, VCCPLL, and VPUMP currents.
2-8
Revision 17
IGLOO nano Low Power Flash FPGAs
Power per I/O Pin
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to IGLOO nano I/O Banks
Dynamic Power
VCCI (V)
PAC9 (µW/MHz) 1
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3 V LVCMOS Wide Range2
3.3 V LVCMOS Wide Range – Schmitt Trigger
2.5 V LVCMOS
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
1.2
1.2
16.38
18.89
16.38
18.89
4.71
6.13
1.64
1.79
0.97
0.96
0.57
0.52
0.57
0.52
2.5 V LVCMOS – Schmitt Trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt Trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.2 V LVCMOS3
1.2 V LVCMOS – Schmitt Trigger3
1.2 V LVCMOS Wide Range3
1.2 V LVCMOS Wide Range – Schmitt Trigger3
Notes:
1. PAC9 is the total dynamic power measured on V
.
CCI
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to IGLOO nano I/O Banks
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
5
5
5
5
5
5
3.3
3.3
2.5
1.8
1.5
1.2
107.98
107.98
61.24
31.28
21.50
15.22
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS4
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PAC10 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4. Applicable for IGLOO nano V2 devices operating at VCCI VCC.
Revision 17
2-9
IGLOO nano DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Device Specific Dynamic Power (µW/MHz)
Parameter
PAC1
Definition
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
Clock contribution of a Global Rib
Clock contribution of a Global Spine
4.421
2.704
4.493
1.976
1.504
0.153
2.700
1.982
1.511
0.153
0
0
0
PAC2
4.002
1.346
0.148
4.002
1.346
0.148
2.633
1.340
0.143
PAC3
Clock contribution of a VersaTile row 1.496
PAC4
Clock contribution of a VersaTile 0.152
used as a sequential module
PAC5
PAC6
PAC7
First contribution of a VersaTile used
as a sequential module
0.057
Second contribution of a VersaTile
used as a sequential module
0.207
0.17
0.7
Contribution of a VersaTile used as
a combinatorial module
PAC8
PAC9
Average contribution of a routing net
Contribution of an I/O input pin
(standard-dependent)
See Table 2-13 on page 2-9.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O output pin
(standard-dependent)
See Table 2-14.
Average contribution of a RAM block
during a read operation
25.00
30.00
2.70
N/A
N/A
N/A
Average contribution of a RAM block
during a write operation
Dynamic contribution for PLL
Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Device -Specific Static Power (mW)
Parameter
PDC1
Definition
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
See Table 2-12 on page 2-8
Array static power in Active mode
PDC2
Array static power in Static (Idle)
mode
See Table 2-12 on page 2-8
PDC3
Array static power in Flash*Freeze
mode
See Table 2-9 on page 2-7
PDC4 1
PDC5
Static PLL contribution
1.84
N/A
Bank quiescent power
(VCCI-dependent)2
See Table 2-12 on page 2-8
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or the SmartPower tool in Libero SoC.
2-10
Revision 17
IGLOO nano Low Power Flash FPGAs
Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Dynamic Power (µW/MHz)
Parameter
PAC1
Definition
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
2.829
1.731
0.957
2.875
1.265
0.963
0.098
1.728
1.268
0.967
0.098
0
0
0
PAC2
2.562
0.862
0.094
2.562
0.862
0.094
1.685
0.858
0.091
PAC3
PAC4
Clock contribution of a VersaTile used 0.098
as a sequential module
PAC5
PAC6
PAC7
First contribution of a VersaTile used
as a sequential module
0.045
Second contribution of a VersaTile
used as a sequential module
0.186
0.11
Contribution of a VersaTile used as a
combinatorial module
PAC8
PAC9
Average contribution of a routing net
0.45
Contribution of an I/O input pin
(standard-dependent)
See Table 2-13 on page 2-9
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O output pin
(standard-dependent)
See Table 2-14 on page 2-9
Average contribution of a RAM block
during a read operation
25.00
N/A
N/A
N/A
Average contribution of a RAM block
during a write operation
30.00
2.10
Dynamic contribution for PLL
Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
PDC1
Definition
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
See Table 2-12 on page 2-8
Array static power in Active mode
PDC2
Array static power in Static (Idle)
mode
See Table 2-12 on page 2-8
PDC3
Array static power in Flash*Freeze
mode
See Table 2-9 on page 2-7
PDC4 1
PDC5
Static PLL contribution
0.90
N/A
Bank quiescent power
(VCCI-dependent)2
See Table 2-12 on page 2-8
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or the SmartPower tool in Libero SoC.
Revision 17
2-11
IGLOO nano DC and Switching Characteristics
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on
page 2-14.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on
page 2-14.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
the "Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
F
N
Sequential Cells Contribution—P
S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
2-12
Revision 17
IGLOO nano Low Power Flash FPGAs
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
F
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on
page 2-14.
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
Revision 17
2-13
IGLOO nano DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
1
2
10%
Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
1
2
3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
2-14
Revision 17
IGLOO nano Low Power Flash FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVCMOS 2.5 V Output Drive
Strength = 8 mA High Slew Rate
t
= 1.18 ns
t
= 0.90 ns
PD
PD
t
= 1.99 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 4 mA
High slew rate
LVTTL
t
= 2.35 ns
DP
t
= 1.60 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
Output drive strength = 8 mA
High slew rate
LVTTL
t
= 1.06 ns
PY
t
= 1.96 ns
DP
t
= 1.17 ns
PD
I/O Module
(Non-Registered)
Input LVCMOS 2.5 V
D
Q
Combinational Cell
Y
Output drive strength = 2 mA
High slew rate
LVCMOS 1.5 V
t
t
= 0.42 ns
= 0.47 ns
ICLKQ
ISUD
t
= 2.65 ns
DP
t
= 0.87 ns
PD
Input LVTTL
Clock
I/O Module
Register Cell
(Registered)
Register Cell
Combinational Cell
Y
t
= 0.85 ns
PY
D
Q
D
Q
D
t
Q
LVTTL 3.3 V Output drive
strength = 8 mA High slew rate
I/O Module
t
= 0.91 ns
PD
t
= 1.96 ns
(Non-Registered)
DP
t
t
= 0.89 ns
= 0.81 ns
= 1.00 ns
= 0.51 ns
CLKQ
SUD
t
t
= 0.89 ns
= 0.81 ns
OCLKQ
CLKQ
t
LVCMOS 1.5 V
OSUD
SUD
Input LVTTL
Clock
Input LVTTL
Clock
t
= 1.15 ns
PY
t
= 0.85 ns
t
= 0.85 ns
PY
PY
Figure 2-3 • Timing Model
Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
Revision 17
2-15
IGLOO nano DC and Switching Characteristics
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
t
t
PY = MAX(tPY(R), tPY(F))
DIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
2-16
Revision 17
IGLOO nano Low Power Flash FPGAs
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
Revision 17
2-17
IGLOO nano DC and Switching Characteristics
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
2-18
Revision 17
IGLOO nano Low Power Flash FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
Equivalent
Software
Default
VIL
VIH
VOL
VOH
IOL1 IOH1
Drive
Drive
Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard
Strength Strength2 Rate
V
mA mA
3.3 V LVTTL /
3.3 V LVCMOS
8 mA
8 mA
8 mA
High –0.3
High –0.3
High –0.3
0.8
2
3.6
3.6
3.6
0.4
2.4
8
8
3.3 V LVCMOS 100 µA
Wide Range3
0.8
0.7
2
0.2
VCCI – 0.2 100 100
µA µA
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
8 mA
4 mA
2 mA
8 mA
4 mA
2 mA
1 mA
1 mA
1.7
0.7
1.7
8
4
2
1
8
4
2
1
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
1.2 V LVCMOS4 1 mA
1.2 V LVCMOS 100 µA
Wide Range4,5
High –0.3 0.3 * VCCI 0.7 * VCCI 3.6
0.1
VCCI – 0.1 100 100
µA µA
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
4. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range, as specified in the JESD8-12 specification.
Table 2-22 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL 3
µA
10
10
10
10
10
10
10
IIH 4
µA
10
IIL 3
µA
15
15
15
15
15
15
15
IIH 4
µA
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCOMS Wide Range
2.5 V LVCMOS
10
15
10
15
1.8 V LVCMOS
10
15
1.5 V LVCMOS
1.2 V LVCMOS5
1.2 V LVCMOS Wide Range5
10
15
10
15
10
15
Notes:
1. Commercial range (–20°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3.
I
is the input leakage current per I/O pin over recommended operating conditions, where VIH < VIN < VCCI. Input
IH
current is larger when operating outside recommended ranges.
4.
I
is the input leakage current per I/O pin over recommended operating conditions, where –0.3 V < VIN < VIL.
IL
5. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
Revision 17
2-19
IGLOO nano DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-23 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.4 V
1.4 V
1.2 V
1.8 V LVCMOS
0.90 V
0.75 V
0.60 V
0.60 V
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Table 2-24 • I/O AC Parameter Definitions
Parameter
Parameter Definition
Data to Pad delay through the Output Buffer
tDP
tPY
Pad to Data delay through the Input Buffer
tDOUT
tEOUT
tDIN
tHZ
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
tZH
tLZ
tZL
Enable to Pad delay through the Output Buffer—Z to LOW
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
2-20
Revision 17
IGLOO nano Low Power Flash FPGAs
Applies to IGLOO nano at 1.5 V Core Operating Conditions
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
8 mA 8 mA High 5 pF 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns
3.3 V LVCMOS
3.3 V LVCMOS 100 µA 8 mA High 5 pF 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns
Wide Range2
2.5 V LVCMOS 8 mA 8 mA High 5 pF 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns
1.8 V LVCMOS 4 mA 4 mA High 5 pF 0.97 2.08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns
1.5 V LVCMOS 2 mA 2 mA High 5 pF 0.97 2.39 0.19 1.19 1.52 0.66 2.44 2.24 2.02 2.15 ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-21
IGLOO nano DC and Switching Characteristics
Applies to IGLOO nano at 1.2 V Core Operating Conditions
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
8 mA 8 mA High 5 pF 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns
3.3 V LVCMOS
3.3 V LVCMOS 100 µA 8 mA High 5 pF 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns
Wide Range2
2.5 V LVCMOS 8 mA 8 mA High 5 pF 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns
1.8 V LVCMOS 4 mA 4 mA High 5 pF 1.55 2.49 0.26 1.13 1.59 1.10 2.53 2.34 2.42 2.81 ns
1.5 V LVCMOS 2 mA 2 mA High 5 pF 1.55 2.78 0.26 1.27 1.77 1.10 2.82 2.62 2.44 2.74 ns
1.2 V LVCMOS 1 mA 1 mA High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns
1.2 V LVCMOS 100 µA 1 mA High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns
Wide Range3
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to
the IBIS models..
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V side range as specified in the JESD8-12 specification.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-22
Revision 17
IGLOO nano Low Power Flash FPGAs
Detailed I/O DC Characteristics
Table 2-27 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min.
Max.
Units
pF
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
Table 2-28 • I/O Output Buffer Maximum Resistances 1
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
()2
()3
3.3 V LVTTL / 3.3V LVCMOS
100
100
50
300
300
150
150
4 mA
6 mA
8 mA
50
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
100 µA
2 mA
Same as equivalent software default drive
100
100
50
200
200
100
100
225
112
224
315
315
4 mA
6 mA
8 mA
50
1.8 V LVCMOS
2 mA
200
100
200
315
315
4 mA
1.5 V LVCMOS
2 mA
1.2 V LVCMOS 4
1.2 V LVCMOS Wide Range 4
Notes:
1 mA
100 µA
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
3.
R
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
4. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
Revision 17
2-23
IGLOO nano DC and Switching Characteristics
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 ()
Min.
VCCI
Max.
45 K
45 K
55 K
70 K
90 K
110 K
110 K
Min.
Max.
45 K
3.3 V
10 K
10 K
11 K
18 K
19 K
25 K
19 K
10 K
10 K
12 K
17 K
19 K
25 K
19 K
3.3 V (wide range I/Os)
45 K
2.5 V
74 K
1.8 V
110 K
140 K
150 K
150 K
1.5 V
1.2 V
1.2 V (wide range I/Os)
Notes:
1.
2.
R
R
= (VCCImax – VOHspec) / I
)
(WEAK PULL-UP-MAX)
(WEAK PULL-UP-MIN
= (VOLspec) / I
(WEAK PULL-DOWN-MAX)
(WEAK PULL-DOWN-MIN)
Table 2-30 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
25
25
51
51
27
27
54
54
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
100 µA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
1 mA
100 µA
Same as equivalent software default drive
16
16
32
32
9
18
18
37
37
11
22
16
13
13
1.8 V LVCMOS
17
13
10
10
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Note: *TJ = 100°C
2-24
Revision 17
IGLOO nano Low Power Flash FPGAs
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-31 • Duration of Short Circuit Event before Failure
Temperature
–40°C
–20°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
6 months
Table 2-32 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
240 mV
140 mV
80 mV
60 mV
40 mV
Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Rise/Fall
Time (min.)
Input Rise/Fall Time
(max.)
Input Buffer
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but
input noise voltage
cannot exceed Schmitt
hysteresis.
20 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board
noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure
that there is no excessive noise coupling into input signals.
Revision 17
2-25
IGLOO nano DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-34 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL 1 IIH 2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
2
2
2
2
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2
4
6
8
2
25
25
51
51
27
27
54
54
4
6
8
1.
2.
I
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IL
IH
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-35 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
2-26
Revision 17
IGLOO nano Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 3.52 0.19 0.86 1.16
0.97 3.52 0.19 0.86 1.16
0.97 2.90 0.19 0.86 1.16
0.97 2.90 0.19 0.86 1.16
0.66 3.59 3.42 1.75 1.90
0.66 3.59 3.42 1.75 1.90
0.66 2.96 2.83 1.98 2.29
0.66 2.96 2.83 1.98 2.29
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 2.16 0.19 0.86 1.16
0.97 2.16 0.19 0.86 1.16
0.97 1.79 0.19 0.86 1.16
0.97 1.79 0.19 0.86 1.16
0.66 2.20 1.80 1.75 1.99
0.66 2.20 1.80 1.75 1.99
0.66 1.83 1.45 1.98 2.38
0.66 1.83 1.45 1.98 2.38
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-27
IGLOO nano DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
1.55 4.09 0.26 0.97 1.36
1.55 4.09 0.26 0.97 1.36
1.55 3.45 0.26 0.97 1.36
1.55 3.45 0.26 0.97 1.36
1.10 4.16 3.91 2.19 2.64
1.10 4.16 3.91 2.19 2.64
1.10 3.51 3.32 2.43 3.03
1.10 3.51 3.32 2.43 3.03
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
1.55 2.68 0.26 0.97 1.36
1.55 2.68 0.26 0.97 1.36
1.55 2.31 0.26 0.97 1.36
1.55 2.31 0.26 0.97 1.36
1.10 2.72 2.26 2.19 2.74
1.10 2.72 2.26 2.19 2.74
1.10 2.34 1.90 2.43 3.14
1.10 2.34 1.90 2.43 3.14
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-28
Revision 17
IGLOO nano Low Power Flash FPGAs
3.3 V LVCMOS Wide Range
Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
3.3 V LVCMOS Equivalent
Wide Range1
Software
Default
VIL
VIH
VOL
VOH
IOL
IOH IIL 2 IIH 3
Drive
Drive
Strength
Strength Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Option4
V
µA
µA µA5 µA5
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
2
2
2
2
3.6
3.6
3.6
3.6
0.2
0.2
0.2
0.2
VCCI – 0.2 100
VCCI – 0.2 100
VCCI – 0.2 100
VCCI – 0.2 100
100
100
100
100
10
10
10
10
10
10
10
10
4 mA
6 mA
8 mA
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B
specification.
2.
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
IL
3.
I
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IH
current is larger when operating outside recommended ranges.
4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
5. Currents are measured at 85°C junction temperature.
6. Software default selection is highlighted in gray.
Revision 17
2-29
IGLOO nano DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS
tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
STD
STD
STD
STD
0.97
0.97
0.97
0.97
5.23 0.19 1.20 1.66
5.23 0.19 1.20 1.66
4.27 0.19 1.20 1.66
4.27 0.19 1.20 1.66
0.66 5.24 5.00 2.47 2.56
0.66 5.24 5.00 2.47 2.56
0.66 4.28 4.12 2.83 3.16
0.66 4.28 4.12 2.83 3.16
ns
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-42 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
STD
STD
STD
STD
0.97
0.97
0.97
0.97
3.11 0.19 1.20 1.66
3.11 0.19 1.20 1.66
2.56 0.19 1.20 1.66
2.56 0.19 1.20 1.66
0.66 3.13 2.55 2.47 2.70
0.66 3.13 2.55 2.47 2.70
0.66 2.57 2.02 2.82 3.31
0.66 2.57 2.02 2.82 3.31
ns
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
2-30
Revision 17
IGLOO nano Low Power Flash FPGAs
Applies to 1.2 V DC Core Voltage
Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS
tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
STD
STD
STD
STD
1.55
1.55
1.55
1.55
6.01 0.26 1.31 1.91
6.01 0.26 1.31 1.91
5.02 0.26 1.31 1.91
5.02 0.26 1.31 1.91
1.10 6.01 5.66 3.02 3.49
1.10 6.01 5.66 3.02 3.49
1.10 5.02 4.76 3.38 4.10
1.10 5.02 4.76 3.38 4.10
ns
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-44 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
STD
STD
STD
STD
1.55
1.55
1.55
1.55
3.82 0.26 1.31 1.91
3.82 0.26 1.31 1.91
3.25 0.26 1.31 1.91
3.25 0.26 1.31 1.91
1.10 3.82 3.15 3.01 3.65
1.10 3.82 3.15 3.01 3.65
1.10 3.25 2.61 3.38 4.27
1.10 3.25 2.61 3.38 4.27
ns
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
Revision 17
2-31
IGLOO nano DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 2.5 V applications.
Table 2-45 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL 1 IIH 2
Drive
Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 µA4 µA4
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
2
2
16
16
32
32
18
18
37
37
10 10
10 10
10 10
10 10
4
4
6
6
8
8
1.
2.
I
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IL
IH
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-46 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
2-32
Revision 17
IGLOO nano Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
STD
STD
STD
STD
0.97 4.13 0.19 1.10 1.24
0.97 4.13 0.19 1.10 1.24
0.97 3.39 0.19 1.10 1.24
0.97 3.39 0.19 1.10 1.24
0.66 4.01 4.13 1.73 1.74
0.66 4.01 4.13 1.73 1.74
0.66 3.31 3.39 1.98 2.19
0.66 3.31 3.39 1.98 2.19
ns
ns
ns
ns
4 mA
8 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-48 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 2.19 0.19 1.10 1.24
0.97 2.19 0.19 1.10 1.24
0.97 1.81 0.19 1.10 1.24
0.97 1.81 0.19 1.10 1.24
0.66 2.23 2.11 1.72 1.80
0.66 2.23 2.11 1.72 1.80
0.66 1.85 1.63 1.97 2.26
0.66 1.85 1.63 1.97 2.26
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-33
IGLOO nano DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-49 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
1.55 4.61 0.26 1.21 1.39
1.55 4.61 0.26 1.21 1.39
1.55 3.86 0.26 1.21 1.39
1.55 3.86 0.26 1.21 1.39
1.10 4.55 4.61 2.15 2.43
1.10 4.55 4.61 2.15 2.43
1.10 3.82 3.86 2.41 2.89
1.10 3.82 3.86 2.41 2.89
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-50 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
1.55 2.68 0.26 1.21 1.39
1.55 2.68 0.26 1.21 1.39
1.55 2.30 0.26 1.21 1.39
1.55 2.30 0.26 1.21 1.39
1.10 2.72 2.54 2.15 2.51
1.10 2.72 2.54 2.15 2.51
1.10 2.33 2.04 2.41 2.99
1.10 2.33 2.04 2.41 2.99
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-34
Revision 17
IGLOO nano Low Power Flash FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-51 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL 1 IIH 2
Drive
Strength
Min.
V
Min.
V
Max. Max.
Min.
V
Max.
mA3
Max.
mA3
V
V
V
µA4 µA4
10 10
10 10
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
2
4
9
11
22
17
1.
2.
I
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IL
IH
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-52 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
Revision 17
2-35
IGLOO nano DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-53 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
Units
ns
STD
STD
0.97 5.44 0.19 1.03 1.44
0.97 4.44 0.19 1.03 1.44
0.66 5.25 5.44 1.69 1.35
0.66 4.37 4.44 1.99 2.11
4 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-54 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.97 2.64 0.19 1.03 1.44
0.97 2.08 0.19 1.03 1.44
0.66 2.59 2.64 1.69 1.40
0.66 2.12 1.95 1.99 2.19
ns
ns
4 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Applies to 1.2 V DC Core Voltage
Table 2-55 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
STD
STD
1.55 5.92 0.26 1.13 1.59
1.55 4.91 0.26 1.13 1.59
1.10 5.72 5.92 2.11 1.95
1.10 4.82 4.91 2.42 2.73
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-56 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
1.55 3.05 0.26 1.13 1.59
1.55 2.49 0.26 1.13 1.59
1.10 3.01 3.05 2.10 2.00
1.10 2.53 2.34 2.42 2.81
ns
ns
4 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-36
Revision 17
IGLOO nano Low Power Flash FPGAs
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH IOSL
IOSH IIL 1 IIH 2
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
V
mA mA mA3
mA3 µA4 µA4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
2
2
13
16
10 10
Notes:
1.
I is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
IL
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-58 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
Revision 17
2-37
IGLOO nano DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-59 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
2 mA
STD 0.97 5.39 0.19 1.19 1.62
0.66 5.48 5.39 2.02 2.06
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-60 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
STD 0.97 2.39 0.19 1.19 1.62
0.66 2.44 2.24 2.02 2.15
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Applies to 1.2 V DC Core Voltage
Table 2-61 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
2 mA
STD 1.55 5.87 0.26 1.27 1.77
1.10 5.92 5.87 2.45 2.65
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-62 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
STD 1.55 2.78 0.26 1.27 1.77
1.10 2.82 2.62 2.44 2.74
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-38
Revision 17
IGLOO nano Low Power Flash FPGAs
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-63 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH IOSL IOSH IIL 1 IIH 2
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
V
mA mA mA3
mA3 µA4 µA4
1 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
1
1
10
13
10 10
Notes:
1.
2.
I
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IL
IH
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-11 • AC Loading
Table 2-64 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-65 • 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade tDOUT
STD 1.55
tDP
tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
1 mA
8.30 0.26 1.56 2.27
1.10 7.97 7.54 2.56 2.55
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-66 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
1 mA
STD 1.55 3.50 0.26 1.56 2.27
1.10 3.37 3.10 2.55 2.66
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-39
IGLOO nano DC and Switching Characteristics
1.2 V LVCMOS Wide Range
Table 2-67 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS
Wide
Range
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH IIL 1 IIH 2
Max.
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
V
V
mA3
µA4 µA4
1 mA
–0.3 0.3 * VCCI 0.7 * VCCI 3.6
0.1
VCCI – 0.1 100 100
10
13
10 10
Notes:
1.
2.
I
I
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
IL
IH
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
6. Software default selection highlighted in gray.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-68 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS
tEOUT tZL
tZH
tLZ
tHZ Units
ns
100 µA
1 mA
STD
1.55 8.30 0.26 1.56 2.27
1.10 7.97 7.54 2.56 2.55
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-69 • 1.2 V LVCMOS Wide Range HIgh Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Grade
Strength Option1
tDOUT tDP
tDIN
tPY
tPYS
tEOUT tZL
tZH
tLZ
tHZ Units
ns
100 µA
1 mA
STD
1.55 3.50 0.26 1.56 2.27
1.10 3.37 3.10 2.55 2.66
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
2-40
Revision 17
IGLOO nano Low Power Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Asynchronous Preset
Preset
Data
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
D
Q
D
Q
C
DFN1P1
DFN1P1
EOUT
H
I
CLK
A
PRE
J
D
Q
DFN1P1
Data Input I/O Register with:
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Preset
Postive-Edge Triggered
CLKBUF
INBUF
Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset
Revision 17
2-41
IGLOO nano DC and Switching Characteristics
Table 2-70 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
J, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
tIREMPRE
tIRECPRE
D, A
D, A
Note: *See Figure 2-12 on page 2-41 for more information.
2-42
Revision 17
IGLOO nano Low Power Flash FPGAs
Fully Registered I/O Buffers with Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1C1
DFN1C1
EOUT
CLR
CLR
LL
HH
CLK
CLR
AA
DD
JJ
D
Q
DFN1C1
Data Input I/O Register with
Active High Clear
CLR
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Clear
Positive-Edge Triggered
INBUF
CLKBUF
Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear
Revision 17
2-43
IGLOO nano DC and Switching Characteristics
Table 2-71 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
FF, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
JJ, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
tIREMCLR
tIRECCLR
Note: *See Figure 2-13 on page 2-43 for more information.
2-44
Revision 17
IGLOO nano Low Power Flash FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
1
CLK
Data
tIHD
50%
50%
tIWPRE
0
tIREMPRE
tIRECPRE
Preset
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-14 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-72 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Std. Units
Clock-to-Q of the Input Data Register
0.42
0.47
0.00
0.79
0.79
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-45
IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-73 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
Std. Units
0.68
0.97
0.00
1.19
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-46
Revision 17
IGLOO nano Low Power Flash FPGAs
Output Register
t
t
OCKMPWH OCKMPWL
50%
t
50%
50%
50%
50%
50%
50%
CLK
t
OSUD OHD
50%
50%
t
1
0
Data_out
Preset
t
OREMPRE
t
OWPRE
ORECPRE
50%
50%
50%
t
t
OREMCLR
t
ORECCLR
OWCLR
50%
50%
50%
Clear
t
OPRE2Q
50%
50%
50%
DOUT
t
OCLR2Q
t
OCLKQ
Figure 2-15 • Output Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-74 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Std. Units
Clock-to-Q of the Output Data Register
1.00
0.51
0.00
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-47
IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-75 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
Std. Units
1.52
1.15
0.00
1.96
1.96
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
tOWPRE
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-48
Revision 17
IGLOO nano Low Power Flash FPGAs
Output Enable Register
t
t
OECKMPWH OECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OESUD OEHD
50%
50%
0
1
D_Enable
t
t
OEWPRE
OEREMPRE
t
OERECPRE
50%
50%
50%
Preset
Clear
t
t
t
OERECCLR
OEREMCLR
OEWCLR
50%
50%
50%
t
t
OECLR2Q
OEPRE2Q
50%
50%
50%
EOUT
t
OECLKQ
Figure 2-16 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-76 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
Description
Std. Units
Clock-to-Q of the Output Enable Register
0.75
0.51
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-49
IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-77 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOECLKQ
Description
Clock-to-Q of the Output Enable Register
Std. Units
1.10
1.15
0.00
1.65
1.65
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-50
Revision 17
IGLOO nano Low Power Flash FPGAs
DDR Module Specifications
Note: DDR is not supported for AGLN010, AGLN015, and AGLN020 devices.
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
C
E
Out_QR
(to core)
CLK
CLKBUF
INBUF
FF2
CLR
DDR_IN
Figure 2-17 • Input DDR Timing Model
Table 2-78 • Parameter Definitions
Parameter Name
Parameter Definition
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Measuring Nodes (from, to)
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
Revision 17
2-51
IGLOO nano DC and Switching Characteristics
CLK
tDDRISUD
6
tDDRIHD
8
Data
CLR
1
2
3
4
5
7
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
2
4
tDDRICLKQ2
tDDRICLR2Q2
7
3
5
Figure 2-18 • Input DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-79 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.25 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Description
Std.
0.48
0.65
0.50
0.40
0.00
0.00
0.82
0.98
0.00
0.23
0.19
0.31
0.28
250.00
Units
ns
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-52
Revision 17
IGLOO nano Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-80 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out Out_QR for Input DDR
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Std.
0.76
0.94
0.93
0.84
0.00
0.00
1.23
1.42
0.00
0.24
0.19
0.31
0.28
160.00
Units
ns
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 17
2-53
IGLOO nano DC and Switching Characteristics
Output DDR Module
Output DDR
A
Data_F
(from core)
X
X
FF1
Out
B
0
1
CLK
E
X
CLKBUF
C
X
OUTBUF
D
Data_R
(from core)
X
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-19 • Output DDR Timing Model
Table 2-81 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Clock-to-Out
Measuring Nodes (from, to)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
2-54
Revision 17
IGLOO nano Low Power Flash FPGAs
CLK
t
t
DDROHD2
DDROSUD2
4
9
5
Data_F
1
2
3
t
t
DDROHD1
DDROREMCLR
Data_R 6
CLR
7
8
10
11
t
DDRORECCLR
t
DDROREMCLR
t
t
DDROCLKQ
DDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-20 • Output DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-82 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
Std.
1.07
0.67
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.31
0.28
250.00
Units
ns
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-83 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Std.
1.60
1.09
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
Units
ns
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
160.00 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO nano Low Power Flash FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO nano library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e,
and ProASIC3/ E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-21 • Sample of Combinatorial Cells
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IGLOO nano DC and Switching Characteristics
tPD
Fanout = 4
A
B
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
tPD = MAX(tPD(RR), tPD(RF),
tPD(FF), tPD(FR)) where edges are
applicable for a particular
combinatorial cell
A
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
Y
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
VCC
50%
50%
VCC
A, B, C
GND
50%
50%
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
tPD
(FR)
OUT
50%
50%
tPD
GND
(RF)
Figure 2-22 • Timing Model and Waveforms
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IGLOO nano Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-84 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
0.76
0.87
0.91
0.90
0.94
1.39
1.44
1.60
1.17
1.18
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A, B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-85 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
1.33
1.48
1.58
1.53
1.63
2.34
2.59
2.74
2.03
2.11
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A, B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO nano DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOO nano library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented
for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and
ProASIC3/E Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-23 • Sample of Sequential Cells
2-60
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IGLOO nano Low Power Flash FPGAs
tCKMPWH CKMPWL
t
50%
tSUD
50%
50%
50%
50%
50%
50%
CLK
tHD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
tREMPRE
50%
tHE
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-24 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-86 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-87 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
1.61
1.17
0.00
1.29
0.00
0.87
0.89
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO nano Low Power Flash FPGAs
Global Resource Characteristics
AGLN125 Clock Tree Topology
Clock delays are device-specific. Figure 2-25 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-25 is driven by a CCC located on the west side of the AGLN125 device.
It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-25 • Example of Global Tree Use in an AGLN125 Device for Clock Routing
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IGLOO nano DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-70. Table 2-88 to Table 2-96 on page 2-68 present
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-88 • AGLN010 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.13
1.15
1.40
1.65
Units
ns
1.42
1.50
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.35
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-89 • AGLN015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.21
1.23
1.40
1.65
Max.2
Units
ns
1.55
tRCKH
Input HIgh Delay for Global Clock
1.65
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO nano Low Power Flash FPGAs
Table 2-90 • AGLN020 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.21
1.23
1.40
1.65
Max.2
Units
ns
1.55
tRCKH
Input High Delay for Global Clock
1.65
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-91 • AGLN060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.32
1.34
1.40
1.65
Max.2
Units
ns
1.62
tRCKH
Input High Delay for Global Clock
1.71
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.38
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO nano DC and Switching Characteristics
Table 2-92 • AGLN125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.36
1.39
1.40
1.65
Units
ns
1.71
1.82
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-93 • AGLN250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.39
1.41
1.40
1.65
Max.2
Units
ns
1.73
tRCKH
Input High Delay for Global Clock
1.84
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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Revision 17
IGLOO nano Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-94 • AGLN010 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.71
1.78
1.40
1.65
Max.2
Units
ns
2.09
tRCKH
Input High Delay for Global Clock
2.31
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.53
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-95 • AGLN015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.81
1.90
1.40
1.65
Max.2
Units
ns
2.26
tRCKH
Input High Delay for Global Clock
2.51
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO nano DC and Switching Characteristics
Table 2-96 • AGLN020 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.81
1.90
1.40
1.65
Units
ns
2.26
2.51
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-97 • AGLN060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.02
2.09
1.40
1.65
Max.2
Units
ns
2.42
tRCKH
Input High Delay for Global Clock
2.65
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.56
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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Revision 17
IGLOO nano Low Power Flash FPGAs
Table 2-98 • AGLN125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.08
2.15
1.40
1.65
Max.2
Units
ns
2.54
tRCKH
Input High Delay for Global Clock
2.77
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-99 • AGLN250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.11
2.19
1.40
1.65
Max.2
Units
ns
2.57
tRCKH
Input High Delay for Global Clock
2.81
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 17
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IGLOO nano DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-100 • IGLOO nano CCC/PLL Specification
For IGLOO nano V2 OR V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL 4,9
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
0.75
250
3603
32
100
1
MHz
ns
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter 5
LockControl = 0
2.5
1.5
ns
ns
%
LockControl = 1
Output Duty Cycle
48.5
1.25
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2,
ns
ns
ns
0.025
Delay Range in Block: Fixed Delay 1, 2
3.5
6
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Jitter Data 6,7,8
SSO 2
0.50
SSO 4 SSO 8 SSO 16
0.75 MHz to 50 MHz
50 MHz to 250 MHz
Notes:
0.60
4.00
0.80
6.00
1.20
%
%
2.50
12.00
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, VCC = 1.5 V
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT, regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, no matter what the settings are for the
output divider.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
8. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out times within ±200 ps of
each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and
Printed Circuit Board Layout" section in the IGLOO nano FPGA Fabric User’s Guide.
9. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
2-70
Revision 17
IGLOO nano Low Power Flash FPGAs
Table 2-101 • IGLOO nano CCC/PLL Specification
For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
160
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL 4,9
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
0.75
160
5803
32
60
0.25
ns
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter 5
LockControl = 0
4
ns
ns
%
LockControl = 1
3
Output Duty Cycle
48.5
2.3
51.5
20.86
20.86
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
ns
ns
ns
0.025
5.7
Max Peak-to-Peak Period Jitter 6,7,8
6
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
SSO 2
SSO 4 SSO 8 SSO 16
0.75 MHz to 50MHz
50 MHz to 100 MHz
0.50
2.50
1.20
5.00
2.00
7.00
3.00
%
%
15.00
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, V = 1.2 V.
J
CC
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT, regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, no matter what the settings are for the
output divider.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
8. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out times within ±200 ps of
each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and
Printed Circuit Board Layout" section in the IGLOO nano FPGA Fabric User’s Guide.
9. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
Revision 17
2-71
IGLOO nano DC and Switching Characteristics
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-26 • Peak-to-Peak Jitter Definition
2-72
Revision 17
IGLOO nano Low Power Flash FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-27 • RAM Models
Revision 17
2-73
IGLOO nano DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
tBKS
A1
A2
[R|W]ADDR
BLK
tBKH
tENS
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-28 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-29 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
2-74
Revision 17
IGLOO nano Low Power Flash FPGAs
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS
tAH
A0
tBKS
A1
A2
tBKH
tENS
tENH
WEN
tDS
tDH
DI1
DI0
DIN|WD
DOUT|RD
Dn
D2
Figure 2-30 • RAM Write, Output Retained (WMODE = 0). Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
ADDR
BLK
tAS tAH
A0
tBKS
A1
A2
tBKH
tENS
WEN
DIN
tDS tDH
DI1
DI0
DI2
DOUT
Dn
DI0
DI1
(pass-through)
DOUT
DI0
Dn
DI1
(pipelined)
Figure 2-31 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.
Revision 17
2-75
IGLOO nano DC and Switching Characteristics
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
Dm
Dn
DOUT|RD
Figure 2-32 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
2-76
Revision 17
IGLOO nano Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-102 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Address setup time
Std. Units
0.69 ns
0.13 ns
0.68 ns
0.13 ns
1.37 ns
0.13 ns
0.59 ns
0.30 ns
2.94 ns
2.55 ns
1.51 ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock HIGH to new data valid on DOUT (output retained, WMODE = 0)
Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1)
Clock HIGH to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address; applicable 0.23 ns
to closing edge
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address; 0.35 ns
applicable to opening edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address; 0.41 ns
applicable to opening edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
1.72 ns
1.72 ns
0.51 ns
2.68 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-77
IGLOO nano DC and Switching Characteristics
Table 2-103 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std. Units
0.69 ns
0.13 ns
0.61 ns
0.07 ns
0.59 ns
0.30 ns
3.51 ns
1.43 ns
Address setup time
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock HIGH to new data valid on RD (output retained)
Clock HIGH to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address; 0.35
applicable to opening edge
ns
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address; 0.42
applicable to opening edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
RESET Low to data out Low on RD (pipelined)
1.72 ns
1.72 ns
0.51 0.51
2.68 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-78
Revision 17
IGLOO nano Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-104 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Address setup time
Std. Units
1.28
0.25
1.25
0.25
2.54
0.25
1.10
0.55
5.51
4.77
2.82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock HIGH to new data valid on DOUT (output retained, WMODE = 0)
Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1)
Clock HIGH to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address; 0.30
applicable to closing edge
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address; 0.89
applicable to opening edge
ns
ns
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address; 1.01
applicable to opening edge
tRSTBQ
RESET LOW to data out LOW on DOUT (flow-through)
RESET LOW to data out LOW on DO (pipelined)
3.21
3.21
0.93
4.94
1.18
10.90
92
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
ns
ns
ns
tCYC
Clock cycle time
ns
FMAX
Notes:
Maximum frequency
MHz
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 17
2-79
IGLOO nano DC and Switching Characteristics
Table 2-105 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std. Units
Address setup time
1.28
0.25
1.13
0.13
1.10
0.55
6.56
2.67
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address; 0.87
applicable to opening edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address; 1.04
applicable to opening edge
ns
tRSTBQ
RESET LOW to data out LOW on RD (flow through)
RESET LOW to data out LOW on RD (pipelined)
3.21
3.21
0.93
4.94
1.18
ns
ns
ns
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
10.90 ns
92 MHz
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-80
Revision 17
IGLOO nano Low Power Flash FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-33 • FIFO Model
Revision 17
2-81
IGLOO nano DC and Switching Characteristics
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKS
tBKH
RBLK
tCKQ1
RD
D1
Dn
D0
D2
(flow-through)
tCKQ2
RD
(pipelined)
Dn
D0
D1
Figure 2-34 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
tBKS
tBKH
WBLK
tDS
tDH
DI1
DI0
WD
Figure 2-35 • FIFO Write
2-82
Revision 17
IGLOO nano Low Power Flash FPGAs
RCLK/
WCLK
t
t
MPWRSTB
RSTCK
RESET
EMPTY
AEMPTY
FULL
t
RSTFG
t
RSTAF
t
RSTFG
t
RSTAF
AFULL
WA/RA
MATCH (A )
(Address Counter)
0
Figure 2-36 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
t
CKAF
AEMPTY
WA/RA
(Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Revision 17
2-83
IGLOO nano DC and Switching Characteristics
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-38 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-40 • FIFO FULL Flag and AFULL Flag Deassertion
2-84
Revision 17
IGLOO nano Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-106 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
Std.
1.66
0.13
0.30
0.00
0.63
0.20
2.77
1.50
2.94
2.79
10.71
2.90
10.60
1.68
1.68
0.51
2.68
0.68
6.24
160
Units
ns
REN, WEN Setup Time
tENH
REN, WEN Hold Time
ns
tBKS
BLK Setup Time
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
ns
ns
ns
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out LOW on RD (flow-through)
RESET Low to Data Out LOW on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 17
2-85
IGLOO nano DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-107 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
Std.
3.44
0.26
0.30
0.00
1.30
0.41
5.67
3.02
6.02
5.71
22.17
5.93
21.94
3.41
4.09
1.02
5.48
1.18
10.90
92
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
ns
ns
ns
WCLK High to Full Flag Valid
ns
Clock High to Almost Empty/Full Flag Valid
RESET LOW to Empty/Full Flag Valid
RESET LOW to Almost Empty/Full Flag Valid
RESET LOW to Data Out Low on RD (flow-through)
RESET LOW to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
3.41
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-86
Revision 17
IGLOO nano Low Power Flash FPGAs
Embedded FlashROM Characteristics
t
t
t
SU
SU
SU
CLK
t
t
t
HOLD
HOLD
HOLD
Address
A
A
1
0
t
t
t
CKQ2
CKQ2
CKQ2
D
D
D
Data
0
0
1
Figure 2-41 • Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-108 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
Std.
0.57
0.00
Units
ns
tHOLD
tCK2Q
Address Hold Time
ns
Clock to Out
20.90
15
ns
FMAX
Maximum Clock Frequency
MHz
1.2 V DC Core Voltage
Table 2-109 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tSU
Description
Std.
0.59
0.00
35.74
10
Units
ns
Address Setup Time
Address Hold Time
Clock to Out
tHOLD
tCK2Q
ns
ns
FMAX
Maximum Clock Frequency
MHz
Revision 17
2-87
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-15 for more details.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-110 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Std.
1.00
2.00
1.00
2.00
8.00
25.00
15
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
tDIHD
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
0.58
0.00
TBD
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-111 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDISU
Description
Test Data Input Setup Time
Std.
1.50
3.00
1.50
3.00
11.00
30.00
9.00
1.18
0.00
TBD
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3 – Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for IGLOO nano V5 devices, and 1.2 V or 1.5 V for
IGLOO nano V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG.
Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG
must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V,
1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI
pins tied to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V,
2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND.
VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be
connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1,
etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V.
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in IGLOO and ProASIC3 Devices" chapter in the IGLOO nano FPGA Fabric User’s Guide for a
complete board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on IGLOO nano devices.
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and-
route tool automatically disables the unused PLLs to lower power consumption. The user should tie
unused VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on IGLOO nano devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
Revision 17
3-1
Pin Descriptions
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
IGLOO nano devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO
and ProASIC3 Devices" chapter in the IGLOO nano FPGA Fabric User’s Guide. All inputs labeled
GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and
GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs
into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global
network are multiplexed, and only one input can be used as a global input.
Refer to the "I/O Structures in nano Devices" chapter of the IGLOO nano FPGA Fabric User’s Guide for
an explanation of the naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze is available on IGLOO nano devices. The FF pin is a dedicated input pin used to enter and
exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O,
and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the
FF pin is available as a regular I/O.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
3-2
Revision 17
IGLOO nano Low Power Flash FPGAs
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO nano devices. The
Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to
larger or smaller IGLOO nano devices while maintaining the same pin location on the board. Refer to the
"Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO nano FPGA Fabric User’s
Guide for more information on I/O states during Flash*Freeze mode.
Table 3-1 • Flash*Freeze Pin Locations for IGLOO nano Devices
Package
CS81/UC81
QN48
Flash*Freeze Pin
H2
14
18
27
E2
QN68
VQ100
UC36
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal
pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a
resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired
state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2
for more information.
Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance 1,2
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
1. The TCK pin can be pulled-up or pulled-down.
2. The TRST pin is pulled-down.
3. Equivalent parallel resistance if more than one device is on the JTAG chain
Revision 17
3-3
Pin Descriptions
Table 3-3 • TRST and TCK Pull-Down Recommendations
VJTAG
Tie-Off Resistance*
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Note: Equivalent parallel resistance if more than one device is on the JTAG chain
TDI Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external
pull-down resistor could be included to ensure the test access port (TAP) is held in reset mode. The
resistor values must be chosen from Table 3-2 and must satisfy the parallel resistance value
requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is
used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
3-4
Revision 17
IGLOO nano Low Power Flash FPGAs
Related Documents
User’s Guides
IGLOO nano FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/IGLOO_nano_UG.pdf
Packaging Documents
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 17
3-5
4 – Package Pin Assignments
UC36
Pin 1 Pad Corner
6
5
4
3
2
1
A
B
C
D
E
F
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 17
4-1
Package Pin Assignments
UC36
UC36
AGLN010
AGLN010
Function
Pin Number
A1
Function
IO21RSB1
IO18RSB1
IO13RSB1
GDC0/IO00RSB0
IO06RSB0
GDA0/IO04RSB0
GEC0/IO37RSB1
IO20RSB1
IO15RSB1
IO09RSB0
IO08RSB0
IO07RSB0
IO22RSB1
GEA0/IO34RSB1
GND
Pin Number
F5
F6
TMS
TDO
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
GND
VCCIB0
IO02RSB0
IO33RSB1
VCCIB1
VCC
VCC
IO10RSB0
IO11RSB0
IO32RSB1
FF/IO31RSB1
TCK
E2
E3
E4
VPUMP
E5
TRST
E6
VJTAG
F1
IO29RSB1
IO25RSB1
IO23RSB1
TDI
F2
F3
F4
4-2
Revision 17
IGLOO nano Low Power Flash FPGAs
UC81
A1 Ball Pad Corner
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 17
4-3
Package Pin Assignments
UC81
UC81
UC81
Pin Number AGLN020 Function
Pin Number AGLN020 Function
Pin Number AGLN020 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
IO64RSB2
IO54RSB2
IO57RSB2
IO36RSB1
IO32RSB1
IO24RSB1
IO20RSB1
IO04RSB0
IO08RSB0
IO59RSB2
IO55RSB2
IO62RSB2
IO34RSB1
IO28RSB1
IO22RSB1
IO18RSB1
IO00RSB0
IO03RSB0
IO51RSB2
IO50RSB2
NC
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GEC0/IO48RSB2
GEA0/IO47RSB2
NC
J1
J2
J3
J4
J5
J6
J7
J8
J9
IO38RSB1
IO37RSB1
IO33RSB1
IO30RSB1
IO27RSB1
IO23RSB1
TCK
VCCIB1
VCC
VCCIB0
NC
GDA0/IO15RSB0
GDC0/IO14RSB0
IO46RSB2
IO45RSB2
NC
TMS
VPUMP
GND
VCCIB1
NC
NC
IO16RSB0
IO17RSB0
IO43RSB2
IO42RSB2
IO41RSB2
IO31RSB1
NC
NC
NC
NC
IO21RSB1
NC
NC
IO10RSB0
IO07RSB0
IO49RSB2
IO44RSB2
NC
VJTAG
TRST
IO40RSB2
FF/IO39RSB1
IO35RSB1
IO29RSB1
IO26RSB1
IO25RSB1
IO19RSB1
TDI
VCC
VCCIB2
GND
NC
IO13RSB0
IO12RSB0
TDO
4-4
Revision 17
IGLOO nano Low Power Flash FPGAs
UC81
AGLN030Z
UC81
AGLN030Z
UC81
AGLN030Z
Pin Number
A1
Function
IO00RSB0
IO02RSB0
IO06RSB0
IO11RSB0
IO16RSB0
IO19RSB0
IO22RSB0
IO24RSB0
IO26RSB0
IO81RSB1
IO04RSB0
IO10RSB0
IO13RSB0
IO15RSB0
IO20RSB0
IO21RSB0
IO28RSB0
IO25RSB0
IO79RSB1
IO80RSB1
IO08RSB0
IO12RSB0
IO17RSB0
IO14RSB0
IO18RSB0
IO29RSB0
IO27RSB0
IO74RSB1
IO76RSB1
IO77RSB1
VCC
Pin Number
D9
E1
Function
IO30RSB0
GEB0/IO71RSB1
GEA0/IO72RSB1
GEC0/IO73RSB1
VCCIB1
Pin Number
Function
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
TDI
A2
TDO
A3
E2
IO63RSB1
IO61RSB1
IO59RSB1
IO56RSB1
IO52RSB1
IO44RSB1
TCK
A4
E3
A5
E4
A6
E5
VCC
A7
E6
VCCIB0
A8
E7
GDC0/IO32RSB0
GDA0/IO33RSB0
GDB0/IO34RSB0
IO68RSB1
IO67RSB1
IO64RSB1
GND
A9
E8
B1
E9
TMS
B2
F1
VPUMP
B3
F2
B4
F3
B5
F4
B6
F5
VCCIB1
B7
F6
IO47RSB1
IO36RSB0
IO38RSB0
IO40RSB0
IO65RSB1
IO66RSB1
IO57RSB1
IO53RSB1
IO49RSB1
IO45RSB1
IO46RSB1
VJTAG
B8
F7
B9
F8
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
TRST
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO54RSB1
IO48RSB1
IO43RSB1
IO42RSB1
VCCIB0
GND
IO23RSB0
IO31RSB0
Revision 17
4-5
Package Pin Assignments
CS81
A1 Ball Pad Corner
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-6
Revision 17
IGLOO nano Low Power Flash FPGAs
CS81
CS81
CS81
Pin Number AGLN020 Function
Pin Number AGLN020 Function
Pin Number AGLN020 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
IO64RSB2
IO54RSB2
IO57RSB2
IO36RSB1
IO32RSB1
IO24RSB1
IO20RSB1
IO04RSB0
IO08RSB0
IO59RSB2
IO55RSB2
IO62RSB2
IO34RSB1
IO28RSB1
IO22RSB1
IO18RSB1
IO00RSB0
IO03RSB0
IO51RSB2
IO50RSB2
NC
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GEC0/IO48RSB2
GEA0/IO47RSB2
NC
J1
J2
J3
J4
J5
J6
J7
J8
J9
IO38RSB1
IO37RSB1
IO33RSB1
IO30RSB1
IO27RSB1
IO23RSB1
TCK
VCCIB1
VCC
VCCIB0
NC
GDA0/IO15RSB0
GDC0/IO14RSB0
IO46RSB2
IO45RSB2
NC
TMS
VPUMP
GND
VCCIB1
NC
NC
IO16RSB0
IO17RSB0
IO43RSB2
IO42RSB2
IO41RSB2
IO31RSB1
NC
NC
NC
NC
IO21RSB1
NC
NC
IO10RSB0
IO07RSB0
IO49RSB2
IO44RSB2
NC
VJTAG
TRST
IO40RSB2
FF/IO39RSB1
IO35RSB1
IO29RSB1
IO26RSB1
IO25RSB1
IO19RSB1
TDI
VCC
VCCIB2
GND
NC
IO13RSB0
IO12RSB0
TDO
Revision 17
4-7
Package Pin Assignments
CS81
CS81
AGLN030Z
CS81
AGLN030Z
AGLN030Z
Pin Number
A1
Function
IO00RSB0
IO02RSB0
IO06RSB0
IO11RSB0
IO16RSB0
IO19RSB0
IO22RSB0
IO24RSB0
IO26RSB0
IO81RSB1
IO04RSB0
IO10RSB0
IO13RSB0
IO15RSB0
IO20RSB0
IO21RSB0
IO28RSB0
IO25RSB0
IO79RSB1
IO80RSB1
IO08RSB0
IO12RSB0
IO17RSB0
IO14RSB0
IO18RSB0
IO29RSB0
IO27RSB0
IO74RSB1
IO76RSB1
IO77RSB1
VCC
Pin Number
D9
E1
Function
IO30RSB0
GEB0/IO71RSB1
GEA0/IO72RSB1
GEC0/IO73RSB1
VCCIB1
Pin Number
Function
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
TDI
A2
TDO
A3
E2
IO63RSB1
IO61RSB1
IO59RSB1
IO56RSB1
IO52RSB1
IO45RSB1
TCK
A4
E3
A5
E4
A6
E5
VCC
A7
E6
VCCIB0
A8
E7
GDC0/IO32RSB0
GDA0/IO33RSB0
GDB0/IO34RSB0
IO68RSB1
IO67RSB1
IO64RSB1
GND
A9
E8
B1
E9
TMS
B2
F1
VPUMP
B3
F2
B4
F3
B5
F4
B6
F5
VCCIB1
B7
F6
IO47RSB1
IO36RSB0
IO38RSB0
IO40RSB0
IO65RSB1
IO66RSB1
IO57RSB1
IO53RSB1
IO49RSB1
IO44RSB1
IO46RSB1
VJTAG
B8
F7
B9
F8
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
TRST
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO54RSB1
IO48RSB1
IO43RSB1
IO42RSB1
VCCIB0
GND
IO23RSB0
IO31RSB0
4-8
Revision 17
IGLOO nano Low Power Flash FPGAs
CS81
CS81
CS81
Pin Number AGLN060 Function
Pin Number AGLN060 Function
Pin Number AGLN060 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
GAA0/IO02RSB0
GAA1/IO03RSB0
GAC0/IO06RSB0
IO09RSB0
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F11
F21
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
GCC1/IO35RSB0
GCC0/IO36RSB0
GFB0/IO83RSB1
GFB1/IO84RSB1
GFA1/IO81RSB1
VCCIB1
H6
H72
H8
H9
J1
IO56RSB1
GDA2/IO51RSB1
TDI
TDO
IO13RSB0
GEA2/IO68RSB1
GEC2/IO66RSB1
IO64RSB1
IO61RSB1
IO58RSB1
IO55RSB1
TCK
IO18RSB0
J2
GBB0/IO21RSB0
GBA1/IO24RSB0
GBA2/IO25RSB0
GAA2/IO95RSB1
GAB0/IO04RSB0
GAC1/IO07RSB0
IO08RSB0
VCC
J3
VCCIB0
J4
GCA1/IO39RSB0
GCA0/IO40RSB0
GCB2/IO42RSB0
VCCPLF
J5
J6
J7
J8
TMS
VCOMPLF
J9
VPUMP
IO15RSB0
GND
GBC0/IO19RSB0
GBB1/IO22RSB0
IO26RSB0
GND
VCCIB1
GND
GBB2/IO27RSB0
GAB2/IO93RSB1
IO94RSB1
GDA1/IO49RSB0
GDC1/IO45RSB0
GDC0/IO46RSB0
GEA0/IO69RSB1
GEC1/IO74RSB1
GEB1/IO72RSB1
IO63RSB1
GND
IO10RSB0
IO17RSB0
GND
GBA0/IO23RSB0
GBC2/IO29RSB0
IO31RSB0
IO60RSB1
IO54RSB1
GDB2/IO52RSB1
VJTAG
GAC2/IO91RSB1
IO92RSB1
TRST
GFA2/IO80RSB1
VCC
GEA1/IO70RSB1
FF/GEB2/IO67RSB1
IO65RSB1
VCCIB0
GND
IO62RSB1
GCC2/IO43RSB0
IO59RSB1
Notes:
1. Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN060-CS81.
2. The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin H7 in AGLN060-CS81.
Revision 17
4-9
Package Pin Assignments
CS81
CS81
CS81
Pin Number AGLN060Z Function
Pin Number AGLN060Z Function
Pin Number AGLN060Z Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
GAA0/IO02RSB0
GAA1/IO03RSB0
GAC0/IO06RSB0
IO09RSB0
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F11
F21
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
GCC1/IO35RSB0
GCC0/IO36RSB0
GFB0/IO83RSB1
GFB1/IO84RSB1
GFA1/IO81RSB1
VCCIB1
H6
H72
H8
H9
J1
IO56RSB1
GDA2/IO51RSB1
TDI
TDO
IO13RSB0
GEA2/IO68RSB1
GEC2/IO66RSB1
IO64RSB1
IO61RSB1
IO58RSB1
IO55RSB1
TCK
IO18RSB0
J2
GBB0/IO21RSB0
GBA1/IO24RSB0
GBA2/IO25RSB0
GAA2/IO95RSB1
GAB0/IO04RSB0
GAC1/IO07RSB0
IO08RSB0
VCC
J3
VCCIB0
J4
GCA1/IO39RSB0
GCA0/IO40RSB0
GCB2/IO42RSB0
VCCPLF
J5
J6
J7
J8
TMS
VCOMPLF
J9
VPUMP
IO15RSB0
GND
GBC0/IO19RSB0
GBB1/IO22RSB0
IO26RSB0
GND
VCCIB1
GND
GBB2/IO27RSB0
GAB2/IO93RSB1
IO94RSB1
GDA1/IO49RSB0
GDC1/IO45RSB0
GDC0/IO46RSB0
GEA0/IO69RSB1
GEC1/IO74RSB1
GEB1/IO72RSB1
IO63RSB1
GND
IO10RSB0
IO17RSB0
GND
GBA0/IO23RSB0
GBC2/IO29RSB0
IO31RSB0
IO60RSB1
IO54RSB1
GDB2/IO52RSB1
VJTAG
GAC2/IO91RSB1
IO92RSB1
TRST
GFA2/IO80RSB1
VCC
GEA1/IO70RSB1
FF/GEB2/IO67RSB1
IO65RSB1
VCCIB0
GND
IO62RSB1
GCC2/IO43RSB0
IO59RSB1
Notes:
1. Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN060Z-CS81.
2. The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin H7 in AGLN060Z-CS81.
4-10
Revision 17
IGLOO nano Low Power Flash FPGAs
CS81
CS81
CS81
Pin Number AGLN125 Function
Pin Number AGLN125 Function
Pin Number AGLN125 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
GAA0/IO00RSB0
GAA1/IO01RSB0
GAC0/IO04RSB0
IO13RSB0
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1*
F2*
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GFB0/IO120RSB1
GFB1/IO121RSB1
GFA1/IO118RSB1
VCCIB1
J1
J2
J3
J4
J5
J6
J7
J8
J9
GEA2/IO103RSB1
GEC2/IO101RSB1
IO97RSB1
IO93RSB1
IO90RSB1
IO78RSB1
TCK
IO22RSB0
VCC
IO32RSB0
VCCIB0
GBB0/IO37RSB0
GBA1/IO40RSB0
GBA2/IO41RSB0
GAA2/IO132RSB1
GAB0/IO02RSB0
GAC1/IO05RSB0
IO11RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCB2/IO58RSB0
VCCPLF
TMS
VPUMP
VCOMPLF
GND
GND
IO25RSB0
VCCIB1
GBC0/IO35RSB0
GBB1/IO38RSB0
IO42RSB0
GND
GDA1/IO65RSB0
GDC1/IO61RSB0
GDC0/IO62RSB0
GEA0/IO104RSB1
GEC0/IO108RSB1
GEB1/IO107RSB1
IO96RSB1
GBB2/IO43RSB0
GAB2/IO130RSB1
IO131RSB1
GND
IO15RSB0
IO28RSB0
IO92RSB1
GND
IO72RSB1
GBA0/IO39RSB0
GBC2/IO45RSB0
IO47RSB0
GDB2/IO68RSB1
VJTAG
TRST
GAC2/IO128RSB1
IO129RSB1
GEA1/IO105RSB1
FF/GEB2/IO102RSB1
IO99RSB1
GFA2/IO117RSB1
VCC
IO94RSB1
VCCIB0
IO91RSB1
GND
IO81RSB1
GCC2/IO59RSB0
GCC1/IO51RSB0
GCC0/IO52RSB0
GDA2/IO67RSB1
TDI
TDO
Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN125-CS81.
Revision 17
4-11
Package Pin Assignments
CS8
CS8
CS8
Pin Number AGLN125Z Function
Pin Number AGLN125Z Function
Pin Number AGLN125Z Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
GAA0/IO00RSB0
GAA1/IO01RSB0
GAC0/IO04RSB0
IO13RSB0
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1*
F2*
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GFB0/IO120RSB1
GFB1/IO121RSB1
GFA1/IO118RSB1
VCCIB1
J1
J2
J3
J4
J5
J6
J7
J8
J9
GEA2/IO103RSB1
GEC2/IO101RSB1
IO97RSB1
IO93RSB1
IO90RSB1
IO78RSB1
TCK
IO22RSB0
VCC
IO32RSB0
VCCIB0
GBB0/IO37RSB0
GBA1/IO40RSB0
GBA2/IO41RSB0
GAA2/IO132RSB1
GAB0/IO02RSB0
GAC1/IO05RSB0
IO11RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCB2/IO58RSB0
VCCPLF
TMS
VPUMP
VCOMPLF
GND
GND
IO25RSB0
VCCIB1
GBC0/IO35RSB0
GBB1/IO38RSB0
IO42RSB0
GND
GDA1/IO65RSB0
GDC1/IO61RSB0
GDC0/IO62RSB0
GEA0/IO104RSB1
GEC0/IO108RSB1
GEB1/IO107RSB1
IO96RSB1
GBB2/IO43RSB0
GAB2/IO130RSB1
IO131RSB1
GND
IO15RSB0
IO28RSB0
IO92RSB1
GND
IO72RSB1
GBA0/IO39RSB0
GBC2/IO45RSB0
IO47RSB0
GDB2/IO68RSB1
VJTAG
TRST
GAC2/IO128RSB1
IO129RSB1
GEA1/IO105RSB1
FF/GEB2/IO102RSB1
IO99RSB1
GFA2/IO117RSB1
VCC
IO94RSB1
VCCIB0
IO91RSB1
GND
IO81RSB1
GCC2/IO59RSB0
GCC1/IO51RSB0
GCC0/IO52RSB0
GDA2/IO67RSB1
TDI
TDO
Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN125Z-CS81.
4-12
Revision 17
IGLOO nano Low Power Flash FPGAs
CS81
CS81
CS81
Pin Number AGLN250 Function
Pin Number AGLN250 Function
Pin Number AGLN250 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
GAA0/IO00RSB0
GAA1/IO01RSB0
GAC0/IO04RSB0
IO13RSB0
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1*
F2*
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GFB0/IO109NDB3
GFB1/IO109PDB3
GFA1/IO108PSB3
VCCIB3
J1
J2
J3
J4
J5
J6
J7
J8
J9
GEA2/IO97RSB2
GEC2/IO95RSB2
IO92RSB2
IO88RSB2
IO84RSB2
IO74RSB2
TCK
IO21RSB0
VCC
IO27RSB0
VCCIB1
GBB0/IO37RSB0
GBA1/IO40RSB0
GBA2/IO41PPB1
GAA2/IO118UPB3
GAB0/IO02RSB0
GAC1/IO05RSB0
IO11RSB0
GCA0/IO50NDB1
GCA1/IO50PDB1
GCB2/IO52PPB1
VCCPLF
TMS
VPUMP
VCOMPLF
GND
GND
IO23RSB0
VCCIB2
GBC0/IO35RSB0
GBB1/IO38RSB0
IO41NPB1
GND
GDA1/IO60USB1
GDC1/IO58UDB1
GDC0/IO58VDB1
GEA0/IO98NDB3
GEC1/IO100PDB3
GEC0/IO100NDB3
IO91RSB2
GBB2/IO42PSB1
GAB2/IO117UPB3
IO118VPB3
GND
IO15RSB0
IO25RSB0
IO86RSB2
GND
IO71RSB2
GBA0/IO39RSB0
GBC2/IO43B1
IO43NDB1
GDB2/IO62RSB2
VJTAG
TRST
GAC2/IO116USB3
IO117VPB3
GEA1/IO98PDB3
FF/GEB2/IO96RSB2
IO93RSB2
GFA2/IO107PSB3
VCC
IO90RSB2
VCCIB0
IO85RSB2
GND
IO77RSB2
IO52NPB1
GDA2/IO61RSB2
TDI
GCC1/IO48PDB1
GCC0/IO48NDB1
TDO
Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN250-CS81.
Revision 17
4-13
Package Pin Assignments
CS81
CS81
CS81
Pin Number AGLN250Z Function
Pin Number AGLN250Z Function
Pin Number AGLN250Z Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
GAA0/IO00RSB0
GAA1/IO01RSB0
GAC0/IO04RSB0
IO07RSB0
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1*
F2*
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GFB0/IO59RSB3
GFB1/IO60RSB3
GFA1/IO58RSB3
VCCIB3
J1
J2
J3
J4
J5
J6
J7
J8
J9
GEA2/IO50RSB2
GEC2/IO48RSB2
IO46RSB2
IO43RSB2
IO40RSB2
IO38RSB2
TCK
IO09RSB0
VCC
IO12RSB0
VCCIB1
GBB0/IO16RSB0
GBA1/IO19RSB0
GBA2/IO20RSB1
GAA2/IO67RSB3
GAB0/IO02RSB0
GAC1/IO05RSB0
IO06RSB0
GCA0/IO28RSB1
GCA1/IO27RSB1
GCB2/IO29RSB1
VCCPLF
TMS
VPUMP
VCOMPLF
GND
GND
IO10RSB0
VCCIB2
GBC0/IO14RSB0
GBB1/IO17RSB0
IO21RSB1
GND
GDA1/IO33RSB1
GDC1/IO31RSB1
GDC0/IO32RSB1
GEA0/IO51RSB3
GEC1/IO54RSB3
GEC0/IO53RSB3
IO45RSB2
GBB2/IO22RSB1
GAB2/IO65RSB3
IO66RSB3
GND
IO08RSB0
IO11RSB0
IO42RSB2
GND
IO37RSB2
GBA0/IO18RSB0
GBC2/IO23RSB1
IO24RSB1
GDB2/IO35RSB2
VJTAG
TRST
GAC2/IO63RSB3
IO64RSB3
GEA1/IO52RSB3
FF/GEB2/IO49RSB2
IO47RSB2
GFA2/IO56RSB3
VCC
IO44RSB2
VCCIB0
IO41RSB2
GND
IO39RSB2
IO30RSB1
GDA2/IO34RSB2
TDI
GCC1/IO25RSB1
GCC0/IO26RSB1
TDO
Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN250Z-CS81.
4-14
Revision 17
IGLOO nano Low Power Flash FPGAs
QN48
Pin 1
48
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 17
4-15
Package Pin Assignments
QN48
QN48
AGLN010
AGLN010
Function
Pin Number
Function
GEC0/IO37RSB1
IO36RSB1
GEA0/IO34RSB1
IO22RSB1
GND
Pin Number
1
36
37
38
39
40
41
42
43
44
45
46
47
48
IO07RSB0
IO06RSB0
2
3
GDA0/IO05RSB0
IO03RSB0
4
5
GDC0/IO01RSB0
IO12RSB1
6
VCCIB1
7
IO24RSB1
IO33RSB1
IO26RSB1
IO32RSB1
IO27RSB1
IO29RSB1
IO30RSB1
FF/IO31RSB1
IO28RSB1
IO25RSB1
IO23RSB1
VCC
IO13RSB1
8
IO15RSB1
9
IO16RSB1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IO18RSB1
IO19RSB1
IO20RSB1
IO21RSB1
VCCIB1
IO17RSB1
IO14RSB1
TCK
TDI
TMS
VPUMP
TDO
TRST
VJTAG
IO11RSB0
IO10RSB0
IO09RSB0
IO08RSB0
VCCIB0
GND
VCC
4-16
Revision 17
IGLOO nano Low Power Flash FPGAs
QN48
QN48
Pin Number AGLN030Z Function
Pin Number AGLN030Z Function
1
IO82RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
GND
37
38
39
40
41
42
43
44
45
46
47
48
IO24RSB0
IO22RSB0
IO20RSB0
IO18RSB0
IO16RSB0
IO14RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
2
3
4
5
6
VCCIB1
7
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO62RSB1
IO61RSB1
FF/IO60RSB1
IO57RSB1
IO55RSB1
IO53RSB1
VCC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
IO46RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
TRST
VJTAG
IO38RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
GND
VCC
IO25RSB0
Revision 17
4-17
Package Pin Assignments
QN68
Pin A1 Mark
68
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-18
Revision 17
IGLOO nano Low Power Flash FPGAs
QN68
QN68
AGLN015
Function
AGLN015
Function
Pin Number
Pin Number
36
1
IO60RSB2
IO54RSB2
IO52RSB2
IO50RSB2
IO49RSB2
TDO
TRST
2
37
3
38
VJTAG
4
39
IO17RSB0
IO16RSB0
5
40
6
GEC0/IO48RSB2
GEA0/IO47RSB2
VCC
41
GDA0/IO15RSB0
GDC0/IO14RSB0
IO13RSB0
VCCIB0
7
42
8
43
9
GND
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VCCIB2
45
GND
IO46RSB2
IO45RSB2
IO44RSB2
IO43RSB2
IO42RSB2
IO41RSB2
IO40RSB2
FF/IO39RSB1
IO37RSB1
IO35RSB1
IO33RSB1
IO31RSB1
IO30RSB1
VCC
46
VCC
47
IO12RSB0
IO11RSB0
IO09RSB0
IO05RSB0
IO00RSB0
IO07RSB0
IO03RSB0
IO18RSB1
IO20RSB1
IO22RSB1
IO24RSB1
IO28RSB1
NC
48
49
50
51
52
53
54
55
56
57
58
59
GND
60
GND
VCCIB1
61
NC
IO27RSB1
IO25RSB1
IO23RSB1
IO21RSB1
IO19RSB1
TCK
62
IO32RSB1
IO34RSB1
IO36RSB1
IO61RSB2
IO58RSB2
IO56RSB2
IO63RSB2
63
64
65
66
67
TDI
68
TMS
VPUMP
Revision 17
4-19
Package Pin Assignments
QN68
QN68
AGLN020
AGLN020
Function
Pin Number
Function
IO60RSB2
IO54RSB2
IO52RSB2
IO50RSB2
IO49RSB2
GEC0/IO48RSB2
GEA0/IO47RSB2
VCC
Pin Number
36
1
TDO
TRST
2
37
3
38
VJTAG
4
39
IO17RSB0
IO16RSB0
5
40
6
41
GDA0/IO15RSB0
GDC0/IO14RSB0
IO13RSB0
VCCIB0
7
42
8
43
9
GND
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VCCIB2
45
GND
IO46RSB2
IO45RSB2
IO44RSB2
IO43RSB2
IO42RSB2
IO41RSB2
IO40RSB2
FF/IO39RSB1
IO37RSB1
IO35RSB1
IO33RSB1
IO31RSB1
IO30RSB1
VCC
46
VCC
47
IO12RSB0
IO11RSB0
IO09RSB0
IO05RSB0
IO00RSB0
IO07RSB0
IO03RSB0
IO18RSB1
IO20RSB1
IO22RSB1
IO24RSB1
IO28RSB1
NC
48
49
50
51
52
53
54
55
56
57
58
59
GND
60
GND
VCCIB1
61
NC
IO27RSB1
IO25RSB1
IO23RSB1
IO21RSB1
IO19RSB1
TCK
62
IO32RSB1
IO34RSB1
IO36RSB1
IO61RSB2
IO58RSB2
IO56RSB2
IO63RSB2
63
64
65
66
67
TDI
68
TMS
VPUMP
4-20
Revision 17
IGLOO nano Low Power Flash FPGAs
QN68
AGLN030Z
QN68
AGLN030Z
Pin Number
Function
IO82RSB1
IO80RSB1
IO78RSB1
IO76RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
VCC
Pin Number
36
Function
1
TDO
2
37
TRST
3
38
VJTAG
4
39
IO40RSB0
IO37RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
5
40
6
41
7
42
8
43
9
GND
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VCCIB1
45
GND
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO56RSB1
IO54RSB1
IO52RSB1
IO51RSB1
VCC
46
VCC
47
IO31RSB0
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO24RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO15RSB0
IO14RSB0
VCCIB0
48
49
50
51
52
53
54
55
56
57
58
59
GND
60
GND
VCCIB1
61
VCC
IO50RSB1
IO48RSB1
IO46RSB1
IO44RSB1
IO42RSB1
TCK
62
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
63
64
65
66
67
TDI
68
TMS
VPUMP
Revision 17
4-21
Package Pin Assignments
VQ100
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-22
Revision 17
IGLOO nano Low Power Flash FPGAs
VQ100
AGLN030Z
VQ100
AGLN030Z
VQ100
AGLN030Z
Pin Number
Function
Pin Number
36
Function
IO51RSB1
VCC
Pin Number
71
Function
IO29RSB0
IO28RSB0
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
VCCIB0
1
GND
2
IO82RSB1
IO81RSB1
IO80RSB1
IO79RSB1
IO78RSB1
IO77RSB1
IO76RSB1
GND
37
72
3
38
GND
73
4
39
VCCIB1
74
5
40
IO49RSB1
IO47RSB1
IO46RSB1
IO45RSB1
IO44RSB1
IO43RSB1
IO42RSB1
TCK
75
6
41
76
7
42
77
8
43
78
9
44
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IO75RSB1
IO74RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
IO70RSB1
IO69RSB1
VCC
45
80
46
81
47
82
48
TDI
83
49
TMS
84
50
NC
85
51
GND
86
52
VPUMP
87
VCCIB1
53
NC
88
GND
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO61RSB1
FF/IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
IO56RSB1
IO55RSB1
IO54RSB1
IO53RSB1
IO52RSB1
54
TDO
89
VCC
55
TRST
90
IO12RSB0
IO10RSB0
IO08RSB0
IO07RSB0
IO06RSB0
IO05RSB0
IO04RSB0
IO03RSB0
IO02RSB0
IO01RSB0
IO00RSB0
56
VJTAG
91
57
IO41RSB0
IO40RSB0
IO39RSB0
IO38RSB0
IO37RSB0
IO36RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
92
58
93
59
94
60
95
61
96
62
97
63
98
64
99
65
100
66
67
GND
68
VCC
69
IO31RSB0
IO30RSB0
70
Revision 17
4-23
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number AGLN060 Function
Pin Number AGLN060 Function
Pin Number AGLN060 Function
1
GND
GAA2/IO51RSB1
IO52RSB1
36
37
38
39
40
41
42
43
44
45*
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
IO61RSB1
VCC
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBB2/IO27RSB0
IO26RSB0
2
3
GND
GBA2/IO25RSB0
VMV0
4
GAB2/IO53RSB1
IO95RSB1
VCCIB1
5
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
GNDQ
6
GAC2/IO94RSB1
IO93RSB1
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
7
8
IO92RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
GFA0/IO85RSB1
VCCPLF
TDI
IO17RSB0
TMS
IO15RSB0
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
VMV1
IO13RSB0
GND
IO11RSB0
VPUMP
VCCIB0
VCCIB1
NC
GND
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
TDO
VCC
TRST
IO10RSB0
VJTAG
IO09RSB0
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
IO08RSB0
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GNDQ
GEA2/IO71RSB1
FF/GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO67RSB1
IO00RSB0
IO66RSB1
IO65RSB1
GND
IO64RSB1
VCC
IO63RSB1
IO31RSB0
GBC2/IO29RSB0
IO62RSB1
Note: *The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin 45 in AGLN060-
VQ100.
4-24
Revision 17
IGLOO nano Low Power Flash FPGAs
VQ100
VQ100
VQ100
Pin Number AGLN060Z Function
Pin Number AGLN060Z Function
Pin Number AGLN060Z Function
1
GND
GAA2/IO51RSB1
IO52RSB1
35
36
37
38
39
40
41
42
43
44
45*
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
IO62RSB1
IO61RSB1
VCC
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IO31RSB0
GBC2/IO29RSB0
GBB2/IO27RSB0
IO26RSB0
2
3
4
GAB2/IO53RSB1
IO95RSB1
GND
5
VCCIB1
GBA2/IO25RSB0
VMV0
6
GAC2/IO94RSB1
IO93RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
7
GNDQ
8
IO92RSB1
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
GFA0/IO85RSB1
VCCPLF
TDI
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
TMS
IO17RSB0
VMV1
IO15RSB0
GND
IO13RSB0
VCCIB1
VPUMP
IO11RSB0
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
NC
VCCIB0
TDO
GND
TRST
VCC
VJTAG
IO10RSB0
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
IO09RSB0
IO08RSB0
GNDQ
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GEA2/IO71RSB1
FF/GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO00RSB0
IO64RSB1
GND
IO63RSB1
VCC
Note: *The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin 45 in AGLN060Z-
VQ100.
Revision 17
4-25
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number AGLN125 Function
Pin Number AGLN125 Function
Pin Number AGLN125 Function
1
GND
GAA2/IO67RSB1
IO68RSB1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41RSB0
VMV0
2
3
VCCIB1
GNDQ
4
GAB2/IO69RSB1
IO132RSB1
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
5
6
GAC2/IO131RSB1
IO130RSB1
7
8
IO129RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
IO28RSB0
TDI
IO25RSB0
GFA0/IO122RSB1
VCCPLF
TMS
IO22RSB0
VMV1
IO19RSB0
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO15RSB0
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO09RSB0
IO07RSB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO106RSB1
FF/GEB2/IO105RSB1
GEC2/IO104RSB1
IO102RSB1
IO100RSB1
IO99RSB1
GND
IO97RSB1
VCC
IO96RSB1
IO47RSB0
GBC2/IO45RSB0
GBB2/IO43RSB0
IO42RSB0
IO95RSB1
IO94RSB1
IO93RSB1
4-26
Revision 17
IGLOO nano Low Power Flash FPGAs
VQ100
VQ100
VQ100
Pin
Pin
Pin
Number
AGLN125Z Function
GND
Number
AGLN125Z Function
IO93RSB1
VCC
Number
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AGLN125Z Function
GBB2/IO43RSB0
IO42RSB0
1
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
2
GAA2/IO67RSB1
IO68RSB1
3
GND
GBA2/IO41RSB0
VMV0
4
GAB2/IO69RSB1
IO132RSB1
VCCIB1
5
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
GNDQ
6
GAC2/IO131RSB1
IO130RSB1
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
7
8
IO129RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
GFA0/IO122RSB1
VCCPLF
TDI
IO28RSB0
TMS
IO25RSB0
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
VMV1
IO22RSB0
GND
IO19RSB0
VPUMP
VCCIB0
VCCIB1
NC
GND
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
TDO
VCC
TRST
IO15RSB0
VJTAG
IO13RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO11RSB0
IO09RSB0
IO07RSB0
GNDQ
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GEA2/IO106RSB1
FF/GEB2/IO105RSB1
GEC2/IO104RSB1
IO102RSB1
IO100RSB1
IO99RSB1
IO97RSB1
GND
IO96RSB1
VCC
IO95RSB1
IO47RSB0
GBC2/IO45RSB0
IO94RSB1
Revision 17
4-27
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number AGLN250 Function
Pin Number AGLN250 Function
Pin Number AGLN250 Function
1
GND
GAA2/IO67RSB3
IO66RSB3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO20RSB1
VMV1
2
3
VCCIB2
GNDQ
4
GAB2/IO65RSB3
IO64RSB3
IO39RSB2
IO38RSB2
IO37RSB2
GDC2/IO36RSB2
GDB2/IO35RSB2
GDA2/IO34RSB2
GNDQ
GBA1/IO19RSB0
GBA0/IO18RSB0
GBB1/IO17RSB0
GBB0/IO16RSB0
GBC1/IO15RSB0
GBC0/IO14RSB0
IO13RSB0
5
6
GAC2/IO63RSB3
IO62RSB3
7
8
IO61RSB3
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO60RSB3
GFB0/IO59RSB3
VCOMPLF
TCK
IO12RSB0
TDI
IO11RSB0
GFA0/IO57RSB3
VCCPLF
TMS
IO10RSB0
VMV2
IO09RSB0
GFA1/IO58RSB3
GFA2/IO56RSB3
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB3
TDO
IO08RSB0
GFC2/IO55RSB3
GEC1/IO54RSB3
GEC0/IO53RSB3
GEA1/IO52RSB3
GEA0/IO51RSB3
VMV3
TRST
IO07RSB0
VJTAG
IO06RSB0
GDA1/IO33RSB1
GDC0/IO32RSB1
GDC1/IO31RSB1
IO30RSB1
GCB2/IO29RSB1
GCA1/IO27RSB1
GCA0/IO28RSB1
GCC0/IO26RSB1
GCC1/IO25RSB1
VCCIB1
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GNDQ
GEA2/IO50RSB2
FF/GEB2/IO49RSB2
GEC2/IO48RSB2
IO47RSB2
VMV0
IO46RSB2
IO45RSB2
GND
IO44RSB2
VCC
IO43RSB2
IO24RSB1
GBC2/IO23RSB1
GBB2/IO22RSB1
IO21RSB1
IO42RSB2
IO41RSB2
IO40RSB2
4-28
Revision 17
IGLOO nano Low Power Flash FPGAs
VQ100
VQ100
VQ100
Pin Number AGLN250Z Function
Pin Number AGLN250Z Function
Pin Number AGLN250Z Function
1
GND
GAA2/IO67RSB3
IO66RSB3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO20RSB1
VMV1
2
3
VCCIB2
GNDQ
4
GAB2/IO65RSB3
IO64RSB3
IO39RSB2
IO38RSB2
IO37RSB2
GDC2/IO36RSB2
GDB2/IO35RSB2
GDA2/IO34RSB2
GNDQ
GBA1/IO19RSB0
GBA0/IO18RSB0
GBB1/IO17RSB0
GBB0/IO16RSB0
GBC1/IO15RSB0
GBC0/IO14RSB0
IO13RSB0
5
6
GAC2/IO63RSB3
IO62RSB3
7
8
IO61RSB3
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO60RSB3
GFB0/IO59RSB3
VCOMPLF
TCK
IO12RSB0
TDI
IO11RSB0
GFA0/IO57RSB3
VCCPLF
TMS
IO10RSB0
VMV2
IO09RSB0
GFA1/IO58RSB3
GFA2/IO56RSB3
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB3
TDO
IO08RSB0
GFC2/IO55RSB3
GEC1/IO54RSB3
GEC0/IO53RSB3
GEA1/IO52RSB3
GEA0/IO51RSB3
VMV3
TRST
IO07RSB0
VJTAG
IO06RSB0
GDA1/IO33RSB1
GDC0/IO32RSB1
GDC1/IO31RSB1
IO30RSB1
GCB2/IO29RSB1
GCA1/IO27RSB1
GCA0/IO28RSB1
GCC0/IO26RSB1
GCC1/IO25RSB1
VCCIB1
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GNDQ
GEA2/IO50RSB2
FF/GEB2/IO49RSB2
GEC2/IO48RSB2
IO47RSB2
VMV0
IO46RSB2
IO45RSB2
GND
IO44RSB2
VCC
IO43RSB2
IO24RSB1
GBC2/IO23RSB1
GBB2/IO22RSB1
IO21RSB1
IO42RSB2
IO41RSB2
IO40RSB2
Revision 17
4-29
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the IGLOO nano datasheet.
Revision
Changes
Page
Revision 17
(May 2013)
Deleted details related to Ambient temperature from "Enhanced Commercial I, III, IV,
Temperature Range", "IGLOO nano Ordering Information", "Temperature Grade and 2-2
Offerings", and Table 2-2 • Recommended Operating Conditions 1 to remove ambiguities
arising due to the same, and modified Note 2 (SAR 47063).
Revision 16
The "IGLOO nano Ordering Information" section has been updated to mention "Y" as
III
(December 2012) "Blank" mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43174).
The note in Table 2-100 • IGLOO nano CCC/PLL Specification and Table 2-101 • IGLOO 2-70,
nano CCC/PLL Specification referring the reader to SmartGen was revised to refer 2-71
instead to the online help associated with the core (SAR 42565).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
II
Revision 15
The status of the AGLN125 device has been modified from ’Advance’ to ’Production’ in
(September 2012) the "IGLOO nano Device Status" section (SAR 41416).
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40274).
NA
1-2
Revision 14
The "Security" section was modified to clarify that Microsemi does not support read-back
(September 2012) of programmed data.
Revision 13
(June 2012)
Figure Figure 2-34 • FIFO Read and Figure 2-35 • FIFO Write have been added (SAR 2-82
34842).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section
in the "Pin Descriptions" section: "Within the package, the VMV plane is decoupled from
the simultaneous switching noise originating from the output buffer VCCI domain" and
replaced with “Within the package, the VMV plane biases the input stage of the I/Os in
the I/O banks” (SAR 38319). The datasheet mentions that "VMV pins must be connected
to the corresponding VCCI pins" for an ESD enhancement.
3-1
Revision 12
(March 2012)
The "In-System Programming (ISP) and Security" section and "Security" section were I, 1-2
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry (SAR
34663).
Notes indicating that AGLN015 is not recommended for new designs have been added II, III
(SAR 35759).
Notes indicating that nano-Z devices are not recommended for new designs have been
added. The "Devices Not Recommended For New Designs" section is new (SAR
36759).
The Y security option and Licensed DPA Logo were added to the "IGLOO nano Ordering
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR 34722).
III
The following sentence was removed from the "Advanced Architecture" section: "In
addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V)
programming of IGLOO nano devices via an IEEE 1532 JTAG interface" (SAR 34683).
1-3
Revision 17
5-1
Datasheet Information
Revision
Changes
The "Specifying I/O States During Programming" section is new (SAR 34694).
Page
Revision 12
(continued)
1-9
The reference to guidelines for global spines and VersaTile rows, given in the "Global 2-12
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"
section of the Global Resources chapter in the IGLOO nano FPGA Fabric User's
Guide (SAR 34732).
Figure 2-4 has been modified for DIN waveform; the Rise and Fall time label has been 2-16
changed to tDIN (37106).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated 2-26,
to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software 2-20
Settings" section (SAR 34885).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics – 2-20,
Default I/O Software Settings" section, "3.3 V LVCMOS Wide Range" section and "1.2 V 2-29,
LVCMOS Wide Range" section tables were revised for clarification. They now state that 2-40
the minimum drive strength for the default software configuration when run in wide range
is ±100 µA. The drive strength displayed in software is supported in normal range only.
For a detailed I/V curve, refer to the IBIS models (SAR 34765).
Added values for minimum pulse width and removed the FRMAX row from Table 2-88 2-64 to
through Table 2-99 in the "Global Tree Timing Characteristics" section. Use the software 2-69
to determine the FRMAX for the device you are using (SAR 36953).
Table 2-100 • IGLOO nano CCC/PLL Specification and Table 2-101 • IGLOO nano 2-70
CCC/PLL Specification were updated. A note was added indicating that when the
and
CCC/PLL core is generated by Mircosemi core generator software, not all delay values 2-71
of the specified delay increments are available (SAR 34817).
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" 2-74,
tables, Figure 2-36 • FIFO Reset, and the FIFO "Timing Characteristics" tables were 2-77,
revised to ensure consistency with the software names (SAR 35754).
2-85
Reference was made to a new application note, Simultaneous Read-Write Operations in
Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail
(SAR 34865).
The "Pin Descriptions" chapter has been added (SAR 34770).
3-1
4-1
Package names used in the "Package Pin Assignments" section were revised to match
standards given in Package Mechanical Drawings (SAR 34770).
Revision 11
(Jul 2010)
The status of the AGLN060 device has changed from Advance to Production.
II
The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-15 • Different 2-10
Components Contributing to Dynamic Power Consumption in IGLOO nano Devices for
1.5 V core supply voltage (SAR 26404).
The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-17 • Different 2-11
Components Contributing to Dynamic Power Consumption in IGLOO nano Devices for
1.2 V core supply voltage (SAR 26404).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOO nano
Device Status" table on page II indicates the status for each device in the device family.
N/A
5-2
Revision 17
IGLOO nano Low Power Flash FPGAs
Revision
Changes
Page
Revision 10
(Apr 2010)
References to differential inputs were removed from the datasheet, since IGLOO nano
devices do not support differential inputs (SAR 21449).
N/A
N/A
I
A parenthetical note, "hold previous I/O state in Flash*Freeze mode," was added to each
occurrence of bus hold in the datasheet (SAR 24079).
The "In-System Programming (ISP) and Security" section was revised to add 1.2 V
programming.
The note connected with the "IGLOO nano Ordering Information" table was revised to
clarify features not available for Z feature grade devices.
III
The "IGLOO nano Device Status" table is new.
II
The definition of C in the "Temperature Grade Offerings" table was changed to "extended
commercial temperature range."
IV
1.2 V wide range was added to the list of voltage ranges in the "I/Os with Advanced I/O
Standards" section.
1-8
2-2
A note was added to Table 2-2 • Recommended Operating Conditions 1 regarding
switching from 1.2 V to 1.5 V core voltage for in-system programming. The VJTAG
voltage was changed from "1.425 to 3.6" to "1.4 to 3.6" (SAR 24052). The note regarding
voltage for programming V2 and V5 devices was revised (SAR 25213). The maximum
value for VPUMP programming voltage (operation mode) was changed from 3.45 V to
3.6 V (SAR 25220).
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to
TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors
for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were updated. Table 2-8 •
Power Supply State per Mode is new.
2-6,
2-7
The tables in the "Quiescent Supply Current" section were updated (SAR 24882 and
SAR 24112).
2-7
2-8
2-8
VJTAG was removed from Table 2-10 • Quiescent Supply Current (IDD) Characteristics,
IGLOO nano Sleep Mode* (SARs 24112, 24882, and 79503).
The note stating what was included in IDD was removed from Table 2-11 • Quiescent
Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode. The note, "per
VCCI or VJTAG bank" was removed from Table 2-12 • Quiescent Supply Current (IDD),
No IGLOO nano Flash*Freeze Mode1. The note giving IDD was changed to "IDD
NBANKS * ICCI + ICCA."
=
The values in Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Software Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) –
Default I/O Software Settings1 were updated. Wide range support information was
added.
2-9
Revision 17
5-3
Datasheet Information
Revision
Changes
Page
Revision 10
(continued)
The following tables were updated with current available information. The equivalent 2-19
software default drive strength option was added.
through
2-40
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-28 • I/O Output Buffer Maximum Resistances 1
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances
Table 2-30 • I/O Short Currents IOSH/IOSL
Timing tables in the "Single-Ended I/O Characteristics" section, including new tables for
3.3 V and 1.2 V LVCMOS wide range.
Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V
Wide Range
Table 2-63 • Minimum and Maximum DC Input and Output Levels
Table 2-67 • Minimum and Maximum DC Input and Output Levels (new)
The formulas in the notes to Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances were 2-24
revised (SAR 21348).
The text introducing Table 2-31 • Duration of Short Circuit Event before Failure was 2-25
revised to state six months at 100° instead of three months at 110° for reliability
concerns. The row for 110° was removed from the table.
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): "It 2-32
uses a 5-V tolerant input buffer and push-pull output buffer."
The FDDRIMAX and FDDOMAX values were added to tables in the "DDR Module 2-51
Specifications" section (SAR 23919). A note was added stating that DDR is not
supported for AGLN010, AGLN015, and AGLN020.
Tables in the "Global Tree Timing Characteristics" section were updated with new 2-64
information available.
Table 2-100 • IGLOO nano CCC/PLL Specification and Table 2-101 • IGLOO nano 2-70,
CCC/PLL Specification were revised (SAR 79390).
2-71
Tables in the SRAM "Timing Characteristics" section and FIFO "Timing Characteristics" 2-77,
section were updated with new information available.
2-85
3-4
Table 3-3 • TRST and TCK Pull-Down Recommendations is new.
A note was added to the "CS81" pin tables for AGLN060, AGLN060Z, AGLN125,
4-9,
AGLN125Z, AGLN250, and AGLN250Z indicating that pins F1 and F2 must be grounded through
(SAR 25007). 4-14
A note was added to the "CS81" and "VQ100" pin tables for AGLN060 and AGLN060Z 4-9,
stating that bus hold is not available for pin H7 or pin 45 (SAR 24079).
4-24
The AGLN250 function for pin C8 in the "CS81" table was revised (SAR 22134).
4-13
5-4
Revision 17
IGLOO nano Low Power Flash FPGAs
Revision / Version
Changes
Page
Revision 9 (Mar2010) All product tables and pin tables were updated to show clearly that AGLN030 is
N/A
available only in the Z feature grade at this time. The nano-Z feature grade
devices are designated with a Z at the end of the part number.
v0.9
Product Brief Advance
Packaging Advance
v0.8
Revision 8 (Jan 2009) The "Reprogrammable Flash Technology" section was revised to add "250 MHz
I
(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."
Product Brief Advance The note for AGLN030 in the "IGLOO nano Devices" table and "I/Os Per
II, II
v0.8
Package" table was revised to remove the statement regarding package
compatibility with lower density nano devices.
The "I/Os with Advanced I/O Standards" section was revised to add definitions for
hot-swap and cold-sparing.
1-8
Packaging Advance
v0.7
The "UC81", "CS81", "QN48", and "QN68" pin tables for AGLN030 are new.
4-5, 4-8,
4-17,4-21
The "CS81"pin table for AGLN060 is new.
4-9
The "CS81" and "VQ100" pin tables for AGLN060Z are new.
The "CS8" and "VQ100" pin tables for AGLN125Z are new.
The "CS81" and "VQ100" pin tables for AGLN250Z is new.
4-10, 4-25
4-12, 4-27
4-14, 4-29
N/A
Revision 7 (Apr 2009) The –F speed grade is no longer offered for IGLOO nano devices and was
removed from the datasheet.
Product Brief Advance
v0.7
DC and Switching
Characteristics
Advance v0.3
Revision 6 (Mar 2009) The "VQ100" pin table for AGLN030 is new.
4-23
N/A
Packaging Advance
v0.6
Revision 5 (Feb 2009) The "100-Pin QFN" section was removed.
Packaging Advance
v0.5
Revision 4 (Feb 2009) The QN100 package was removed for all devices.
N/A
II
Product Brief Advance "IGLOO nano Devices" table was updated to change the maximum user I/Os for
v0.6
AGLN030 from 81 to 77.
The "Device Marking" section is new.
III
II
Revision 3 (Feb 2009) The following table note was removed from "IGLOO nano Devices" table: "Six
chip (main) and three quadrant global networks are available for AGLN060 and
above."
v0.5
Product Brief Advance
The CS81 package was added for AGLN250 in the "IGLOO nano Products
Available in the Z Feature Grade" table.
IV
Packaging Advance
v0.4
The "UC81" and "CS81" pin tables for AGLN020 are new.
4-4, 4-7
4-13
The "CS81" pin table for AGLN250 is new.
Revision 17
5-5
Datasheet Information
Revision / Version
Changes
Page
Revision 2 (Dec 2008) The second table note in "IGLOO nano Devices" table was revised to state,
II
"AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
AGLN030 and smaller devices do not support this feature."
Product Brief Advance
v0.4
The I/Os per package for CS81 were revised to 60 for AGLN060, AGLN125, and
AGLN250 in the "I/Os Per Package"table.
II
4-2
I
Packaging Advance
v0.3
The "UC36" pin table is new.
Revision 1 (Nov 2008) The "Advanced I/Os" section was updated to include wide power supply voltage
support for 1.14 V to 1.575 V.
Product Brief Advance
v0.3
The AGLN030 device was added to product tables and replaces AGL030 entries
that were formerly in the tables.
IV
II
The "I/Os Per Package"table was updated for the CS81 package to change the
number of I/Os for AGLN060, AGLN125, and AGLN250 from 66 to 64.
The "Wide Range I/O Support" section is new.
1-8
2-2
The table notes and references were revised in Table 2-2 • Recommended
Operating Conditions 1. VMV was included with VCCI and a table note was added
stating, "VMV pins must be connected to the corresponding VCCI pins. See Pin
Descriptions for further information." Please review carefully.
VJTAG was added to the list in the table note for Table 2-9 • Quiescent Supply
Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*. Values were
added for AGLN010, AGLN015, and AGLN030 for 1.5 V.
2-7
VCCI was removed from the list in the table note for Table 2-10 • Quiescent
Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*.
2-8
2-8
Values for ICCA current were updated for AGLN010, AGLN015, and AGLN030 in
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze
Mode1.
Values for PAC1 and PAC2 were added to Table 2-15 • Different Components 2-10, 2-11
Contributing to Dynamic Power Consumption in IGLOO nano Devices and Table
2-17 • Different Components Contributing to Dynamic Power Consumption in
IGLOO nano Devices.
Table notes regarding wide range support were added to Table 2-21 • Summary of
Maximum and Minimum DC Input and Output Levels.
2-19
1.2 V LVCMOS wide range values were added to Table 2-22 • Summary of 2-19, 2-20
Maximum and Minimum DC Input Levels and Table 2-23 • Summary of AC
Measuring Points.
The following table note was added to Table 2-25 • Summary of I/O Timing
Characteristics—Software Default Settings and Table 2-26 • Summary of I/O
Timing Characteristics—Software Default Settings: "All LVCMOS 3.3 V software
macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B
specification."
2-21
3.3 V LVCMOS Wide Range and 1.2 V Wide Range were added to Table 2-28 • 2-23, 2-24
I/O Output Buffer Maximum Resistances 1 andTable 2-30 • I/O Short Currents
IOSH/IOSL.
5-6
Revision 17
IGLOO nano Low Power Flash FPGAs
Revision / Version
Revision 1 (cont’d)
Changes
The "QN48" pin diagram was revised.
Page
4-16
Packaging Advance
v0.2
Note 2 for the "QN48", "QN68", and "100-Pin QFN" pin diagrams was changed to 4-16, 4-19
"The die attach paddle of the package is tied to ground (GND)."
The "VQ100" pin diagram was revised to move the pin IDs to the upper left corner
instead of the upper right corner.
4-23
Revision 0 (Oct 2008) The following tables and sections were updated to add the UC81 and CS81
N/A
packages for AGL030:
Product Brief Advance
v0.2
"IGLOO nano Devices"
"I/Os Per Package"
"IGLOO nano Products Available in the Z Feature Grade"
"Temperature Grade Offerings"
The "I/Os Per Package" table was updated to add the following information to
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
II
The "IGLOO nano Products Available in the Z Feature Grade" section was
updated to remove QN100 for AGLN250.
IV
The device architecture figures, Figure 1-3 • IGLOO Device Architecture Overview
1-4
with Two I/O Banks (AGLN060, AGLN125) through Figure 1-4 • IGLOO Device through
Architecture Overview with Four I/O Banks (AGLN250), were revised. Figure 1-1 •
IGLOO Device Architecture Overview with Two I/O Banks and No RAM
(AGLN010 and AGLN030) is new.
1-5
The "PLL and CCC" section was revised to include information about CCC-GLs in
AGLN020 and smaller devices.
1-7
1-8
The "I/Os with Advanced I/O Standards" section was revised to add information
about IGLOO nano devices supporting double-data-rate applications.
Revision 17
5-7
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "IGLOO nano Device Status" table on page II, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The Microsemi products described in this advance status document may not have completed
Microsemi’s qualification process. Microsemi may amend or enhance products during the product
introduction and qualification process, resulting in changes in device functionality or performance. It is
the responsibility of each customer to ensure the fitness of any Microsemi product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and other
high-reliability applications. Consult Microsemi’s Terms and Conditions for specific liability exclusions
relating to life-support applications. A reliability report covering all of the Microsemi SoC Products
Group’s products is at http://www.microsemi.com/socdocuments/ORT_Report.pdf. Microsemi also offers
a variety of enhanced qualification and lot acceptance screening procedures. Contact your local
Microsemi sales office for additional reliability information.
5-8
Revision 17
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
51700110-17/6.13
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