AGLP030V5-VQG128YC [MICROSEMI]
Field Programmable Gate Array;型号: | AGLP030V5-VQG128YC |
厂家: | Microsemi |
描述: | Field Programmable Gate Array 栅 |
文件: | 总134页 (文件大小:6979K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 14
IGLOO PLUS Low Power Flash FPGAs
with Flash*Freeze Technology
Advanced I/O
Features and Benefits
Low Power
•
•
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—4 Banks per Chip on All
®
IGLOO PLUS Devices
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
•
Single-Ended
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
Selectable Schmitt Trigger Inputs
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
I/O
Standards:
LVTTL,
LVCMOS
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
•
•
Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
•
•
Configurable Hold Previous State, Tristate, HIGH, or LOW State
per I/O in Flash*Freeze Mode
Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode
•
•
•
•
•
•
•
Feature Rich
•
•
•
30 k to 125 k System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 212 User I/Os
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL†
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
In-System Programming (ISP) and Security
•
•
1 kbit of FlashROM User Nonvolatile Memory
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
†
†
(AES) Decryption via JTAG (IEEE 1532–compliant)
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except ×18)
®
†
•
FlashLock Designed to Secure FPGA Contents
•
High-Performance Routing Hierarchy
•
Segmented, Hierarchical Routing and Clock Structure
Table 1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
AGLP030
AGLP060
AGLP125
30,000
60,000
512
1,584
10
125,000
1,024
3,120
16
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
256
792
5
–
18
36
–
4
8
Secure (AES) ISP
–
Yes
1
Yes
1
FlashROM Kbits
1
Integrated PLL in CCCs 1
VersaNet Globals 2
–
1
1
6
18
18
I/O Banks
4
4
4
Maximum User I/Os
120
157
212
Package Pins
CS
VQ
CS201, CS289
VQ128
CS201, CS289
VQ176
CS281, CS289
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
September 2012
I
© 2012 Microsemi Corporation
IGLOO PLUS Low Power Flash FPGAs
1
I/Os Per Package
IGLOO PLUS Devices
Package
CS201
AGLP030
AGLP060
AGLP125
Single-Ended I/Os
120
–
157
–
–
212
212
–
CS281
CS289
120
101
–
157
–
VQ128
VQ176
137
–
Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
Table 2 • IGLOO PLUS FPGAs Package Size Dimensions
Package
CS201
8 × 8
64
CS281
10 × 10
100
CS289
14 × 14
196
VQ128
14 × 14
196
VQ176
20 × 20
400
Length × Width (mm/mm)
Nominal Area (mm2)
Pitch (mm)
0.5
0.5
0.8
0.4
0.4
Height (mm)
0.89
1.05
1.20
1.0
1.0
IGLOO PLUS Device Status
IGLOO PLUS Device
Status
AGLP030
Production
Production
Production
AGLP060
AGLP125
II
Revision 14
IGLOO PLUS Low Power Flash FPGAs
IGLOO PLUS Ordering Information
_
AGLP125
V2
CS
G
289
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C ambient temperature)
I = Industrial (–40°C to +85°C ambient temperature)
PP= Pre-Production
ES= Engineering Sample (room temperature only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
=
=
CS
VQ
Chip Scale Package (0.5 mm and 0.8 mm pitches)
Very Thin Quad Flat Pack (0.4 mm pitch)
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
AGLP030 = 30,000 System Gates
AGLP060 = 60,000 System Gates
AGLP125 = 125,000 System Gates
Notes:
1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly.
2. "G" indicates RoHS-compliant packages.
Revision 14
III
IGLOO PLUS Low Power Flash FPGAs
Temperature Grade Offerings
Package
CS201
CS281
CS289
VQ128
VQ176
Notes:
AGLP030
AGLP060
AGLP125
C, I
–
C, I
–
–
C, I
C, I
–
C, I
C, I
–
C, I
–
C, I
–
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/company/contact/default.aspx.
IV
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table of Contents
IGLOO PLUS Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO PLUS DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Package Pin Assignments
VQ128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
VQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
CS201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
CS289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Revision 14
V
1 – IGLOO PLUS Device Family Overview
General Description
The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power
FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of
advanced features.
The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-low
power mode that consumes as little as 5 µW while retaining the design information, SRAM content,
registers, and I/O states. Flash*Freeze technology simplifies power management through I/O and clock
management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO
PLUS device is completely functional in the system. This allows the IGLOO PLUS device to control
system power management based on external inputs (e.g., scanning for keyboard stimulus) while
consuming minimal power.
Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low power,
single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have
up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os.
The AGLP030 devices have no PLL or RAM support.
Flash*Freeze Technology
The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low power Flash*Freeze mode. IGLOO PLUS devices do not need additional components to turn off
I/Os or clocks while retaining the design information, SRAM content, registers, and I/O states.
Flash*Freeze technology is combined with in-system programmability, which enables users to quickly
and easily upgrade and update their designs in the final stages of manufacturing or in the field. The
ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages (1.2 V to 1.5 V)
allows further reduction in power consumption, thus achieving the lowest total system power.
During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,
tristate, or set as HIGH or LOW.
The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage
solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS devices the
best fit for portable electronics.
Flash Advantages
Low Power
IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal
choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings;
power is even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.
Revision 14
1-1
IGLOO PLUS Device Family Overview
Security
Nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOO PLUS devices incorporate FlashLock, which
provides a unique combination of reprogrammability and design security without external overhead,
advantages that only an FPGA with nonvolatile flash programming can offer.
IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to
provide the highest level of security in the FPGA industry for programmed intellectual property and
configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to
loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was
adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977
DES standard. IGLOO PLUS devices have a built-in AES decryption engine and a flash-based AES key
that make them the most comprehensive programmable logic device security solution available today.
IGLOO PLUS devices with AES-based security provide a high level of protection for secure, remote field
updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands
of system overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and AES security,
is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
with industry-standard security, making remote ISP possible. An IGLOO PLUS device provides the best
available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO PLUS
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and
system reliability.
The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and I/Os,
eliminating the need for additional supplies while minimizing total power consumption.
Live at Power-Up
Flash-based IGLOO PLUS devices support Level 0 of the LAPU classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature
of flash-based IGLOO PLUS devices greatly simplifies total system design and reduces total system
cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and
brownouts in system power will not corrupt the IGLOO PLUS device's flash configuration, and unlike
SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This
enables the reduction or complete removal of the configuration PROM, expensive voltage monitor,
brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO PLUS
devices simplify total system design and reduce cost and design risk while increasing system reliability
and improving system initialization time.
IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done
almost instantly (within 1 µs), and the device retains configuration and data in registers and RAM. Unlike
SRAM-based FPGAs, the device does not need to reload configuration and design state from external
memory components; instead, it retains all necessary information to resume operation immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based IGLOO PLUS devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The IGLOO PLUS family device architecture mitigates the need for
1-2
Revision 14
IGLOO PLUS Low Power Flash FPGAs
ASIC migration at higher user volumes. This makes the IGLOO PLUS family a cost-effective ASIC
replacement solution, especially for applications in the consumer, networking/communications,
computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS flash-
based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS FPGAs
cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection
and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO PLUS family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130 nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs. The
IGLOO PLUS device consists of five distinct and programmable architectural features (Figure 1-1 on
page 1-4):
•
•
•
•
•
•
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory†
Extensive CCCs and PLLs†
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the IGLOO PLUS core tile as either a three-input lookup table (LUT)
equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs. VersaTiles are
connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
† The AGLP030 device does not support PLL or SRAM.
Revision 14
1-3
IGLOO PLUS Device Family Overview
Bank 0
*
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 2
Note: *Not supported by AGLP030 devices
Figure 1-1 • IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030,
AGLP060, and AGLP125)
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains
all SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state
or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pull-
up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins,
or PLL, and the device consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of entering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
Flash*Freeze
Mode Control
IGLOO PLUS
FPGA
Flash*Freeze Pin
Figure 1-2 • IGLOO PLUS Flash*Freeze Mode
1-4
Revision 14
IGLOO PLUS Low Power Flash FPGAs
VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®
core tiles. The IGLOO PLUS VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
User Nonvolatile FlashROM
IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in AGLP030 devices), as in security keys
stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The IGLOO PLUS development software solutions, Libero® Integrated Design Environment (IDE) and
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential
programming files for applications requiring a unique serial number in each part. Another feature allows
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly
and easily using Libero IDE and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
Revision 14
1-5
IGLOO PLUS Device Family Overview
SRAM and FIFO
IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side.
Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are
256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports
that can be configured with different bit widths on each port. For example, data can be sent through a
4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.
Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL.
The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine
access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
•
•
•
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps ×
250 MHz / fOUT_CCC
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2
V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO PLUS FPGAs support many different I/O
standards.
The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration
of these banks determines the I/O standards supported.
1-6
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Each I/O module contains several input, output, and output enable registers.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
IGLOO PLUS devices support JEDEC-defined wide range I/O operation. IGLOO PLUS devices support
both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of
2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to
1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-4 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
Revision 14
1-7
IGLOO PLUS Device Family Overview
Figure 1-4 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
1-8
Revision 14
2 – IGLOO PLUS DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
Limits
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
–0.3 V to 3.6 V
–65 to +150
+125
Units
V
VJTAG
VPUMP
VCCPLL
VCCI
JTAG DC voltage
V
Programming voltage
Analog power supply (PLL)
DC I/O buffer supply voltage
I/O input voltage
V
V
V
VI1
V
2
TSTG
Storage temperature
Junction temperature
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 14
2-1
IGLOO PLUS DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions1,2
Symbol
TA
Parameter
Commercial
0 to +70
Industrial
–40 to +85
–40 to +100
Units
°C
°C
V
Ambient temperature
Junction temperature2
TJ
0 to + 85
VCC3
1.5 V DC core supply voltage 4
1.2 V–1.5 V wide range core voltage5,6
JTAG DC voltage
1.425 to 1.575 1.425 to 1.575
1.14 to 1.575
1.4 to 3.6
1.14 to 1.575
1.4 to 3.6
V
VJTAG
V
VPUMP7 Programming voltage
Programming mode
Operation
3.15 to 3.45
0 to 3.6
3.15 to 3.45
0 to 3.6
V
V
VCCPLL8 Analog power supply (PLL) 1.5 V DC core supply voltage4
1.425 to 1.575 1.425 to 1.575
V
1.2 V–1.5 V wide range core 1.14 to 1.575
1.14 to 1.575
V
voltage5
VCCI
1.2 V DC supply voltage5
1.14 to 1.26
1.14 to 1.26
V
V
V
V
V
V
V
1.2 V DC wide range supply voltage5
1.14 to 1.575
1.14 to 1.575
1.5 V DC supply voltage
1.425 to 1.575 1.425 to 1.575
1.8 V DC supply voltage
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
2.5 V DC supply voltage
3.3 V wide range DC supply voltage9
3.3 V DC supply voltage
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank.
®
4. For IGLOO PLUS V5 devices
5. For IGLOO PLUS V2 devices only, operating at VCCI VCC.
6. All IGLOO PLUS devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using V2
devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming.
7. VPUMP can be left floating during operation (not programming mode).
8. VCCPLL pins should be tied to VCC pins. See the Pin Descriptions chapter of the IGLOO PLUS FPGA Fabric User’s
Guide for further information.
9. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature 1
Program
Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG
(°C) 2
Maximum Operating
Junction
Product
Grade
Programming
Cycles
Temperature TJ (°C) 2
Commercial
Industrial
Notes:
500
500
20 years
20 years
110
110
100
100
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or
Undershoot Duration
Maximum Overshoot/
Undershoot2
VCCI
as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These
circuits ensure easy transition from the powered-off state to the powered-up state of the device. The
many different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in
Figure 2-1 on page 2-4.
There are five regions to consider during power-up.
IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on
page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
VCC Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Revision 14
2-3
IGLOO PLUS DC and Switching Characteristics
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes Low and/or the
output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the IGLOO PLUS Device Family User’s Guide for information on clock
and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential inputs)
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
V
= 0.85 V ± 0.25 V
a
Deactivation trip point:
= 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
V
d
VCCI
Activation trip point:
= 0.9 V ± 0.3 V
Min VCCI datasheet specification
V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
a
Deactivation trip point:
= 0.8 V ± 0.3 V
V
d
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Revision 14
IGLOO PLUS Low Power Flash FPGAs
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
V
= 0.85 V ± 0.2 V
a
Deactivation trip point:
= 0.75 V ± 0.2 V
Region 1: I/O buffers are OFF
V
d
VCCI
Activation trip point:
Va = 0.9 V ± 0.15 V
Deactivation trip point:
Vd = 0.8 V ± 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Revision 14
2-5
IGLOO PLUS DC and Switching Characteristics
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction temperature to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction
temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C
------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------
Maximum Power Allowed =
=
= 1.46 W
EQ 2
ja(C/W)
20.5°C/W
Table 2-5 • Package Thermal Resistivities
ja
Pin
200 ft./
min.
500 ft./
Package Type
Count
CS201
CS281
CS289
VQ128
VQ176
jc
Still Air
TBD
min.
TBD
TBD
TBD
TBD
TBD
Units
Chip Scale Package (CSP)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
C/W
C/W
C/W
C/W
C/W
TBD
TBD
Very Thin Quad Flat Package (VQFP)
TBD
TBD
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.425 V)
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.425
1.5
–40°C
0.934
0.855
0.799
0°C
25°C
0.971
0.891
0.832
70°C
1.000
0.917
0.857
85°C
1.007
0.924
0.864
100°C
0.953
0.874
0.816
1.013
0.929
0.868
1.575
2-6
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.14 V)
For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
–40°C
0.963
0.853
0.781
0°C
25°C
0.989
.0877
0.803
70°C
1.000
0.893
0.813
85°C
1.007
0.893
0.819
100°C
1.011
0.897
0.822
1.14
0.975
0.865
0.792
1.2
1.26
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages
(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage.
Microsemi recommends using the Power Calculator and SmartPower software estimation tools to
evaluate the projected static and active power based on the user design, power mode usage, operating
voltage, and temperature.
Table 2-8 • Power Supply State per Mode
Power Supply Configurations
Modes/Power Supplies
Flash*Freeze
Sleep
VCC
On
VCCPLL
On
VCCI
On
VJTAG
On
VPUMP
On/off/floating
Off
Off
Off
On
Off
Shutdown
Off
Off
Off
Off
Off
No Flash*Freeze
On
On
On
On
On/off/floating
Note: Off: Power Supply level = 0 V
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode*
Core Voltage
1.2 V
AGLP030
AGLP060
AGLP125
Units
µA
Typical (25°C)
4
6
8
13
18
1.5 V
10
µA
Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.
Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode*
ICCI Current
Core Voltage
1.2 V
AGLP030 AGLP060 AGLP125 Units
VCCI = 1.2 V (per bank) Typical (25°C)
VCCI = 1.5 V (per bank) Typical (25°C)
VCCI = 1.8 V (per bank) Typical (25°C)
VCCI = 2.5 V (per bank) Typical (25°C)
VCCI = 3.3 V (per bank) Typical (25°C)
Note: *IDD = NBANKS * ICCI
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
Revision 14
2-7
IGLOO PLUS DC and Switching Characteristics
Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode
Core Voltage
AGLP030
AGLP060
AGLP125
Units
Typical (25°C)
1.2 V / 1.5 V
0
0
0
µA
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1
Core Voltage AGLP030 AGLP060 AGLP125 Units
ICCA Current 2
Typical (25°C)
1.2 V
1.5 V
6
10
20
13
28
µA
µA
16
ICCI or IJTAG Current
VCCI / VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI / VJTAG = 1.5 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
VCCI / VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI / VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI / VJTAG = 3.3 V (per bank)
Typical (25°C)
Notes:
1. IDD = N
* ICCI + ICCA. JTAG counts as one bank when powered.
BANKS
2. Includes VCC, VCCPLL, and VPUMP currents.
2-8
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Power per I/O Pin
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Dynamic Power
VCCI (V)
PAC9 (µW/MHz) 1
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3 V LVCMOS Wide Range2
3.3 V LVCMOS Wide Range2 – Schmitt Trigger
2.5 V LVCMOS
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
1.2
1.2
16.26
18.95
16.26
18.95
4.59
6.01
1.61
1.70
0.96
0.90
0.55
0.47
0.55
0.47
2.5 V LVCMOS – Schmitt Trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt Trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.2 V LVCMOS3
1.2 V LVCMOS3 – Schmitt Trigger
1.2 V LVCMOS Wide Range3
1.2 V LVCMOS Wide Range3 – Schmitt Trigger
Notes:
1. PAC9 is the total dynamic power measured on VCCI.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC.
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
5
5
5
5
5
5
5
3.3
3.3
2.5
1.8
1.5
1.2
1.2
127.11
127.11
70.71
35.57
24.30
15.22
15.22
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS4
1.2 V LVCMOS Wide Range4
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PAC10 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC.
Revision 14
2-9
IGLOO PLUS DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLP125 AGLP060 AGLP030
11.03
0.81
9.3
0.81
0.81
0.11
0.057
0.207
0.17
0.7
9.3
PAC2
Clock contribution of a Global Spine
0.41
PAC3
Clock contribution of a VersaTile row
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
PAC5
PAC6
PAC7
PAC8
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
See Table 2-13 on page 2-9.
PAC10
PAC11
PAC12
PAC13
See Table 2-14 on page 2-9.
25.00
30.00
2.70
2-10
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
PDC1
Definition
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
AGLP125
AGLP060
AGLP030
See Table 2-12 on page 2-8
See Table 2-11 on page 2-8
See Table 2-9 on page 2-7
1.841
PDC2
PDC3
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-12 on page 2-8
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
®
calculator or the SmartPower tool in Libero Integrated Design Environment (IDE) software.
Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLP125 AGLP060 AGLP030
7.07
0.52
5.96
0.52
0.52
0.07
0.045
0.186
0.11
5.96
0.26
PAC2
Clock contribution of a Global Spine
PAC3
Clock contribution of a VersaTile row
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
PAC5
PAC6
PAC7
PAC8
0.45
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
See Table 2-13 on page 2-9
PAC10
PAC11
PAC12
PAC13
See Table 2-14 on page 2-9
25.00
30.00
2.10
Revision 14
2-11
IGLOO PLUS DC and Switching Characteristics
Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
PDC1
Definition
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
AGLP125
AGLP060
AGLP030
See Table 2-12 on page 2-8
See Table 2-11 on page 2-8
See Table 2-9 on page 2-7
0.901
PDC2
PDC3
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-12 on page 2-8
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or the SmartPower tool in Libero IDE software.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on
page 2-14.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on
page 2-14.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
PTOTAL = PSTAT + PDYN
TOTAL
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA
Fabric User's Guide.
2-12
Revision 14
IGLOO PLUS Low Power Flash FPGAs
NROW is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric
User's Guide.
F
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
N
S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
F
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on
page 2-14.
Revision 14
2-13
IGLOO PLUS DC and Switching Characteristics
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
1
2
10%
Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
1
2
3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
2-14
Revision 14
IGLOO PLUS Low Power Flash FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVCMOS 2.5 V Output Drive
Strength = 12 mA High Slew Rate
t
= 1.40 ns
t
= 0.89 ns
PD
PD
t
= 1.62 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
High slew rate
LVTTL
t
= 1.62 ns
DP
t
= 1.98 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
Output drive strength = 8 mA
High slew rate
LVTTL
t
= 1.06 ns
PY
t
= 1.70 ns
DP
t
= 1.24 ns
PD
I/O Module
(Non-Registered)
Input LVCMOS 2.5 V
D
Q
Combinational Cell
Y
Output drive strength = 4 mA
High slew rate
LVCMOS 1.5 V
t
t
= 0.63 ns
= 0.18 ns
ICLKQ
ISUD
t
= 2.07 ns
DP
t
= 0.86 ns
PD
Input LVTTL
Clock
I/O Module
Register Cell
(Registered)
Register Cell
Combinational Cell
Y
t
= 0.85 ns
PY
D
Q
D
Q
D
t
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
I/O Module
t
= 0.87 ns
PD
t
= 1.62 ns
(Non-Registered)
DP
t
t
= 0.80 ns
= 0.84 ns
CLKQ
= 0.89 ns
= 0.18 ns
t
t
= 0.80 ns
= 0.84 ns
OCLKQ
CLKQ
SUD
t
LVCMOS 1.5 V
OSUD
SUD
Input LVTTL
Clock
Input LVTTL
Clock
t
= 1.15 ns
PY
t
= 0.85 ns
t
= 0.85 ns
PY
PY
Figure 2-3 • Timing Model
Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
Revision 14
2-15
IGLOO PLUS DC and Switching Characteristics
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
t
PY = MAX(tPY(R), tPY(F))
DIN = MAX(tDIN(R), tDIN(F))
t
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
2-16
Revision 14
IGLOO PLUS Low Power Flash FPGAs
t
t
DOUT
DP
D Q
CLK
PAD
DOUT
Std
Load
D
From Array
t
t
= MAX(t (R), t (F))
DP
DP
DP
I/O Interface
t
= MAX(t
(R), t
(F))
DOUT
DOUT
DOUT
t
DOUT
DOUT
VCC
(R)
(F)
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
Vtrip
V
OL
t
t
DP
DP
(R)
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
Revision 14
2-17
IGLOO PLUS DC and Switching Characteristics
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
2-18
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Equiv.
Software
VIL
VIH
VOL
VOH
IOL1 IOH1
Default
Drive
Drive Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard Strength Option2 Rate
V
mA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
12 mA High –0.3
0.8
2
3.6
3.6
3.6
0.4
2.4
12 12
3.3 V LVCMOS 100 µA 12 mA High –0.3
Wide Range3
0.8
0.7
2
0.2
VDD 3 0.2 0.1 0.1
2.5 V LVCMOS 12 mA 12 mA High –0.3
1.7
0.7
1.7
12 12
1.8 V LVCMOS 8 mA
1.5 V LVCMOS 4 mA
8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
8
4
2
8
4
2
4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
1.2 V
2 mA
LVCMOS4
1.2 V LVCMOS 100 µA
Wide Range4,5
2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 3.6
0.1
VCCI – 0.1 0.1 0.1
Notes:
1. Currents are measured at 85°C junction temperature.
2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 µA drive strength only. The configuration
will not operate at the equivalent software default drive strength. These values are for normal ranges only.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to IGLOO PLUS V2 devices operating at VCC VCC.
I
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
Revision 14
2-19
IGLOO PLUS DC and Switching Characteristics
Table 2-22 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL3
µA
10
10
10
10
10
10
10
IIH4
µA
10
10
10
10
10
10
10
IIL3
µA
15
15
15
15
15
15
15
IIH4
µA
15
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS5
1.2 V LVCMOS Wide Range5
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
5. Applicable to IGLOO PLUS V2 devices operating at VCCI ³ VCC.
2-20
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-23 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.4 V
1.4 V
1.2 V
1.8 V LVCMOS
0.90 V
0.75 V
0.60 V
0.60 V
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Table 2-24 • I/O AC Parameter Definitions
Parameter
Parameter Definition
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
tDP
tPY
tDOUT
tEOUT
tDIN
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
tZH
tLZ
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Revision 14
2-21
IGLOO PLUS DC and Switching Characteristics
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
12 mA 12 mA High 5 pF
–
0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns
3.3 V LVCMOS
3.3 V LVCMOS 100 µA 12 mA High 5 pF – 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns
Wide Range2
2.5 V LVCMOS 12 mA 12 mA High 5 pF
–
–
–
0.97 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 ns
0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns
0.97 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57 ns
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
8 mA 8 mA High 5 pF
4 mA 4 mA High 5 pF
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-22
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5 pF
–
–
0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns
0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns
3.3 V LVCMOS 100 µA12 mA High 5 pF
Wide Range2
2.5 V LVCMOS 12 mA 12 mA High 5 pF
–
–
–
–
–
0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns
0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns
0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns
0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns
0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
8 mA 8 mA High 5 pF
4 mA 4 mA High 5 pF
2 mA 2 mA High 5 pF
1.2 V LVCMOS 100 µA 2 mA High 5 pF
Wide Range3
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-23
IGLOO PLUS DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-27 • Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
pF
CIN
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
Table 2-28 • I/O Output Buffer Maximum Resistances 1
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
() 2
100
100
50
() 3
3.3 V LVTTL / 3.3V LVCMOS
2 mA
4 mA
6 mA
8 mA
300
300
150
150
75
50
12 mA
16 mA
100 µA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
100 µA
25
25
75
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as equivalent software default drive
100
100
50
200
200
100
100
50
50
25
1.8 V LVCMOS
1.5 V LVCMOS
200
100
50
225
112
56
50
56
200
100
157.5
157.5
224
112
163.8
163.8
1.2 V LVCMOS
1.2 V LVCMOS Wide Range4
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCC , drive strength selection, temperature, and process. For board design considerations and detailed output buffer
I
resistances, use the corresponding IBIS model on the Microsemi SoC Products Group website at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
3.
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
R
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC.
2-24
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
()
()
VCCI
Min.
10 K
10 K
11 K
18 K
19 K
25 K
19 K
Max.
45 K
45 K
55 K
70 K
90 K
110 K
110 K
Min.
10 K
10 K
12 K
17 K
19 K
25 K
19 K
Max.
45 K
3.3 V
3.3 V (wide range I/Os)
45 K
2.5 V
74 K
1.8 V
110 K
140 K
150 K
150 K
1.5 V
1.2 V
1.2 V (wide range I/Os)
Notes:
1.
2.
R
R
= (VCCImax – VOHspec) / I
(WEAK PULL-UP-MAX)
(WEAK PULL-UP-MIN)
= (VOLspec) / I
(WEAK PULLDOWN-MAX)
(WEAK PULLDOWN-MIN)
Table 2-30 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
27
27
25
25
54
51
54
51
12 mA
16 mA
100 µA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
100 µA
109
109
103
103
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as equivalent software default drive
18
18
37
37
74
11
22
44
44
16
33
26
26
16
16
32
32
65
9
1.8 V LVCMOS
1.5 V LVCMOS
17
35
35
13
25
20
20
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Note: *TJ = 100°C
Revision 14
2-25
IGLOO PLUS DC and Switching Characteristics
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-31 • Duration of Short Circuit Event before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
6 months
Table 2-32 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
240 mV
3.3 V LVTTL/LVCMOS (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
140 mV
80 mV
60 mV
40 mV
Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Rise/Fall
Time (min.)
Input Rise/Fall Time
Input Buffer
(max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but
input noise voltage
cannot exceed Schmitt
hysteresis.
20 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board
noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure
that there is no excessive noise coupling into input signals.
2-26
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-34 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
8
2
4
6
8
25
25
27
27
4 mA
6 mA
51
54
8 mA
51
54
12 mA
16 mA
Notes:
12 12
16 16
103
103
109
109
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-35 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Revision 14
2-27
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.97 3.94 0.18 0.85 1.15
0.97 3.20 0.18 0.85 1.15
0.97 3.20 0.18 0.85 1.15
0.97 2.72 0.18 0.85 1.15
0.97 2.72 0.18 0.85 1.15
0.66 4.02 3.46 1.82 1.87
0.66 3.27 2.94 2.04 2.27
0.66 3.27 2.94 2.04 2.27
0.66 2.78 2.57 2.20 2.53
0.66 2.78 2.57 2.20 2.53
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.97 2.36 0.18 0.85 1.15
0.97 1.96 0.18 0.85 1.15
0.97 1.96 0.18 0.85 1.15
0.97 1.76 0.18 0.85 1.15
0.97 1.76 0.18 0.85 1.15
0.66 2.41 1.90 1.82 1.98
0.66 2.01 1.56 2.04 2.38
0.66 2.01 1.56 2.04 2.38
0.66 1.80 1.39 2.20 2.64
0.66 1.80 1.39 2.20 2.64
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Applies to 1.2 V DC Core Voltage
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.98 4.56 0.19 0.99 1.37
0.98 3.80 0.19 0.99 1.37
0.98 3.80 0.19 0.99 137
0.98 3.31 0.19 0.99 1.37
0.98 3.31 0.19 0.99 1.37
0.67 4.63 3.98 2.26 2.57
0.67 3.96 3.45 2.49 2.98
0.67 3.86 3.45 2.49 2.98
0.67 3.36 3.07 2.65 3.25
0.67 3.36 3.07 2.65 3.25
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.98 2.92 0.19 0.99 1.37
0.98 2.52 0.19 0.99 1.37
0.98 2.52 0.19 0.99 1.37
0.98 2.31 0.19 0.99 1.37
0.98 2.31 0.19 0.99 1.37
0.67 2.97 2.38 2.25 2.70
0.67 2.56 2.03 2.49 3.11
0.67 2.56 2.03 2.49 3.11
0.67 2.34 1.86 2.65 3.38
0.67 2.34 1.86 2.65 3.38
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray
2-28
Revision 14
IGLOO PLUS Low Power Flash FPGAs
3.3 V LVCMOS Wide Range
Table 2-40 • Minimum and Maximum DC Input and Output Levels
Equivalent
Software
Default
Drive
3.3 V LVCMOS Strength
Wide Range
Option1
VIL
VIH
VOL
VOH
IOL IOH IOSL
Max.
µA µA
IOSH IIL2 IIH3
Max.
Drive
Strength
Min. Max. Min. Max. Max.
Min.
V
V
V
V
2
2
2
2
2
2
V
V
µA4
25
µA4
27
µA5 µA5
10 10
10 10
10 10
10 10
10 10
10 10
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
3.6
3.6
3.6
3.6
3.6
3.6
0.2 VDD – 0.2 100 100
0.4 VDD – 0.2 100 100
0.4 VDD – 0.2 100 100
0.4 VDD – 0.2 100 100
4 mA
6 mA
8 mA
12 mA
16 mA
25
27
51
54
51
54
0.4 VDD – 0.2 100 100 103
0.4 VDD – 0.2 100 100 103
109
109
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Revision 14
2-29
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-42 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
STD
STD
STD
STD
STD
0.97 5.85 0.18 1.18 1.64
0.97 4.70 0.18 1.18 1.64
0.97 4.70 0.18 1.18 1.64
0.97 3.96 0.18 1.18 1.64
0.97 3.96 0.18 1.18 1.64
0.66 5.86 5.05 2.57 2.57
0.66 4.72 4.27 2.92 3.19
0.66 4.72 4.27 2.92 3.19
0.66 3.98 3.70 3.16 3.59
0.66 3.98 3.70 3.16 3.59
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-43 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
STD
STD
STD
STD
STD
0.97
0.97
0.97
0.97
0.97
3.39 0.18 1.18 1.64
2.79 0.18 1.18 1.64
2.79 0.18 1.18 1.64
2.47 0.18 1.18 1.64
2.47 0.18 1.18 1.64
0.66
0.66
0.66
0.66
0.66
3.41 2.69 2.57 2.73
2.80 2.17 2.92 3.36
2.80 2.17 2.92 3.36
2.48 1.91 3.16 3.76
2.48 1.91 3.16 3.76
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
Applies to 1.2 V DC Core Voltage
2-30
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-44 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
STD
STD
STD
STD
STD
0.98 6.68 0.19 1.32 1.92
0.98 5.51 0.19 1.32 1.92
0.98 5.51 0.19 1.32 1.92
0.98 4.75 0.19 1.32 1.92
0.98 4.75 0.19 1.32 1.92
0.67 6.68 5.74 3.13 3.47
0.67 5.51 4.94 3.48 4.11
0.67 5.51 4.94 3.48 4.11
0.67 4.75 4.36 3.73 4.52
0.67 4.75 4.36 3.73 4.52
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-45 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
STD
STD
STD
STD
STD
0.98
0.98
0.98
0.98
0.98
4.16 0.19 1.32 1.92
3.54 0.19 1.32 1.92
3.54 0.19 1.32 1.92
3.21 0.19 1.32 1.92
3.21 0.19 1.32 1.92
0.67
0.67
0.67
0.67
0.67
4.16 3.32 3.12 3.66
3.54 2.79 3.48 4.31
3.54 2.79 3.48 4.31
3.21 2.52 3.73 4.73
3.21 2.52 3.73 4.73
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
Revision 14
2-31
IGLOO PLUS DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-46 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
16
16
32
32
65
18
18
37
37
74
12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2-32
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-48 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 4.44 0.18 1.06 1.22
0.97 3.61 0.18 1.06 1.22
0.97 3.61 0.18 1.06 1.22
0.97 3.07 0.18 1.06 1.22
0.66 4.53 4.15 1.80 1.70
0.66 3.69 3.50 2.05 2.18
0.66 3.69 3.50 2.05 2.18
0.66 3.14 3.03 2.22 2.48
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-49 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 2.41 0.18 1.06 1.22
0.97 1.99 0.18 1.06 1.22
0.97 1.99 0.18 1.06 1.22
0.97 1.77 0.18 1.06 1.22
0.66 2.47 2.22 1.79 1.77
0.66 2.04 1.75 2.04 2.25
0.66 2.04 1.75 2.04 2.25
0.66 1.81 1.51 2.22 2.56
ns
ns
ns
ns
6 mA
8 mA
12 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Applies to 1.2 V DC Core Voltage
Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 5.04 0.19 1.19 1.40
0.98 4.19 0.19 1.19 1.40
0.98 4.19 0.19 1.19 1.40
0.98 3.63 0.19 1.19 1.40
0.67 5.12 4.65 2.22 2.36
0.67 4.25 3.98 2.48 2.85
0.67 4.25 3.98 2.48 2.85
0.67 3.69 3.50 2.66 3.16
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 2.96 0.19 1.19 1.40
0.98 2.52 0.19 1.19 1.40
0.98 2.52 0.19 1.19 1.40
0.98 2.29 0.19 1.19 1.40
0.67 3.00 2.67 2.22 2.46
0.67 2.56 2.18 2.47 2.95
0.67 2.56 2.18 2.47 2.95
0.67 2.32 1.94 2.65 3.27
ns
ns
ns
ns
6 mA
8 mA
12 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Revision 14
2-33
IGLOO PLUS DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-52 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL1 IIH2
Drive
Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 µA4 µA4
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
2
4
6
8
9
11
22
44
44
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
17
35
35
6
8
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-53 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2-34
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-54 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
Units
ns
STD
STD
STD
STD
0.97 5.89 0.18 1.00 1.43
0.97 4.82 0.18 1.00 1.43
0.97 4.13 0.18 1.00 1.43
0.97 4.13 0.18 1.00 1.43
0.66 6.01 5.43 1.78 1.30
0.66 4.92 4.56 2.08 2.08
0.66 4.21 3.96 2.30 2.46
0.66 4.21 3.96 2.30 2.46
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-55 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 2.82 0.18 1.00 1.43
0.97 2.30 0.18 1.00 1.43
0.97 2.00 0.18 1.00 1.43
0.97 2.00 0.18 1.00 1.43
0.66 2.88 2.78 1.78 1.35
0.66 2.35 2.11 2.08 2.15
0.66 2.04 1.76 2.29 2.55
0.66 2.04 1.76 2.29 2.55
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Applies to 1.2 V DC Core Voltage
Table 2-56 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 6.43 0.19 1.12 1.61
0.98 5.33 0.19 1.12 1.61
0.98 4.61 0.19 1.12 1.61
0.98 4.61 0.19 1.12 1.61
0.67 6.54 5.93 2.19 1.88
0.67 5.41 5.03 2.50 2.68
0.67 4.69 4.41 2.72 3.07
0.67 4.69 4.41 2.72 3.07
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-57 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 3.30 0.19 1.12 1.61
0.98 2.76 0.19 1.12 1.61
0.98 2.45 0.19 1.12 1.61
0.98 2.45 0.19 1.12 1.61
0.67 3.34 3.21 2.19 1.93
0.67 2.79 2.51 2.50 2.76
0.67 2.48 2.16 2.71 3.16
0.67 2.48 2.16 2.71 3.16
ns
ns
ns
ns
4 mA
6 mA
8 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Revision 14
2-35
IGLOO PLUS DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-58 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA3
mA3 µA4 µA4
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.7 * VCCI
–0.3 0.35 * VCCI 0.7 * VCCI
3.6
3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
2
4
13
25
16
33
10 10
10 10
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2-36
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-60 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.97 6.07 0.18 1.16 1.62
0.97 5.24 0.18 1.16 1.62
0.66 6.19 5.53 2.13 2.02
0.66 5.34 4.81 2.37 2.47
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-61 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.97 2.65 0.18 1.16 1.62
0.97 2.29 0.18 1.16 1.62
0.66 2.71 2.43 2.13 2.11
0.66 2.33 2.00 2.37 2.57
ns
ns
4 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Applies to 1.2 V DC Core Voltage
Table 2-62 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.98 6.57 0.19 1.26 1.80
0.98 5.72 0.19 1.26 1.80
0.67 6.68 6.01 2.54 2.59
0.67 5.81 5.27 2.79 3.05
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-63 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.98 3.08 0.19 1.26 1.80
0.98 2.71 0.19 1.26 1.80
0.67 3.13 2.82 2.53 2.68
0.67 2.75 2.39 2.78 3.15
ns
ns
4 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
Revision 14
2-37
IGLOO PLUS DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-64 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS1
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA4
mA4 µA5 µA5
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
2
2
20
26
10 10
Notes:
1. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-11 • AC Loading
Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-66 • 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
2 mA
STD 0.98 8.27 0.19 1.57 2.34
0.67 7.94 6.77 3.00 3.11
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-67 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
STD 0.98 3.38 0.19 1.57 2.34
0.67 3.26 2.78 2.99 3.24
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
2-38
Revision 14
IGLOO PLUS Low Power Flash FPGAs
1.2 V LVCMOS Wide Range
Table 2-68 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS Wide
Range1
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL3 IIH4
Equivalent
Software
Default
Drive
Drive
Strength Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max
Strength Option2
V
mA mA mA5 mA5 µA6 µA6
100 µA
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
2
2
20
26 10 10
Notes:
1. Applicable to V2 devices only.
2. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
5. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
6. Currents are measured at 85°C junction temperature.
7. Software default selection highlighted in gray.
Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Revision 14
2-39
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-70 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
100 µA
2 mA
STD
0.98 8.27 0.19 1.57 2.34
0.67 7.94 6.77 3.00 3.11
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-71 • 1.2 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT tDP
tDIN
tPY
tPYS tEOUT
0.67
tZL
tZH
tLZ
tHZ Units
ns
100 µA
2 mA
STD
0.98 3.38 0.19 1.57 2.34
3.26 2.78 2.99 3.24
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3. Software default selection highlighted in gray.
2-40
Revision 14
IGLOO PLUS Low Power Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Asynchronous Preset
Preset
Data
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
D
Q
D
Q
C
DFN1P1
DFN1P1
EOUT
H
I
CLK
A
PRE
J
D
Q
DFN1P1
Data Input I/O Register with:
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Preset
Postive-Edge Triggered
CLKBUF
INBUF
Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset
Revision 14
2-41
IGLOO PLUS DC and Switching Characteristics
Table 2-72 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
J, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
tIREMPRE
tIRECPRE
D, A
D, A
Note: *See Figure 2-12 on page 2-41 for more information.
2-42
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Fully Registered I/O Buffers with Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1C1
DFN1C1
EOUT
CLR
CLR
LL
HH
CLK
CLR
AA
DD
JJ
D
Q
DFN1C1
Data Input I/O Register with
Active High Clear
CLR
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Clear
Positive-Edge Triggered
INBUF
CLKBUF
Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear
Revision 14
2-43
IGLOO PLUS DC and Switching Characteristics
Table 2-73 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
FF, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
JJ, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
tIREMCLR
tIRECCLR
Note: *See Figure 2-13 on page 2-43 for more information.
2-44
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
Data
tIHD
50%
50%
tIWPRE
1
0
tIREMPRE
tIRECPRE
Preset
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-14 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-74 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Std. Units
Clock-to-Q of the Input Data Register
0.41
0.32
0.00
0.57
0.57
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-45
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-75 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tICLKQ
Description
Clock-to-Q of the Input Data Register
Std. Units
0.66
0.43
0.00
0.86
0.86
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-46
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
Preset
tOREMPRE
tOWPRE tORECPRE
50%
50%
50%
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-15 • Output Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-76 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Std. Units
Clock-to-Q of the Output Data Register
0.66
0.33
0.00
0.82
0.88
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-47
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-77 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
Std. Units
1.03
0.52
0.00
1.22
1.31
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
tOWPRE
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-48
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Output Enable Register
t
t
OECKMPWH OECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OESUD OEHD
50%
50%
0
1
D_Enable
t
t
OEWPRE
OEREMPRE
t
OERECPRE
50%
50%
50%
Preset
Clear
t
t
t
OERECCLR
OEREMCLR
OEWCLR
50%
50%
50%
t
t
OECLR2Q
OEPRE2Q
50%
50%
50%
EOUT
t
OECLKQ
Figure 2-16 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-78 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
Description
Std. Units
Clock-to-Q of the Output Enable Register
0.68
0.33
0.00
0.84
0.91
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-49
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-79 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOECLKQ
Description
Clock-to-Q of the Output Enable Register
Std. Units
1.06
0.52
0.00
1.25
1.36
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-50
Revision 14
IGLOO PLUS Low Power Flash FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e,
and ProASIC3/ E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-17 • Sample of Combinatorial Cells
Revision 14
2-51
IGLOO PLUS DC and Switching Characteristics
t
PD
Fanout = 4
A
B
Net
NAND2 or Any
Combinatorial
Logic
Y
Length = 1 VersaTile
t
= MAX(t
, t
, t
, t
)
PD
PD(RR) PD(RF) PD(FF) PD(FR)
where edges are applicable for a particular
combinatorial cell
A
Net
NAND2 or Any
Combinatorial
Logic
Y
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Y
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Y
Length = 1 VersaTile
B
VCC
50%
50%
VCC
A, B, C
GND
50%
50%
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
tPD
(FR)
OUT
50%
50%
tPD
GND
(RF)
Figure 2-18 • Timing Model and Waveforms
2-52
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-80 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Y = !A
Parameter
Std.
0.72
0.86
1.00
1.26
1.16
1.46
1.47
2.12
1.24
1.40
Units
ns
INV
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
AND2
NAND2
OR2
Y = A · B
ns
Y = !(A · B)
Y = A + B
ns
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y = !(A + B)
Y = A B
Y = MAJ(A, B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-81 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
1.26
1.46
1.78
2.47
2.17
2.62
2.66
3.77
2.20
2.49
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A, B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 14
2-53
IGLOO PLUS DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented
for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and
ProASIC3/E Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-19 • Sample of Sequential Cells
2-54
Revision 14
IGLOO PLUS Low Power Flash FPGAs
tCKMPWH CKMPWL
t
50%
tSUD
50%
50%
50%
50%
50%
50%
CLK
tHD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
tREMPRE
50%
tHE
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-20 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-82 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-55
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-83 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
1.61
1.17
0.00
1.29
0.00
0.87
0.89
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-56
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Global Resource Characteristics
AGLP125 Clock Tree Topology
Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device.
It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-21 • Example of Global Tree Use in an AGLP125 Device for Clock Routing
Revision 14
2-57
IGLOO PLUS DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-61. Table 2-84 to Table 2-89 on page 2-60 present
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-84 • AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.21
1.23
1.18
1.15
Units
ns
1.42
1.49
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.27
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-85 • AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.32
1.34
1.18
1.15
Max.2
Units
ns
1.62
tRCKH
Input High Delay for Global Clock
1.72
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.38
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-58
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-86 • AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.36
1.39
1.18
1.15
Max.2
Units
ns
1.71
tRCKH
Input High Delay for Global Clock
1.82
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-87 • AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.80
1.88
1.40
1.65
Max.2
Units
ns
2.09
tRCKH
Input High Delay for Global Clock
2.27
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.39
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 14
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IGLOO PLUS DC and Switching Characteristics
Table 2-88 • AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.02
2.09
1.40
1.65
Units
ns
2.43
2.65
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.56
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-89 • AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.08
2.15
1.40
1.65
Max.2
Units
ns
2.54
tRCKH
Input High Delay for Global Clock
2.77
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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Revision 14
IGLOO PLUS Low Power Flash FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-90 • IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL4,5
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
0.75
250
3603
32
100
1
MHz
ns
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter6
LockControl = 0
2.5
1.5
ns
ns
%
LockControl = 1
Output Duty Cycle
48.5
1.25
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
ns
ns
ns
0.469
3.5
Maximum Peak-to-Peak Period Jitter7,8,9
7
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
SSO 2 SSO 4 SSO 8 SSO 16
0.75 MHz to 50 MHz
50 MHz to 250 MHz
Notes:
0.50%
2.50%
0.60%
4.00%
0.80%
6.00%
1.20%
12.00%
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, VCC = 1.5 V
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction
temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. The AGLP030 device does not support a PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.425 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
9. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of
each other. Switching I/Os are placed outside of the PLL bank. Refer to ProASIC3/E SSO and Pin Placement
Guidelines.
Revision 14
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IGLOO PLUS DC and Switching Characteristics
Table 2-91 • IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
160
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL4,5
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
1.5
0.75
160
5803
32
60
MHz
ns
.25
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter6
LockControl = 0
4
ns
ns
%
LockControl = 1
3
Output Duty Cycle
48.5
2.3
51.5
20.86
20.86
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
ns
ns
ns
0.863
5.7
Maximum Peak-to-Peak Period Jitter7,8,9
7
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
SSO 2 SSO 4 SSO 8 SSO 16
0.75 MHz to 50 MHz
50 MHz to 160 MHz
Notes:
0.50%
2.50%
1.20%
5.00%
2.00%
7.00%
3.00%
15.00%
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, VCC = 1.2 V
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. The AGLP030 device does not support PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
8. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
9. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ±200 ps of each
other. Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement Guidelines"
chapter of the IGLOO PLUS FPGA Fabric User’s Guide.
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Revision 14
IGLOO PLUS Low Power Flash FPGAs
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-22 • Peak-to-Peak Jitter Definition
Revision 14
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IGLOO PLUS DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-23 • RAM Models
2-64
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
[R|W]ADDR
BLK
tBKS
tBKH
tENS
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-24 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-25 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
Revision 14
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IGLOO PLUS DC and Switching Characteristics
tCYC
tCKH
tCKL
CLK
tAS
tAH
A0
tBKS
A1
A2
[R|W]ADDR
BLK
tBKH
tENS
tENH
WEN
tDS
tDH
DI1
DI0
DIN|WD
DOUT|RD
Dn
D2
Figure 2-26 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
ADDR
BLK
tAS tAH
A0
tBKS
A1
A2
tBKH
tENS
WEN
DIN
tDS tDH
DI1
DI0
DI2
DOUT
Dn
DI0
DI1
(pass-through)
DOUT
DI0
Dn
DI1
(pipelined)
Figure 2-27 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only.
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IGLOO PLUS Low Power Flash FPGAs
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
Dm
Dn
DOUT|RD
Figure 2-28 • RAM Reset
Revision 14
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IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std. Units
0.69 ns
0.13 ns
0.68 ns
0.13 ns
1.37 ns
0.13 ns
0.59 ns
0.30 ns
2.94 ns
2.55 ns
1.51 ns
Address setup time
Address hold time
tAH
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
Input data (DIN) hold time
tDH
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address – applicable 0.29 ns
to closing edge
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address – 0.24 ns
applicable to opening edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 0.40 ns
applicable to opening edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
1.72 ns
1.72 ns
0.51 ns
2.68 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-93 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
0.69 ns
0.13 ns
0.61 ns
0.07 ns
0.59 ns
0.30 ns
3.51 ns
1.43 ns
tAS
Address setup time
tAH
Address hold time
tENS
tENH
tDS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tDH
tCKQ1
tCKQ2
tC2CRWH
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
1
Address collision clk-to-clk delay for reliable read access after write on same address – 0.21 ns
applicable to opening edge
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 0.25 ns
applicable to opening edge
tRSTBQ
RESET Low to data out Low on RD (flow-through)
RESET Low to data out Low on RD (pipelined)
1.72 ns
1.72 ns
0.51 ns
2.68 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
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IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-94 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std. Units
Address setup time
Address hold time
1.28
0.25
1.25
0.25
2.54
0.25
1.10
0.55
5.51
4.77
2.82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
Input data (DIN) hold time
tDH
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address – 0.30
applicable to closing edge
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address – 0.32
applicable to opening edge
ns
ns
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 0.44
applicable to opening edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
3.21
3.21
0.93
4.94
1.18
10.90
92
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
ns
ns
ns
tCYC
Clock cycle time
ns
FMAX
Notes:
Maximum frequency
MHz
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-70
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Table 2-95 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tAS
Address setup time
1.28
0.25
1.13
0.13
1.10
0.55
6.56
2.67
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
tENH
tDS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tDH
tCKQ1
tCKQ2
tC2CRWH
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
1
Address collision clk-to-clk delay for reliable read access after write on same address – 0.29
applicable to opening edge
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 0.36
applicable to opening edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow through)
RESET Low to data out Low on RD (pipelined)
3.21
3.21
0.93
4.94
1.18
ns
ns
ns
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
10.90 ns
92 MHz
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
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IGLOO PLUS DC and Switching Characteristics
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-29 • FIFO Model
2-72
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKS
tBKH
RBLK
tCKQ1
RD
D1
Dn
D0
D2
(flow-through)
tCKQ2
RD
(pipelined)
Dn
D0
D1
Figure 2-30 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
tBKS
tBKH
WBLK
tDS
tDH
DI1
DI0
WD
Figure 2-31 • FIFO Write
Revision 14
2-73
IGLOO PLUS DC and Switching Characteristics
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET
tRSTFG
EMPTY
tRSTAF
AEMPTY
tRSTFG
FULL
tRSTAF
AFULL
WA/RA
MATCH (A0)
(Address Counter)
Figure 2-32 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-33 • FIFO EMPTY Flag and AEMPTY Flag Assertion
2-74
Revision 14
IGLOO PLUS Low Power Flash FPGAs
t
CYC
WCLK
FULL
t
WCKFF
t
CKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-34 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
Dist = AEF_TH + 1
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
(EMPTY)
(Address Counter)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
t
WCKF
t
CKAF
AFULL
Figure 2-36 • FIFO FULL Flag and AFULL Flag Deassertion
Revision 14
2-75
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-96 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
Std.
1.66
0.13
0.30
0.00
0.63
0.20
2.77
1.50
2.94
2.79
10.71
2.90
10.60
1.68
1.68
0.51
2.68
0.68
6.24
160
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
Input Data (WD) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
ns
ns
ns
WCLK High to Full Flag Valid
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-76
Revision 14
IGLOO PLUS Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-97 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
Std.
3.44
0.26
0.30
0.00
1.30
0.41
5.67
3.02
6.02
5.71
22.17
5.93
21.94
3.41
3.41
1.02
5.48
1.18
10.90
92
Units
ns
REN, WEN Setup Time
tENH
REN, WEN Hold Time
ns
tBKS
BLK Setup Time
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 14
2-77
IGLOO PLUS DC and Switching Characteristics
Embedded FlashROM Characteristics
t
t
t
SU
SU
SU
CLK
t
t
t
HOLD
HOLD
HOLD
Address
A
A
1
0
t
t
t
CKQ2
CKQ2
CKQ2
D
D
D
Data
0
0
1
Figure 2-37 • Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-98 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
Std.
0.57
0.00
Units
ns
tHOLD
tCK2Q
Address Hold Time
ns
Clock to Out
17.58
15
ns
FMAX
Maximum Clock Frequency
MHz
1.2 V DC Core Voltage
Table 2-99 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tSU
Description
Std.
0.59
0.00
30.94
10
Units
ns
Address Setup Time
Address Hold Time
Clock to Out
tHOLD
tCK2Q
ns
ns
FMAX
Maximum Clock Frequency
MHz
2-78
Revision 14
IGLOO PLUS Low Power Flash FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-15 for more details.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-100 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Std.
1.00
2.00
1.00
2.00
8.00
25.00
15
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
tDIHD
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
0.58
0.00
TBD
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-101 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDISU
Description
Test Data Input Setup Time
Std.
1.50
3.00
1.50
3.00
11.00
30.00
9.00
1.18
0.00
TBD
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 14
2-79
IGLOO PLUS DC and Switching Characteristics
2-80
Revision 14
3 – Pin Descriptions and Packaging
Supply Pins
GND
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Ground
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for IGLOO PLUS V5 devices, and 1.2 V or 1.5 V for
IGLOO PLUS V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG.
Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG
must remain powered to allow JTAG signals to pass through the device.
For IGLOO PLUS V2 devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This
allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when
VCC is at 1.2 V.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are four
I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate
VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V,
2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to
GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V,
2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to
GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be
connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1,
etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device.
•
•
1.5 V for IGLOO PLUS V5 devices
1.2 V or 1.5 V for IGLOO PLUS V2 devices
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in Low Power Flash Devices and Mixed signal FPGAs " chapter of the IGLOO PLUS FPGA
Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on IGLOO PLUS devices.
Revision 14
3-1
Pin Descriptions and Packaging
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on IGLOO PLUS devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
IGLOO PLUS devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO PLUS FPGA Fabric User’s Guide. All
inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an
input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled
GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.
The inputs to the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure chapter of the IGLOO PLUS FPGA Fabric User’s Guide for an explanation of
the naming of global pins.
3-2
Revision 14
IGLOO PLUS Low Power Flash FPGAs
FF
Flash*Freeze Mode Activation Pin
The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low,
has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times.
When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L
devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing
migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer
to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS Device Family
User’s Guide for more information on I/O states during Flash*Freeze mode.
Table 3-1 • Flash*Freeze Pin Location in IGLOO PLUS Devices
Package
CS281
CS201
CS289
VQ128
VQ176
Flash*Freeze Pin
W2
R4
U1
34
47
Revision 14
3-3
Pin Descriptions and Packaging
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2
for more information.
Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The
values in Table 3-2 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
3-4
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Related Documents
IGLOO PLUS Device Family User’s Guide
http://www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are available at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 14
3-5
4 – Package Pin Assignments
VQ128
128
1
128-Pin
VQFP
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Pin information is in the "Pin Descriptions" chapter of the IGLOO PLUS FPGA Fabric User’s Guide.
Revision 14
4-1
Package Pin Assignments
VQ128
VQ128
VQ128
AGLP030
AGLP030
Function
AGLP030
Function
Pin Number
Function
IO119RSB3
IO118RSB3
IO117RSB3
IO115RSB3
IO116RSB3
IO113RSB3
IO114RSB3
GND
Pin Number
36
Pin Number
71
1
IO88RSB2
IO86RSB2
IO84RSB2
IO83RSB2
GND
IO57RSB1
VCCIB1
2
37
72
3
38
73
GND
4
39
74
IO55RSB1
IO54RSB1
IO53RSB1
IO52RSB1
IO51RSB1
IO50RSB1
IO49RSB1
VCC
5
40
75
6
41
VCCIB2
76
7
42
IO82RSB2
IO81RSB2
IO79RSB2
IO78RSB2
IO77RSB2
IO75RSB2
IO74RSB2
VCC
77
8
43
78
9
VCCIB3
44
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IO112RSB3
IO111RSB3
IO110RSB3
IO109RSB3
GEC0/IO108RSB3
GEA0/IO107RSB3
GEB0/IO106RSB3
VCC
45
80
46
81
47
82
GDB0/IO48RSB1
GDA0/IO47RSB1
GDC0/IO46RSB1
IO45RSB1
IO44RSB1
IO43RSB1
IO42RSB1
VCCIB1
48
83
49
84
50
IO73RSB2
IO72RSB2
IO70RSB2
IO69RSB2
IO68RSB2
IO66RSB2
IO65RSB2
GND
85
51
86
52
87
IO104RSB3
IO103RSB3
IO102RSB3
IO101RSB3
IO100RSB3
IO99RSB3
GND
53
88
54
89
55
90
GND
56
91
IO40RSB1
IO41RSB1
IO39RSB1
IO38RSB1
IO37RSB1
IO36RSB1
IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO30RSB0
IO28RSB0
IO27RSB0
VCCIB0
57
92
58
VCCIB2
93
59
IO63RSB2
IO61RSB2
IO59RSB2
TCK
94
VCCIB3
60
95
IO97RSB3
IO98RSB3
IO95RSB3
IO96RSB3
IO94RSB3
IO93RSB3
IO92RSB3
IO91RSB2
FF/IO90RSB2
IO89RSB2
61
96
62
97
63
TDI
98
64
TMS
99
65
VPUMP
100
101
102
103
104
105
66
TDO
67
TRST
68
IO58RSB1
VJTAG
69
70
IO56RSB1
GND
4-2
Revision 14
IGLOO PLUS Low Power Flash FPGAs
VQ128
AGLP030
Function
Pin Number
106
107
108
109
110
IO26RSB0
IO25RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO18RSB0
VCC
111
112
113
114
IO17RSB0
IO16RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO10RSB0
IO09RSB0
VCCIB0
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GND
IO07RSB0
IO05RSB0
IO03RSB0
IO02RSB0
IO01RSB0
IO00RSB0
Revision 14
4-3
Package Pin Assignments
VQ176
176
1
176-Pin
VQFP
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-4
Revision 14
IGLOO PLUS Low Power Flash FPGAs
VQ176
VQ176
VQ176
AGLP060
Function
AGLP060
Function
AGLP060
Pin Number
Pin Number
Pin Number
70
Function
IO89RSB2
IO88RSB2
IO87RSB2
IO86RSB2
IO85RSB2
IO84RSB2
GND
1
GAA2/IO156RSB3
IO155RSB3
GAB2/IO154RSB3
IO153RSB3
GAC2/IO152RSB3
GND
36
37
38
39
40
41
42
43
44
45
46
47
IO119RSB3
GND
2
71
3
VCCIB3
72
4
GEC1/IO116RSB3
GEB1/IO114RSB3
GEC0/IO115RSB3
GEB0/IO113RSB3
GEA1/IO112RSB3
GEA0/IO111RSB3
GEA2/IO110RSB2
NC
73
5
74
6
75
7
VCCIB3
76
8
IO149RSB3
IO147RSB3
IO145RSB3
IO144RSB3
IO143RSB3
VCC
77
VCCIB2
9
78
IO83RSB2
IO82RSB2
GDC2/IO80RSB2
IO81RSB2
GDA2/IO78RSB2
GDB2/IO79RSB2
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
79
80
FF/GEB2/IO109R
SB2
81
82
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
GEC2/IO108RSB2
IO106RSB2
IO107RSB2
IO104RSB2
IO105RSB2
IO102RSB2
IO103RSB2
GND
IO141RSB3
GFC1/IO140RSB3
GFB1/IO138RSB3
GFB0/IO137RSB3
VCOMPLF
83
84
85
NC
86
TCK
87
TDI
GFA1/IO136RSB3
VCCPLF
88
TMS
89
VPUMP
GFA0/IO135RSB3
GND
90
TDO
VCCIB2
91
TRST
IO101RSB2
IO100RSB2
IO99RSB2
IO98RSB2
IO97RSB2
IO96RSB2
IO95RSB2
IO94RSB2
IO93RSB2
VCC
VCCIB3
92
VJTAG
GFA2/IO134RSB3
GFB2/IO133RSB3
GFC2/IO132RSB3
IO131RSB3
IO130RSB3
IO129RSB3
IO127RSB3
IO126RSB3
IO125RSB3
IO123RSB3
IO122RSB3
IO121RSB3
93
GDA1/IO76RSB1
GDC0/IO73RSB1
GDB1/IO74RSB1
GDC1/IO72RSB1
VCCIB1
94
95
96
97
98
GND
99
IO70RSB1
IO69RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO63RSB1
100
101
102
103
104
IO92RSB2
IO91RSB2
IO90RSB2
Revision 14
4-5
Package Pin Assignments
VQ176
VQ176
VQ176
AGLP060
Function
AGLP060
Function
AGLP060
Function
Pin Number
105
106
107
108
109
110
Pin Number
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
Pin Number
175
IO62RSB1
GBB0/IO32RSB0
GBC0/IO30RSB0
IO29RSB0
IO28RSB0
IO27RSB0
VCCIB0
GAA1/IO01RSB0
GAA0/IO00RSB0
IO61RSB1
176
GCC2/IO60RSB1
GCB2/IO59RSB1
GCA2/IO58RSB1
GCA0/IO57RSB1
GCA1/IO56RSB1
VCCIB1
111
GND
112
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
VCC
113
GND
114
GCB0/IO55RSB1
GCB1/IO54RSB1
GCC0/IO53RSB1
GCC1/IO52RSB1
IO51RSB1
115
116
117
118
119
IO50RSB1
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
VCC
IO48RSB1
IO47RSB1
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
IO10RSB0
IO09RSB0
VCCIB0
IO45RSB1
IO44RSB1
IO43RSB1
VCCIB1
GND
GBC2/IO40RSB1
IO39RSB1
GBB2/IO38RSB1
IO37RSB1
GBA2/IO36RSB1
GBA1/IO35RSB0
NC
GND
IO07RSB0
IO08RSB0
GAC1/IO05RSB0
IO06RSB0
GAB1/IO03RSB0
GAC0/IO04RSB0
GAB0/IO02RSB0
GBA0/IO34RSB0
NC
GBB1/IO33RSB0
NC
GBC1/IO31RSB0
4-6
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS201
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 14
4-7
Package Pin Assignments
CS201
CS201
CS201
AGLP030
Function
AGLP030
Function
AGLP030
Function
Pin Number
A1
Pin Number
C6
Pin Number
F3
NC
IO12RSB0
IO23RSB0
IO19RSB0
IO28RSB0
IO32RSB0
IO35RSB0
NC
IO119RSB3
IO111RSB3
GND
A2
IO04RSB0
IO06RSB0
IO09RSB0
IO11RSB0
IO13RSB0
IO17RSB0
IO18RSB0
IO24RSB0
IO26RSB0
IO27RSB0
IO31RSB0
NC
C7
F4
A3
C8
F6
A4
C9
F7
VCC
A5
C10
C11
C12
C13
C14
C15
D1
F8
VCCIB0
VCCIB0
VCCIB0
NC
A6
F9
A7
F10
F12
F13
F14
F15
G1
A8
GND
A9
IO41RSB1
IO37RSB1
IO117RSB3
IO118RSB3
NC
NC
A10
A11
A12
A13
A14
A15
B1
IO40RSB1
IO38RSB1
NC
D2
D3
G2
IO112RSB3
IO110RSB3
IO109RSB3
VCCIB3
GND
NC
D4
GND
G3
NC
D5
IO01RSB0
IO03RSB0
IO10RSB0
IO21RSB0
IO25RSB0
IO30RSB0
IO33RSB0
GND
G4
NC
D6
G6
B2
NC
D7
G7
B3
IO08RSB0
IO05RSB0
IO07RSB0
IO15RSB0
IO14RSB0
IO16RSB0
IO20RSB0
IO22RSB0
IO34RSB0
IO29RSB0
NC
D8
G8
VCC
B4
D9
G9
GND
B5
D10
D11
D12
D13
D14
D15
E1
G10
G12
G13
G14
G15
H1
GND
B6
NC
B7
NC
B8
NC
IO42RSB1
IO44RSB1
NC
B9
IO36RSB1
IO39RSB1
IO115RSB3
IO114RSB3
NC
B10
B11
B12
B13
B14
B15
C1
H2
GEB0/IO106RSB3
GEC0/IO108RSB3
NC
E2
H3
E3
H4
NC
E4
NC
H6
VCCIB3
GND
NC
E12
E13
E14
E15
F1
NC
H7
NC
NC
H8
VCC
C2
NC
GDC0/IO46RSB1
GDB0/IO48RSB1
IO113RSB3
IO116RSB3
H9
GND
C3
GND
H10
H12
H13
VCCIB1
IO54RSB1
GDA0/IO47RSB1
C4
IO00RSB0
IO02RSB0
C5
F2
4-8
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS201
CS201
CS201
AGLP030
Function
AGLP030
Function
AGLP030
Pin Number
H14
H15
J1
Pin Number
L15
M1
Pin Number
P5
Function
IO87RSB2
IO86RSB2
IO84RSB2
IO80RSB2
IO74RSB2
IO73RSB2
IO76RSB2
IO67RSB2
IO64RSB2
VPUMP
IO45RSB1
IO43RSB1
GEA0/IO107RSB3
IO105RSB3
IO104RSB3
IO102RSB3
VCCIB3
IO58RSB1
IO93RSB3
IO92RSB3
IO97RSB3
GND
P6
M2
P7
J2
M3
P8
J3
M4
P9
J4
M5
NC
P10
P11
P12
P13
P14
P15
R1
J6
M6
IO79RSB2
IO77RSB2
IO72RSB2
IO70RSB2
IO61RSB2
IO59RSB2
GND
J7
GND
M7
J8
VCC
M8
J9
GND
M9
J10
J12
J13
J14
J15
K1
VCCIB1
M10
M11
M12
M13
M14
M15
N1
TRST
NC
NC
NC
R2
NC
IO52RSB1
IO50RSB1
IO103RSB3
IO101RSB3
IO99RSB3
IO100RSB3
GND
NC
R3
IO91RSB2
FF/IO90RSB2
IO89RSB2
IO83RSB2
IO82RSB2
IO85RSB2
IO78RSB2
IO69RSB2
IO62RSB2
IO60RSB2
TMS
IO55RSB1
IO56RSB1
NC
R4
R5
K2
R6
K3
N2
NC
R7
K4
N3
GND
R8
K6
N4
NC
R9
K7
VCCIB2
N5
IO88RSB2
IO81RSB2
IO75RSB2
IO68RSB2
IO66RSB2
IO65RSB2
IO71RSB2
IO63RSB2
GND
R10
R11
R12
R13
R14
R15
K8
VCCIB2
N6
K9
VCCIB2
N7
K10
K12
K13
K14
K15
L1
VCCIB1
N8
NC
N9
TDI
IO57RSB1
IO49RSB1
IO53RSB1
IO96RSB3
IO98RSB3
IO95RSB3
IO94RSB3
NC
N10
N11
N12
N13
N14
N15
P1
TCK
L2
TDO
L3
VJTAG
L4
NC
L12
L13
L14
P2
NC
NC
P3
NC
IO51RSB1
P4
NC
Revision 14
4-9
Package Pin Assignments
CS201
CS201
CS201
AGLP060
AGLP060
Function
AGLP060
Function
Pin Number
A1
Function
IO150RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
IO08RSB0
Pin Number
C6
Pin Number
F3
IO07RSB0
IO16RSB0
IO145RSB3
IO147RSB3
GND
A2
C7
F4
A3
C8
IO21RSB0
F6
A4
C9
IO28RSB0
F7
VCC
A5
IO11RSB0
C10
C11
C12
C13
C14
C15
D1
GBB1/IO33RSB0
GBA1/IO35RSB0
GBB2/IO38RSB1
GND
F8
VCCIB0
A6
IO15RSB0
F9
VCCIB0
A7
IO17RSB0
F10
F12
F13
F14
F15
G1*
G2
VCCIB0
A8
IO18RSB0
IO47RSB1
IO45RSB1
GCC1/IO52RSB1
GCA1/IO56RSB1
VCOMPLF
GFB0/IO137RSB3
GFC0/IO139RSB3
IO143RSB3
VCCIB3
A9
IO22RSB0
IO48RSB1
A10
A11
A12
A13
A14
A15
B1
IO26RSB0
IO39RSB1
IO29RSB0
IO146RSB3
IO144RSB3
IO148RSB3
GND
GBC1/IO31RSB0
GBA2/IO36RSB1
IO41RSB1
D2
D3
D4
G3
NC
D5
GAB0/IO02RSB0
GAC1/IO05RSB0
IO14RSB0
G4
IO151RSB3
GAB2/IO154RSB3
IO06RSB0
D6
G6
B2
D7
G7
GND
B3
D8
IO19RSB0
G8
VCC
B4
IO09RSB0
D9
GBC0/IO30RSB0
GBB0/IO32RSB0
GBA0/IO34RSB0
GND
G9
GND
B5
IO13RSB0
D10
D11
D12
D13
D14
D15
E1
G10
G12
G13
G14
G15
H1*
H2
GND
B6
IO10RSB0
IO50RSB1
GCB1/IO54RSB1
GCC2/IO60RSB1
GCA2/IO58RSB1
VCCPLF
B7
IO12RSB0
B8
IO20RSB0
GBC2/IO40RSB1
IO51RSB1
B9
IO23RSB0
B10
B11
B12
B13
B14
B15
C1
IO25RSB0
IO44RSB1
IO24RSB0
IO142RSB3
IO149RSB3
IO153RSB3
GAC2/IO152RSB3
IO43RSB1
GFA1/IO136RSB3
GFB1/IO138RSB3
NC
IO27RSB0
E2
H3
IO37RSB1
E3
H4
IO46RSB1
E4
H6
VCCIB3
IO42RSB1
E12
E13
E14
E15
F1
H7
GND
IO155RSB3
GAA2/IO156RSB3
GND
IO49RSB1
H8
VCC
C2
GCC0/IO53RSB1
GCB0/IO55RSB1
IO141RSB3
GFC1/IO140RSB3
H9
GND
C3
H10
H12
H13
VCCIB1
C4
GAA1/IO01RSB0
GAB1/IO03RSB0
GCB2/IO59RSB1
GCA0/IO57RSB1
C5
F2
Note: *Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201.
4-10
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS201
CS201
CS201
AGLP060
Function
AGLP060
Function
AGLP060
Pin Number
H14
H15
J1
Pin Number
L15
M1
Pin Number
P5
Function
IO106RSB2
IO105RSB2
IO103RSB2
IO99RSB2
IO93RSB2
IO92RSB2
IO95RSB2
IO64RSB1
IO62RSB1
GFA2/IO134RSB3
GFA0/IO135RSB3
GFB2/IO133RSB3
IO131RSB3
VCCIB3
GDC0/IO73RSB1
IO122RSB3
IO124RSB3
IO119RSB3
GND
P6
M2
P7
J2
M3
P8
J3
M4
P9
J4
M5
IO125RSB3
IO98RSB2
P10
P11
P12
P13
P14
P15
R1
J6
M6
J7
GND
M7
IO96RSB2
IO86RSB2
IO83RSB2
VPUMP
J8
VCC
M8
IO91RSB2
J9
GND
M9
IO89RSB2
J10
J12
J13
J14
J15
K1
VCCIB1
M10
M11
M12
M13
M14
M15
N1
IO82RSB2
TRST
IO61RSB1
IO63RSB1
IO68RSB1
IO66RSB1
IO130RSB3
GFC2/IO132RSB3
IO127RSB3
IO129RSB3
GND
GDA2/IO78RSB2
GND
IO118RSB3
GEB0/IO113RSB3
GEA2/IO110RSB2
R2
GDA1/IO76RSB1
GDA0/IO77RSB1
GDB0/IO75RSB1
IO117RSB3
IO120RSB3
GND
R3
R4
FF/GEB2/IO109RS
B2
R5
R6
GEC2/IO108RSB2
IO102RSB2
IO101RSB2
IO104RSB2
IO97RSB2
IO88RSB2
IO81RSB2
GDB2/IO79RSB2
TMS
K2
K3
N2
R7
K4
N3
R8
K6
N4
GEB1/IO114RSB3
IO107RSB2
IO100RSB2
IO94RSB2
R9
K7
VCCIB2
N5
R10
R11
R12
R13
R14
R15
K8
VCCIB2
N6
K9
VCCIB2
N7
K10
K12
K13
K14
K15
L1
VCCIB1
N8
IO87RSB2
IO65RSB1
IO67RSB1
IO69RSB1
IO70RSB1
IO126RSB3
IO128RSB3
IO121RSB3
IO123RSB3
GDB1/IO74RSB1
GDC1/IO72RSB1
IO71RSB1
N9
IO85RSB2
TDI
N10
N11
N12
N13
N14
N15
P1
GDC2/IO80RSB2
IO90RSB2
TCK
IO84RSB2
GND
L2
TDO
L3
VJTAG
L4
GEC0/IO115RSB3
GEC1/IO116RSB3
GEA0/IO111RSB3
GEA1/IO112RSB3
L12
L13
L14
P2
P3
P4
Revision 14
4-11
Package Pin Assignments
CS281
19 18 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
4-12
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS281
CS281
CS281
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
A1
A2
GND
GAB0/IO02RSB0
GAC1/IO05RSB0
IO09RSB0
B18
B19
C1
VCCIB1
IO64RSB1
E13
E14
E15
E16
E18
E19
F1
IO48RSB0
GBB1/IO60RSB0
IO53RSB0
A3
GAB2/IO209RSB3
IO210RSB3
IO12RSB0
A4
C2
IO69RSB1
A5
IO13RSB0
C6
IO68RSB1
A6
IO15RSB0
C14
C18
C19
D1
IO47RSB0
IO71RSB1
A7
IO18RSB0
IO54RSB0
IO198RSB3
GND
A8
IO23RSB0
GBB2/IO65RSB1
IO206RSB3
IO208RSB3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO10RSB0
F2
A9
IO25RSB0
F3
IO201RSB3
IO204RSB3
IO16RSB0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
VCCIB0
D2
F4
IO33RSB0
D4
F5
IO41RSB0
D5
F15
F16
F17
F18
F19
G1
IO50RSB0
IO43RSB0
D6
IO74RSB1
IO46RSB0
D7
IO17RSB0
IO72RSB1
IO55RSB0
D8
IO24RSB0
GND
IO56RSB0
D9
IO27RSB0
IO73RSB1
GBC1/IO58RSB0
GBA0/IO61RSB0
GND
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
IO195RSB3
IO200RSB3
IO202RSB3
IO08RSB0
IO31RSB0
G2
IO40RSB0
G4
GAA2/IO211RSB3
VCCIB0
IO49RSB0
G5
B2
IO45RSB0
G7
GAC2/IO207RSB3
VCCIB0
B3
GAB1/IO03RSB0
GAC0/IO04RSB0
IO11RSB0
GBB0/IO59RSB0
GBA2/IO63RSB1
GBC2/IO67RSB1
IO66RSB1
G8
B4
G9
IO26RSB0
B5
G10
G11
G12
G13
G15
G16
G18
G19
H1
IO35RSB0
B6
GND
IO44RSB0
B7
IO21RSB0
IO203RSB3
IO205RSB3
IO07RSB0
VCCIB0
B8
IO22RSB0
E2
IO51RSB0
B9
IO28RSB0
E4
IO70RSB1
B10
B11
B12
B13
B14
B15
B16
B17
IO32RSB0
E5
IO06RSB0
IO75RSB1
IO36RSB0
E6
IO14RSB0
GCC0/IO80RSB1
GCB1/IO81RSB1
GFB0/IO191RSB3
IO196RSB3
GFC1/IO194RSB3
GFB1/IO192RSB3
VCCIB3
IO39RSB0
E7
IO20RSB0
IO42RSB0
E8
IO29RSB0
GND
E9
IO34RSB0
H2
IO52RSB0
E10
E11
E12
IO30RSB0
H4
GBC0/IO57RSB0
GBA1/IO62RSB0
IO37RSB0
H5
IO38RSB0
H7
Revision 14
4-13
Package Pin Assignments
CS281
CS281
CS281
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
H8
H9
VCC
VCCIB0
K15
K16
K18
K19
L1
IO89RSB1
GND
N4
N5
IO182RSB3
IO161RSB2
GEA2/IO164RSB2
VCCIB2
H10
H11
H12
H13
H15
H16
H18
H19
J1
VCC
IO88RSB1
VCCIB1
N7
VCCIB0
N8
VCC
GFB2/IO187RSB3
IO185RSB3
GFC2/IO186RSB3
IO184RSB3
IO199RSB3
VCCIB3
N9
IO137RSB2
IO135RSB2
IO131RSB2
VCCIB2
VCCIB1
L2
N10
N11
N12
N13
N15
N16
N18
N19
P1
IO77RSB1
GCB0/IO82RSB1
GCA1/IO83RSB1
GCA2/IO85RSB1
VCOMPLF
GFA0/IO189RSB3
VCCPLF
L4
L5
L7
VPUMP
L8
IO117RSB2
IO96RSB1
L9
GND
J2
L10
L11
L12
L13
L15
L16
L18
L19
M1
GND
IO98RSB1
J4
GND
IO94RSB1
J5
GFC0/IO193RSB3
GFA2/IO188RSB3
VCCIB3
VCCIB1
IO174RSB3
GND
J7
IO95RSB1
IO91RSB1
NC
P2
J8
P3
IO176RSB3
IO177RSB3
GEA0/IO165RSB3
IO111RSB2
IO108RSB2
GDC1/IO99RSB1
GND
J9
GND
P4
J10
J11
J12
J13
J15
J16
J18
J19
K1
GND
IO90RSB1
NC
P5
GND
P15
P16
P17
P18
P19
R1
VCCIB1
IO180RSB3
IO179RSB3
IO181RSB3
IO183RSB3
VCCIB3
GCC1/IO79RSB1
GCA0/IO84RSB1
GCB2/IO86RSB1
IO76RSB1
IO78RSB1
VCCIB3
M2
M4
M5
IO97RSB1
M7
IO173RSB3
IO172RSB3
GEC1/IO170RSB3
GEB1/IO168RSB3
IO154RSB2
IO149RSB2
IO146RSB2
IO138RSB2
IO134RSB2
IO132RSB2
IO130RSB2
IO118RSB2
IO112RSB2
M8
VCC
R2
M9
VCCIB2
R4
K2
GFA1/IO190RSB3
GND
M10
M11
M12
M13
M15
M16
M18
M19
N1
VCC
R5
K4
VCCIB2
R6
K5
IO19RSB0
IO197RSB3
VCC
VCC
R7
K7
VCCIB1
R8
K8
IO122RSB2
IO93RSB1
IO92RSB1
NC
R9
K9
GND
R10
R11
R12
R13
R14
K10
K11
K12
K13
GND
GND
VCC
IO178RSB3
IO175RSB3
GCC2/IO87RSB1
N2
4-14
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS281
CS281
Pin Number AGLP125 Function
Pin Number AGLP125 Function
R15
R16
R18
R19
T1
IO109RSB2
GDA1/IO103RSB1
GDB0/IO102RSB1
GDC0/IO100RSB1
IO171RSB3
GEC0/IO169RSB3
GEB0/IO167RSB3
IO157RSB2
IO158RSB2
IO148RSB2
IO145RSB2
IO143RSB2
GND
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
IO133RSB2
IO127RSB2
IO123RSB2
IO120RSB2
GND
T2
IO113RSB2
GDA2/IO105RSB2
TDI
T4
T5
T6
VCCIB2
T7
TDO
T8
GND
T9
W2
FF/GEB2/IO163RSB
2
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
W3
W4
IO155RSB2
IO152RSB2
IO150RSB2
IO147RSB2
IO142RSB2
IO139RSB2
IO136RSB2
VCCIB2
IO129RSB2
IO126RSB2
IO125RSB2
IO116RSB2
GDC2/IO107RSB2
TMS
W5
W6
W7
W8
W9
VJTAG
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
GDB1/IO101RSB1
IO160RSB2
GEA1/IO166RSB3
IO151RSB2
IO121RSB2
TRST
IO128RSB2
IO124RSB2
IO119RSB2
IO115RSB2
IO114RSB2
IO110RSB2
GDB2/IO106RSB2
TCK
U2
U6
U14
U18
U19
V1
GDA0/IO104RSB1
IO159RSB2
VCCIB3
V2
GND
V3
GEC2/IO162RSB2
IO156RSB2
IO153RSB2
GND
V4
V5
V6
V7
IO144RSB2
IO141RSB2
IO140RSB2
V8
V9
Revision 14
4-15
Package Pin Assignments
CS289
A1 Ball Pad Corner
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx .
4-16
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS289
AGLP030
CS289
AGLP030
CS289
AGLP030
Pin Number
A1
Function
IO03RSB0
NC
Pin Number
C4
Function
Pin Number
E7
Function
IO06RSB0
IO11RSB0
IO22RSB0
IO26RSB0
VCCIB0
NC
NC
A2
C5
VCCIB0
IO09RSB0
IO13RSB0
IO15RSB0
IO21RSB0
GND
E8
A3
NC
C6
E9
A4
GND
C7
E10
E11
E12
E13
E14
E15
E16
E17
F1
A5
IO10RSB0
IO14RSB0
IO16RSB0
IO18RSB0
GND
C8
A6
C9
A7
C10
C11
C12
C13
C14
C15
C16
C17
D1
IO33RSB0
IO36RSB1
IO38RSB1
VCCIB1
NC
A8
IO29RSB0
NC
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO23RSB0
IO27RSB0
NC
NC
NC
GND
IO111RSB3
NC
NC
IO34RSB0
NC
F2
GND
F3
IO116RSB3
VCCIB3
IO117RSB3
NC
NC
NC
F4
NC
D2
IO119RSB3
GND
F5
IO30RSB0
IO01RSB0
GND
D3
F6
D4
IO02RSB0
NC
F7
NC
B2
D5
F8
IO08RSB0
IO12RSB0
NC
B3
NC
D6
NC
F9
B4
NC
D7
NC
F10
F11
F12
F13
F14
F15
F16
F17
G1
B5
IO07RSB0
NC
D8
GND
NC
B6
D9
IO20RSB0
IO25RSB0
NC
NC
B7
VCCIB0
IO17RSB0
IO19RSB0
IO24RSB0
IO28RSB0
VCCIB0
NC
D10
D11
D12
D13
D14
D15
D16
D17
E1
NC
B8
GND
B9
NC
NC
B10
B11
B12
B13
B14
B15
B16
B17
C1
GND
IO37RSB1
IO41RSB1
IO110RSB3
GND
IO32RSB0
IO35RSB0
NC
G2
NC
NC
G3
IO113RSB3
NC
NC
VCCIB3
IO114RSB3
IO115RSB3
IO118RSB3
IO05RSB0
NC
G4
IO31RSB0
GND
E2
G5
NC
E3
G6
NC
NC
E4
G7
GND
C2
IO00RSB0
IO04RSB0
E5
G8
GND
C3
E6
G9
VCC
Revision 14
4-17
Package Pin Assignments
CS289
CS289
AGLP030
CS289
AGLP030
AGLP030
Pin Number
G10
G11
G12
G13
G14
G15
G16
G17
H1
Function
Pin Number
J13
J14
J15
J16
J17
K1
Function
IO43RSB1
IO51RSB1
IO52RSB1
GDC0/IO46RSB1
GDA0/IO47RSB1
GND
Pin Number
L16
L17
M1
Function
GND
NC
GND
NC
IO40RSB1
NC
NC
M2
VCCIB3
IO100RSB3
IO98RSB3
IO93RSB3
IO97RSB3
NC
IO39RSB1
IO44RSB1
NC
M3
M4
K2
GEB0/IO106RSB3
IO102RSB3
IO104RSB3
IO99RSB3
NC
M5
GND
K3
M6
NC
K4
M7
H2
GEC0/IO108RSB3
NC
K5
M8
NC
H3
K6
M9
IO71RSB2
NC
H4
IO112RSB3
NC
K7
GND
M10
M11
M12
M13
M14
M15
M16
M17
N1
H5
K8
GND
IO63RSB2
NC
H6
IO109RSB3
GND
K9
GND
H7
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
IO57RSB1
NC
H8
GND
GND
H9
GND
NC
NC
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
NC
NC
GND
NC
VCCIB1
NC
NC
IO53RSB1
GND
NC
N2
NC
IO45RSB1
VCCIB1
GDB0/IO48RSB1
IO42RSB1
NC
IO49RSB1
IO103RSB3
IO101RSB3
NC
N3
IO95RSB3
IO96RSB3
GND
N4
L2
N5
L3
N6
NC
L4
GND
N7
IO85RSB2
IO79RSB2
IO77RSB2
VCCIB2
NC
J2
GEA0/IO107RSB3
VCCIB3
IO105RSB3
NC
L5
NC
N8
J3
L6
NC
N9
J4
L7
GND
N10
N11
N12
N13
N14
N15
N16
N17
P1
J5
L8
GND
J6
NC
L9
VCC
NC
J7
VCC
L10
L11
L12
L13
L14
L15
GND
IO59RSB2
NC
J8
GND
GND
J9
GND
IO58RSB1
IO54RSB1
VCCIB1
NC
GND
J10
J11
J12
GND
IO56RSB1
IO55RSB1
IO94RSB3
VCC
IO50RSB1
4-18
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS289
AGLP030
CS289
AGLP030
Pin Number
P2
Function
Pin Number
T5
Function
NC
NC
P3
GND
T6
IO84RSB2
IO81RSB2
IO76RSB2
VCCIB2
IO69RSB2
IO65RSB2
IO64RSB2
NC
P4
NC
T7
P5
NC
T8
P6
IO87RSB2
IO80RSB2
GND
T9
P7
T10
T11
T12
T13
T14
T15
T16
T17
U1
P8
P9
IO72RSB2
IO67RSB2
IO61RSB2
NC
P10
P11
P12
P13
P14
P15
P16
P17
R1
GND
NC
VCCIB2
NC
TDI
TDO
IO60RSB2
IO62RSB2
VJTAG
GND
FF/IO90RSB2
GND
U2
U3
NC
U4
IO88RSB2
IO86RSB2
IO82RSB2
GND
R2
IO91RSB2
NC
U5
R3
U6
R4
NC
U7
R5
NC
U8
IO75RSB2
IO73RSB2
IO68RSB2
IO66RSB2
GND
R6
VCCIB2
IO83RSB2
IO78RSB2
IO74RSB2
IO70RSB2
GND
U9
R7
U10
U11
U12
U13
U14
U15
U16
U17
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T1
NC
NC
NC
NC
NC
TCK
NC
VPUMP
NC
TMS
TRST
IO92RSB3
IO89RSB2
NC
T2
T3
T4
GND
Revision 14
4-19
Package Pin Assignments
CS289
CS289
CS289
Pin Number AGLP060 Function
Pin Number AGLP060 Function
Pin Number AGLP060 Function
A1
A2
GAB1/IO03RSB0
NC
C5
C6
VCCIB0
IO09RSB0
IO13RSB0
IO15RSB0
IO21RSB0
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
F1
IO22RSB0
IO26RSB0
VCCIB0
A3
NC
C7
A4
GND
C8
NC
A5
IO10RSB0
IO14RSB0
IO16RSB0
IO18RSB0
GND
C9
GBB1/IO33RSB0
GBA2/IO36RSB1
GBB2/IO38RSB1
VCCIB1
A6
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
IO29RSB0
NC
A8
A9
NC
IO44RSB1
GFC1/IO140RSB3
IO142RSB3
IO149RSB3
VCCIB3
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO23RSB0
IO27RSB0
NC
NC
GND
F2
GBA0/IO34RSB0
IO39RSB1
IO150RSB3
IO151RSB3
GND
F3
NC
F4
GND
F5
GAB2/IO154RSB3
IO153RSB3
NC
NC
D2
F6
NC
D3
F7
GBC0/IO30RSB0
GAA1/IO01RSB0
GND
D4
GAB0/IO02RSB0
NC
F8
IO08RSB0
IO12RSB0
NC
D5
F9
B2
D6
NC
F10
F11
F12
F13
F14
F15
F16
F17
G1
B3
NC
D7
NC
NC
B4
NC
D8
GND
NC
B5
IO07RSB0
NC
D9
IO20RSB0
IO25RSB0
NC
GBC2/IO40RSB1
GND
B6
D10
D11
D12
D13
D14
D15
D16
D17
E1
B7
VCCIB0
IO17RSB0
IO19RSB0
IO24RSB0
IO28RSB0
VCCIB0
NC
IO43RSB1
IO46RSB1
IO45RSB1
GFC0/IO139RSB3
GND
B8
NC
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
C1
GBB0/IO32RSB0
GBA1/IO35RSB0
IO37RSB1
IO42RSB1
VCCIB3
G2
G3
IO144RSB3
IO145RSB3
IO146RSB3
IO148RSB3
GND
G4
NC
G5
NC
E2
IO147RSB3
GAC2/IO152RSB3
GAA2/IO156RSB3
GAC1/IO05RSB0
NC
G6
GBC1/IO31RSB0
GND
E3
G7
E4
G8
GND
IO155RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
NC
E5
G9
VCC
C2
E6
G10
G11
G12
GND
C3
E7
IO06RSB0
IO11RSB0
GND
C4
E8
IO48RSB1
4-20
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS289
CS289
CS289
Pin Number AGLP060 Function
Pin Number AGLP060 Function
Pin Number AGLP060 Function
G13
G14
G15
G16
G17
H1
IO41RSB1
IO47RSB1
IO49RSB1
IO50RSB1
GND
J17
K1
GCA1/IO56RSB1
GND
M4
M5
IO122RSB3
GEB0/IO113RSB3
GEB1/IO114RSB3
NC
K2
GFA0/IO135RSB3
GFB2/IO133RSB3
IO128RSB3
IO123RSB3
IO125RSB3
GND
M6
K3
M7
K4
M8
NC
VCOMPLF
GFB0/IO137RSB3
NC
K5
M9
IO90RSB2
NC
H2
K6
M10
M11
M12
M13
M14
M15
M16
M17
N1
H3
K7
IO83RSB2
NC
H4
IO141RSB3
IO143RSB3
GFB1/IO138RSB3
GND
K8
GND
H5
K9
GND
GDA1/IO76RSB1
GDA0/IO77RSB1
IO71RSB1
IO69RSB1
VCCIB1
H6
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
H7
GND
H8
GND
IO64RSB1
IO61RSB1
IO66RSB1
IO65RSB1
GND
H9
GND
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
IO119RSB3
IO120RSB3
GEC0/IO115RSB3
GEA0/IO111RSB3
GND
GND
N2
GCC1/IO52RSB1
IO51RSB1
GCA0/IO57RSB1
VCCIB1
N3
GCC2/IO60RSB1
GFA2/IO134RSB3
GFC2/IO132RSB3
IO127RSB3
GND
N4
N5
L2
N6
NC
GCA2/IO58RSB1
GCC0/IO53RSB1
VCCPLF
L3
N7
IO104RSB2
IO98RSB2
IO96RSB2
VCCIB2
L4
N8
L5
IO121RSB3
GEC1/IO116RSB3
GND
N9
J2
GFA1/IO136RSB3
VCCIB3
L6
N10
N11
N12
N13
N14
N15
N16
N17
P1
J3
L7
NC
J4
IO131RSB3
IO130RSB3
IO129RSB3
VCC
L8
GND
NC
J5
L9
VCC
GDB2/IO79RSB2
NC
J6
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
J7
GND
GND
J8
GND
GDC1/IO72RSB1
GDB1/IO74RSB1
VCCIB1
GDB0/IO75RSB1
GDC0/IO73RSB1
IO118RSB3
IO117RSB3
GND
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
VCC
IO70RSB1
IO68RSB1
IO67RSB1
IO126RSB3
VCCIB3
P2
GCB2/IO59RSB1
GCB1/IO54RSB1
IO62RSB1
IO63RSB1
GCB0/IO55RSB1
P3
P4
NC
P5
NC
P6
IO106RSB2
IO99RSB2
IO124RSB3
P7
Revision 14
4-21
Package Pin Assignments
CS289
CS289
Pin Number AGLP060 Function
Pin Number AGLP060 Function
P8
P9
GND
IO91RSB2
IO86RSB2
IO81RSB2
NC
T12
T13
T14
T15
T16
T17
U1
IO82RSB2
NC
P10
P11
P12
P13
P14
P15
P16
P17
R1
GND
NC
TDI
VCCIB2
NC
TDO
FF/GEB2/IO109RS
B2
GDA2/IO78RSB2
GDC2/IO80RSB2
VJTAG
U2
U3
GND
NC
U4
IO107RSB2
IO105RSB2
IO101RSB2
GND
GND
U5
R2
GEA2/IO110RSB2
NC
U6
R3
U7
R4
NC
U8
IO94RSB2
IO92RSB2
IO87RSB2
IO85RSB2
GND
R5
NC
U9
R6
VCCIB2
IO102RSB2
IO97RSB2
IO93RSB2
IO89RSB2
GND
U10
U11
U12
U13
U14
U15
U16
U17
R7
R8
R9
NC
R10
R11
R12
R13
R14
R15
R16
R17
T1
NC
NC
NC
TCK
NC
VPUMP
NC
NC
TMS
TRST
GEA1/IO112RSB3
GEC2/IO108RSB2
NC
T2
T3
T4
GND
T5
NC
T6
IO103RSB2
IO100RSB2
IO95RSB2
VCCIB2
IO88RSB2
IO84RSB2
T7
T8
T9
T10
T11
4-22
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS289
CS289
CS289
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
A1
A2
GAB1/IO03RSB0
IO11RSB0
IO08RSB0
GND
C5
C6
VCCIB0
IO17RSB0
IO23RSB0
IO27RSB0
IO33RSB0
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
F1
IO32RSB0
IO36RSB0
VCCIB0
A3
C7
A4
C8
IO56RSB0
GBB1/IO60RSB0
GBA2/IO63RSB1
GBB2/IO65RSB1
VCCIB1
A5
IO19RSB0
IO24RSB0
IO26RSB0
IO30RSB0
GND
C9
A6
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
IO43RSB0
IO45RSB0
IO50RSB0
IO52RSB0
GND
A8
A9
IO73RSB1
GFC1/IO194RSB3
IO196RSB3
IO202RSB3
VCCIB3
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO35RSB0
IO38RSB0
IO40RSB0
IO42RSB0
GND
F2
GBA0/IO61RSB0
IO68RSB1
IO204RSB3
IO205RSB3
GND
F3
F4
F5
GAB2/IO209RSB3
IO208RSB3
IO14RSB0
IO20RSB0
IO25RSB0
IO29RSB0
IO51RSB0
IO53RSB0
GBC2/IO67RSB1
GND
IO48RSB0
IO54RSB0
GBC0/IO57RSB0
GAA1/IO01RSB0
GND
D2
F6
D3
F7
D4
GAB0/IO02RSB0
IO07RSB0
IO10RSB0
IO18RSB0
GND
F8
D5
F9
B2
D6
F10
F11
F12
F13
F14
F15
F16
F17
G1
B3
IO06RSB0
IO13RSB0
IO15RSB0
IO21RSB0
VCCIB0
D7
B4
D8
B5
D9
IO34RSB0
IO41RSB0
IO47RSB0
IO55RSB0
GND
B6
D10
D11
D12
D13
D14
D15
D16
D17
E1
B7
IO75RSB1
IO71RSB1
IO77RSB1
GFC0/IO193RSB3
GND
B8
IO28RSB0
IO31RSB0
IO37RSB0
IO39RSB0
VCCIB0
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
GBB0/IO59RSB0
GBA1/IO62RSB0
IO66RSB1
IO70RSB1
VCCIB3
G2
G3
IO198RSB3
IO203RSB3
IO201RSB3
IO206RSB3
GND
IO44RSB0
IO46RSB0
IO49RSB0
GBC1/IO58RSB0
GND
G4
G5
E2
IO200RSB3
GAC2/IO207RSB3
GAA2/IO211RSB3
GAC1/IO05RSB0
IO12RSB0
IO16RSB0
IO22RSB0
G6
E3
G7
E4
G8
GND
IO210RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
IO09RSB0
E5
G9
VCC
C2
E6
G10
G11
G12
GND
C3
E7
GND
C4
E8
IO72RSB1
Revision 14
4-23
Package Pin Assignments
CS289
CS289
CS289
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
G13
G14
G15
G16
G17
H1
IO64RSB1
IO69RSB1
IO78RSB1
IO76RSB1
GND
J17
K1
GCA1/IO83RSB1
GND
M4
M5
IO172RSB3
GEB0/IO167RSB3
GEB1/IO168RSB3
IO159RSB2
IO161RSB2
IO135RSB2
IO128RSB2
IO121RSB2
IO113RSB2
GDA1/IO103RSB1
GDA0/IO104RSB1
IO97RSB1
K2
GFA0/IO189RSB3
GFB2/IO187RSB3
IO179RSB3
IO175RSB3
IO177RSB3
GND
M6
K3
M7
K4
M8
VCOMPLF
GFB0/IO191RSB3
IO195RSB3
IO197RSB3
IO199RSB3
GFB1/IO192RSB3
GND
K5
M9
H2
K6
M10
M11
M12
M13
M14
M15
M16
M17
N1
H3
K7
H4
K8
GND
H5
K9
GND
H6
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
H7
GND
H8
GND
IO88RSB1
IO94RSB1
IO95RSB1
IO93RSB1
GND
IO96RSB1
H9
GND
VCCIB1
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
IO180RSB3
IO178RSB3
GEC0/IO169RSB3
GEA0/IO165RSB3
GND
GND
N2
GCC1/IO79RSB1
IO74RSB1
GCA0/IO84RSB1
VCCIB1
N3
GCC2/IO87RSB1
GFA2/IO188RSB3
GFC2/IO186RSB3
IO182RSB3
GND
N4
N5
L2
N6
IO156RSB2
IO148RSB2
IO144RSB2
IO137RSB2
VCCIB2
GCA2/IO85RSB1
GCC0/IO80RSB1
VCCPLF
L3
N7
L4
N8
L5
IO173RSB3
GEC1/IO170RSB3
GND
N9
J2
GFA1/IO190RSB3
VCCIB3
L6
N10
N11
N12
N13
N14
N15
N16
N17
P1
J3
L7
IO119RSB2
IO111RSB2
J4
IO185RSB3
IO183RSB3
IO181RSB3
VCC
L8
GND
J5
L9
VCC
GDB2/IO106RSB2
IO109RSB2
GND
J6
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
J7
GND
J8
GND
GDC1/IO99RSB1
GDB1/IO101RSB1
VCCIB1
GDB0/IO102RSB1
GDC0/IO100RSB1
IO174RSB3
IO171RSB3
GND
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
VCC
IO98RSB1
IO92RSB1
IO91RSB1
IO184RSB3
VCCIB3
P2
GCB2/IO86RSB1
GCB1/IO81RSB1
IO90RSB1
IO89RSB1
GCB0/IO82RSB1
P3
P4
IO160RSB2
IO157RSB2
IO154RSB2
IO152RSB2
P5
P6
IO176RSB3
P7
4-24
Revision 14
IGLOO PLUS Low Power Flash FPGAs
CS289
CS289
Pin Number AGLP125 Function
Pin Number AGLP125 Function
P8
P9
GND
IO132RSB2
IO125RSB2
IO126RSB2
IO112RSB2
VCCIB2
T12
T13
T14
T15
T16
T17
U1
IO124RSB2
IO122RSB2
GND
P10
P11
P12
P13
P14
P15
P16
P17
R1
IO115RSB2
TDI
TDO
IO108RSB2
GDA2/IO105RSB2
GDC2/IO107RSB2
VJTAG
FF/GEB2/IO163RS
B2
U2
U3
GND
IO151RSB2
IO149RSB2
IO146RSB2
IO142RSB2
GND
U4
GND
U5
R2
GEA2/IO164RSB2
IO158RSB2
IO155RSB2
IO150RSB2
VCCIB2
U6
R3
U7
R4
U8
IO138RSB2
IO136RSB2
IO133RSB2
IO129RSB2
GND
R5
U9
R6
U10
U11
U12
U13
U14
U15
U16
U17
R7
IO145RSB2
IO141RSB2
IO134RSB2
IO130RSB2
GND
R8
R9
IO123RSB2
IO120RSB2
IO117RSB2
TCK
R10
R11
R12
R13
R14
R15
R16
R17
T1
IO118RSB2
IO116RSB2
IO114RSB2
IO110RSB2
TMS
VPUMP
TRST
GEA1/IO166RSB3
GEC2/IO162RSB2
IO153RSB2
GND
T2
T3
T4
T5
IO147RSB2
IO143RSB2
IO140RSB2
IO139RSB2
VCCIB2
T6
T7
T8
T9
T10
T11
IO131RSB2
IO127RSB2
Revision 14
4-25
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet.
Revision
Changes
Page
Revision 14
(September 2012)
Revision 13
(June 2012)
The "Security" section was modified to clarify that Microsemi does not support read-
back of programmed data.
1-2
Figure Figure 2-30 • FIFO Read and Figure 2-31 • FIFO Write have been added
(SAR 34843).
2-73
2-76
3-1
Updated the terminology used in Timing Characteristics in the following tables:
Table 2-96 • FIFO and Table 2-97 • FIFO(SAR 38236).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" section: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the
output buffer VCCI domain" and replaced with “Within the package, the VMV plane
biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet
mentions that "VMV pins must be connected to the corresponding VCCI pins" for an
ESD enhancement.
Revision 12
(March 2012)
The "In-System Programming (ISP) and Security" section and "Security" section I, 1-2
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 34664).
The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography Research
(SAR 34724).
III
The "Specifying I/O States During Programming" section is new (SAR 34695).
The following sentence was removed from the "Advanced Architecture" section:
1-7
1-3
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface"
(SAR 34684).
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"
section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric
User's Guide (SAR 34733).
2-12
tDOUT was corrected to tDIN in Figure 2-4 • Input Buffer Timing Model and Delays
(example) (SAR 37107).
2-16
2-27
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34887).
Minimum pulse width High and Low values were added to the tables in the "Global
Tree Timing Characteristics" section. The maximum frequency for global clock
parameter was removed from these tables because a frequency on the global is only
an indication of what the global network can do. There are other limiters such as the
SRAM, I/Os, and PLL. SmartTime software should be used to determine the design
frequency (SAR 36963).
2-58
Revision 14
5-1
Datasheet Information
Revision
Changes
Page
Revision 12
(continued)
Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS 2-61,
CCC/PLL Specification were updated. A note was added to both tables indicating
that when the CCC/PLL core is generated by Microsemi core generator software, not
all delay values of the specified delay increments are available (SAR 34820).
2-62
The value for serial clock was missing from these tables and has been restored. The
value and units for input cycle-to-cycle jitter were incorrect and have been restored.
The note to Table 2-90 • IGLOO PLUS CCC/PLL Specification giving specifications
for which measurements done was corrected from VCC/VCCPLL = 1.14 V to
VCC/VCCPLL = 1.425 V. The Delay Range in Block: Programmable Delay 2 value in
Table 2-91 • IGLOO PLUS CCC/PLL Specification was corrected from 0.025 to 0.863
(SAR 37058).
Figure 2-28 • Write Access after Read onto Same Address was deleted. Reference
was made to a new application note, Simultaneous Read-Write Operations in Dual-
Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail
(SAR 34868).
2-65,
2-68,
2-74,
2-76
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-32 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35748).
The "Pin Descriptions and Packaging" chapter has been added (SAR 34769).
3-1
4-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34769).
Revision 11
(July 2010)
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOO
PLUS Device Status" table indicates the status for each device in the family.
N/A
The "Reprogrammable Flash Technology" section was revised to add "250 MHz
(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."
I
The "I/Os with Advanced I/O Standards" section was revised to add definitions for
hot-swap and cold-sparing.
1-6
2-1
Conditional statements regarding hot insertion were removed from the description of
VI in Table 2-1 • Absolute Maximum Ratings, since all IGLOO PLUS devices are hot
insertion enabled.
Table 2-2 • Recommended Operating Conditions1,2 was revised. 1.2 V DC wide
range supply voltage and 3.3 V wide range supply voltage (SAR 26270) were added
for VCCI. VJTAG DC Voltage was revised (SAR 24052). The value range for VPUMP
programming voltage for operation was changed from "0 to 3.45" to "0 to 3.6" (SAR
25220).
2-2
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized 2-6, 2-7
to TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating
Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were revised.
Table 2-8 • Power Supply State per Mode is new.
2-7
2-7
The tables in the "Quiescent Supply Current" section were updated (SARs 24882
and 24112). Some of the table notes were changed or deleted.
VIH maximum values in tables were updated as needed to 3.6 V (SARs 20990,
79370).
N/A
5-2
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Revision
Changes
Page
Revision 11
(continued)
The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V LVCMOS
wide range were added to the tables where applicable.
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
2-9
2-9
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings1
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
2-19
2-20
2-21
Table 2-22 • Summary of Maximum and Minimum DC Input Levels
Table 2-23 • Summary of AC Measuring Points
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.425 V, Worst-Case VCCI = 3.0 V
2-22
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.14 V, Worst-Case VCCI = 3.0 V
2-23
2-24
Table 2-28 • I/O Output Buffer Maximum Resistances 1
A table note was added to Table 2-16 • Different Components Contributing to the 2-11,
Static Power Consumption in IGLOO PLUS Devices and Table 2-18 • Different
Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
stating the value for PDC4 is the minimum contribution of the PLL when operating at
lowest frequency.
2-12
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances was revised, including
addition of 3.3 V and 1.2 V LVCMOS wide range.
2-25
The notes defining RWEAK PULL-UP-MAX and RWEAK PULLDOWN-MAX were revised
(SAR 21348).
Table 2-30 • I/O Short Currents IOSH/IOSL was revised to include data for 3.3 V and
1.2 V LVCMOS wide range (SAR 79353 and SAR 79366).
2-25
2-26
Table 2-31 • Duration of Short Circuit Event before Failure was revised to change the
maximum temperature from 110°C to 100°C, with an example of six months instead
of three months (SAR 26259).
The tables in the "Single-Ended I/O Characteristics" section were updated. Notes
clarifying IIL and IIH were added.
2-27
Tables for 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added (SAR 79370,
SAR 79353, and SAR 79366).
Notes in the wide range tables state that the minimum drive strength for any
LVCMOS 3.3 V (or LVCMOS 1.2 V) software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only.
For a detailed I/V curve, refer to the IBIS models (SAR 25700).
The following sentence was deleted from the "2.5 V LVCMOS" section: It uses a
5 V–tolerant input buffer and push-pull output buffer (SAR 24916).
2-32
2-45
The tables in the "Input Register" section, "Output Register" section, and "Output
Enable Register" section were updated. The tables in the "VersaTile Characteristics" through
section were updated. 2-56
Revision 14
5-3
Datasheet Information
Revision
Changes
Page
Revision 11
(continued)
The following tables were updated in the "Global Tree Timing Characteristics"
section:
2-58
Table 2-85 • AGLP060 Global Resource (1.5 V)
Table 2-86 • AGLP125 Global Resource (1.5 V)
Table 2-88 • AGLP060 Global Resource (1.2 V)
Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS
CCC/PLL Specification were revised (SAR 79388). VCO output jitter and maximum
peak-to-peak jitter data were changed. Three notes were added to the table in
connection with these changes.
2-61
N/A
Figure 2-28 • Write Access after Write onto Same Address and Figure 2-29 • Write
Access after Read onto Same Address were deleted.
The tables in the "SRAM", "FIFO" and "Embedded FlashROM Characteristics" 2-68,
sections were updated. 2-78
5-4
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Revision
Changes
Page
Revision 10 (Apr 2009) The –F speed grade is no longer offered for IGLOO PLUS devices. References to III, IV
it have been removed from the document. The speed grade column and note
regarding –F speed grade were removed from "IGLOO PLUS Ordering
Product Brief v1.5
DC and Switching
Information". The "Speed Grade and Temperature Grade Matrix" section was
Characteristics
removed.
Advance v0.5
Revision 9 (Feb 2009)
The "Advanced I/O" section was revised to add two bullets regarding support of
wide range power supply voltage.
I
Product Brief v1.4
The "I/Os with Advanced I/O Standards" section was revised to add 3.0 V wide
range to the list of supported voltages. The "Wide Range I/O Support" section is
new.
1-7
Revision 8 (Jan 2009)
The "CS201" pin table was revised to add a note regarding pins G1 and H1.
4-8
Packaging v1.5
Revision 7 (Dec 2008)
A note was added to IGLOO PLUS Devices: "AGLP060 in CS201 does not
support the PLL."
I
Product Brief v1.3
Table 2 • IGLOO PLUS FPGAs Package Size Dimensions was updated to
change the nominal size of VQ176 from 100 to 400 mm2.
II
Revision 6 (Oct 2008)
Data was revised significantly in the following tables:
2-22,
2-33
DC and Switching
Characteristics
Advance v0.4
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.425 V, Worst-Case VCCI = 3.0 V
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =
1.14 V, Worst-Case VCCI = 3.0 V
Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Revision 5 (Aug 2008) The VQ128 and VQ176 packages were added to Table 1 • IGLOO PLUS Product I to IV
Family, the "I/Os Per Package 1" table, Table 2 • IGLOO PLUS FPGAs Package
Size Dimensions, "IGLOO PLUS Ordering Information", and the "Temperature
Grade Offerings" table.
Product Brief v1.2
Packaging v1.4
The "VQ128" package drawing and pin table are new.
The "VQ176" package drawing and pin table are new.
4-2
4-5
N/A
Revision 4 (Jul 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
Revision 3 (Jun 2008)
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
N/A
DC and Switching
Characteristics
Advance v0.2
Table note 3 was updated in Table 2-2 • Recommended Operating Conditions1,2
to add the sentence, "VCCI should be at the same voltage within a given I/O
bank." References to table notes 5, 6, 7, and 8 were added. Reference to table
note 3 was removed from VPUMP Operation and placed next to VCC.
2-2
2-3
Table 2-4 • Overshoot and Undershoot Limits 1 was revised to remove "as
measured on quiet I/Os" from the title. Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
Revision 14
5-5
Datasheet Information
Revision
Changes
Page
Revision 3 (continued) The table note for Table 2-9 • Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do
not include I/O static contribution.
2-7
The table note for Table 2-10 • Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Sleep Mode* was updated to remove VJTAG and VCCI and the
statement that values do not include I/O static contribution.
2-7
2-8
2-8
The table note for Table 2-11 • Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Shutdown Mode was updated to remove the statement that values
do not include I/O static contribution.
Note 2 of Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS
Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was
deleted.
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software 2-9, 2-9
Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default
I/O Software Settings1 were updated to remove static power. The table notes
were updated to reflect that power was measured on VCCI. Table note 2 was
added to Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Software Settings.
Table 2-16 • Different Components Contributing to the Static Power Consumption 2-11,
in IGLOO PLUS Devices and Table 2-18 • Different Components Contributing to
the Static Power Consumption in IGLOO PLUS Devices were updated to change
the definition for PDC5 from bank static power to bank quiescent power. Table
subtitles were added for Table 2-16 • Different Components Contributing to the
Static Power Consumption in IGLOO PLUS Devices, Table 2-17 • Different
Components Contributing to Dynamic Power Consumption in IGLOO PLUS
Devices, and Table 2-18 • Different Components Contributing to the Static Power
Consumption in IGLOO PLUS Devices.
2-12
The "Total Static Power Consumption—PSTAT" section was revised.
Table 2-32 • Schmitt Trigger Input Hysteresis is new.
The "CS281" package drawing is new.
2-12
2-26
4-13
4-13
4-17
Packaging v1.3
The "CS281" table for the AGLP125 device is new.
Revision 3 (continued) The "CS289" package drawing was incorrect. The graphic was showing the
CS281 mechanical drawing and not the CS289 mechanical drawing. This has
now been corrected.
Revision 2 (Jun 2008)
The "CS289" table for the AGLP030 device is new.
4-17
Packaging v1.2
Revision 1 (Jun 2008)
The "CS289" table for the AGLP060 device is new.
The "CS289" table for the AGLP125 device is new.
4-20
4-23
Packaging v1.1
5-6
Revision 14
IGLOO PLUS Low Power Flash FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "IGLOO PLUS Device" table on page II, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
Revision 14
5-7
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
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