APA1000-CQ208M [MICROSEMI]

Field Programmable Gate Array, 1000000 Gates, 180MHz, 56320-Cell, CMOS, CQFP208, 1.05 MM PITCH, CERAMIC, QFP-208;


型号：	APA1000-CQ208M
厂家：	Microsemi
描述：	Field Programmable Gate Array, 1000000 Gates, 180MHz, 56320-Cell, CMOS, CQFP208, 1.05 MM PITCH, CERAMIC, QFP-208 时钟栅可编程逻辑
文件：	总83页 (文件大小：2197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v5.8

ProASIC^PLUS®Flash Family FPGAs

High Performance Routing Hierarchy

Features and Benefits

High Capacity

•

Ultra-Fast Local and Long-Line Network

High-Speed Very Long-Line Network

High-Performance, Low Skew, Splittable Global Network

100% Routability and Utilization

Commercial and Industrial

•

75,000 to 1 Million System Gates

27 k to 198 kbits of Two-Port SRAM

66 to 712 User I/Os

I/O

•

Schmitt-Trigger Option on Every Input

2.5 V/3.3 V Support with Individually-Selectable Voltage and

Slew Rate

Military

•

Bidirectional Global I/Os

•

300, 000 to 1 million System Gates

72 k to 198 kbits of Two Port SRAM

158 to 712 User I/Os

Compliance with PCI Specification Revision 2.2

Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

PLUS

Pin Compatible Packages across the ProASIC

Family

Reprogrammable Flash Technology

Unique Clock Conditioning Circuitry

•

0.22 µm 4 LM Flash-Based CMOS Process

Live At Power-Up (LAPU) Level 0 Support

Single-Chip Solution

No Configuration Device Required

Retains Programmed Design during Power-Down/Up Cycles

Mil/Aero Devices Operate over Full Military Temperature

Range

•

PLL with Flexible Phase, Multiply/Divide and Delay

Capabilities

Internal and/or External Dynamic PLL Configuration

Two LVPECL Differential Pairs for Clock or Data Inputs

•

Standard FPGA and ASIC Design Flow

•

Flexibility with Choice of Industry-Standard Front-End Tools

Efficient Design through Front-End Timing and Gate Optimization

Performance

•

3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military

temperature)

ISP Support

•

In-System Programming (ISP) via JTAG Port

•

Two Integrated PLLs

SRAMs and FIFOs

External System Performance up to 150 MHz

•

SmartGen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150 MHz (typical)

Secure Programming

•

The Industry’s Most Effective Security Key (FlashLock )

•

Low Power

•

Low Impedance Flash Switches

Segmented Hierarchical Routing Structure

Small, Efficient, Configurable (Combinatorial or Sequential)

Logic Cells

Table 1 • ProASIC^PLUSProduct Profile

Device

Maximum System Gates

Tiles (Registers)

Embedded RAM Bits (k=1,024 bits)

APA075

75,000

3,072

27 k

APA150

150,000

6,144

36k

APA300

APA450

450,000

12,288

108 k

APA600

APA750

750,000

32,768

144 k

APA1000

300,000

8,192

72 k

600,000

21,504

126 k

1,000,000

56,320

198 k

Embedded RAM Blocks (256x9)

LVPECL

PLL

Global Networks

Maximum Clocks

Maximum User I/Os

JTAG ISP

158

Yes

242

Yes

290

Yes

344

Yes

454

Yes

562

Yes

712

Yes

PCI

Package (by pin count)

TQFP

PQFP

100, 144

208

100

208

456

–

208

456

–

208

456

–

208

456

–

208

456

–

208

456

PBGA

–

FBGA

CQFP

CCGA/LGA

144

144, 256

208, 352

144, 256, 484 256, 484, 676

676, 896

896, 1152

208, 352

624

208, 352

624

Notes:

1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.

2. These packages are available only for Military/MIL-STD-883B devices.

June 2009

See the Actel website for the latest version of the datasheet.

PLUS

ProASIC

Flash Family FPGAs

Ordering Information

APA1000

1152

Application (Ambient Temperature Range)

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

PP = Pre-production

ES = Engineering Silicon (Room Temperature Only)

M = Military (-55˚C to 125˚C)

= MIL-STD-883 Class B

Package Lead Count

Lead-free packaging

Blank = Standard Packaging

G = RoHS Compliant Packaging

Package Type

Thin Quad Flat Pack (0.5 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Plastic Ball Grid Array (1.27 mm pitch)

Ceramic Quad Flat Pack (1.05 mm pitch)

Ceramic Column Grid Array (1.27 mm pitch)

Land Grid Array (1.27 mm pitch)

Speed Grade

Blank

Standard Speed

= 20% Slower than Standard

Part Number

APA075 = 75,000 Equivalent System Gates

APA150 = 150,000 Equivalent System Gates

APA300 = 300,000 Equivalent System Gates

APA450 = 450,000 Equivalent System Gates

APA600 = 600,000 Equivalent System Gates

APA750 = 750,000 Equivalent System Gates

APA1000 = 1,000,000 Equivalent System Gates

v5.8

PLUS

ProASIC

Flash Family FPGAs

Device Resources

User I/Os²

Commercial/Industrial

Military/MIL-STD-883B

CCGA/

TQFP

107

PQFP

PBGA FBGA FBGA FBGA FBGA FBGA

FBGA

CQFP

LGA

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Notes:

100-Pin 144-Pin 208-Pin 456-Pin 144-Pin 256-Pin 484-Pin 676-Pin 896-Pin 1152-Pin 208-Pin 352-Pin 624-Pin

158

158 ⁴

100

242

290 ⁴

344

186 ³

100 ⁴186 ^{3, 4}

100

186 ³

186 ^{3, 4}370 ³

158

248

158

344 ³

158 ⁴

158

158 ⁴

356 ⁴

454

440

356

562 ⁵

356 ⁴

642 ^{4, 5}712 ⁵

1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid

Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array

2. Each pair of PECL I/Os is counted as one user I/O.

3. FG256 and FG484 are footprint-compatible packages.

4. Military Temperature Plastic Package Offering

5. FG896 and FG1152 are footprint-compatible packages.

General Guideline

Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee

performance beyond the limits specified within the datasheet.

v5.8

iii

PLUS

ProASIC

Flash Family FPGAs

Temperature Grade Offerings

Package

TQ100

TQ144

PQ208

BG456

FG144

FG256

FG484

FG676

FG896

FG1152

CQ208

CQ352

CG624

APA075

APA150

APA300

APA450

APA600

APA750 APA1000

C, I

C, I, M

C, I

C, I, M

C, I

C, I, M

C, I

C, I, M

C, I

C, I, M

C, I

M, B

Note: C = Commercial

I = Industrial

M = Military

B = MIL-STD-883

Speed Grade and Temperature Matrix

–F

Std.

✓

M, B

✓

Note: C = Commercial

I = Industrial

M = Military

B = MIL-STD-883

v5.8

PLUS

ProASIC

Flash Family FPGAs

Table of Contents

General Description

ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49

Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51

Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53

Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53

Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76

Recommended Design Practice for V /V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77

PN PP

Package Pin Assignments

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 3-8

v5.8

PLUS

ProASIC

Flash Family FPGAs

General Description

The ProASIC^PLUSfamily of devices, Actel’s second-

generation Flash FPGAs, offers enhanced performance

over Actel’s ProASIC family. It combines the advantages

of ASICs with the benefits of programmable devices

through nonvolatile Flash technology. This enables

engineers to create high-density systems using existing

ASIC or FPGA design flows and tools. In addition, the

ProASIC^PLUSfamily offers a unique clock conditioning

circuit based on two on-board phase-locked loops (PLLs).

The family offers up to one million system gates,

supported with up to 198 kbits of two-port SRAM and up

to 712 user I/Os, all providing 50 MHz PCI performance.

combination of fine granularity, flexible routing

resources, and abundant Flash switches allow 100%

utilization and over 95% routability for highly congested

designs. Tiles and larger functions are interconnected

through a four-level routing hierarchy.

Embedded two-port SRAM blocks with built-in FIFO/RAM

control logic can have user-defined depths and widths.

Users can also select programming for synchronous or

asynchronous operation, as well as parity generations or

checking.

The unique clock conditioning circuitry in each device

includes two clock conditioning blocks. Each block

provides a PLL core, delay lines, phase shifts (0° and

180°), and clock multipliers/dividers, as well as the

circuitry needed to provide bidirectional access to the

PLL. The PLL block contains four programmable

frequency dividers which allow the incoming clock signal

to be divided by a wide range of factors from 1 to 64.

The clock conditioning circuit also delays or advances the

incoming reference clock up to 8 ns (in increments of

0.25 ns). The PLL can be configured internally or

externally during operation without redesigning or

reprogramming the part. In addition to the PLL, there

are two LVPECL differential input pairs to accommodate

high-speed clock and data inputs.

Advantages

the

designer

extend

beyond

performance. Unlike SRAM-based FPGAs, four levels of

routing hierarchy simplify routing, while the use of Flash

technology allows all functionality to be live at power-

up. No external boot PROM is required to support device

programming. While on-board security mechanisms

prevent

access

the

program

information,

reprogramming can be performed in-system to support

future design iterations and field upgrades. The device’s

architecture mitigates the complexity of ASIC migration

at higher user volume. This makes ProASIC^PLUSa cost-

effective solution for applications in the networking,

communications, computing, and avionics markets.

The ProASIC^PLUSfamily achieves its nonvolatility and

reprogrammability through an advanced Flash-based

0.22 μm LVCMOS process with four layers of metal.

Standard CMOS design techniques are used to

implement logic and control functions, including the

PLLs and LVPECL inputs. This results in predictable

performance compatible with gate arrays.

The ProASIC^PLUSarchitecture provides granularity

comparable to gate arrays. The device core consists of a

Sea-of-Tiles™. Each tile can be configured as a flip-flop,

latch, or three-input/one-output logic function by

programming the appropriate Flash switches. The

To support customer needs for more comprehensive,

lower-cost, board-level testing, Actel’s ProASIC^PLUS

devices are fully compatible with IEEE Standard 1149.1

for test access port and boundary-scan test architecture.

For more information concerning the Flash FPGA

implementation, please refer to the "Boundary Scan

(JTAG)" section on page 1-11.

ProASIC^PLUSdevices are available in a variety of high-

performance plastic packages. Those packages and the

performance features discussed above are described in

more detail in the following sections.

v5.8

1-1

PLUS

ProASIC

Flash Family FPGAs

PLUS

the appropriate logic cell inputs and outputs. Dedicated

high-performance lines are connected as needed for fast,

low-skew global signal distribution throughout the core.

Maximum core utilization is possible for virtually any

design.

ProASIC^PLUSdevices also contain embedded, two-port

SRAM blocks with built-in FIFO/RAM control logic.

ProASIC

Architecture

The proprietary ProASIC^PLUSarchitecture provides

granularity comparable to gate arrays.

The ProASIC^PLUSdevice core consists of a Sea-of-Tiles

(Figure 1-1). Each tile can be configured as a three-input

logic function (e.g., NAND gate, D-Flip-Flop, etc.) by

programming

the

appropriate

Flash

switch

Programming

options

include

synchronous

interconnections (Figure 1-2 and Figure 1-3 on page 1-3).

Tiles and larger functions are connected with any of the

four levels of routing hierarchy. Flash switches are

distributed throughout the device to provide

nonvolatile, reconfigurable interconnect programming.

Flash switches are programmed to connect signal lines to

asynchronous operation, two-port RAM configurations,

user defined depth and width, and parity generation or

checking. Please see the "Embedded Memory

Configurations" section on page 1-23 for more

information.

RAM Block

256x9 Two-Port SRAM

or FIFO Block

I/Os

Logic Tile

RAM Block

256x9 Two Port SRAM

or FIFO Block

Figure 1-1 • The ProASIC^PLUSDevice Architecture

Switch In

Floating Gate

Sensing

Switching

Word

Switch Out

Figure 1-2 • Flash Switch

1-2

v5.8

PLUS

ProASIC

Flash Family FPGAs

Local Routing

In 1

Efficient Long-Line Routing

In 2 (CLK)

In 3 (Reset)

Figure 1-3 • Core Logic Tile

Live at Power-Up

Flash Switch

The Actel Flash-based ProASIC^PLUSdevices support

Level 0 of the live at power-up (LAPU) classification

standard. This feature helps in system component

initialization, executing critical tasks before the

processor wakes up, setting up and configuring memory

blocks, clock generation, and bus activity management.

The LAPU feature of Flash-based ProASIC^PLUSdevices

greatly simplifies total system design and reduces total

system cost, often eliminating the need for Complex

Programmable Logic Device (CPLD) and clock generation

PLLs that are used for this purpose in a system. In

addition, glitches and brownouts in system power will

not corrupt the ProASIC^PLUSdevice's Flash configuration,

and unlike SRAM-based FPGAs, the device will not have

to be reloaded when system power is restored. This

enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from

the PCB design. Flash-based ProASIC^PLUSdevices simplify

total system design, and reduce cost and design risk,

while increasing system reliability and improving system

initialization time.

Unlike SRAM FPGAs, ProASIC^PLUSuses a live-on-power-up

ISP Flash switch as its programming element.

In the ProASIC^PLUSFlash switch, two transistors share the

floating gate, which stores the programming

information. One is the sensing transistor, which is only

used for writing and verification of the floating gate

voltage. The other is the switching transistor. It can be

used in the architecture to connect/separate routing nets

or to configure logic. It is also used to erase the floating

gate (Figure 1-2 on page 1-2).

Logic Tile

The logic tile cell (Figure 1-3) has three inputs (any or all

of which can be inverted) and one output (which can

connect to both ultra-fast local and efficient long-line

routing resources). Any three-input, one-output logic

function (except a three-input XOR) can be configured as

one tile. The tile can be configured as a latch with clear

or set or as a flip-flop with clear or set. Thus, the tiles can

flexibly map logic and sequential gates of a design.

v5.8

1-3

PLUS

ProASIC

Flash Family FPGAs

Routing Resources

The routing structure of ProASIC^PLUSdevices is designed

to provide high performance through a flexible four-

level hierarchy of routing resources: ultra-fast local

resources, efficient long-line resources, high-speed, very

long-line resources, and high performance global

networks.

can in turn access every input of every tile. Active buffers

are inserted automatically by routing software to limit

the loading effects due to distance and fanout.

The high-speed, very long-line resources, which span the

entire device with minimal delay, are used to route very

long or very high fanout nets. (Figure 1-6 on page 1-6).

The ultra-fast local resources are dedicated lines that

allow the output of each tile to connect directly to every

input of the eight surrounding tiles (Figure 1-4).

The high-performance global networks are low-skew,

high fanout nets that are accessible from external pins or

from internal logic (Figure 1-7 on page 1-7). These nets

are typically used to distribute clocks, resets, and other

high fanout nets requiring a minimum skew. The global

networks are implemented as clock trees, and signals can

be introduced at any junction. These can be employed

hierarchically with signals accessing every input on all

tiles.

The efficient long-line resources provide routing for

longer distances and higher fanout connections. These

resources vary in length (spanning 1, 2, or 4 tiles), run

both vertically and horizontally, and cover the entire

ProASIC^PLUSdevice (Figure 1-5 on page 1-5). Each tile can

drive signals onto the efficient long-line resources, which

Inputs

Ultra-Fast

Local Lines

(connects a tile to the

adjacent tile, I/O buffer,

or memory block)

Figure 1-4 • Ultra-Fast Local Resources

1-4

v5.8

PLUS

ProASIC

Flash Family FPGAs

Spans 4 Tiles

Spans 2 Tiles

Spans 1 Tile

Logic Tile

Spans 1 Tile

Spans 2 Tiles

Spans 4 Tiles

Logic Cell

Figure 1-5 • Efficient Long-Line Resources

v5.8

1-5

PLUS

ProASIC

Flash Family FPGAs

High Speed Very Long-Line Resouces

PAD RING

SRAM

PAD RING

Figure 1-6 • High-Speed, Very Long-Line Resources

Clock Resources

Clock Trees

The ProASIC^PLUSfamily offers powerful and flexible

control of circuit timing through the use of analog

circuitry. Each chip has two clock conditioning blocks

containing a phase-locked loop (PLL) core, delay lines,

phase shifter (0° and 180°), clock multiplier/dividers, and

all the circuitry needed for the selection and

interconnection of inputs to the global network (thus

providing bidirectional access to the PLL). This permits

the PLL block to drive inputs and/or outputs via the two

global lines on each side of the chip (four total lines).

This circuitry is discussed in more detail in the

"ProASICPLUS Clock Management System" section on

page 1-13.

One of the main architectural benefits of ProASIC^PLUSis

the set of power- and delay-friendly global networks.

ProASIC^PLUSoffers four global trees. Each of these trees

is based on a network of spines and ribs that reach all

the tiles in their regions (Figure 1-7 on page 1-7). This

flexible clock tree architecture allows users to map up to

88 different internal/external clocks in an APA1000

device. Details on the clock spines and various numbers

of the family are given in Table 1-1 on page 1-7.

The flexible use of the ProASIC^PLUSclock spine allows the

designer to cope with several design requirements. Users

implementing clock-resource intensive applications can

easily route external or gated internal clocks using global

routing spines. Users can also drastically reduce delay

penalties and save buffering resources by mapping

critical high fanout nets to spines. For design hints on

using these features, refer to Actel’s Efficient Use of

ProASIC Clock Trees application note.

1-6

v5.8

PLUS

ProASIC

Flash Family FPGAs

High-Performance

Global Network

PAD RING

Top Spine

Global Networks

Global

Pads

Global

Pads

Global Spine

Global Ribs

Bottom Spine

Scope of Spine

(Shaded area

plus local RAMs

and I/Os)

PAD RING

Note: This figure shows routing for only one global path.

Figure 1-7 • High-Performance Global Network

Table 1-1 • Clock Spines

APA075

APA150

APA300

APA450

APA600

APA750 APA1000

Global Clock Networks (Trees)

Clock Spines/Tree

Total Spines

Top or Bottom Spine Height (Tiles)

Tiles in Each Top or Bottom Spine

Total Tiles

512

3,072

768

6,144

1,024

8,192

1,024

12,288

1,536

21,504

2,048

32,768

2,560

56,320

v5.8

1-7

PLUS

ProASIC

Flash Family FPGAs

Array Coordinates

During many place-and-route operations in Actel’s

Designer software tool, it is possible to set constraints

that require array coordinates.

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination.

Core cell coordinates start at the lower left corner

(represented as (1,1)) or at (1,5) if memory blocks are

present at the bottom. Memory coordinates use the

same system and are indicated in Table 1-2. The memory

coordinates for an APA1000 are illustrated in Figure 1-8.

For more information on how to use constraints, see the

Designer User’s Guide or online help for ProASIC^PLUS

software tools.

Table 1-2 is provided as a reference. The array coordinates

are measured from the lower left (0,0). They can be used in

region constraints for specific groups of core cells, I/Os, and

RAM blocks. Wild cards are also allowed.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

Table 1-2 • Array Coordinates

Logic Tile

Memory Rows

Min.

Max.

Bottom

Top

All

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Min.

0,0

Max.

97, 37

–

(33,33) or (33, 35)

(49,49) or (49, 51)

(69,69) or (69, 71)

(101,101) or (101, 103)

(133,133) or (133, 135)

(165,165) or (165, 167)

128

192

224

256

352

–

129, 53

129, 73

193, 73

(1,1) or (1,3)

100

132

164

225, 105

257, 137

353, 169

Memory

Blocks

(1,169)

(1,167)

(1,165)

(1,164)

(353,169)

(352,167)

(352,165)

(352,164)

Core

(1,5)

(1,3)

(1,1)

(352,5)

(352,3)

(352,1)

(0,0)

(353,0)

Memory

Blocks

Figure 1-8 • Core Cell Coordinates for the APA1000

1-8

v5.8

PLUS

ProASIC

Flash Family FPGAs

Table 1-3 • ProASIC^PLUSI/O Power Supply Voltages

Input/Output Blocks

V_DDP

To meet complex system demands, the ProASIC^PLUS

family offers devices with a large number of user I/O

pins, up to 712 on the APA1000. Table 1-3 shows the

available supply voltage configurations (the PLL block

uses an independent 2.5 V supply on the AVDD and

AGND pins). All I/Os include ESD protection circuits. Each

I/O has been tested to 2000 V to the human body model

(per JESD22 (HBM)).

2.5 V

3.3 V

Input Compatibility

Output Drive

3.3V/2.5V

Signal Control

Six or seven standard I/O pads are grouped with a GND

pad and either a V_DD(core power) or V_DDP(I/O power)

pad. Two reference bias signals circle the chip. One

protects the cascaded output drivers, while the other

creates a virtual V_DDsupply for the I/O ring.

Pull-up

Control

Pad

I/O pads are fully configurable to provide the maximum

flexibility and speed. Each pad can be configured as an

input, an output, a tristate driver, or a bidirectional

buffer (Figure 1-9 and Table 1-4).

3.3 V/2.5 V Signal Control Drive

Strength and Slew-Rate Control

Figure 1-9 • I/O Block Schematic Representation

Table 1-4 • I/O Features

Function

Description

I/O pads configured as inputs

•

Selectable 2.5 V or 3.3 V threshold levels

Optional pull-up resistor

Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be

configured as an input only, not a bidirectional buffer. This input type may be slower than

a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros

with an “S” in the standard I/O library have added Schmitt capabilities.

•

3.3 V PCI Compliant (except Schmitt trigger inputs)

Selectable 2.5 V or 3.3 V compliant output signals

2.5 V – JEDEC JESD 8-5

I/O pads configured as outputs

3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3 V PCI compliant

Ability to drive LVTTL and LVCMOS levels

Selectable drive strengths

Selectable slew rates

Tristate

I/O pads configured as bidirectional • Selectable 2.5 V or 3.3 V compliant output signals

buffers

•

2.5 V – JEDEC JESD 8-5

3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3 V PCI compliant

Optional pull-up resistor

Selectable drive strengths

Selectable slew rates

Tristate

v5.8

1-9

PLUS

ProASIC

Flash Family FPGAs

low voltage differential amplifier) and a signal and its

complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).

The LVPECL input pad cell differs from the standard I/O

cell in that it is operated from V_DDonly.

Power-Up Sequencing

While ProASIC^PLUSdevices are live at power-up, the order

of V_DDand V_DDPpower-up is important during system

start-up. V_DDshould be powered up simultaneously with

V_DDPon ProASIC^PLUSdevices. Failure to follow these

guidelines may result in undesirable pin behavior during

system start-up. For more information, refer to Actel’s

Power-Up Behavior of ProASIC^PLUSDevices application

note.

Since it is exclusively an input, it requires no output

signal, output enable signal, or output configuration

bits. As a special high-speed differential input, it also

does not require pull ups. Recommended termination for

LVPECL inputs is shown in Figure 1-10. The LVPECL pad

cell compares voltages on the PPECL (I/P) pad (as

illustrated in Figure 1-11) and the NPECL pad and sends

the results to the global MUX (Figure 1-14 on page 1-14).

This high-speed, low-skew output essentially controls the

clock conditioning circuit.

LVPECL Input Pads

In addition to standard I/O pads and power pads,

ProASIC^PLUSdevices have a single LVPECL input pad on

both the east and west sides of the device, along with

AVDD and AGND pins to power the PLL block. The

LVPECL pad cell consists of an input buffer (containing a

LVPECLs are designed to meet LVPECL JEDEC receiver

standard levels (Table 1-5).

Z ₀= 50 Ω

PPECL

From LVPECL Driver

R = 100 Ω

Data

Z ₀= 50 Ω

NPECL

Figure 1-10 • Recommended Termination for LVPECL Inputs

Voltage

2.72

2.125

1.49

0.86

Figure 1-11 • LVPECL High and Low Threshold Values

Table 1-5 • LVPECL Receiver Specifications

Symbol

V_IH

Parameter

Input High Voltage

Min.

Max

2.72

2.125

V_DD

Units

1.49

0.86

0.3

V_IL

Input Low Voltage

V_ID

Differential Input Voltage

1-10

v5.8

PLUS

ProASIC

Flash Family FPGAs

pins are dedicated for boundary-scan test usage. Actel

recommends that a nominal 20 kΩ pull-up resistor is

added to TDO and TCK pins.

Boundary Scan (JTAG)

ProASIC^PLUSdevices are compatible with IEEE Standard

1149.1, which defines a set of hardware architecture and

mechanisms for cost-effective, board-level testing. The

basic ProASIC^PLUSboundary-scan logic circuit is composed

of the TAP (test access port), TAP controller, test data

registers, and instruction register (Figure 1-12). This

circuit supports all mandatory IEEE 1149.1 instructions

(EXTEST, SAMPLE/PRELOAD and BYPASS) and the

optional IDCODE instruction (Table 1-6).

The TAP controller is a four-bit state machine (16 states)

that operates as shown in Figure 1-13 on page 1-12. The

’1’s and ‘0’s represent the values that must be present at

TMS at a rising edge of TCK for the given state transition

to occur. IR and DR indicate that the instruction register

or the data register is operating in that state.

ProASIC^PLUSdevices have to be programmed at least

once for complete boundary-scan functionality to be

available. Prior to being programmed, EXTEST is not

available. If boundary-scan functionality is required prior

to programming, refer to online technical support on the

Actel website and search for ProASIC^PLUSBSDL.

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI and TDO

(test data input and output), TMS (test mode selector)

and TRST (test reset input). TMS, TDI and TRST are

equipped with pull-up resistors to ensure proper

operation when no input data is supplied to them. These

I/O

Test Data

Registers

Bypass Register

Instruction

TAP

Controller

Device

Logic

I/O

Figure 1-12 • ProASIC^PLUSJTAG Boundary Scan Test Logic Circuit

Table 1-6 • Boundary-Scan Opcodes

Hex Opcode

EXTEST

CLAMP

BYPASS

SAMPLE/PRELOAD

IDCODE

v5.8

1-11

PLUS

ProASIC

Flash Family FPGAs

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain high for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASIC^PLUSdevices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (lowest significant byte (LSB), ID number,

part number and version). The boundary-scan register

observes and controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output, and control

ports of an I/O buffer to capture and load data into the

Test-Logic

Reset

Run-Test/

Idle

Select-DR-

Scan

Select-IR-

Scan

Capture-DR

Capture-IR

Shift-IR

Shift-DR

Exit-DR

Exit-IR

Pause-DR

Pause-IR

Exit2-DR

Exit2-IR

Update-DR

Update-IR

Figure 1-13 • TAP Controller State Diagram

1-12

v5.8

PLUS

ProASIC

Flash Family FPGAs

follows (Figure 1-15 on page 1-15, Table 1-7 on page 1-

15, and Table 1-8 on page 1-16):

Timing Control and

Characteristics

Global A (secondary clock)

•

Output from Global MUX A

PLUS

ProASIC

Clock Management System

•

Conditioned version of PLL output (f_OUT) – delayed

or advanced

ProASIC^PLUSdevices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASIC^PLUSfamily contains two phase-locked loop (PLL)

blocks which perform the following functions:

•

Divided version of either of the above

Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)¹

•

Clock Phase Adjustment via Programmable Delay

(250 ps steps from –7 ns to +8 ns)

Global B

•

Output from Global MUX B

Delayed or advanced version of f_OUT

Divided version of either of the above

Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)²

•

Clock Skew Minimization

Clock Frequency Synthesis

Each PLL has the following key features:

•

Input Frequency Range (f_IN) = 1.5 to 180 MHz

Feedback Frequency Range (f_VCO) = 24 to 180 MHz

Output Frequency Range (f_OUT) = 8 to 180 MHz

Output Phase Shift = 0 ° and 180 °

Functional Description

Each PLL block contains four programmable dividers as

shown in Figure 1-14 on page 1-14. These allow

frequency scaling of the input clock signal as follows:

Output Duty Cycle = 50%

Low Output Jitter (max at 25°C)

•

The n divider divides the input clock by integer

factors from 1 to 32.

–

_VCO<10 MHz. Jitter 1% or better

10 MHz < f_VCO< 60 MHz. Jitter 2% or better

_VCO> 60 MHz. Jitter 1% or better

•

The m divider in the feedback path allows

multiplication of the input clock by integer factors

ranging from 1 to 64.

Note: Jitter(ps) = Jitter(%)* period

•

The two dividers together can implement any

combination of multiplication and division

resulting in a clock frequency between 24 and 180

MHz exiting the PLL core. This clock has a fixed

50% duty cycle.

The output frequency of the PLL core is given by

the formula EQ 1-1 (f_REFis the reference clock

frequency):

For Example:

Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps

•

Maximum Acquisition = 80 µs for f_VCO> 40 MHz

Time

= 30 µs for f_VCO< 40 MHz

Low Power Consumption – 6.9 mW (max – analog

_OUT= f_REF* m/n

supply) + 7.0μW/MHz (max – digital supply)

EQ 1-1

Physical Implementation

•

The third and fourth dividers (u and v) permit the

signals applied to the global network to each be

further divided by integer factors ranging from 1

to 4.

Each side of the chip contains a clock conditioning circuit

based on a 180 MHz PLL block (Figure 1-14 on page 1-

14). Two global multiplexed lines extend along each side

of the chip to provide bidirectional access to the PLL on

that side (neither MUX can be connected to the opposite

side's PLL). Each global line has optional LVPECL input

pads (described below). The global lines may be driven

by either the LVPECL global input pad or the outputs

from the PLL block, or both. Each global line can be

driven by a different output from the PLL. Unused global

pins can be configured as regular I/Os or left

unconnected. They default to an input with pull-up. The

two signals available to drive the global networks are as

The implementations shown in EQ2 and EQ3 enable the

user to define a wide range of frequency multiplier and

divisors.

f_GLB= m/(n*u)

EQ 1-2

f_GLA= m/(n*v)

EQ 1-3

1. This mode is available through the delay feature of the Global MUX driver.

v5.8

1-13

PLUS

ProASIC

Flash Family FPGAs

enable the user to define a wide range of frequency

multipliers and divisors. The clock conditioning circuit can

advance or delay the clock up to 8 ns (in increments of

0.25 ns) relative to the positive edge of the incoming

reference clock. The system also allows for the selection of

output frequency clock phases of 0° and 180°.

signals relative to other signals to assist in the control of

input set-up times. Not all possible combinations of input

and output modes can be used. The degrees of freedom

available in the bidirectional global pad system and in

the clock conditioning circuit have been restricted. This

avoids unnecessary and unwieldy design kit and software

work.

Prior to the application of signals to the rib drivers, they

pass through programmable delay units, one per global

network. These units permit the delaying of global

AVDD AGND

GND

GLA

GLB

Global MUX B OUT

Input Pins to the PLL

See Figure 1-15

Clock Conditioning

Circuitry

(Top level view)

External Feedback Signal

Global MUX A OUT

Flash

Configuration Bits

Dynamic

on page 1-14

Configuration Bits

Clock Conditioning Circuitry Detailed Block Diagram

CLK

Bypass Primary

OBMUX[2:0]

P+

P-

FIVDIV[4:0]

DLYB[1:0]

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

÷n

GLB

180˚

0˚

PLL Core

÷u

÷m

OBDIV[1:0]

FBDIV[5:0]

Clock from Core

(GLINT mode)

Delay Line

0.25 ns to

4.00 ns,

16 steps,

0.25 ns

increments

Deskew

Delay

2.95 ns

OADIV[1:0]

DLYA[1:0]

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

XDLYSEL

÷v

EXTFB

FBDLY[3:0]

GLA

FBSEL[1:0]

OAMUX[1:0]

CLKA

Bypass Secondary

Clock from Core

(GLINT mode)

Notes:

1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.

2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.

3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.

Figure 1-14 • PLL Block – Top-Level View and Detailed PLL Block Diagram

1-14

v5.8

PLUS

ProASIC

Flash Family FPGAs

Package Pins

Physical I/O

Buffers

Global MUX

Configuration Tile

Std. Pad Cell

PECL Pad Cell

Global MUX B

OUT

NPECL

PPECL

External

Feedback

Global MUX A

OUT

GLMX

Std. Pad Cell

Configuration Tile

CORE

Legend

Physical Pin

DATA Signals to the Global MUX

DATA Signals to the Core

Control Signals to the Global MUX

DATA Signals to the PLL Block

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.

Figure 1-15 • Input Connectors to ProASIC^PLUSClock Conditioning Circuitry

Table 1-7 • Clock-Conditioning Circuitry MUX Settings

MUX

Datapath

Comments

FBSEL

Internal Feedback

Internal Feedback and Advance Clock Using FBDLY

External Feedback (EXTFB)

–0.25 to –4 ns in 0.25 ns increments

XDLYSEL

Feedback Unchanged

Deskew feedback by advancing clock by system delay

GLB

Fixed delay of -2.95 ns

OBMUX

Primary bypass, no divider

Primary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

Reserved

+0.25 to +4 ns in 0.25 ns increments

Phase Shift Clock by +180°

Reserved

OAMUX

GLA

Secondary bypass, no divider

Secondary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

+0.25 to +4 ns in 0.25 ns increments

v5.8

1-15

PLUS

ProASIC

Flash Family FPGAs

Table 1-8 • Clock-Conditioning Circuitry Delay-Line

Sample Implementations

Settings

Delay Line

Delay Value (ns)

Frequency Synthesis

DLYB

Figure 1-16 on page 1-17 illustrates an example where

the PLL is used to multiply a 33 MHz external clock up to

133 MHz. Figure 1-17 on page 1-17 uses two dividers to

synthesize a 50 MHz output clock from a 40 MHz input

reference clock. The input frequency of 40 MHz is

multiplied by five and divided by four, giving an output

clock (GLB) frequency of 50 MHz. When dividers are

used, a given ratio can be generated in multiple ways,

allowing the user to stay within the operating frequency

ranges of the PLL. For example, in this case the input

divider could have been two and the output divider also

two, giving us a division of the input frequency by four

to go with the feedback loop division (effective

multiplication) by five.

+0.25

+0.50

+4.0

DLYA

+0.25

+0.50

+4.0

Lock Signal

An active-high Lock signal (added via the SmartGen PLL

development tool) indicates that the PLL has locked to

the incoming clock signal. The PLL will acquire and

maintain lock even when there is jitter on the incoming

clock signal. The PLL will maintain lock with an input

jitter up to 5% of the input period, with a maximum of

5 ns. Users can employ the Lock signal as a soft reset of

the logic driven by GLB and/or GLA. Note if F_INis not

within specified frequencies, then both the F_OUTand lock

signal are indeterminate.

Adjustable Clock Delay

Figure 1-18 on page 1-18 illustrates the delay of the

input clock by employing one of the adjustable delay

lines. This is easily done in ProASIC^PLUSby bypassing the

PLL core entirely and using the output delay line. Notice

also that the output clock can be effectively advanced

relative to the input clock by using the delay line in the

feedback path. This is shown in Figure 1-19 on page 1-18.

PLL Configuration Options

Clock Skew Minimization

The PLL can be configured during design (via Flash-

configuration bits set in the programming bitstream) or

dynamically during device operation, thus eliminating

the need to reprogram the device. The dynamic

configuration bits are loaded into a serial-in/parallel-out

shift register provided in the clock conditioning circuit.

The shift register can be accessed either from user logic

within the device or via the JTAG port. Another option is

internal dynamic configuration via user-designed

hardware. Refer to Actel's ProASIC^PLUSPLL Dynamic

Reconfiguration Using JTAG application note for more

information.

Figure 1-20 on page 1-19 indicates how feedback from

the clock network can be used to create minimal skew

between the distributed clock network and the input

clock. The input clock is fed to the reference clock input

of the PLL. The output clock (GLA) feeds a clock network.

The feedback input to the PLL uses a clock input delayed

by a routing network. The PLL then adjusts the phase of

the input clock to match the delayed clock, thus

providing nearly zero effective skew between the two

clocks. Refer to Actel's Using ProASIC^PLUSClock

Conditioning Circuits application note for more

information.

For information on the clock conditioning circuit, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note.

1-16

v5.8

PLUS

ProASIC

Flash Family FPGAs

÷1

÷n

Global MUX B OUT

33 MHz

180

GLB

PLL Core

÷u

÷1

133 MHz

÷m

÷4

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-16 • Using the PLL 33 MHz In, 133 MHz Out

÷4

÷n

180

Global MUX B OUT

40 MHz

GLB

PLL Core

÷u

÷1

50 MHz

÷m

÷5

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-17 • Using the PLL 40 MHz In, 50 MHz Out

v5.8

1-17

PLUS

ProASIC

Flash Family FPGAs

÷1

÷n

Global MUX B OUT

180

GLB

133 MHz

PLL Core

÷u

÷1

133 MHz

÷m

÷1

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-18 • Using the PLL to Delay the Input Clock

÷1

÷n

180

Global MUX B OUT

133 MHz

GLB

PLL Core

÷u

÷1

133 MHz

÷m

÷1

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-19 • Using the PLL to Advance the Input Clock

1-18

v5.8

PLUS

ProASIC

Flash Family FPGAs

On chip

Off chip

÷n

180˚

0˚

Global MUX B

OUT

PLL Core

133 MHz

÷u

÷m

External

Feedback

133 MHz

÷v

Global MUX A

OUT

^SETD

Reference

clock

CLR

Figure 1-20 • Using the PLL for Clock Deskewing

v5.8

1-19

PLUS

ProASIC

Flash Family FPGAs

Logic Tile Timing Characteristics

Timing Derating

Timing characteristics for ProASIC^PLUSdevices fall into

three categories: family dependent, device dependent,

and design dependent. The input and output buffer

characteristics are common to all ProASIC^PLUSfamily

members. Internal routing delays are device dependent.

Design dependency means that actual delays are not

determined until after placement and routing of the

user’s design are complete. Delay values may then be

determined by using the Timer utility or by performing

simulation with post-layout delays.

Since ProASIC^PLUSdevices are manufactured with a

CMOS process, device performance will vary with

temperature, voltage, and process. Minimum timing

parameters reflect maximum operating voltage,

minimum operating temperature, and optimal process

variations. Maximum timing parameters reflect minimum

operating voltage, maximum operating temperature,

and worst-case process variations (within process

specifications). The derating factors shown in Table 1-9

should be applied to all timing data contained within

this datasheet.

All timing numbers listed in this datasheet represent

sample timing characteristics of ProASIC^PLUSdevices.

Actual timing delay values are design-specific and can be

derived from the Timer tool in Actel’s Designer software

after place-and-route.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most

timing-critical paths. Critical nets are determined by net

property assignment prior to place-and-route. Refer to

the Actel Designer User’s Guide or online help for details

on using constraints.

Table 1-9 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_DD= 2.3 V)

–55°C

0.84

–40°C

0.86

0°C

0.91

0.87

0.83

25°C

0.94

0.90

0.86

70°C

1.00

0.95

0.91

85°C

1.02

0.98

0.93

110°C

1.05

125°C

1.13

135°C

1.18

150°C

1.27

2.3 V

2.5 V

2.7 V

Notes:

0.81

0.82

1.01

1.09

1.13

1.21

0.77

0.79

0.96

1.04

1.08

1.16

1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 175°C.

2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.

1-20

v5.8

PLUS

ProASIC

Flash Family FPGAs

PLL Electrical Specifications

Parameter

Value T_J≤ –40°C

Value T_J> –40°C

Notes

Frequency Ranges

Reference Frequency f_IN(min.)

2.0 MHz

180 MHz

1.5 MHz

180 MHz

24 MHz

180 MHz

6 MHz

Clock conditioning circuitry (min.) lowest input

frequency

Reference Frequency f_IN(max.)

OSC Frequency f_VCO(min.)

OSC Frequency f_VCO(max.)

Clock conditioning circuitry (max.) highest input

frequency

Lowest output frequency voltage controlled

oscillator

180

Highest output frequency voltage controlled

oscillator

Clock Conditioning Circuitry f_OUT(min.) f_IN≤ 40 = 18 MHz

Lowest output frequency clock conditioning

circuitry

f_IN> 40 = 16 MHz

Clock Conditioning Circuitry f_OUT(max.) 180

180 MHz

Highest output frequency clock conditioning

circuitry

Acquisition Time from Cold Start

Acquisition Time (max.)

80 μs

30 μs

80 μs

f_VCO≤ 40 MHz

f_VCO> 40 MHz

Long Term Jitter Peak-to-Peak Max.*

Temperature

Frequency MHz

_VCO< 10<f_Vf_VCO

_CO<60 >60

25°C (or higher)

1ꢀ

2ꢀ

1ꢀ Jitter(ps) = Jitter(ꢀ)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

1.5ꢀ 2.5ꢀ 1ꢀ

2.5ꢀ 3.5ꢀ 1ꢀ

–40°C

–55°C

Power Consumption

Analog Supply Power (max.*)

Digital Supply Current (max.)

Duty Cycle

6.9 mW per PLL

7 μW/MHz

50ꢀ 0.5ꢀ

5ꢀ input period (max. Maximum jitter allowable on an input

5 ns) clock to acquire and maintain lock.

Input Jitter Tolerance

Note: *High clock frequencies (>60 MHz) under typical setup conditions

v5.8

1-21

PLUS

ProASIC

Flash Family FPGAs

PLL I/O Constraints

PLL locking is guaranteed only when the following constraints are followed:

Table 1-10 • PLL I/O Constraints

T_J≤ –40°C

Value T_J> –40°C

I/O Type

PLL locking is guaranteed only when using low drive strength and

low slew rate I/O. PLL locking may be inconsistent when using high

drive strength or high slew rate I/Os

No Constraints

SSO

APA300

APA600

APA1000

APA300

APA600

APA1000

Hermetic packages ≤ 8 SSO

Plastic packages ≤ 16 SSO

Hermetic packages ≤ 16 SSO

Plastic packages ≤ 32 SSO

Hermetic packages ≤ 16 SSO

Plastic packages ≤ 32 SSO

Hermetic packages ≤ 12 SSO

Plastic packages ≤ 20 SSO

Hermetic packages ≤ 32 SSO

Plastic packages ≤ 64 SSO

Hermetic packages ≤ 32 SSO

Plastic packages ≤ 64 SSO

With FIN

outputs

simultaneously

≤

180 MHz and

switching

With FIN ≤ 50 MHz and half

outputs switching on positive

clock edge, half switching on

the negative clock edge no less

than 10nsec later

1-22

v5.8

PLUS

ProASIC

Flash Family FPGAs

User Security

Embedded Memory Configurations

ProASIC^PLUSdevices have FlashLock protection bits that,

once programmed, block the entire programmed

contents from being read externally. Please refer to

Table 1-11 for details on the number of bits in the key for

each device. If locked, the user can only reprogram the

device employing the user-defined security key. This

protects the device from being read back and duplicated.

Since programmed data is stored in nonvolatile memory

cells (actually very small capacitors) rather than in the

wiring, physical deconstruction cannot be used to

compromise data. This type of security breach is further

discouraged by the placement of the memory cells

beneath the four metal layers (whose removal cannot be

accomplished without disturbing the charge in the

capacitor). This is the highest security provided in the

industry. For more information, refer to Actel’s Design

Security in Nonvolatile Flash and Antifuse FPGAs white

paper.

The embedded memory in the ProASIC^PLUSfamily

provides great configuration flexibility (Table 1-12). Each

ProASIC^PLUSblock is designed and optimized as a two-

port memory (one read, one write). This provides 198

kbits of two-port and/or single port memory in the

APA1000 device.

Each memory block can be configured as FIFO or SRAM,

with independent selection of synchronous or

asynchronous read and write ports (Table 1-13).

Additional characteristics include programmable flags as

well as parity checking and generation. Figure 1-21 on

page 1-25 and Figure 1-22 on page 1-26 show the block

diagrams of the basic SRAM and FIFO blocks. Table 1-14

on page 1-25 and Table 1-15 on page 1-26 describe

memory block SRAM and FIFO interface signals,

respectively. A single memory block is designed to

operate at up to 150 MHz (standard speed grade typical

conditions). Each block is comprised of 256 9-bit words

(one read port, one write port). The memory blocks may

be cascaded in width and/or depth to create the desired

memory organization. (Figure 1-23 on page 1-27). This

provides optimal bit widths of 9 (one block), 18, 36, and

72, and optimal depths of 256, 512, 768, and 1,024. Refer

to Actel’s SmartGen User’s Guide for more information.

Table 1-11 • Flashlock Key Size by Device

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Key Size

79 bits

Figure 1-24 on page 1-27 gives an example of optimal

memory usage. Ten blocks with 23,040 bits have been

used to generate three arrays of various widths and

depths. Figure 1-25 on page 1-27 shows how RAM blocks

can be used in parallel to create extra read ports. In this

example, using only 10 of the 88 available blocks of the

APA1000 yields an effective 6,912 bits of multiple port

RAM. The Actel SmartGen software facilitates building

wider and deeper memory configurations for optimal

memory usage.

119 bits

167 bits

191 bits

263 bits

Embedded Memory Floorplan

The embedded memory is located across the top and

bottom of the device in 256x9 blocks (Figure 1-1 on page

1-2). Depending on the device, up to 88 blocks are

available to support a variety of memory configurations.

Each block can be programmed as an independent

memory array or combined (using dedicated memory

routing resources) to form larger, more complex memory

configurations. A single memory configuration could

include blocks from both the top and bottom memory

locations.

Table 1-12 • ProASIC^PLUSMemory Configurations by Device

Maximum Width

Maximum Depth

Device

APA075

APA150

APA300

APA450

APA600

Bottom

Top

256

108

144

216

252

1,536

2,048

3,072

3,584

v5.8

1-23

PLUS

ProASIC

Flash Family FPGAs

Table 1-12 • ProASIC^PLUSMemory Configurations by Device

Maximum Width

Maximum Depth

Device

APA750

APA1000

Bottom

Top

256

288

396

4,096

5,632

Table 1-13 • Basic Memory Configurations

Write Access

Asynchronous

Type

RAM

FIFO

Read Access

Parity

Library Cell Name

Asynchronous

Checked

RAM256x9AA

Asynchronous

Synchronous

Asynchronous

Synchronous

Asynchronous

Generated

Checked

RAM256x9AAP

RAM256x9AST

RAM256x9ASTP

RAM256x9ASR

RAM256x9ASRP

RAM256x9SA

RAM256xSAP

RAM256x9SST

RAM256x9SSTP

RAM256x9SSR

RAM256x9SSRP

FIFO256x9AA

FIFO256x9AAP

FIFO256x9AST

FIFO256x9ASTP

FIFO256x9ASR

FIFO256x9ASRP

FIFO256x9SA

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

FIFO256x9SAP

FIFO256x9SST

FIFO256x9SSTP

FIFO256x9SSR

FIFO256x9SSRP

Synchronous Transparent

Synchronous Pipelined

Generated

Checked

Generated

1-24

v5.8

PLUS

ProASIC

Flash Family FPGAs

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

SRAM

(256x9)

SRAM

(256x9)

WRB

WBLKB

RDB

RBLKB

RCLKS

RDB

RBLKB

RCLKS

WRB

Sync Write

and

Sync Read

Ports

Async Write

and

Async Read

Ports

WCLKS

WBLKB

WPE

RPE

WPE

PARODD

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

SRAM

(256x9)

SRAM

(256x9)

WRB

WBLKB

WRB

WBLKB

RDB

RBLKB

RDB

RBLKB

Sync Write

and

Async Read

Ports

Async Write

and

Sync Read

Ports

WCLKS

WPE

RCLKS

RPE

WPE

PARODD

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not

consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when

RAM blocks are cascaded and are automatically inserted by the software tools.

Figure 1-21 • Example SRAM Block Diagrams

Table 1-14 • Memory Block SRAM Interface Signals

Description

Write clock used on synchronization on write side

Read clock used on synchronization on read side

Read address

SRAM Signal

WCLKS

RCLKS

Bits

In/Out

RADDR<0:7>

RBLKB

Read block select (active Low)

RDB

Read pulse (active Low)

WADDR<0:7>

WBLKB

Write address

Write block select (active Low)

DI<0:8>

WRB

Input data bits <0:8>, <8> can be used for parity In

Write pulse (active Low)

DO<0:8>

RPE

Out

Output data bits <0:8>, <8> can be used for parity Out

Read parity error (active High)

WPE

Write parity error (active High)

PARODD

Selects Odd parity generation/detect when High, Even parity when Low

Note: Not all signals shown are used in all modes.

v5.8

1-25

PLUS

ProASIC

Flash Family FPGAs

DI<0:8>

LEVEL<0:7>

LGDEP<0:2>

DO <0:8>

LEVEL<0:7>

DO <0:8>

WPE

LGDEP<0:2>

FIFO

(256x9)

FIFO

(256x9)

WPE

RPE

WRB

WBLKB

WRB

WBLKB

RPE

FULL

EMPTY

FULL

EMPTY

Sync Write

and

Sync Read

Ports

Sync Write

and

Async Read

Ports

RDB

RBLKB

RDB

RBLKB

EQTH

PARODD

GEQTH

WCLKS

RESET

RCLKS

RESET

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DO <0:8>

WPE

DO <0:8>

FIFO

(256x9)

FIFO

(256x9)

WRB

WBLKB

WRB

WBLKB

WPE

RPE

FULL

EMPTY

Async Write

and

Sync Read

Ports

Async Write

and

Async Read

Ports

RDB

RBLKB

EMPTY

EQTH

RDB

PARODD

RBLKB

GEQTH

RESET

RCLKS

GEQTH

PARODD

RESET

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not

consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when

RAM blocks are cascaded and are automatically inserted by the software tools.

Figure 1-22 • Basic FIFO Block Diagrams

Table 1-15 • Memory Block FIFO Interface Signals

FIFO Signal

WCLKS

Bits

In/Out

Description

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active Low)

RCLKS

LEVEL <0:7>

RBLKB

RDB

Read pulse (active Low)

RESET

Reset for FIFO pointers (active Low)

WBLKB

Write block select (active Low)

DI<0:8>

WRB

Input data bits <0:8>, <8> will be generated parity if PARGEN is true

Write pulse (active Low)

FULL, EMPTY

EQTH, GEQTH

Out

FIFO flags. FULL prevents write and EMPTY prevents read

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

Out

Output data bits <0:8>. <8> will be parity output if PARGEN is true.

Read parity error (active High)

WPE

Write parity error (active High)

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

LGDEP <0:2>

PARODD

Parity generation/detect – Even when Low, Odd when High

1-26

v5.8

PLUS

ProASIC

Flash Family FPGAs

Word Width

256

Word

Depth

256

88 blocks

Figure 1-23 • APA1000 Memory Block Architecture

Word Width

Word

256

256 256

Depth

256 words x 18 bits, 1 read, 1 write

256

512 words x 18 bits, 1 read, 1 write

256

1,024 words x 9 bits, 1 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 23,040

Figure 1-24 • Example Showing Memory Arrays with Different Widths and Depths

Word Width

Write Port

Word

Depth

256 256

256 256 256 256

Read Ports

256 words x 9 bits, 2 read, 1 write

Read Ports

512 words x 9 bits, 4 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 6,912

Figure 1-25 • Multi-Port Memory Usage

v5.8

1-27

PLUS

ProASIC

Flash Family FPGAs

Design Environment

The ProASIC^PLUSfamily of FPGAs is fully supported by

both Actel's Libero^®Integrated Design Environment

(IDE) and Designer FPGA Development software. Actel

Libero IDE is an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log

files, and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment (see Actel’s

website for more information about Libero IDE). Libero

IDE includes Synplify^®AE from Synplicity®, ViewDraw^®

AE from Mentor Graphics^®, ModelSim^®HDL Simulator

from Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, PALACE™ AE Physical Synthesis from

Magma, and Designer software from Actel.

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel’s back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the SmartGen

macro builder, which easily creates popular and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

PALACE is an effective tool when designing with

ProASIC^PLUS. PALACE AE Physical Synthesis from Magma

takes an EDIF netlist and optimizes the performance of

ProASIC^PLUSdevices through a physical placement-driven

process, ensuring that timing closure is easily achieved.

ISP

The user can generate *.bit or *.stp programming files

from the Designer software and can use these files to

program a device.

ProASIC^PLUSdevices can be programmed in-system. For

more information on ISP of ProASIC^PLUSdevices, refer to

the In-System Programming ProASIC^PLUSDevices and

Performing Internal In-System Programming Using Actel’s

ProASIC^PLUSDevices application notes. Prior to being

programmed for the first time, the ProASIC^PLUSdevice I/Os

are in a tristate condition with the pull-up resistor option

enabled.

Actel's Designer software is a place-and-route tool that

provides a comprehensive suite of back-end support

tools for FPGA development. The Designer software

includes the following:

•

Timer – a world-class integrated static timing

analyzer and constraints editor that support

timing-driven place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and

editor

•

SmartPower – allows the designer to quickly

estimate the power consumption of a design

PinEditor – a graphical application for editing pin

assignments and I/O attributes

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

1-28

v5.8

PLUS

ProASIC

Flash Family FPGAs

Related Documents

Application Notes

Efficient Use of ProASIC Clock Trees

http://www.actel.com/documents/A500K_Clocktree_AN.pdf

I/O Features in ProASIC^PLUSFlash FPGAs

http://www.actel.com/documents/APA_LVPECL_AN.pdf

Power-Up Behavior of ProASIC^PLUSDevices

http://www.actel.com/documents/APA_PowerUp_AN.pdf

ProASIC^PLUSPLL Dynamic Reconfiguration Using JTAG

http://www.actel.com/documents/APA_PLLdynamic_AN.pdf

Using ProASIC^PLUSClock Conditioning Circuits

http://www.actel.com/documents/APA_PLL_AN.pdf

In-System Programming ProASIC^PLUSDevices

http://www.actel.com/documents/APA_External_ISP_AN.pdf

Performing Internal In-System Programming Using Actel’s ProASIC^PLUSDevices

http://www.actel.com/documents/APA_Microprocessor_AN.pdf

ProASIC^PLUSRAM and FIFO Blocks

http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity_WP.pdf

User’s Guide

Designer User’s Guide

http://www.actel.com/documents/designer_UG.pdf

SmartGen Cores Reference Guide

http://www.actel.com/documents/gen_refguide_ug.pdf

ProASIC and ProASIC^PLUSMacro Library Guide

http://www.actel.com/documents/pa_libguide_UG.pdf

Additional Information

The following link contains additional information on ProASIC^PLUSdevices.

http://www.actel.com/products/proasicplus/default.aspx

v5.8

1-29

PLUS

ProASIC

Flash Family FPGAs

the maximum allowable temperature on the active

surface of the IC and is 110° C. P is defined as:

Package Thermal Characteristics

The ProASIC^PLUSfamily is available in several package

types with a range of pin counts. Actel has selected

packages based on high pin count, reliability factors, and

superior thermal characteristics.

T_J– T_A

P = ------------------

Θ_ja

EQ 1-4

Thermal resistance defines the ability of a package to

conduct heat away from the silicon, through the

package to the surrounding air. Junction-to-ambient

thermal resistance is measured in degrees Celsius/Watt

is a function of the rate (in linear feet per minute

(lfpm)) of airflow in contact with the package. When the

estimated power consumption exceeds the maximum

allowed power, other means of cooling, such as

increasing the airflow rate, must be used. The maximum

power dissipation allowed for a Military temperature

and is represented as Theta ja (Θ ). The lower the

thermal resistance, the more efficiently a package will

dissipate heat.

device is specified as a function of Θ . The absolute

maximum junction temperature is 150°C.

A package’s maximum allowed power (P) is a function of

maximum junction temperature (T_J), maximum ambient

operating temperature (T_A), and junction-to-ambient

The calculation of the absolute maximum power

dissipation allowed for

application is illustrated in the following example for a

456-pin PBGA package:

Military temperature

thermal resistance Θ . Maximum junction temperature is

Max. junction temp. (°C) – Max. case temp. (°C) 150°C – 125°C

------------------------------------------------------------------------------------------------------------------------ -------------------------------------

Maximum Power Allowed =

= 8.333W

θ_jc(°C/W)

3.0°C/W

EQ 1-5

Table 1-16 • Package Thermal Characteristics

θ_ja

1.0 m/s

2.5 m/s

Plastic Packages

Pin Count

θ_jc

14.0

11.0

8.0

3.8

3.0

3.8

3.2

2.4

1.8

2.0

6.5

Still Air

33.5

26.1

16.2

15.6

26.9

26.6

18.0

20.5

16.4

13.6

12.0

22.0

17.9

8.9

200 ft./min.

500 ft./min.

Units

Thin Quad Flat Pack (TQFP)

Plastic Quad Flat Pack (PQFP)¹

PQFP with Heat spreader²

100

144

208

456

144

256

484

676

896

1152

208

352

624

27.4

28.0

22.5

13.3

12.5

22.9

22.8

14.7

17.0

13.0

10.4

8.9

25.0

25.7

20.8

11.9

11.6

21.5

13.6

15.9

12.0

9.4

°C/W

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

Fine Pitch Ball Grid Array (FBGA)³

Fine Pitch Ball Grid Array (FBGA)⁴

Fine Pitch Ball Grid Array (FBGA)

Ceramic Quad Flat Pack (CQFP)

Ceramic Column Grid Array (CCGA/LGA)

Notes:

7.9

19.8

16.1

8.5

18.0

14.7

8.0

1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300

2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000

3. Depopulated Array

4. Full array

1-30

v5.8

PLUS

ProASIC

Flash Family FPGAs

Calculating Typical Power Dissipation

ProASIC^PLUSdevice power is calculated with both a static and an active component. The active component is a function

of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following

formula:

Total Power Consumption—P

total

P_total= P_dc+ P_ac

where:

P_dc

7 mW for the APA075

8 mW for the APA150

11 mW for the APA300

12 mW for the APA450

12 mW for the APA600

13 mW for the APA750

19 mW for the APA1000

_dcincludes the static components of P_VDDP+ P_VDD+ P_AVDD

P_clock+ P_storage+ P_logic+ P_outputs+ P_inputs+ P_pll+ P_memory

Global Clock Contribution—P

P_ac

clock

P_clock, the clock component of power dissipation, is given by the piece-wise model:

for R < 15000 the model is: (P1 + (P2*R) - (P7*R2)) * Fs (lightly-loaded clock trees)

for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)

where:

100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the

clock

0.00003 µW/MHz is a correction factor for partially-loaded clock trees

6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

P10

P11

0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of

the clock

the number of storage tiles clocked by this clock

the clock frequency

Storage-Tile Contribution—P

storage

P_storage, the storage-tile (Register) component of AC power dissipation, is given by

P_storage= P5 * ms * Fs

where:

1.1 μW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate. The

maximum output toggling rate is Fs/2.

the number of storage tiles (Register) switching during each Fs cycle

the clock frequency

v5.8

1-31

PLUS

ProASIC

Flash Family FPGAs

Logic-Tile Contribution—P

logic

P_logic, the logic-tile component of AC power dissipation, is given by

P_logic= P3 * mc * Fs

where:

1.4 μW/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The

maximum output toggling rate is Fs/2.

the number of logic tiles switching during each Fs cycle

the clock frequency

I/O Output Buffer Contribution—P

outputs

P_outputs, the I/O component of AC power dissipation, is given by

P_outputs= (P4 + (C_load* V_DDP²)) * p * Fp

where:

326 μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output

frequency. This is the total I/O current V_DDP

C_load

the output load

the number of outputs

the average output frequency

I/O Input Buffer's Buffer Contribution—P

inputs

The input’s component of AC power dissipation is given by

P_inputs= P8 * q * Fq

where:

29 μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input

frequency.

the number of inputs

the average input frequency

PLL Contribution—P

pll

P_pll= P9 * N_pll

where:

7.5 mW. This value has been estimated at maximum PLL clock frequency.

number of PLLs used

N_Pll

RAM Contribution—P

memory

Finally, P_memory, the memory component of AC power consumption, is given by

P_memory= P6 * N_memory* F_memory* E_memory

where:

N_memory

175 μW/MHz is the average power consumption of a memory block per MHz of the clock

the number of RAM/FIFO blocks

(1 block = 256 words * 9 bits)

F_memory

E_memory

the clock frequency of the memory

the average number of active blocks divided by the total number of blocks (N) of the memory.

•

Typical values for E_memorywould be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8,

9, 16, and 32 memory configuration

•

In addition, an application-dependent component to E_memorycan be considered. For

example, for a 1kx8 memory configuration using only 1 cycle out of 2, E_memory= 1/4*1/2 = 1/8

1-32

v5.8

PLUS

ProASIC

Flash Family FPGAs

The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.

This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as

follows:

clock

Fs = 10 MHz

= 13,440

=> P_clock= (P1 + (P2*R) - (P7*R²)) * Fs = 121.5 mW

storage

= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)

=> P_storage= P5 * ms * Fs = 147.8 mW

logic

mc = 0 (no logic tiles in this shift register)

=> P_logic= 0 mW

outputs

C_load

40 pF

3.3 V

V_DDP

5 MHz

=> P_outputs= (P4 + (C_load* V_DDP²)) * p * Fp = 91.4 mW

inputs

10 MHz

=> P_inputs= P8 * q * Fq = 0.3 mW

memory

N_memory

0 (no RAM/FIFO blocks in this shift register)

=> P_memory= 0 mW

P_ac

=> 361 mW

P_total

P_dc+ P_ac= 374 mW (typical)

v5.8

1-33

PLUS

ProASIC

Flash Family FPGAs

Operating Conditions

Standard and –F parts are the same unless otherwise noted. All –F parts are only available as commercial.

Table 1-17 • Absolute Maximum Ratings*

Parameter

Condition

Minimum

–0.3

–1.0

Maximum

3.0

Units

Supply Voltage Core (V_DD

)

Supply Voltage I/O Ring (V_DDP

)

4.0

DC Input Voltage

V_DDP+ 0.3

V_DDP+ 1.0

PCI DC Input Voltage

PCI DC Input Clamp Current (absolute)

LVPECL Input Voltage

GND

V_IN< –1 or V_IN= V_DDP+ 1 V

–0.3

V_DDP+ 0.5

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

Recommended Operating Conditions.

Table 1-18 • Programming, Storage, and Operating Limits

Storage Temperature Operating

T_JMax.

Junction

Product Grade

Commercial

Industrial

Programming Cycles (min.)

Program Retention (min.)

20 years

Min.

–55°C

–65°C

Max.

110°C

150°C

Temperature

500

100

110°C

20 years

110°C

Military

Refer to Table 1-19 on page 1-35

150°C

MIL-STD-883

150°C

Example – the ambient temperature of a system cycles

between 100°C (25% of the time) and 50°C (75% of the

time). No forced ventilation cooling system is in use. An

APA600-PQ208M FPGA operates in the system,

dissipating 1 W. The package thermal resistance

Performance Retention

For devices operated and stored at 110°C or less, the

performance retention period is 20 years after

programming. For devices operated and stored at

temperatures greater than 110°C, refer to Table 1-19 on

page 1-35 to determine the performance retention

period. Actel does not guarantee performance if the

performance retention period is exceeded. Designers can

determine the performance retention period from the

following table.

(junction-to-ambient) in still air Θ is 20°C/W, indicating

that the junction temperature of the FPGA will be 120°C

(25% of the time) and 70°C (75% of the time). The entry

in Table 1-19 on page 1-35, which most closely matches

the application, is 25% at 125°C with 75% at 110°C.

Performance retention in this example is at least 16.0

years.

Evaluate the percentage of time spent at the highest

temperature, then determine the next highest

temperature to which the device will be exposed. In

Table 1-19 on page 1-35, find the temperature profile

that most closely matches the application.

Note that exceeding the stated retention period may

result in a performance degradation in the FPGA below

the worst-case performance indicated in the Actel Timer.

To ensure that performance does not degrade below the

worst-case values in the Actel Timer, the FPGA must be

reprogrammed within the performance retention

period. In addition, note that performance retention is

independent of whether or not the FPGA is operating.

The retention period of a device in storage at a given

temperature will be the same as the retention period of

a device operating at that junction temperature.

1-34

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Table 1-19 • Military Temperature Grade Product Performance Retention

Minimum Time at T_JMinimum Time at T_JMinimum Time at T_JMinimum Time at T_J

Minimum

Performance

110°C or below

100ꢀ

90ꢀ

125°C or below

135°C or below

150°C or below

Retention (Years)

20.0

18.2

10ꢀ

25ꢀ

75ꢀ

90ꢀ

10ꢀ

25ꢀ

15.4

13.3

11.8

11.4

50ꢀ

90ꢀ

10ꢀ

75ꢀ

100ꢀ

90ꢀ

10ꢀ

50ꢀ

25ꢀ

9.1

50ꢀ

75ꢀ

90ꢀ

10ꢀ

25ꢀ

7.7

7.3

6.7

5.7

50ꢀ

75ꢀ

50ꢀ

25ꢀ

100ꢀ

90ꢀ

10ꢀ

50ꢀ

25ꢀ

50ꢀ

100ꢀ

4.5

4.4

50ꢀ

75ꢀ

50ꢀ

3.3

2.5

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Table 1-20 • Recommended Maximum Operating Conditions Programming and PLL Supplies

Commercial/Industrial/Military/MIL-STD-883

Parameter

Condition

During Programming

Normal Operation¹

During Programming

Normal Operation²

During Programming

Minimum

15.8

Maximum

16.5

–13.2

0.5

Units

V_PP

V_PN

–13.8

I_PP

I_PN

AVDD

V_DD

AGND

GND

Notes:

1. Please refer to the "VPP Programming Supply Pin" section on page 1-77 for more information.

2. Please refer to the "VPN Programming Supply Pin" section on page 1-77 for more information.

Table 1-21 • Recommended Operating Conditions

Limits

Parameter

Symbol

Commercial

Industrial

Military/MIL-STD-883

DC Supply Voltage (2.5 V I/Os)

DC Supply Voltage (3.3 V I/Os)

V_DDand V_DDP

2.5 V ± 0.2 V

V_DDP

V_DD

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

Operating Ambient Temperature Range

Maximum Operating Junction Temperature

T_A, T_C

T_J

0°C to 70°C

–40°C to 85°C

–55°C (T_A) to 125°C (T_C)

110°C

150°C

Note: For I/O long-term reliability, external pull-up resistors cannot be used to increase output voltage above V_DDP

1-36

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Table 1-22 • DC Electrical Specifications (V_DDP= 2.5 V ±0.2V)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_OH

Output High Voltage

High Drive (OB25LPH)

I_OH= –6 mA

I_OH= –12 mA

I_OH= –24 mA

2.1

2.0

1.7

_OH= –3 mA

2.1

1.9

1.7

Low Drive (OB25LPL)

I_OH= –6 mA

I_OH= –8 mA

V_OL

Output Low Voltage

High Drive (OB25LPH)

I_OL= 8 mA

I_OL= 15 mA

I_OL= 24 mA

0.2

0.4

0.7

Low Drive (OB25LPL)

I_OL= 4 mA

I_OL= 8 mA

I_OL= 15 mA

0.2

0.4

0.7

V_IH

Input High Voltage

Input Low Voltage

1.7

–0.3

V_DDP+ 0.3

V_IL

0.7

R_WEAKPULLUPWeak Pull-up Resistance

(OTB25LPU)

V_IN≥ 1.25 V

kΩ

HYST

I_IN

Input Hysteresis Schmitt

Input Current

See Table 1-4 on page 1-9

with pull up (V_IN= GND)

without pull up (V_IN= GND or V_DD

V_IN= GND⁴or V_DD

0.3

–240

–10

0.35

0.45

– 20

µA

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

Std.

–F³

5.0

Quiescent Supply Current

(standby)

Industrial

V_IN= GND⁴or V_DD

Std.

5.0

Quiescent Supply Current

(standby)

Military/MIL-STD-883

Std.

µA

I_OZ

Tristate Output Leakage Current V_OH= GND or V_DD

Std.

–10

–F^{3, 5}

100

Notes:

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are available only as commercial.

4. No pull-up resistor.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle.

v5.8

1-37

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Table 1-22 • DC Electrical Specifications (V_DDP= 2.5 V ±0.2V) (Continued)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

I_OSH

Output Short Circuit Current High

High Drive (OB25LPH)

Low Drive (OB25LPL)

V_IN= V_SS

–120

–100

I_OSL

Output Short Circuit Current Low

High Drive (OB25LPH)

Low Drive (OB25LPL)

V_IN= V_DDP

100

C_I/O

I/O Pad Capacitance

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are available only as commercial.

4. No pull-up resistor.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle.

1-38

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Table 1-23 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V)

Applies to Commercial and Industrial Temperature Only

Commercial/Industrial¹

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_OH

Output High Voltage

3.3 V I/O, High Drive (OB33P)

I_OH= –14 mA

I_OH= –24 mA

0.9∗V_DDP

2.4

3.3 V I/O, Low Drive (OB33L)

I_OH= –6 mA

0.9∗V_DDP

I_OH= –12 mA

2.4

V_OL

Output Low Voltage

3.3 V I/O, High Drive (OB33P)

I_OL= 15 mA

I_OL= 20 mA

I_OL= 28 mA

0.1V_DDP

0.4

0.7

3.3 V I/O, Low Drive (OB33L)

I_OL= 7 mA

I_OL= 10 mA

I_OL= 15 mA

0.1V_DDP

0.4

0.7

V_IH

Input High Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

1.6

1.7

V_DDP+ 0.3

V_IL

Input Low Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

–0.3

0.8

0.7

R_WEAKPULLUPWeak

(IOB33U)

Pull-up

Resistance V_IN≥ 1.5 V

kΩ

R_WEAKPULLUPWeak

(IOB25U)

Pull-up

Resistance V_IN≥ 1.5 V

I_IN

Input Current

with pull up (V_IN= GND)

–300

–10

–40

µA

without pull up (V_IN= GND or V_DD

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

V_IN= GND³or V_DD

Std.

–F²

5.0

I_DDQ

Quiescent Supply Current

(standby)

V_IN= GND³or V_DD

Industrial

Std.

5.0

I_DDQ

Quiescent Supply Current

(standby)

Military

_IN= GND³or V_DD

Notes:

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All –F parts are only available as commercial.

3. No pull-up resistor required.

4. This will not exceed 2 mA total per device.

5. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

6. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

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Table 1-23 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V) (Continued)

Applies to Commercial and Industrial Temperature Only

Commercial/Industrial¹

Symbol

Parameter

Conditions

Min.

–10

Typ.

Max.

Units

µA

I_OZ

Tristate

Current

Output

Leakage V_OH= GND or V_DD

Std.

–F^{2, 4}

–10

100

µA

I_OSH

Output Short Circuit Current

High

3.3 V High Drive (OB33P)

3.3 V Low Drive (OB33L)

V_IN= GND

–200

–100

I_OSL

Output Short Circuit Current

Low

3.3 V High Drive

3.3 V Low Drive

V_IN= V_DD

200

100

C_I/O

I/O Pad Capacitance

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All –F parts are only available as commercial.

3. No pull-up resistor required.

4. This will not exceed 2 mA total per device.

5. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

6. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

1-40

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Table 1-24 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V)

Applies to Military Temperature and MIL-STD-883B Temperature Only

Military/MIL-STD-883B¹

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_OH

Output High Voltage

3.3 V I/O, High Drive, High Slew I_OH= –8 mA

(OB33PH) I_OH= –16 mA

0.9∗V_DDP

2.4

3.3V I/O, High Drive, Normal/ I_OH= –3mA

Low Slew (OB33PN/OB33PL)

0.9∗V_DDP

2.4

_OH= –8mA

3.3 V I/O, Low Drive , High/

Normal/Low Slew (OB33LH/

OB33LN/OB33LL)

0.9∗V_DDP

I_OH= –3 mA

I_OH= –8 mA

2.4

V_OL

Output Low Voltage

3.3 V I/O, High Drive, High Slew I_OL= 12 mA

0.1V_DDP

0.4

0.7

(OB33PH)

I_OL= 17 mA

I_OL= 28 mA

3.3V I/O, High Drive, Normal/ I_OL= 4 mA

0.1V_DDP

0.4

0.7

Low Slew (OB33PN/OB33PL))

I_OL= 6 mA

I_OL= 13 mA

3.3 V I/O, Low Drive, High/ I_OL= 4 mA

Normal/Low Slew (OB33LH/ I_OL= 6 mA

0.1V_DDP

0.4

0.7

OB33LN/OB33LL)

I_OL= 13 mA

V_IH

Input High Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

1.6

1.7

V_DDP+ 0.3

V_IL

Input Low Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

–0.3

0.7

0.8

0.7

R_WEAKPULLUPWeak Pull-up Resistance

(IOB33U)

V_IN≥ 1.5 V

kΩ

R_WEAKPULLUPWeak Pull-up Resistance

(IOB25U)

I_IN

Input Current

with pull up (V_IN= GND)

without pull up (V_IN= GND or V_DD

V_IN= GND²or V_DD

–300

–10

–40

µA

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

Std.

–F

5.0

Notes:

1. All process conditions. Military Temperature / MIL-STD-883 Class B: Junction Temperature: –55 to +125°C.

2. No pull-up resistor required.

3. This will not exceed 2 mA total per device.

4. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

5. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

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Table 1-24 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V) (Continued)

Applies to Military Temperature and MIL-STD-883B Temperature Only

Military/MIL-STD-883B¹

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

I_DDQ

Quiescent Supply Current

(standby)

_IN= GND²or V_DD

Industrial

Std.

5.0

I_DDQ

Quiescent Supply Current

(standby)

_IN= GND²or V_DD

Military

Std.

–F³

5.0

µA

I_OZ

Tristate

Current

Output

Leakage V_OH= GND or V_DD

–10

100

I_OSH

Output Short Circuit Current

High

3.3 V High Drive (OB33P)

3.3 V Low Drive (OB33L)

V_IN= GND

–200

–100

I_OSL

Output Short Circuit Current

Low

3.3 V High Drive

3.3 V Low Drive

V_IN= V_DD

200

100

C_I/O

I/O Pad Capacitance

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Military Temperature / MIL-STD-883 Class B: Junction Temperature: –55 to +125°C.

2. No pull-up resistor required.

3. This will not exceed 2 mA total per device.

4. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

5. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

1-42

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Table 1-25 • DC Specifications (3.3 V PCI Operation)¹

Commercial/

Industrial^2,3

Military/MIL-STD- 883^2,3

Symbol Parameter

Condition

Min.

2.3

Max.

2.7

Min.

2.3

Max.

2.7

Units

V_DD

V_DDP

V_IH

V_IL

Supply Voltage for Core

Supply Voltage for I/O Ring

Input High Voltage

3.0

3.6

3.0

3.6

0.5V_DDPV_DDP+ 0.5

0.5V_DDP

–0.5

V_DDP+ 0.5

0.3V_DDP

Input Low Voltage

–0.5

0.7V_DDP

–10

0.3V_DDP

I_IPU

I_IL

Input Pull-up Voltage⁴

Input Leakage Current⁵

0.7V_DDP

–50

0 < V_IN< V_DDP

Std.

μA

–F^{3, 6}

–10

100

V_OH

Output High Voltage

I_OUT= –500 µA

I_OUT= 1500 µA

0.9V_DDP

V_OL

Output Low Voltage

0.1V_DDP

C_IN

Input Pin Capacitance (except CLK)

CLK Pin Capacitance

C_CLK

Notes:

1. For PCI operation, use GL33, OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.

2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.

3. All –F parts are available as commercial only.

4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum

current at this input voltage.

5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

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Table 1-26 • AC Specifications (3.3 V PCI Revision 2.2 Operation)

Commercial/Industrial/Military/MIL-STD- 883

Symbol Parameter

Condition

Min.

–12V_DDP

Max.

Units

I_OH(AC)Switching Current High 0 < V_OUT≤ 0.3V_DDP

0.3V_DDP≤ V_OUT< 0.9V_DDP

(–17.1 + (V_DDP– V_OUT))

0.7V_DDP< V_OUT< V_DDP

See equation C – page 124 of

the PCI Specification

document rev. 2.2

(Test Point)

V_OUT= 0.7V_DDP

–32V_DDP

I_OL(AC)

Switching Current Low V_DDP> V_OUT≥ 0.6V_DDP

16V_DDP

0.6V_DDP> V_OUT> 0.1V_DDP

(26.7V_OUT

)

0.18V_DDP> V_OUT> 0^*

See equation D – page 124 of

the PCI Specification

document rev. 2.2

(Test Point)

V_OUT= 0.18V_DDP

38V_DDP

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

I_CH

V_DDP+ 4 > V_IN≥ V_DDP+ 1

0.2V_DDPto 0.6V_DDPload^*

0.6V_DDPto 0.2V_DDPload^*

25 + (V_IN– V_DDP– 1)/0.015

slew_R

slew_F

V/ns

Note: * Refer to the PCI Specification document rev. 2.2.

Pad Loading Applicable to the Rising Edge PCI

1/2 in. max

output

buffer

10 pF

1kΩ

Pad Loading Applicable to the Falling Edge PCI

1kΩ

output

buffer

10 pF

1-44

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Tristate Buffer Delays

PA D

OTBx

50% 50%

35pF

50% 50%

PAD

50% 50%

V_DDP

V_OH

50%

V_OL

90%

50%

PAD

50%

PAD

GND

10%

50%

V_OL

t_DLH

t_ENZL

t_ENZH

t_DHL

Figure 1-26 • Tristate Buffer Delays

Table 1-27 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max

Max₃

t_ENZH

Max₄

t_ENZL

t_DLH

t_DHL

Macro Type

OTB33PH

OTB33PN

OTB33PL

OTB33LH

OTB33LN

OTB33LL

Notes:

Description

Std. –F Std. –F Std. –F Std. –F Units

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4

2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5

2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4

2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6

2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9

3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. All –F parts are only available as commercial.

Table 1-28 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max

Max₃

t_ENZH

Max₄

t_ENZL

t_DLH

t_DHL

Macro Type

Description

2.5 V, Low Power, High Output Current, High Slew Rate⁵

2.5 V, Low Power, High Output Current, Nominal Slew Rate⁵2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5

Std. –F Std. –F Std. –F Std. –F Units

OTB25LPHH

OTB25LPHN

OTB25LPHL

OTB25LPLH

Notes:

2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4

2.5 V, Low Power, High Output Current, Low Slew Rate⁵

2.5 V, Low Power, Low Output Current, High Slew Rate⁵

2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2

2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. Low power I/O work with V_DDP=2.5 V 10% only. V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

v5.8

1-45

PLUS

ProASIC

Flash Family FPGAs

Table 1-28 • Worst-Case Commercial Conditions

_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max

Max₃

t_ENZH

Max₄

t_ENZL

t_DLH

t_DHL

Macro Type

Description

2.5 V, Low Power, Low Output Current, Nominal Slew Rate⁵3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6

2.5 V, Low Power, Low Output Current, Low Slew Rate⁵

4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1

Std. –F Std. –F Std. –F Std. –F Units

OTB25LPLN

OTB25LPLL

Notes:

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. Low power I/O work with V_DDP=2.5 V 10% only. V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

Table 1-29 • Worst-Case Military Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max

t_DLH

Max

t_DHL

Std.

2.4

t_ENZH

Std.

2.3

t_ENZL

Std.

2.1

Macro Type

OTB33PH

OTB33PN

OTB33PL

OTB33LH

OTB33LN

OTB33LL

Notes:

Description

Std.

2.2

2.4

2.7

3.3

3.2

Units

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

3.2

2.7

2.3

3.5

2.9

3.0

4.3

3.0

3.1

4.7

3.4

4.4

6.0

3.5

5.9

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

Table 1-30 • Worst-Case Military Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max

t_DLH

Max

t_DHL

Std.

2.3

t_ENZH

Std.

2.4

t_ENZL

Std.

2.1

Macro Type

OTB25LPHH

OTB25LPHN

Description

Std.

2.3

Units

2.5 V, Low Power, High Output Current, High Slew Rate⁵

2.5 V, Low Power, High Output Current, Nominal Slew

Rate⁵

2.7

3.2

2.8

2.1

OTB25LPHL

OTB25LPLH

OTB25LPLN

OTB25LPLL

Notes:

2.5 V, Low Power, High Output Current, Low Slew Rate⁵

2.5 V, Low Power, Low Output Current, High Slew Rate⁵

2.5 V, Low Power, Low Output Current, Nominal Slew Rate⁵

2.5 V, Low Power, Low Output Current, Low Slew Rate⁵

3.2

3.0

3.7

4.4

3.5

5.0

4.5

5.8

3.3

3.2

4.1

4.4

2.8

4.1

5.4

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. Low power I/O work with V_DDP=2.5V 10% only. V_DDP=2.3V for delays.

1-46

v5.8

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Flash Family FPGAs

Output Buffer Delays

50%

V_OH

PAD

50%

PAD

V_OL

50%

35pF

OBx

t_DLH

t_DHL

Figure 1-27 • Output Buffer Delays

Table 1-31 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max t_DLH

Max t_DHL

Std.

Macro Type

OB33PH

OB33PN

OB33PL

Description

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

Std.

2.0

2.2

2.5

2.6

2.9

3.0

–F

2.6

3.5

3.9

4.8

5.2

6.7

Units

2.4

2.6

3.0

3.1

3.5

3.6

2.2

2.9

3.2

4.0

4.3

5.6

OB33LH

OB33LN

OB33LL

Notes:

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. All –F parts are only available as commercial.

Table 1-32 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max t_DLH

Max t_DHL

Macro Type

Description

Std.

2.0

2.4

2.9

2.7

3.5

4.0

–F

Std.

2.1

3.0

3.2

4.6

4.2

5.3

–F

2.6

3.6

3.8

5.5

5.1

6.4

Units

OB25LPHH

OB25LPHN

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

2.5 V, Low Power, High Output Current, High Slew Rate³

2.4

2.9

3.5

3.3

4.2

4.8

2.5 V, Low Power, High Output Current, Nominal Slew Rate³

2.5 V, Low Power, High Output Current, Low Slew Rate³

2.5 V, Low Power, Low Output Current, High Slew Rate³

2.5 V, Low Power, Low Output Current, Nominal Slew Rate³

2.5 V, Low Power, Low Output Current, Low Slew Rate³

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. Low-power I/Os work with V_DDP=2.5 V 10% only. V_DDP=2.3 V for delays.

4. All –F parts are only available as commercial.

v5.8

1-47

PLUS

ProASIC

Flash Family FPGAs

Table 1-33 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max.

t_DLH

Max.

t_DHL

Macro Type

OB33PH

OB33PN

OB33PL

Description

Std.

2.1

2.5

2.7

3.3

Std.

2.3

3.2

3.5

4.3

4.7

6.1

Units

3.3V, PCI Output Current, High Slew Rate

3.3V, High Output Current, Nominal Slew Rate

3.3V, High Output Current, Low Slew Rate

3.3V, Low Output Current, High Slew Rate

3.3V, Low Output Current, Nominal Slew Rate

3.3V, Low Output Current, Low Slew Rate

OB33LH

OB33LN

OB33LL

Notes:

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

Table 1-34 • Worst-Case Military Conditions

V_DDP= 2.3 V, V_DD= 2.3V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max.

t_DLH

Max.

t_DHL

Macro Type

Description

Std.

2.3

2.7

3.2

3.0

3.9

4.3

Std.

2.4

3.3

3.5

5.0

4.6

5.7

Units

OB25LPHH

OB25LPHN

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

2.5V, Low Power, High Output Current, High Slew Rate³

2.5V, Low Power, High Output Current, Nominal Slew Rate³

2.5V, Low Power, High Output Current, Low Slew Rate³

2.5V, Low Power, Low Output Current, High Slew Rate³

2.5V, Low Power, Low Output Current, Nominal Slew Rate³

2.5V, Low Power, Low Output Current, Low Slew Rate³

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. Low power I/O work with V_DDP=2.5V 10% only. V_DDP=2.3V for delays.

1-48

v5.8

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ProASIC

Flash Family FPGAs

Input Buffer Delays

DDP

PAD

0 V

50% 50%

V_DD

PAD

50%

GND

50%

IBx

INYH

INYL

Figure 1-28 • Input Buffer Delays

Table 1-35 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max. t_INYH

Max. t_INYL

Macro Type

IB33

Description

Std.

–F

0.5

0.7

Std.

0.6

–F

0.7

0.9

Units

3.3 V, CMOS Input Levels³, No Pull-up Resistor

0.4

0.6

IB33S

3.3 V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

0.8

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3 V for delays.

5. All –F parts are only available as commercial.

Table 1-36 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, T_J= 70°C

Max. t_INYH

Max. t_INYL

Macro Type

Description

Std.

0.9

–F

1.1

0.9

Std.

0.6

–F

0.8

1.1

Units

IB25LP

2.5 V, CMOS Input Levels³, Low Power

IB25LPS

Notes:

2.5 V, CMOS Input Levels³, Low Power, Schmitt Trigger

0.7

0.9

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3 V for delays.

5. All –F parts are only available as commercial.

v5.8

1-49

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Flash Family FPGAs

Table 1-37 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Max. t_INYH

Std.

Max. t_INYL

Std.

Macro Type

IB33

Description

Units

3.3V, CMOS Input Levels³, No Pull-up Resistor

0.5

0.6

IB33S

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

0.6

0.8

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

Table 1-38 • Worst-Case Military Conditions

V_DDP= 2.3V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Max. t_INYH

Std.

Max. t_INYL

Std.

Macro Type

IB25LP

Description

Units

2.5V, CMOS Input Levels³, Low Power

0.9

0.7

IB25LPS

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

0.8

1.0

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

1-50

v5.8

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Flash Family FPGAs

Global Input Buffer Delays

Table 1-39 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max. t_INYH

Max. t_INYL

Units

Macro Type

GL33

Description

Std.³

–F

1.2

Std.³

–F

1.3

3.3 V, CMOS Input Levels⁴, No Pull-up Resistor

3.3 V, CMOS Input Levels⁴, No Pull-up Resistor, Schmitt Trigger

PPECL Input Levels

1.0

1.1

GL33S

1.0

1.1

PECL

1.0

1.1

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. Applies to Military ProASIC^PLUSdevices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

Table 1-40 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, T_J= 70°C

Max. t_INYH

Max. t_INYL

Units

Macro Type

GL25LP

Description

2.5 V, CMOS Input Levels⁴, Low Power

2.5 V, CMOS Input Levels⁴, Low Power, Schmitt Trigger

Std.³

–F

Std.³

–F

1.1

1.2

1.6

1.0

1.3

1.1

GL25LPS

Notes:

1.3

1.0

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. Applies to Military ProASIC^PLUSdevices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

v5.8

1-51

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Flash Family FPGAs

Table 1-41 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Max. t_INYH

Max. t_INYL

Std.

Macro Type

GL33

Description

3.3V, CMOS Input Levels³, No Pull-up Resistor

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

PPECL Input Levels

Std.

1.1

GL33S

1.1

PECL

1.1

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

Table 1-42 • Worst-Case Military Conditions

V_DDP= 2.3V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Max. t_INYH

Std.

Max. t_INYL

Std.

Macro Type

Description

2.5V, CMOS Input Levels³, Low Power

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

GL25LP

GL25LPS

Notes:

1.0

1.1

1.4

1.0

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

1-52

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Flash Family FPGAs

Predicted Global Routing Delay

Table 1-43 • Worst-Case Commercial Conditions¹

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max.

Parameter

t_RCKH

Description

Std.

1.1

1.0

0.8

–F²

1.3

1.2

1.0

Units

Input Low to High³

Input High to Low³

Input Low to High⁴

Input High to Low⁴

t_RCKL

t_RCKH

t_RCKL

Notes:

1. The timing delay difference between tile locations is less than 15ps.

2. All –F parts are only available as commercial.

3. Highly loaded row 50%.

4. Minimally loaded row.

Table 1-44 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Parameter

t_RCKH

Description

Max.

Units

Input Low to High (high loaded row of 50ꢀ)

Input High to Low (high loaded row of 50ꢀ)

Input Low to High (minimally loaded row)

Input High to Low (minimally loaded row)

1.1

1.0

0.8

t_RCKL

t_RCKH

t_RCKL

Note: * The timing delay difference between tile locations is less than 15 ps.

Global Routing Skew

Table 1-45 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max.

Parameter

t_RCKSWH

Description

Maximum Skew Low to High

Maximum Skew High to Low

Std.

270

–F*

320

Units

t_RCKSHH

Note: *All –F parts are only available as commercial.

Table 1-46 • Worst-Case Commercial Conditions

_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Description

Maximum Skew Low to High

Maximum Skew High to Low

Parameter

t_RCKSWH

Max.

Units

270

t_RCKSHH

v5.8

1-53

PLUS

ProASIC

Flash Family FPGAs

Module Delays

50%50%

50%

t_DBLH

50%

t_DCHL

t_DCLH

t_DBHL

t_DAHL

t_DALH

Figure 1-29 • Module Delays

Sample Macrocell Library Listing

Table 1-47 • Worst-Case Military Conditions¹

V_DD= 2.3 V, T_J= 70º C, T_J= 70°C, T_J= 125°C for Military/MIL-STD-883

Std.

–F²

Cell Name

NAND2

AND2

Description

Max

Min

Max

0.6

0.8

1.0

0.6

1.0

0.8

Min

Units

2-Input NAND

2-Input AND

3-Input NOR

0.5

0.7

0.8

0.5

0.8

0.6

NOR3

MUX2L

OA21

2-1 MUX with Active Low Select

2-Input OR into a 2-Input AND

2-Input Exclusive OR

XOR2

LDL

Active Low Latch (LH/HL)

LH³

HL³

0.9

0.8

1.1

0.9

CLK-Q

t_setup

0.7

0.1

0.8

0.2

t_hold

DFFL

Negative Edge-Triggered D-type Flip-Flop (LH/HL)

LH³

HL³

0.9

0.8

1.1

1.0

CLK-Q

t_setup

t_hold

0.6

0.0

0.7

0.0

Notes:

1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

2. All –F parts are only available as commercial.

3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.

1-54

v5.8

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Flash Family FPGAs

Table 1-48 • Recommended Operating Conditions

Limits

Parameter

Symbol

f_CLOCK

f_RAM

Commercial/Industrial

180 MHz

Military/MIL-STD-883

180 MHz

Maximum Clock Frequency*

Maximum RAM Frequency*

Maximum Rise/Fall Time on Inputs*

150 MHz

•

Schmitt Trigger Mode (10ꢀ to 90ꢀ)

t_R/t_F

N/A

100 ns

10 ns

Non-Schmitt Trigger Mode (10ꢀ to

90ꢀ)

100 ns

Maximum LVPECL Frequency*

Maximum TCK Frequency (JTAG)

180 MHz

10 MHz

180 MHz

10 MHz

f_TCK

Note: *All –F parts will be 20% slower than standard commercial devices.

Table 1-49 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C

Type

Trig. Level Rising Edge (ns) Slew Rate (V/ns) Falling Edge (ns) Slew Rate (V/ns)

PCI Mode

Yes

OB33PH

OB33PN

OB33PL

OB33LH

OB33LN

OB33LL

10ꢀ-90ꢀ

1.60

1.57

3.80

4.19

5.49

1.55

1.70

1.97

3.57

4.65

5.52

1.65

1.68

0.70

0.63

0.48

1.29

1.18

1.02

0.56

0.43

0.36

1.65

3.32

1.99

4.84

3.37

2.98

1.56

2.08

2.09

3.93

3.28

3.44

1.60

0.80

1.32

0.55

0.78

0.89

1.28

0.96

0.51

0.61

0.58

OB25LPHH 10ꢀ-90ꢀ

OB25LPHN 10ꢀ-90ꢀ

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

10ꢀ-90ꢀ

1. Standard and –F parts.

2. All –F only available as commercial.

v5.8

1-55

PLUS

ProASIC

Flash Family FPGAs

Table 1-50 • JTAG Switching Characteristics

Description

Symbol

t_TCKTDI

t_TDOTCK

t_TCKTDO

t_TCK

Min

–4

Max

Unit

Output delay from TCK falling to TDI, TMS

TDO Setup time before TCK rising

TDO Hold time after TCK rising

TCK period

100 ²

1,000

RCK period

t_RCK

100

Notes:

1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-22 on page 1-37 when V_DDP= 2.5 V

and Table 1-24 on page 1-41 when V_DDP= 3.3 V.

2. If RCK is being used, there is no minimum on the TCK period.

TCK

t_TCK

TMS, TDI

t_TCKTDI

TDO

t_TDOTCK

t_TCKTDO

Figure 1-30 • JTAG Operation Timing

1-56

v5.8

PLUS

ProASIC

Flash Family FPGAs

Embedded Memory Specifications

This section discusses ProASIC^PLUSSRAM/FIFO embedded

memory and its interface signals, including timing

diagrams that show the relationships of signals as they

pertain to single embedded memory blocks (Table 1-51).

Table 1-13 on page 1-24 shows basic SRAM and FIFO

configurations. Simultaneous read and write to the same

location must be done with care. On such accesses the DI

bus is output to the DO bus. Refer to the ProASIC^PLUS

RAM and FIFO Blocks application note for more

information.

•

"Asynchronous SRAM Read, RDB Controlled"

section on page 1-62

•

"Synchronous SRAM Write"

Embedded Memory Specifications

The difference between synchronous transparent and

pipeline modes is the timing of all the output signals

from the memory. In transparent mode, the outputs will

change within the same clock cycle to reflect the data

requested by the currently valid access to the memory. If

clock cycles are short (high clock speed), the data

requires most of the clock cycle to change to valid values

(stable signals). Processing of this data in the same clock

cycle is nearly impossible. Most designers add registers at

all outputs of the memory to push the data processing

into the next clock cycle. An entire clock cycle can then

be used to process the data. To simplify use of this

Enclosed Timing Diagrams—SRAM Mode:

•

"Synchronous SRAM Read, Access Timed Output

Strobe (Synchronous Transparent)" section on

page 1-58

•

"Synchronous SRAM Read, Pipeline Mode Outputs

(Synchronous Pipelined)" section on page 1-59

memory

setup,

suitable

registers

have

been

•

"Asynchronous SRAM Write" section on page 1-60

implemented as part of the memory primitive and are

available to the user in the synchronous pipeline mode.

In this mode, the output signals will change shortly after

the second rising edge, following the initiation of the

read access.

"Asynchronous SRAM Read, Address Controlled,

RDB=0" section on page 1-61

Table 1-51 • Memory Block SRAM Interface Signals

SRAM Signal

WCLKS

RCLKS

Bits

In/Out

Description

Write clock used on synchronization on write side

Read clock used on synchronization on read side

Read address

RADDR<0:7>

RBLKB

True read block select (active Low)

True read pulse (active Low)

RDB

WADDR<0:7>

WBLKB

Write address

Write block select (active Low)

DI<0:8>

WRB

Input data bits <0:8>, <8> can be used for parity In

Negative true write pulse

DO<0:8>

RPE

Out

Output data bits <0:8>, <8> can be used for parity Out

Read parity error (active High)

WPE

Write parity error (active High)

PARODD

Selects Odd parity generation/detect when high, Even when low

Note: Not all signals shown are used in all modes.

v5.8

1-57

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

RCLKS

Cycle Start

RBD, RBLKB

New Valid

RADDR

Address

Old Data Out

New Valid Data Out

RPE

RACS

RDCS

RDCH

RACH

OCH

RPCH

CMH

CML

OCA

RPCA

CCYC

Note: The plot shows the normal operation status.

Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-52 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max.

Units

Notes

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

7.5

OCH

3.0

RACH

RACS

0.5

1.0

0.5

1.0

9.5

RDCH

RDCS

RPCA

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

RPCH

3.0

Note: All –F speed grade devices are 20% slower than the standard numbers.

1-58

v5.8

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLKS

Cycle Start

RDB, RBLKB

New Valid

RADDR

Address

New Valid Data Out

New RPE Out

Old Data Out

RPE

Old RPE Out

RACS

OCA

RACH

RPCH

RDCH

OCH

RPCA

RDCS

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-32 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-53 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= 0°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max.

Units

Notes

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

2.0

OCH

0.75

RACH

RACS

0.5

1.0

0.5

1.0

4.0

RDCH

RDCS

RPCA

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

RPCH

1.0

Note: All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-59

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Write

WADDR

WRB, WBLKB

WPE

AWRS

AWRH

DWRH

WPDH

WPDA

DWRS

WRMH

WRML

WRCYC

Note: The plot shows the normal operation status.

Figure 1-33 • Asynchronous SRAM Write

Table 1-54 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883B

Symbol t_xxx

AWRH

Description

WADDR hold from WB ↑

Min.

1.0

0.5

1.5

0.5

2.5

3.0

Max.

Units

Notes

AWRS

WADDR setup to WB ↓

DI hold from WB ↑

DI setup to WB ↑

WPE access from DI

WPE hold from DI

Cycle time

DWRH

DWRS

PARGEN is inactive.

PARGEN is active.

DWRS

WPDA

WPE is invalid, while PARGEN is

active.

WPDH

1.0

WRCYC

WRMH

WRML

7.5

3.0

WB high phase

Inactive

Active

WB low phase

Note: All –F speed grade devices are 20% slower than the standard numbers.

1-60

v5.8

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Read, Address Controlled, RDB=0

RADDR

RPE

OAH

RPAH

OAA

RPAA

ACYC

Note: The plot shows the normal operation status.

Figure 1-34 • Asynchronous SRAM Read, Address Controlled, RDB=0

Table 1-55 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883B

Symbol t_xxx

ACYC

Description

Read cycle time

Min.

7.5

Max.

Units

Notes

OAA

New DO access from RADDR stable

Old DO hold from RADDR stable

New RPE access from RADDR stable

Old RPE hold from RADDR stable

7.5

OAH

3.0

RPAA

10.0

RPAH

Note: All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-61

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Read, RDB Controlled

RB=(RDB+RBLKB)

RPE

ORDH

RPRDH

ORDA

RPRDA

RDML

RDMH

RDCYC

Note: The plot shows the normal operation status.

Figure 1-35 • Asynchronous SRAM Read, RDB Controlled

Table 1-56 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

Min.

Max.

Units

Notes

7.5

ORDH

3.0

RDCYC

RDMH

7.5

3.0

9.5

RB high phase

Inactive setup to new cycle

Active

RDML

RB low phase

RPRDA

RPRDH

New RPE access from RB ↓

Old RPE valid from RB ↓

3.0

Note: All –F speed grade devices are 20% slower than the standard numbers.

1-62

v5.8

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Write

WCLKS

WRB, WBLKB

WADDR, DI

WPE

Cycle Start

, t

WRCH WBCH

, t

WRCS WBCS

, t

DCS WDCS

WPCH

, t

DCH WACH

WPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-36 • Synchronous SRAM Write

Table 1-57 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

3.0

0.5

1.0

0.5

1.0

3.0

Max.

Units

Notes

Cycle time

Clock high phase

CML

Clock low phase

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

DCS

WACH

WDCS

WPCA

WPCH

WADDR hold from WCLKS ↑

WADDR setup to WCLKS ↑

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

WPE is invalid while

PARGEN is active

0.5

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

1. On simultaneous read and write accesses to the same location, DI is output to DO.

2. All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-63

PLUS

ProASIC

Flash Family FPGAs

Synchronous Write and Read to the Same Location

CCYC

CMH

CML

RCLKS

New Data*

Last Cycle Data

WCLKS

WCLKRCLKH

WCLKRCLKS

OCH

OCA

* New data is read if WCLKS ↑ occurs before setup time.

The data stored is read if WCLKS ↑ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-37 • Synchronous Write and Read to the Same Location

Table 1-58 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max.

Units

Notes

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WCLKRCLKS

WCLKRCLKH

OCH

WCLKS ↑ to RCLKS ↑ setup time

WCLKS ↑ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

– 0.1

7.0

3.0

OCA/OCH displayed for

Access Timed Output

OCA

7.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write

clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS

and RCLKS driven by the same design signal.

3. If WCLKS changes after the hold time, the data will be read.

4. A setup or hold time violation will result in unknown output data.

5. All –F speed grade devices are 20% slower than the standard numbers.

1-64

v5.8

PLUS

ProASIC

Flash Family FPGAs

Asynchronous Write and Synchronous Read to the Same Location

CMH

CML

RCLKS

New Data*

Last Cycle Data

WB = {WRB + WBLKB}

WRCKS

BRCLKH

OCH

OCA

DWRRCLKS

DWRH

CCYC

* New data is read if WB ↓ occurs before setup time.

The stored data is read if WB ↓ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-38 • Asynchronous Write and Synchronous Read to the Same Location

Table 1-59 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max.

Units

Notes

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WBRCLKS

WBRCLKH

OCH

WB ↓ to RCLKS ↑ setup time

WB ↓ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

DI to RCLKS ↑ setup time

DI to WB ↑ hold time

–0.1

7.0

3.0

OCA/OCH

Access Timed Output

displayed

for

OCA

7.5

DWRRCLKS

DWRH

1.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write

signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be

read.

3. A setup or hold time violation will result in unknown output data.

4. All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-65

PLUS

ProASIC

Flash Family FPGAs

Asynchronous Write and Read to the Same Location

RB, RADDR

NEW

NEWER

OLD

WB = {WRB+WBLKB}

ORDA

RAWRH

ORDH

RAWRS

OWRA

OWRH

Note: The plot shows the normal operation status.

Figure 1-39 • Asynchronous Write and Read to the Same Location

Table 1-60 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Min.

Max.

Units

Notes

7.5

ORDH

3.0

OWRA

New DO access from WB ↑

Old DO valid from WB ↑

RB ↓ or RADDR from WB ↓

RB ↑ or RADDR from WB ↑

3.0

OWRH

0.5

RAWRS

RAWRH

Notes:

5.0

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data. Refer to the ProASIC^PLUSRAM and FIFO Blocks application note for more

information.

2. Violation or RAWRS will disturb access to the OLD data.

3. Violation of RAWRH will disturb access to the NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

1-66

v5.8

PLUS

ProASIC

Flash Family FPGAs

Synchronous Write and Asynchronous Read to the Same Location

RB, RADDR

NEW

NEWER

OLD

WCLKS

ORDA

RAWCLKH

ORDH

OWRA

OWRH

RAWCLKS

Note: The plot shows the normal operation status.

Figure 1-40 • Synchronous Write and Asynchronous Read to the Same Location

Table 1-61 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Min.

Max.

Units

Notes

7.5

ORDH

3.0

OWRA

New DO access from WCLKS ↓

Old DO valid from WCLKS ↓

RB ↓ or RADDR from WCLKS ↑

RB ↑ or RADDR from WCLKS ↓

3.0

OWRH

0.5

RAWCLKS

RAWCLKH

Notes:

5.0

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data.

2. Violation of RAWCLKS will disturb access to OLD data.

3. Violation of RAWCLKH will disturb access to NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-67

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Full and Empty Transitions

The asynchronous FIFO accepts writes and reads while

not full or not empty. When the FIFO is full, all writes are

inhibited. Conversely, when the FIFO is empty, all reads

are inhibited. A problem is created if the FIFO is written

to during the transition from full to not full, or read

during the transition from empty to not empty. The

exact time at which the write or read operation changes

from inhibited to accepted after the read (write) signal

which causes the transition from full or empty to not full

or not empty is indeterminate. For slow cycles, this

indeterminate period starts 1 ns after the RB (WB)

transition, which deactivates full or not empty and ends

3 ns after the RB (WB) transition. For fast cycles, the

indeterminate period ends 3 ns (7.5 ns – RDL (WRL)) after

the RB (WB) transition, whichever is later (Table 1-1 on

page 1-7).

empty flag will be asserted, the counters will reset, the

outputs go to zero, but the internal RAM is not erased.

Enclosed Timing Diagrams – FIFO Mode:

The following timing diagrams apply only to single cell;

they are not applicable to cascaded cells. For more

information, refer to the ProASIC^PLUSRAM/FIFO Blocks

application note.

•

"Asynchronous FIFO Read" section on page 1-70

"Asynchronous FIFO Write" section on page 1-71

"Synchronous FIFO Read, Access Timed Output

Strobe (Synchronous Transparent)" section on

page 1-72

•

"Synchronous FIFO Read, Pipeline Mode Outputs

(Synchronous Pipelined)" section on page 1-73

The timing diagram for write is shown in Figure 1-38 on

page 1-65. The timing diagram for read is shown in

Figure 1-39 on page 1-66. For basic SRAM configurations,

see Table 1-14 on page 1-25. When reset is asserted, the

•

"Synchronous FIFO Write" section on page 1-74

"FIFO Reset" section on page 1-75

Table 1-62 • Memory Block FIFO Interface Signals

FIFO Signal

WCLKS

Bits

In/Out

Description

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active Low)

RCLKS

LEVEL <0:7>*

RBLKB

RDB

Read pulse (active Low)

RESET

Reset for FIFO pointers (active Low)

WBLKB

Write block select (active Low)

DI<0:8>

WRB

Input data bits <0:8>, <8> will be generated if PARGEN is true

Write pulse (active Low)

FULL, EMPTY

EQTH, GEQTH*

Out

FIFO flags. FULL prevents write and EMPTY prevents read

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

Out

Output data bits <0:8>

Read parity error (active High)

WPE

Write parity error (active High)

LGDEP <0:2>

PARODD

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

Selects Odd parity generation/detect when high, Even when low

Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be

possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that

indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.

Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.

1-68

v5.8

PLUS

ProASIC

Flash Family FPGAs

FULL

Write

cycle

Write inhibited

Write accepted

1 ns

3 ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

Figure 1-41 • Write Timing Diagram

EMPTY

Read

cycle

Read inhibited

Read accepted

1 ns

3 ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

Figure 1-42 • Read Timing Diagram

v5.8

1-69

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Read

RPRDA

RDH

RDL

Cycle Start

RB = (RDB+RBLKB)

(Empty inhibits read)

RDATA

RPE

EMPTY

FULL

EQTH, GETH

, t

RDWRS

ERDH FRDH

, t

ORDH

ERDA FRDA

RPRDH

THRDH

ORDA

THRDA

RPRDA

RDL

RDH

RDCYC

Note: The plot shows the normal operation status.

Figure 1-43 • Asynchronous FIFO Read

Table 1-63 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

Description

Min.

Max. Units

Notes

ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

Empty/full/thresh are invalid from the end of

hold until the new access is complete

THRDH

time from RB ↑

ERDA

New EMPTY access from RB ↑

FULL↓ access from RB ↑

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

3.0¹

7.5

FRDA

ORDA

ORDH

RDCYC

RDWRS

3.0

1.0

7.5

3.0²

WB ↑, clearing EMPTY, setup to

RB ↓

Enabling the read operation

Inhibiting the read operation

Inactive

RDH

RB high phase

3.0

9.5

RDL

RB low phase

Active

RPRDA

RPRDH

THRDA

Notes:

New RPE access from RB ↓

Old RPE valid from RB ↓

EQTH or GETH access from RB↑

4.0

4.5

1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.

2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.

3. All –F speed grade devices are 20% slower than the standard numbers.

1-70

v5.8

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Write

Cycle Start

WB = (WRB+WBLKB)

WDATA

WPE

(Full inhibits write)

FULL

EMPTY

EQTH, GETH

WRRDS

DWRH

WPDH

WPDA

DWRS

, t

EWRH FWRH

, t

EWRA FWRA

THWRH

THWRA

WRL

WRH

WRCYC

Note: The plot shows the normal operation status.

Figure 1-44 • Asynchronous FIFO Write

Table 1-64 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

DWRH

Description

DI hold from WB ↑

Min.

1.5

Max.

Units

Notes

DWRS

DI setup to WB ↑

0.5

PARGEN is inactive

PARGEN is active

DWRS

2.5

EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THWRH

time after WB ↑

EWRA

EMPTY ↓ access from WB ↑

New FULL access from WB ↑

EQTH or GETH access from WB ↑

WPE access from DI

3.0¹

4.5

FWRA

THWRA

WPDA

WPDH

WRCYC

WRRDS

3.0

WPE is invalid while PARGEN is active

WPE hold from DI

1.0

Cycle time

7.5

3.0²

RB ↑, clearing FULL, setup to

WB ↓

Enabling the write operation

Inhibiting the write operation

Inactive

WRH

WRL

WB high phase

WB low phase

3.0

Active

Notes:

1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.

2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.

3. All –F speed grade devices are 20% slower than the standard numbers.

4. After FIFO reset, WRB needs an initial falling edge prior to any write actions.

v5.8

1-71

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out (Empty Inhibits Read)

EMPTY

FULL

EQTH, GETH

, t

RDCH

ECBH FCBH

, t

ECBA FCBA

RDCS

THCBH

OCH

RPCH

HCBA

OCA

RPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-65 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max. Units

Notes

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓ access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

1.0

3.0

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THCBH

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

7.5

OCH

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

9.5

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

3.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

1-72

v5.8

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out

New RPE Out

Old RPE Out

EMPTY

FULL

EQTH, GETH

, t

ECBH FCBH

OCA

, t

RDCH

ECBA FCBA

RDCS

THCBH

RPCH

OCH

HCBA

RPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-66 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min. Max. Units

Notes

Cycle time

7.5

3.0

CMH

Clock high phase

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓ access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

THCBH

1.0

Empty/full/thresh are invalid from the end of

hold until the new access is complete

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

2.0

OCH

0.75

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

4.0

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

1.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-73

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Write

WCLKS

Cycle Start

WRB, WBLKB

(Full Inhibits Write)

WPE

FULL

EMPTY

EQTH, GETH

, t

WRCH WBCH

ECBH FCBH

, t

ECBA FCBA

WRCS WBCS

DCS

HCBH

HCBA

WPCH

DCH

WPCA

CMH

CML

CCYC

Note: The plot shows the normal operation status.

Figure 1-47 • Synchronous FIFO Write

Table 1-67 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max. Units

Notes

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

0.5

DCS

1.0

FCBA

New FULL access from WCLKS ↓

EMPTY↓ access from WCLKS ↓

3.0¹

ECBA

ECBH,

FCBH,

HCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from WCLKS ↓

1.0

0.5

Empty/full/thresh are invalid from the end of

hold until the new access is complete

HCBA

WPCA

WPCH

EQTH or GETH access from WCLKS ↓

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

4.5

3.0

WPE is invalid, while PARGEN is active

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

1-74

v5.8

PLUS

ProASIC

Flash Family FPGAs

FIFO Reset

RESETB

Cycle Start

WRB/RBD¹

WCLKS, RCLKS¹

FULL

Cycle Start

EMPTY

EQTH, GETH

CBRSS

, t

ERSA FRSA

CBRSH

WBRSH

THRSA

RSL

WBRSS

Notes:

1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.

2. The plot shows the normal operation status.

Figure 1-48 • FIFO Reset

Table 1-68 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CBRSH¹

CBRSS¹

ERSA

Description

WCLKS or RCLKS ↑ hold from RESETB ↑

WCLKS or RCLKS ↓ setup to RESETB ↑

New EMPTY ↑ access from RESETB ↓

FULL ↓ access from RESETB ↓

RESETB low phase

Min.

1.5

3.0

7.5

4.5

1.5

Max.

Units

Notes

Synchronous mode only

FRSA

RSL

THRSA

WBRSH¹

WBRSS¹

Notes:

EQTH or GETH access from RESETB ↓

WB ↓ hold from RESETB ↑

Asynchronous mode only

WB ↑ setup to RESETB ↑

1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.

2. All –F speed grade devices are 20% slower than the standard numbers.

v5.8

1-75

TMS

Test Mode Select

Pin Description

The TMS pin controls the use of boundary-scan circuitry.

This pin has an internal pull-up resistor.

User Pins

TCK

Test Clock

I/O

User Input/Output

Clock input pin for boundary scan (maximum 10 MHz). Actel

recommends adding a nominal 20 kΩ pull-up resistor to this

pin.

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with standard LVTTL and LVCMOS

specifications. Unused I/O pins are configured as inputs

with pull-up resistors.

TDI

Test Data In

Serial input for boundary scan. A dedicated pull-up

resistor is included to pull this pin high when not being

driven.

No Connect

To maintain compatibility with other Actel ProASIC^PLUS

products, it is recommended that this pin not be

connected to the circuitry on the board.

TDO

Test Data Out

Serial output for boundary scan. Actel recommends

adding a nominal 20kΩ pull-up resistor to this pin.

Global Pin

TRST

Test Reset Input

Low skew input pin for clock or other global signals. This

pin can be configured with an internal pull-up resistor.

When it is not connected to the global network or the

clock conditioning circuit, it can be configured and used

as a normal I/O.

Asynchronous, active-low input pin for resetting

boundary-scan circuitry. This pin has an internal pull-up

resistor. For more information, please refer to Power-up

Behavior of ProASIC^PLUSDevices application note.

GLMX

Global Multiplexing Pin

Special Function Pins

Low skew input pin for clock or other global signals. This

pin can be used in one of two special ways (refer to

Actel’s Using ProASIC^PLUSClock Conditioning Circuits).

RCK

Running Clock

A free running clock is needed during programming if

the programmer cannot guarantee that TCK will be

uninterrupted. If not used, this pin has an internal pull-

up and can be left floating.

When the external feedback option is selected for the

PLL block, this pin is routed as the external feedback

source to the clock conditioning circuit.

In applications where two different signals access the

same global net at different times through the use of

GLMXx and GLMXLx macros, this pin will be fixed as one

of the source pins.

NPECL

User Negative Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

This pin can be configured with an internal pull-up

resistor. When it is not connected to the global network

or the clock conditioning circuit, it can be configured and

used as any normal I/O. If not used, the GLMXx pin will

be configured as an input with pull-up.

PPECL

User Positive Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

AVDD

PLL Power Supply

Analog V_DDshould be V_DD(core voltage) 2.5 V (nominal)

and be decoupled from GND with suitable decoupling

capacitors to reduce noise. For more information, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note. If the clock conditioning circuitry is not

used in a design, AVDD can either be left floating or tied

to 2.5 V.

Dedicated Pins

GND

Ground

Common ground supply voltage.

Logic Array Power Supply Pin

2.5 V supply voltage.

AGND

PLL Power Ground

I/O Pad Power Supply Pin

DDP

The analog ground can be connected to the system

ground. For more information, refer to Actel’s Using

ProASIC^PLUSClock Conditioning Circuits application note.

If the PLLs or clock conditioning circuitry are not used in

a design, AGND should be tied to GND.

2.5 V or 3.3 V supply voltage.

PLUS

ProASIC

Flash Family FPGAs

Programming Supply Pin

finite length conductors that distribute the power to the

device. This can be accomplished by providing sufficient

bypass capacitance between the V_PPand V_PNpins and

GND (using the shortest paths possible). Without

sufficient bypass capacitance to counteract the

inductance, the V_PPand V_PNpins may incur a voltage

spike beyond the voltage that the device can withstand.

This issue applies to all programming configurations.

This pin may be connected to any voltage between GND

and 16.5 V during normal operation, or it can be left

unconnected.²For information on using this pin during

programming,

ProASIC^PLUSDevices application note. Actel recommends

floating the pin or connecting it to V_DDP

see

the

In-System Programming

Programming Supply Pin

The solution prevents spikes from damaging the

ProASIC^PLUSdevices. Bypass capacitors are required for

the V_PPand V_PNpads. Use a 0.01 µF to 0.1 µF ceramic

capacitor with a 25 V or greater rating. To filter low-

frequency noise (decoupling), use a 4.7 µF (low ESR, <1

<Ω, tantalum, 25 V or greater rating) capacitor. The

capacitors should be located as close to the device pins as

possible (within 2.5 cm is desirable). The smaller, high-

frequency capacitor should be placed closer to the device

pins than the larger low-frequency capacitor. The same

dual-capacitor circuit should be used on both the V_PPand

V_PNpins (Figure 1-49).

This pin may be connected to any voltage between 0.5V

and –13.8 V during normal operation, or it can be left

unconnected.³For information on using this pin during

programming,

see

the

In-System Programming

ProASIC^PLUSDevices application note. Actel recommends

floating the pin or connecting it to GND.

Recommended Design Practice

for V /V

PN PP

PLUS

ProASIC

Devices – APA450, APA600,

ProASIC

APA300

Devices – APA075, APA150,

APA750, APA1000

Bypass capacitors are required from V_PPto GND and V_PN

to GND for all ProASIC^PLUSdevices during programming.

During the erase cycle, ProASIC^PLUSdevices may have

current surges on the V_PPand V_PNpower supplies. The

only way to maintain the integrity of the power

distribution to the ProASIC^PLUSdevice during these

current surges is to counteract the inductance of the

These devices do not require bypass capacitors on the V_PP

and V_PNpins as long as the total combined distance of

the programming cable and the trace length on the

board is less than or equal to 30 inches. Note: For trace

lengths greater than 30 inches, use the bypass capacitor

recommendations in the previous section.

2.5cm

0.1μF

4.7μF

Programming

Header

Actel

ProASIC

Device

0.01μF

PLUS

Supplies

0.1μF

0.01μF

Figure 1-49 • ProASIC^PLUSV_PPand V_PNCapacitor Requirements

2. There is a nominal 40 kΩ pull-up resistor on V_PP.

3. There is a nominal 40 kΩ pull-down resistor on V_PN

v5.8

1-77

APA1000-CQ208M [MICROSEMI]

相关型号：

APA1000-CQB

APA1000-CQES

APA1000-CQGB

APA1000-CQGES

APA1000-CQGI

APA1000-CQGM

APA1000-CQGPP

APA1000-CQI

APA1000-CQM

APA1000-CQPP

APA1000-FBGB

APA1000-FBGES