APT6M100K [MICROSEMI]
N-Channel MOSFET; N沟道MOSFET
| 型号： | APT6M100K |
| 厂家： | 
Microsemi |
| 描述： | N-Channel MOSFET |
| 文件： | 总4页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APT6M100K
1000V, 6A, 2.50Ω Max
N-Channel MOSFET
Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET.
A proprietary planar stripe design yields excellent reliability and manufacturability. Low
switching loss is achieved with low input capacitance and ultra low Crss "Miller" capaci-
tance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure
help control slew rates during switching, resulting in low EMI and reliable paralleling,
even when switching at very high frequency. Reliability in flyback, boost, forward, and
other circuits is enhanced by the high avalanche energy capability.
D
APT6M100K
Single die MOSFET
G
S
FEATURES
TYPICAL APPLICATIONS
• PFC and other boost converter
• Fast switching with low EMI/RFI
• Buck converter
• Low RDS(on)
• Two switch forward (asymmetrical bridge)
• Single switch forward
• Flyback
• Ultra low Crss for improved noise immunity
• Low gate charge
• Avalanche energy rated
• RoHS compliant
• Inverters
Absolute Maximum Ratings
Symbol Parameter
Unit
Ratings
Continuous Drain Current @ TC = 25°C
ID
6
4
Continuous Drain Current @ TC = 100°C
A
Pulsed Drain Current 1
IDM
VGS
EAS
IAR
20
±30
310
3
V
mJ
A
Gate-Source Voltage
Single Pulse Avalanche Energy 2
Avalanche Current, Repetitive or Non-Repetitive
Thermal and Mechanical Characteristics
Symbol Characteristic
Min
Typ
Max
225
Unit
PD
Total Power Dissipation @ TC = 25°C
W
RθJC
0.43
Junction to Case Thermal Resistance
°C/W
°C
RθCS
0.11
Case to Sink Thermal Resistance, Flat, Greased Surface
TJ,TSTG
-55
150
300
Operating and Storage Junction Temperature Range
TL
Soldering Temperature for 10 Seconds (1.6mm from case)
oz
g
0.07
1.2
WT
Package Weight
in·lbf
N·m
10
Torque
Mounting Torque ( TO-220 Package), 6-32 or M3 screw
1.1
Microsemi Website - http://www.microsemi.com
Static Characteristics
T = 25°C unless otherwise specified
J
APT6M100K
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Symbol
VBR(DSS)
V
= 0V, I = 250µA
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Drain-Source On Resistance 3
Gate-Source Threshold Voltage
Threshold Voltage Temperature Coefficient
1000
GS
D
∆VBR(DSS)/∆TJ
Reference to 25°C, I = 250µA
D
V/°C
Ω
1.15
2.05
4
V
= 10V, I = 3A
D
RDS(on)
VGS(th)
2.50
5
GS
V
3
V
= VDS, I = 1mA
D
GS
∆VGS(th)/∆TJ
mV/°C
-10
V
= 1000V
= 0V
T = 25°C
J
100
500
DS
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
µA
nA
V
T = 125°C
J
GS
V
= ±30V
±100
GS
Dynamic Characteristics
T = 25°C unless otherwise specified
J
Symbol
Parameter
Test Conditions
Min
Typ
5.6
Max
Unit
gfs
V
= 50V, I = 3A
S
Forward Transconductance
Input Capacitance
DS
D
Ciss
Crss
Coss
1410
19
V
= 0V, V = 25V
DS
GS
Reverse Transfer Capacitance
Output Capacitance
f = 1MHz
120
pF
4
Co(cr)
48
Effective Output Capacitance, Charge Related
Effective Output Capacitance, Energy Related
V
= 0V, V = 0V to 667V
DS
GS
5
Co(er)
25
Qg
Qgs
Qgd
td(on)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Current Rise Time
Turn-Off Delay Time
Current Fall Time
43
8
V
= 0 to 10V, I = 3A,
GS
D
nC
ns
V
= 500V
DS
21
6.4
5.8
22
5.4
Resistive Switching
V = 667V, I = 3A
DD
tr
td(off)
tf
D
R
= 10Ω 6 , V
= 15V
GG
G
Source-Drain Diode Characteristics
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Continuous Source Current
(Body Diode)
D
S
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
IS
6
A
G
Pulsed Source Current
(Body Diode) 1
ISM
20
VSD
trr
I
= 3A, T = 25°C, V
= 0V
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
1.0
V
SD
J
GS
3
I
= 3A, V = 100V
DD
1025
17
ns
µC
SD
Qrr
diSD/dt = 100A/µs, T = 25°C
J
I
≤ 3A, di/dt ≤1000A/µs, V = 667V,
DD
SD
V/ns
dv/dt
Peak Recovery dv/dt
10
T = 125°C
J
1
2
3
Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
Starting at TJ = 25°C, L = 68.89mH, RG = 10Ω, IAS = 3A.
Pulse test: Pulse Width < 380µs, duty cycle < 2%.
4
5
Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS.
Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of
VDS less than V(BR)DSS, use this equation: Co(er) = -4.09E-8/VDS^2 + 7.21E-9/VDS + 1.40E-11.
6
RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452)
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
APT6M100K
6
5
4
3
2
1
0
16
14
12
10
8
V
= 10V
T
= 125°C
GS
J
TJ = -55°C
V
GS= 6, 7, 8 & 9V
TJ = 25°C
5V
6
4
TJ = 125°C
TJ = 150°C
4.5V
2
0
0
5
10
15
20
25
30
0
0
0
5
10
15
20
25
30
V
, DRAIN-TO-SOURCE VOLTAGE (V)
V
, DRAIN-TO-SOURCE VOLTAGE (V)
DS(ON)
DS
Figure 1, Output Characteristics
Figure 2, Output Characteristics
3.0
2.5
2.0
1.5
1.0
20
18
16
14
12
10
8
NORMALIZED TO
= 10V 3A
VDS> ID(ON)
x RDS(ON) MAX.
250µSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
V
@
GS
TJ = -55°C
TJ = 25°C
TJ = 125°C
6
4
0.5
0
2
0
-55 -25
0
25 50 75 100 125 150
1
2
3
4
5
6
7
8
T , JUNCTION TEMPERATURE (°C)
V
, GATE-TO-SOURCE VOLTAGE (V)
J
GS
Figure 3, R
vs Junction Temperature
Figure 4, Transfer Characteristics
DS(ON)
3,000
1,000
8
7
6
5
4
3
2
1
0
Ciss
TJ = -55°C
TJ = 25°C
100
TJ = 125°C
Coss
10
1
Crss
0
0.5
1.0 1.5
2.0 2.5
3.0 3.5
200
, DRAIN-TO-SOURCE VOLTAGE (V)
DS
400
600
800
1000
I , DRAIN CURRENT (A)
V
D
Figure 5, Gain vs Drain Current
Figure 6, Capacitance vs Drain-to-Source Voltage
16
14
12
10
8
20
I
= 3A
D
18
16
14
VDS = 200V
VDS = 500V
TJ = 25°C
12
10
TJ = 150°C
8
6
4
6
VDS = 800V
4
2
2
0
0
0
10
20
30
40
50
60
0
0.3
, SOURCE-TO-DRAIN VOLTAGE (V)
SD
0.6
0.9
1.2
1.5
Q , TOTAL GATE CHARGE (nC)
V
g
Figure 7, Gate Charge vs Gate-to-Source Voltage
Figure 8, Reverse Drain Current vs Source-to-Drain Voltage
APT6M100K
40
10
40
10
I
I
DM
DM
R
ds(on)
13µs
100µs
1ms
13µs
100µs
1
1
10ms
100ms
DC line
1ms
R
T
T
J = 150°C
C = 25°C
ds(on)
10ms
Scaling for Different Case & Junction
Temperatures:
100ms
T
T
J = 125°C
C = 75°C
I
D = ID(T = 25°C)*(T - TC)/125
DC line
J
C
0.1
0.1
1
10
100
1000
1
10
100
1000
V
, DRAIN-TO-SOURCE VOLTAGE (V)
V
, DRAIN-TO-SOURCE VOLTAGE (V)
DS
DS
Figure 9, Forward Safe Operating Area
Figure 10, Maximum Forward Safe Operating Area
TJ (°C)
TC (°C)
ZEXT are the external thermal
0.0654
0.231
0.266
impedances: Case to sink,
sink to ambient, etc. Set to
zero when modeling only
the case to junction.
Dissipated Power
(Watts)
0.0023
0.0057
0.0803
Figure 11, Transient Thermal Impedance Model
0.60
0.50
0.40
0.30
0.20
D = 0.9
0.7
0.5
0.3
Note:
t
1
t
2
t
= Pulse Duration
t
1
SINGLE PULSE
1
t
/
2
Duty Factor D =
0.10
0
0.1
Peak T = P
x Z
+ T
θJC C
J
DM
0.05
10-5
10-4
10-3
10-2
10-1
1.0
RECTANGULAR PULSE DURATION (seconds)
Figure 12. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
TO-220 (K) Package Outline
e3
100% Sn Plated
Drain
Gate
Drain
Source
Dimensions in Inches and (Millimeters)
Microsemi's products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786
5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 and foreign patents. US and Foreign patents pending. All Rights Reserved.
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