LE87251NQCT [MICROSEMI]
Line Driver, 1 Func, 1 Driver, 1 Rcvr, BIPolar, 4 X 4 MM, GREEN, QFN-16;
| 型号： | LE87251NQCT |
| 厂家： | 
Microsemi |
| 描述： | Line Driver, 1 Func, 1 Driver, 1 Rcvr, BIPolar, 4 X 4 MM, GREEN, QFN-16 驱动 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Le87251
Worldwide ADSL2+ Dual Channel
Line Driver BD870 Series
Data Sheet
June 2009
Features
Document Number
129739
•
•
•
Fixed Voltage Gain Of 13
450 mA Peak Output Drive Capability
Ordering Information
Le87251NQC16 pin QFN Green Pkg.Tray
Le87251NQCT16 pin QFN Green Pkg.Tape & Reel
±5 V to ±12 V Dual Supplies Or 10 V to 24 V
Single Supply
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of electrical
equipment.
•
•
•
•
•
•
•
44 Vp-p Differential Output Into a 100 Ω Load
40.5 Vp-p Differential Output Into a 60 Ω Load
Low-power Disable Mode For Each Driver
4 mA Per Amplifier Quiescent Supply Current
-75 dBc THD With 1 MHz Signal Into a 60 Ω load
16-pin (4 mm x 4 mm) QFN Package
RoHS Compliant
Logic
Control
VS+
ENAB
VS-
Logic
Control
ENCD
VINA
GND
+
–
Applications
VOUTA
VS+
A
•
•
Dual Port Full Rate ADSL2+ Line Drivers
HDSL Line Drivers
7.5k
7.5k
RF
50k
50k
VCMAB
RG
Description
RF
The Le87251 is a dual channel differential amplifier
designed to drive full rate ADSL2+ signals with very
low power dissipation. The Le87251 contains two pairs
of wide band amplifiers designed with Zarlink’s HV30
Bipolar SOI process for low power consumption in
DSL systems. The amplifiers have an internal fixed
gain, which helps to eliminate external feedback and
gain setting resistors.
VOUTB
VOUTC
VS-
B
VINB
VINC
+
–
VS+
C
7.5k
7.5k
RF
50k
50k
The drivers achieve better than -75 dB MTPR while
driving a 1 MHz, 16Vp_p signal into a 60 Ω load. The
amplifiers are enabled by forcing the ENAB/ENCD
pins to ground. Leaving the ENAB/ENCD pins floating
or forcing them high will disable the two amplifiers. The
ENAB and ENCD pins are pulled up to an internal
2.5 V through on-chip 50 kΩ resistors.
VCMCD
RG
RF
VS-
VOUTD
D
VIND
Le87251 device is one of the most cost-effective and
high performance line drivers for xDSL2+ applications.
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
Le87251
Data Sheet
Table of Contents
1.0 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Component Values for Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.3 Output Driving Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.4 Power Supplies and Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.5 Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Cable Termination Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Line Driver Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Package Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.0 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Version 1 to Version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Version 2 to Version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Zarlink Semiconductor Inc.
Le87251
Data Sheet
1.0 Pin Diagram
Top View
1
2
12
11
VOUTB
GND
VINA
VINB
GND
VINC
16-pin QFN
10
9
VOUTC
3
4
VOUTD
EXPOSED PAD
Notes:
1. Pin 1 is marked for orientation.
2. The Le87251 device incorporates an exposed die pad on the underside of its package. The pad acts as a heat sink and must be
connected to a copper plane through thermal vias, for proper heat dissipation.
1.1 Pin Description
Pin Name
Type
Description
Note
ENAB
ENCD
VINA
Input
Input
DSL channel #1 enable/disable control pin
DSL channel #2 enable/disable control pin
Amplifier A non-inverting input
Amplifier B non-inverting input
Amplifier C non-inverting input
Amplifier D non-inverting input
Bias voltage for amplifier A and B
Bias voltage for amplifier C and D
Positive power supply
Reference Circuit 1
Reference Circuit 1
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Input
VINB
Input
VINC
Input
VIND
Input
VCMAB
VCMCD
VS+
Input
Input
Power
Power
Ground
Output
Output
Output
Output
VS-
Negative power supply
GND
Ground connection
VOUTA
VOUTB
VOUTC
VOUTD
Amplifier A output
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Amplifier B output
Amplifier C output
Amplifier D output
Note 1: Amplifiers A and B comprise DSL channel #1. ENAB allows enable/disable control for DSL channel #1.
Note 2: Amplifiers C and D comprise DSL channel #2. ENCD allows enable/disable control for DSL channel #2.
Note 3: Reference circuits 1 and 2 are shown in Figure 2.
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Zarlink Semiconductor Inc.
Le87251
Data Sheet
2.5V
VS+
50K
150K
ENAB/CD
Reference circuit 1
GND
VS+
VINx
VOUTx
x = A, B, C,
Internal
Circuit
Reference circuit
2
D
VS-
Figure 2 - Reference Circuit
4
Zarlink Semiconductor Inc.
Le87251
Data Sheet
2.0 Applications
The Le87251 integrates two sets of high-power line driver amplifiers that can be connected for full duplex
differential line transmission. The amplifiers are designed to be used with signals up to 10 MHz with low signal
distortion. The driver can put out 20.5 dBm power level onto the telephone line and can drive 450 mA current, which
exceeds the level required when using a transformer with 1:2 ratio.
2.1 Typical Application Circuit
A typical application interface circuit (one channel) is shown in Figure 3.
ROUT
CTX
VINA
+
–
TX+
VOUTA
RF
100
2RG
RF
ROUT
CTX
VOUTB
VINB
TX-
RF
RX1
–
RX+
RX-
+
RX2
RX1
RF
RX2
Data Receive
Figure 3 - Typical Application Interface Circuit
As shown in Figure 3 the amplifiers have identical positive gain connections with common-mode rejection. Any DC
input errors are duplicated and create common-mode rather than differential line errors.
5
Zarlink Semiconductor Inc.
Le87251
Data Sheet
2.1.1 Component Values for Typical Application
Item
Quantity
Type
Value
49.9
0.22 µF
Tolerance
Rating
ROUT
CTX
2
2
SMT
X7R
Ω
1%
1/16 W
50V
10%
Table 1 - Parts List for Typical Application Circuit
2.1.2 Input Considerations
The driving source impedance should be less than 100 nH to avoid any ringing or oscillation. This inductance is
equivalent to about 4" of unshielded wiring, or 6" of unterminated transmission line. Normal high-frequency
construction obviates any such problem.
2.1.3 Output Driving Considerations
While the drive amplifiers can output in excess of 450 mA peak, the internal metallization is not designed to carry
more than 100 mA of steady DC current and there is no current limit mechanism. The device can safely drive
sinusoidal currents of 2 x 100 mArms, or 200 mArms. This current is more than that required to drive line
impedance to large output levels, but output short circuits can not be tolerated. The series output resistor will
usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is not
recommended.
The amplifiers are sensitive to capacitive loading. More than 100pF may cause peaking of the frequency response.
The same is true of badly terminated lines connected without a series matching resistor.
When in power down mode, several volts of differential voltage may appear across the line driver outputs. If a DC
current path exists between the two outputs, a large DC current can flow from the positive supply rail to the negative
supply rail through the outputs. To avoid DC current flow, the most effective solution is to place DC blocking
capacitors in series at the output, as shown in the typical application circuit.
2.1.4 Power Supplies and Component Placement
The power supplies should be well bypassed close to the Le87251 device. A 2.2 µF tantalum capacitor and a 0.1 µF
ceramic capacitor for each supply is recommended. The ground terminal of the positive and negative bypass
capacitors should be connected to each other directly and then returned to circuit ground to prevent ground current
loops.
The Le87251 can also be powered from a single positive voltage supply. When operating in this mode, the VS+ pin
is connected to the positive supply. The VS- pin is connected to GND.
2.1.5 Stability
The Le87251 features improved frequency compensation for all applications, allowing stable operation at very low
power levels and eliminating any need for external “snubber” circuit. Differential circuits, such as ADSL line driver
applications, can be especially prone to common-mode oscillation. The Le87251 is specifically compensated to
eliminate this type of instability and allows for reliable operation even at very low power levels.
2.2 Cable Termination Technique
There are various techniques available. Figure 4 shows a passive termination technique. Figure 5 shows an active
termination technique. A quick comparison of the reduction in voltage and power requirements for the driver with
passive or active termination is shown in Table 2.
6
Zarlink Semiconductor Inc.
Le87251
Data Sheet
The output impedance and the voltage gain of the circuit in Figure 5 are shown in the following equations.
Z
OUT = K • RBM
V
O
RD( P2)
------------------------ ---- --------------
---------
--- ---
2(RD(G) – RD(P1))
=
V
IN
where
ZOUT is the output impedance.
1
-----------------------------
K =
RD( P1)
------------ ----
1 –
RD(G)
And the resistor dividers are defined as following
RP1
--------------
--------
-----
-
-
RD(P1) =
RD(P2) =
RD(G) =
RP1 + RP2
RP2
---------------------------
-
-
RP1 + RP2
RG
----------------------
RG + RF
And VO/VIN represents the voltage gain.
RG
RF
RBM
ZL
VO
VIN
RL
Figure 4 - Passive Termination Technique
RG
RF
RBM
ZL
VO
RP1
RP2
RL
VIN
Figure 5 - Active Termination Technique
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Zarlink Semiconductor Inc.
Le87251
Data Sheet
Passive Termination
16.5 VP-P into a 100 Ω line
VOUT DRIVER = VRBM + VRLOAD
RBM = RLOAD
Active Termination
16.5 VP-P into a 100 Ω line
VOUT DRIVER = VRBM + VRLOAD
RBM = RLOAD/5
VRBM = VRLOAD
VRBM = VRLOAD/5
VOUT DRIVER = 33.52 V
VSUPPLY = 37.52 V
IOUT = 31.6 mA
VOUT DRIVER = 20.11 V
VSUPPLY = 24.11 V
IOUT = 31.6 mA
POUT DRIVER = VSUPPLY * IOUT = 0.714 W
(plus quiescent power)
POUT DRIVER = VSUPPLY * IOUT = 1.185 W (plus
quiescent power)
Table 2 - Passive and Active Termination Comparison
2.3 Line Driver Protection
High voltage transients such as lightning can appear on the telephone lines. Transient protection devices should be
used to absorb the transient energy and clamp the transient voltages. However, large transient voltages can still
couple to the primary side of the transformer. As shown in Reference Circuit 2, the outputs of the Le87251
incorporate on-chip circuitry that clamps the output voltage to no more than a diode drop beyond either rail. No
external diodes immediately at the output of the amplifiers are required. As shown in Figure 6, the series output
termination resistors limit the current going into the line driver and internal clamps, thus these termination resistors
should be specified at 0.5 W. The actual protection scheme may vary depending on the type of data transformer
used and the line protection components used in the front of the data transformer.
RBM
VIN+
0.5W
RF
Subscriber
Line
2RG
RF
RBM
VIN-
0.5W
Figure 6 - Line Driver Protection
A large DC voltage can develop between the line driver outputs during system turn-on when the AFE has not been
reset or when the line driver is disabled. Figure 6 shows an AC coupling capacitor between the two line driver
outputs. This AC coupling capacitor prevents large DC current from flowing from one output of the line driver to
another.
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Zarlink Semiconductor Inc.
Le87251
Data Sheet
3.0 Absolute Maximum Ratings
Stresses above the values listed under Absolute Maximum Ratings can cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods
can affect device reliability.
Storage Temperature
−65 ≤ TA ≤ +150°C
−40 ≤ TA ≤ +85°C
−40 ≤ TA ≤ +150°C
Operating Ambient Temperature
Operating Junction Temperature
(See Notes 1 and 2)
VS+ to VS- Supply Voltage
−0.3 V to 30 V
−0.3 V to 30 V
−30 V to +0.3 V
VS- to VS+
VS+ with respect to GND
VS- with respect to GND
Driver inputs VINA/B/C/D
Control inputs ENAB/ENCD with respect to GND
Maximum current on any input
−0.3 V to 6 V
10 mA
Maximum current at amplifier output (DC continuous)
ESD Immunity (Human Body Model)
ESD Immunity (Charge Device Model)
100 mA
JESD22 Class 2 compliant
JESD22 Class IV compliant
Note: Continuous operation above 145°C junction temperature may degrade device reliability.
3.1 Thermal Resistance
The thermal performance of a thermally enhanced package is assured through optimized printed circuit
board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized
exposed copper surface, which, in turn, conducts heat through multiple vias to larger internal copper
planes.Please refer to the QFN Package application note, available from http://www.zarlink.com, for layout and
heat sinking guidelines.
3.2 Package Assembly
The green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and
antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board
assembly processes or newer lead-free board assembly processes.
Refer to IPC/JEDEC J-Std-020 Table 4-2 for recommended peak soldering temperature and Table 5-2 for the
recommended solder reflow temperature profile.
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Zarlink Semiconductor Inc.
Le87251
Data Sheet
4.0 Operating Ranges
Zarlink guarantees the performance of this device over commercial (0°C to 70°C) and industrial (−40°C to 85°C)
temperature ranges by conducting electrical characterization over each range and by conducting a single insertion
production test coupled with periodic sampling. These characterization and test procedures comply with section
4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications
Equipment.
Ambient temperature
-40°C to +85°C
+12 V ± 5%
-12 V ± 5%
VS+ with respect to GND
VS- with respect to GND
Single battery operation, VS+ with respect to GND (VS- to GND)
+24V ± 5%
5.0 Device Specifications
Typical Conditions: VS = ±12V, RL = 65Ω, unless otherwise specified, TA = 25°C.
Min/Max Parameters: TA = −40 to +85°C
Amplifiers are tested separately.
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Supply Current Characteristics
IS+ (Full IS)
IS- (Full IS)
Positive Supply Current
per Amplifier
All outputs at 0V, ENAB = ENCD = 0V
All outputs at 0V, ENAB = ENCD = 0V
All outputs at 0V, ENAB = ENCD = 5V
All outputs at 0V, ENAB = ENCD = 5V
All outputs at 0V
3.75
-5.1
4.0
-3.8
0.2
5.3
-3.0
0.4
mA
mA
mA
mA
mA
Negative Supply
Current per Amplifier
IS+ (power down) Positive Supply Current
per Amplifier
IS- (power down)
Negative Supply
Current per Amplifier
-0.3
1.6
0.1
IGND
GND Supply Current
per Amplifier
0.25
Control Input (C0 and C1) Characteristics
VIH
VIL
IIH
IIL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
ENAB and ENCD inputs
ENAB and ENCD inputs
ENAB = ENCD = 5V
ENAB = ENCD = 0V
V
V
0.8
40
5
20
µA
µA
-85
-50
-30
Amplifier Input (VINx+ and VINx-) Characteristics
VOS
Input Offset Voltage
VOS mismatch
Input Bias Current
IB Mismatch
-10
-5
0
0
10
5
mV
mV
µA
ΔVOS
IB
-15
-25
14
25
ΔIB
0
µA
VCM
Driver common mode
voltage
|VS+| +
|VS-|
pins VCMAB/CD floating, reference to VS- 0.475
0.5
0.525
1
ROL
5
MΩ
Transimpedance
Table 3 - Electrical Specifications
10
Zarlink Semiconductor Inc.
Le87251
Data Sheet
Parameter
Description
Input Noise Voltage
Input Noise Current
Condition
Min.
Typ.
3.5
13
Max.
Unit
eN
iN
1
1
nV/ Hz
pA/ Hz
Amplifier Output (VOUT) Characteristics
VOUT
±11.
1
RL = 100
Ω
±10.3
10.1
V
Loaded Output Swing
(RL Single-ended to
GND)
RL = 30 Ω (+)
10.7
V
V
RL = 30 Ω (−)
-10.5 -10.1
600
1
IOUT
VOUT = 0.6 V, RL = 1
Ω
mA
Output Current
Amplifier Dynamic Characteristics
THD
Total Harmonic
Distortion
f = 1 MHz, RL = 50 Ω, VOUT = 16 Vpp
-75
-70
dBc
dBc
MTPR
26 kHz to 1.1 MHz, RL = 100
PLINE =20.4 dBm
Ω,
Multi-Tone Power Ratio
Slew rate
SR
AV
VOUT from -8 V to +8 V measured at ±4 V
VOUT = 16 Vpp, RL = 100
200
400
V/µs
V/V
1
(single-ended)
Voltage Gain
Ω
12.9
13.0
13.1
Note 1: This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 3 - Electrical Specifications
1
1
Le87251
Data Sheet
6.0 Physical Dimensions
6.1 16-Pin QFN
GIFN 16L 4x4
0.10 CAB
PIN 1 AREA
0.10
c
c
16X
c:::r. 0.08
SEATING PLANE
.0.
30±0 05
16X
1-$-IO.!O@ICIAIB
IO.o5@ICI -·
-t--
/
I
\ \,
\
I
i
fr ----
_/
If)
'-.. ----
ru
If)
' "'
ci
40±0.05
0.
ci
' "'
DETAIL
A <SCALE 3•D
NOTES:
1. DIMENSIONING AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5-1994
ALl.. DIMENSIONS ARE IN MIWMETERS
" IN DEGREES
12
Zarlink Semiconductor Inc.
Le87251
Data Sheet
7.0 Revision History
7.1 Version 1 to Version 2
•
•
Document is changed from “Preliminary Data Sheet” to “Data Sheet”.
Added a note in Table 3 on page 10 and 11.
7.2 Version 2 to Version 3
•
Updated the Absolute Maximum Rating table on page 9.
13
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively
“Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the
application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may
result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under
patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified
that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property
rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
2
2
2
Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided that the system
2
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