LE9500DBJC [MICROSEMI]
SLIC, PQCC28, GREEN, PLASTIC, MS-018AB, LCC-28;
| 型号： | LE9500DBJC |
| 厂家： | 
Microsemi |
| 描述： | SLIC, PQCC28, GREEN, PLASTIC, MS-018AB, LCC-28 电信 电信集成电路 |
| 文件： | 总25页 (文件大小：779K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Le9500
High-Voltage Ringing SLIC Device for VolP Applications
VE950 Series
ORDERING INFORMATION
APPLICATIONS
Interface to Broadcom:
Device
Le9500ABJC
Le9500BBJC
Le9500CBJC
Package Type1
Packing2
— BCM3367/3368 cable modem
— BCM3341/3351/3352 cable modem
— BCM6352 integrated multimedia adaptor
— BCM1101 residential gateway
28-Pin PLCC, -75V (Green)
28-Pin PLCC, -85V (Green)
28-Pin PLCC, -100V (Green)
Tube
28-Pin PLCC, -100V
operation / -145V ringing
(Green)
Cable modems
Le9500DBJC
Voice over Internet Protocol (VoIP)
Voice over DSL
Remote subscriber units
Broadband wireless
Short-loop access
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2. For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
FEATURES
Differential ringing and codec interface
Single-ended application also supported
On-board ringing generation
— 15 to 70 Hz ring frequency supported
Three ringing options:
DESCRIPTION
The Zarlink Le9500 device, part of the VE950 series, is a
subscriber line interface circuit (SLIC) that is optimized for
short-loop, power-sensitive applications. This device provides
the complete set of line interface functionality (including power
ringing) needed to interface to a subscriber loop while
providing ultra low power dissipation. The Le9500 SLIC device
is capable of operating with a VCC supply of 3.3 V, and is
designed to minimize external components required at all
device interfaces. The differential ringing and receive inputs
make the device ideal for direct interface to Data Over Cable
Service Interface Specification (DOCSIS) compliant cable
modem gateways, to multimedia adaptors, and to residential
gateway products, such as the Broadcom® BCM3367/3368,
BCM3341/3351/3352, BCM6353, BCM1101 and equivalent
products.
— Sine wave input - sine wave output
— PWM input - sine wave output
— Square wave input - trapezoidal output
Flexible power supply options:
— VBAT2 for active talking
— VBAT1 for ringing, scan, and so on
— 3.3 V for VCC
Battery switch to minimize off-hook power
Eight operating states:
— Scan
— Forward and reverse battery active
— Forward and reverse battery on-hook transmission
— Ground start
— Ring
— Disconnect
BLOCK DIAGRAM
AGND
V
CC
BGND
V
BAT2
VBAT1
VPROG
V
REF
NSTAT
RTFLT DCOUT
Ultra-low on-hook power:
— 29 mW scan state
CURRENT
LIMIT
GAIN = 20
RING
TRIP
AND
POWER
1.5 V
— 38 mW active state
INRUSH
CONTROL
AAC
VITR
TXI
Loop start, ring trip, and ground start detection
— Fixed off hook threshold with hysteresis
— Fixed ground start threshold with hysteresis
— Fixed ring-trip threshold as a function of battery voltage
Software-controllable dual-current limit option
— 25 mA or 40mA via ground or open control input
UL1950 Compatible
LOOP
CLOSURE
BAND-GAP
REFERENCE
RECTIFIER
X1
+
–
FB2
CF2
AX
VTX
ITR
(ITR/306)
–
+
RFT
PT
AT
18
Ω
X1
CF1
FB1
— When not in ringing, |VTIP| and |VRING| are clamped to
be less than 56.5 V
TIP/RING
CURRENT
SENSE
+
–
RCVP
RCVN
+
–
RFR
Thermal shutdown protection with hysteresis
PR
AR
AC
GAIN = 4
18
Ω
28-pin PLCC package
HV7 Technology
PARALLEL
RINGING
GAIN = 65
DATA
INTERFACE
B0 B1 B2
RINGINP
RINGINN
Document ID# 081189 Date:
Sep 17, 2007
2
Rev:
G
Version:
Distribution:
Public Document
Le9500
Data Sheet
TABLE OF CONTENTS
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating State Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Loop Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Overhead Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Loop Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Battery Reversal Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision F1 to F2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision F2 to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision G1 to G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2
Zarlink Semiconductor Inc.
Le9500
Data Sheet
PRODUCT DESCRIPTION
The Le9500 device is optimized to provide battery feed, ringing, and supervision on short Plain Old Telephone Service (POTS)
loops. This device provides power ringing to the subscriber loop through amplification of a low-voltage input. It also provides
forward and reverse battery feed states, on-hook transmission, a low-power scan state, ground start (tip open), and a forward
disconnect state.
The Le9500 device requires a 3.3V VCC and battery to operate eight operating states. A battery switch is included to allow for
use of a lower-voltage battery in the off-hook condition, thus minimizing short-loop off-hook power.
The following two batteries are used:
1. A high-voltage operation and ringing battery (VBAT1):
VBAT1 is used for scan, on-hook transmission, ground start, and power ringing. It can be a maximum of –75 V for Le9500A,
–85 V for Le9500B, or –100V for Le9500C and Le9500D.
For Le9500D during ringing only this voltage may be extended to –145 V. The supply has to be externally adjustable. It has
to be adjusted back to no more than -100 V for other operation states. Further, when –145 V is used for ringing special care
should be applied to prevent certain faults from happening such as tip to ring, tip or ring to ground.
2. A lower-voltage talk battery (VBAT2):
VBAT2 is used for active state powering.
Loop closure, ring trip, and ground start detection is available. The loop closure detector has fixed threshold with hysteresis. The
ring trip detector requires a single-pole filter, thus minimizing external components required. The ring trip threshold at a given
battery voltage is fixed and with hysteresis. Ground start detection also has fixed threshold with hysteresis.
The DC current limit is set and fixed by a logic-controllable pin. Ground or open applied to this pin sets the current limit at the low
or high value.
This device is designed for ultra-low power in all operating states.
Forward and reverse battery active states are used for off-hook conditions. Since this device is designed for short-loop
applications, the lower-voltage VBAT2 is applied during the forward and reverse active states. Battery reversal is quiet, without
breaking the AC path. Rate of battery reversal may be ramped to control switching time.
The magnitude of the overhead voltage in the forward and reverse active states has a typical default value of 7.2 V, allowing for
an on-hook transmission of an undistorted signal of 3.14 dBm into 900 Ω. Additionally, this allows sufficient overhead for 500 mV
of meter pulse if desired. This overhead is fixed. The ring trip detector is turned off during active states to conserve power.
Because on-hook transmission is not allowed in the scan state, an on-hook transmission state is defined. This state is functionally
similar to the active state, except the tip ring voltage is derived from the higher VBAT1 rather than VBAT2.
In the on-hook transmission states with a primary battery whose magnitude is greater than a nominal 56.5 V, the magnitude of
the tip-to-ground and ring-to-ground voltage is clamped at less than 56.5 V.
To minimize on-hook power, a low-power scan state is available. In this state, all functions except off-hook supervision are turned
off to conserve power. On-hook transmission is not allowed in the scan state.
In the scan state with a primary battery whose magnitude is greater than a nominal 56.5 V, the magnitude of the tip-to-ground
and ring-to-ground voltage is clamped at less than 56.5 V.
A forward disconnect state is provided, where all circuits are turned off and power is denied to the loop.
The device offers a ring state, in which a power ring signal is provided to the tip/ring pair. During the ring state, user-supplied low-
voltage ring signals are input to the device’s RINGINP/N inputs. The input signals can be differential or single-ended, and can
either or both include certain DC offset. Both inputs should reference to Vref. The two signals are amplified to produce the power
ring signal. The input signal or signals may be a sine wave or filtered square wave to produce a sine wave or trapezoidal output.
The Ring Trip detector is active during the ring state. The flexibility makes the device ideal to directly interface to DOCSIS
compliant cable modem gateway products.
This feature eliminates the need for a separate external ring relay, associated external circuitry, and a bulk ringing generator.
The device offers a ground start state. In this state, the tip drive amplifier is turned off. The device presents a high impedance
(>100 kΩ) to PT and a current-limited battery (VBAT1) to PR. The voltage on PR is clamped to be less than 56.5 V in magnitude.
The NSTAT loop current detector is used for ring ground detection. In the ground start state, since the loop current is common
state, the loop closure threshold is reduced in half, thus maintaining loop supervision at specified levels.
Upon reaching the thermal shutdown temperature, the device will enter an all off state. Upon cooling, the device will re-enter the
state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation.
Data control is via a parallel unlatched control scheme.
Circuitry is added to the Le9500 device to minimize the inrush of current from the VCC supply and to the battery supply during an
on- to off-hook transition, thus saving in power supply design cost.
3
Zarlink Semiconductor Inc.
Le9500
Data Sheet
The Le9500 device uses a voltage feed-current sense architecture. The transmit gain is a transimpedance. The Le9500 device
transimpedance is set via a single external resistor, and this device is designed for optimal performance with a transimpedance
set at 300 V/A. This interface is single ended. The Le9500 device offers a differential receive interface with a gain of 8.
The Le9500 device is internally referenced to 1.5 V. This reference voltage is output at the VREF pin of the device. The VITR output
is also referenced to 1.5 V. The RCVP/RCVN receive inputs are floating inputs.
The Le9500 device is available in a 28-pin PLCC package.
CONNECTION DIAGRAM
Figure 1. Le9500 28-Pin PLCC Connection Diagram
4
3
2
1
28
27
26
RINGINN
RINGINP
DCOUT
CF2
5
25
24
23
22
21
20
19
B0
6
B1
7
B2
8
PR
PT
28-PIN PLCC
CF1
9
RTFLT
10
11
FB1
FB2
VREF
12
13
14
15
16
17
18
4
Zarlink Semiconductor Inc.
Le9500
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
Loop Closure Detector Output—Ring Trip Detector Output. When Low, this logic output indicates that
NSTAT
Output
an off-hook condition exists or ringing is tripped or a ring ground has occurred.
Transmit AC Output Voltage. Output of internal AAC amplifier. This output is a voltage that is directly
VITR
RCVP
RCVN
Output
Input
proportional to the differential AC tip/ring current.
Receive AC Signal Input (Non inverting). This high-impedance input controls to AC differential voltage
on tip and ring. This node is a floating input.
Receive AC Signal Input (Inverting). This high-impedance input controls to AC differential voltage on tip
Input
and ring. This node is a floating input.
Power Ring Signal Input. Couple to a sine wave or lower crest factor low-voltage ring signal. The input
here is amplified to provide the full power ring signal at tip and ring. This signal may be applied
continuously, even during nonringing states.
RINGINN
Input
Power Ring Signal Input. Couple to a sine wave or lower crest factor low-voltage ring signal. The input
here is amplified to provide the full power ring signal at tip and ring. This signal may be applied
continuously, even during nonringing states.
RINGINP
DCOUT
Input
DC Output Voltage. This output is a voltage that is directly proportional to the absolute value of the
Output
differential tip/ring current. This is used to set ring trip threshold.
CF2
CF1
—
—
Filter Capacitor. Connect a capacitor from this node to ground.
Filter Capacitor. Connect a capacitor from this node to CF2.
Ring Trip Filter. Connect this lead to DCOUT via a resistor and to AGND with a capacitor to filter the ring
RTFLT
—
trip circuit to prevent spurious responses. A single-pole filter is needed.
VREF
AGND
VCC
VBAT1
VBAT2
BGND
NC
Output SLIC Device Internal Reference Voltage. Output of internal 1.5 V reference voltage.
Ground Analog Signal Ground.
Power
Power
Power
Analog Power Supply. 3.3 V typical.
Battery Supply 1. High-voltage battery.
Battery Supply 2. Lower-voltage battery.
Ground Battery Ground. Ground return for the battery supplies.
—
No Connection.
Current-Limit Program Input. Connect this pin to ground to set current limit to 25 mA; leave this pin open
VPROG
FB2
FB1
PT
Input
to set current limit to 40 mA.
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node for controlling rate of battery
—
—
reversal. If ramped battery reversal is not desired, leave this pin floating.
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node for controlling rate of battery
reversal. If ramped battery reversal is not desired, leave this pin floating.
Protected Tip. The output drive of the tip amplifier and input to the loop-sensing circuit. Connect to loop
I/O
I/O
through overvoltage and overcurrent protection.
Protected Ring. The output drive of the ring amplifier and input to the loop sensing circuit. Connect to
PR
loop through overvoltage and overcurrent protection.
B2
B1
B0
Input
Input
Input
State Control Input. These pins have an internal 150 kΩ pull-up.
State Control Input. These pins have an internal 150 kΩ pull-up.
State Control Input. These pins have an internal 150 kΩ pull-up.
Transmit Gain. Input to AX amplifier. Connect a 4.75 kΩ resistor from this node to VTX to set transmit
gain. Gain shaping for termination impedance with a first-generation codec is also achieved with a network
from this node to VTX.
ITR
Input
AC Output Voltage. Output of internal AX amplifier. The voltage at this pin is directly proportional to the
VTX
TXI
Output
Input
differential tip/ring current.
AC/DC Separation. Input to internal AAC amplifier. Connect a capacitor from this pin to VTX.
5
Zarlink Semiconductor Inc.
Le9500
Data Sheet
ABSOLUTE MAXIMUM RATINGS
(at TA = 25 °C)
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Parameter
Symbol
VCC
Min
–0.5
Max
4.0
Unit
V
DC Supply (VCC)
Battery Supply (VBAT1) (Le9500A)
Battery Supply (VBAT1) (Le9500B)
Battery Supply (VBAT1) (Le9500C)
Battery Supply (VBAT1) (Le9500D Non-Ringing)
Battery Supply (VBAT1) (Le9500D Ringing)
Battery Supply (VBAT2)
VBAT1
VBAT1
VBAT1
VBAT1
VBAT1
VBAT2
—
BGND
BGND
BGND
BGND
BGND
BGND
–0.5
–80
–90
–110
–110
V
V
V
V
V
V
V
–155 + VCC
VBAT1
VCC + 0.5
Logic Input Voltage
Logic Output Voltage
—
–0.5
VCC + 0.5
V
Operating Temperature Range
Storage Temperature Range
Relative Humidity Range
—
—
—
–40
–40
5
125
150
95
3
15
±1
°C
°C
%
V
V
V
PT or PR Fault Voltage (DC)
VPT, VPR
VPT, VPR
—
VBAT1 – 5
VBAT1 – 15
—
PT or PR Fault Voltage (10 x 1000 µs)
Ground Potential Difference (BGND to AGND)
ESD Immunity (Human Body Model)
—
—
JESD22 Class 1C compliant
Note: Continuous operation above 145ºC junction temperature may degrade device reliability.
Package Assembly
Green package devices are assembled with enhanced environmental compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-
free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Environmental Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment.
–40° C < TA < +85° C
Ambient Temperature
Ambient Relative Humidity
5 to 95%
Electrical Ranges
Parameter
3.3 V DC Supplies (VCC)
High Office Battery Supply (VBAT1) (Le9500A)
High Office Battery Supply (VBAT1) (Le9500B)
High Office Battery Supply (VBAT1) (Le9500C)
High Office Battery Supply (VBAT1) (Le9500D)
Min
Typ
3.3
–
–
–
Max
3.47
–75
–85
–100
–100
Unit
V
V
V
V
3.13
–60
–60
–60
–60
–
V
High Office Battery Supply (VBAT1) (Le9500D)
(during ringing only)
–60
–
–145
V
VBAT1
(|VBAT1|<=100)
Auxiliary Office Battery Supply (VBAT2)
–12
–
V
6
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Thermal Characteristics
Parameter
Min
Typ
Max
Unit
Thermal Protection Shutdown (Tjc)1
175
190
—
°C
28 PLCC Thermal Resistance Junction to Ambient (θJA)1, 2
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
:
°C/W
°C/W
°C/W
°C/W
—
—
—
—
35.5
50.5
31.5
42.5
—
—
—
—
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
ELECTRICAL CHARACTERISTICS
Supply Currents
Unless otherwise specified, VBAT1 = –75 V for Le9500A; VBAT1 = –85 V for Le9500B; VBAT1 = –100 V for Le9500C and Le9500D;
VBAT2 = –21 V, Vcc = 3.3 V.
Parameter
Scan state; no loop current:
Min
Typ
Max
Unit
IVCC
IVBAT1
IVBAT2
—
—
—
3.2
0.25
1
4.4
0.44
6
mA
mA
µA
Forward/reverse active; no loop current, with or without
PPM, VBAT2 applied:
IVCC
IVBAT1
IVBAT2
—
—
—
4.6
23
1.0
5.8
85
1.4
mA
µA
mA
On-hook transmission state; no loop current, with or without
PPM, VBAT1 applied:
IVCC
IVBAT1
IVBAT2
—
—
—
6.2
1.9
6
mA
mA
µA
4.7
1.4
1
Disconnect state:
IVCC
IVBAT1
—
—
—
1.8
0
1
2.8
110
25
mA
µA
µA
IVBAT2
Ground start state, no loop current:
IVCC
IVBAT1
IVBAT2
—
—
—
3.2
0.25
1
—
—
—
mA
mA
µA
Ring state; no load (VBAT1= –145V for Le9500D):
IVCC
IVBAT1
IVBAT2
—
—
—
4.9
2
1
6.5
2.8
6
mA
mA
µA
7
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Power Dissipation
VBAT2 = –21V, VCC=3.3V.
Parameter
Min
Typ
Max
Unit
Le9500A (VBAT1 = −75 V)
Scan state; no loop current
—
29
38
111
6
29
150
45
53
151
15
—
200
Forward/reverse active; no loop current, VBAT2 applied
On-hook transmission state; no loop current, VBAT1 applied
Disconnect state
Ground start state
Ring state; no load
—
—
—
—
—
mW
mW
mW
mW
Le9500B (VBAT1 = −85 V)
Scan state; no loop current
—
32
38
127
6
32
171
50
54
182
17
—
235
Forward/reverse active; no loop current, VBAT2 applied
On-hook transmission state; no loop current, VBAT1 applied
Disconnect state
—
—
—
—
—
Ground start state
Ring state; no load
Le9500C (VBAT1 = −100 V)
Scan state; no loop current
—
36
38
154
6
35
204
58
56
215
20
—
280
Forward/reverse active; no loop current, VBAT2 applied
On-hook transmission state; no loop current, VBAT1 applied
Disconnect state
—
—
—
—
—
Ground start state
Ring state; no load
Le9500D (VBAT1 = −100 V; VBAT1 = −145 V during ringing only)
Scan state; no loop current
—
—
—
—
—
—
36
38
154
6
58
56
215
20
Forward/reverse active; no loop current, VBAT2 applied
On-hook transmission state; no loop current, VBAT1 applied
Disconnect state
Ground start state
Ring state; no load1
35
—
324
435
1. Tested at -100 V VBAT1 in production with proportioned limits
8
Zarlink Semiconductor Inc.
Le9500
Data Sheet
LINE CHARACTERISTICS
Unless otherwise specified, the test conditions are as specified in Figure 2, on page 14.
Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are for information
purposes only and are not a part of the testing requirements. Minimum and maximum values apply across the operating
temperature range and the entire battery range unless otherwise specified. Typical is defined as TA=25º C. Vcc = 3.3 V, VBAT2 =
–24 V, VBAT1 = –60 V for Scan/OHT/Ground Start/Disconnect states, –75 V/–85 V/ –100 V/–145 V for Ringing state of Le9500A/
B/C/D.
Table 1. Two-Wire Port
Parameter
Min
105
65
Typ
—
Max
—
Unit
Tip or Ring Drive Current = DC + Longitudinal + Signal Currents1
Tip or Ring Drive Current = Ringing + Longitudinal1
mApk
—
—
Signal Current1
10
—
—
Longitudinal Current Capability per Wire (Longitudinal current is
8.5
29
15
—
—
—
mArms
mA
independent of DC loop current.)1
Ringing Current (RLOAD = 1386 Ω + 40 µF)1
DC Loop Current Limit – ILIM (VBAT2 applied, RLOOP = 100 Ω):
VPROG = AGND
—
—
25
40
—
—
VPROG = Open
DC Current Limit Variation
DC Feed Resistance (does not include protection resistors)
Open Loop Voltages:
—
—
—
40
±8
—
%
Ω
Scan state:
|VBAT1| > 51 V |VTIP| – |VRING|
|VTIP|, |VRING| to Battery Ground
OHT state:
44
—
51
—
—
56.5
|VBAT1| > 51 V |VTIP| – |VRING|
|VTIP|, |VRING| to Battery Ground
Active state:
41
—
49
—
—
56.5
V
|VTIP – VRING| – |VBAT2|
Ring state:
|VTIP – VRING| – |VBAT1|
5.75
—
7.2
4
8.5
—
Loop Closure Threshold:
Scan/Active/On-hook Transmission states, On– to Off–hook
Loop Closure Threshold Hysteresis:
Scan/Active/On-hook Transmission states
9.4
—
11.0
3.0
12.6
—
mA
mA
Longitudinal to Metallic Balance at PT/PR2:
Test Method: Q552 (11/96) Section 2.1.2 and IEEE ® 455:
300 Hz to 600 Hz
600 Hz to 3.4 kHz
dB
52
52
—
—
—
—
Metallic to Longitudinal (HARM) Balance3:
200 Hz to 1000 Hz
100 Hz to 4000 Hz
PSRR 500 Hz – 3000 Hz1:
VBAT1, VBAT2
VCC
40
40
—
—
—
—
dB
dB
45
25
—
30
—
—
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Tested at 1KHz in production.
3. DC test only.
9
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Table 2. Analog Pin Characteristics
Parameter
TXI (input impedance)
Min
—
Typ
100
Max
—
Unit
kΩ
Output Offset (VTX)
—
—
—
—
—
—
±10
100
—
mV
mV
µA
Output Offset (VITR)
Output Drive Current (VTX)
±300
±10
Output Drive Current (VITR)
—
µA
Output Voltage Swing:
Maximum (VTX, VITR)
Minimum (VTX)
AGND
—
—
—
—
—
20
VCC
VCC – 0.5
VCC – 0.4
±50
V
V
V
mA
kΩ
pF
AGND + 0.25
Minimum (VITR)
AGND + 0.35
—
10
—
Output Short-circuit Current
Output Load Resistance1
Output Load Capacitance1
—
—
RCVN and RCVP:
Input Voltage Range
Input Bias Current
0
—
—
0.12
VCC – 0.3
—
V
µA
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
Offset Voltage at ILOOP = 0
—
–15
15
—
—
15
V/A
mV
AC Termination Impedance2
150
600
1400
Ω
Total Harmonic Distortion (200 Hz – 4 kHz)1:
Off-hook
On-hook
—
—
—
—
0.3
1.0
%
%
Transmit Gain (f = 1004 Hz, 1020 Hz)3:
291
300
8
309
V/A
—
PT/PR Current to VITR
Receive Gain, f = 1004 Hz, 1020 Hz Open Loop
RCVP or RCVN to PT – PR
7.76
8.24
Gain vs. Frequency (transmit and receive)1,
600 Ω Termination, 1004 Hz, 1020 Hz Reference:
–0.3
–0.05
–3.0
—
0
0
0.05
0.05
0.05
2.0
200 Hz to 300 Hz
300 Hz to 3.4 kHz
3.4 kHz to 20 kHz
20 kHz to 266 kHz
dB
dB
0
—
Gain vs. Level (transmit and receive)1, 0 dBV Reference:
–55 dB to +3.0 dB
–0.05
0
0.05
Idle-channel Noise (tip/ring), 600 Ω Termination:
C-Message
—
—
—
8
–82
—
13
–77
20
dBmC
dBrnp
dBrn
Psophometric1
3 kHz Flat1
Idle-channel Noise (VTX), 600 Ω Termination:
C-Message
—
—
—
8
–82
—
13
–77
20
dBmC
dBrnp
dBrn
Psophometric1
3 kHz Flat1
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance
R1 + R2 || C between 150 Ω and 1400 Ω can be synthesized.
3. VITR transconductance depends on the resistor from ITR to VITR. This gain assumes an ideal 4.75 kΩ, (the
recommended value). Positive current is defined as the differential current flowing from PT to PR.
10
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Table 3. Logic Inputs and Outputs
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
VIL
VIH
–0.5
2.0
0.2
2.5
0.5
VCC
V
Input Current:
IIL
IIH
Low Level (VCC = 3.46 V, VI = 0.4 V)
High Level (VCC = 3.46 V, VI = 2.4 V)
—
—
—
—
±50
±50
µA
V
Output Voltages (open collector with internal 60 kΩ pull-up resistor):
Low Level (VCC = 3.13 V, IOL = 360 µA)
High Level (VCC = 3.13 V, IOH = –5 µA)
VOL
VOH
0
2.2
0.2
—
0.5
VCC
Table 4. Ground Start
Parameter
Tip Open state – Tip Input Impedance
Threshold, On– to Off–hook
Hysteresis
Min
150
—
Typ
Max
Unit
kΩ
mA
mA
—
13
2
—
—
—
—
Table 5. Ringing Specifications
Parameter
RINGINN/P:
Input Voltage Swing
Ring Signal Isolation:
PT/PR to VTX
Ring state
Ring Signal Isolation:
RINGIN to PT/PR
Min
Typ
Max
Unit
0
—
VCC
V
—
—
—
60
80
3
—
—
—
dB
dB
%
Non-ringing state
Ring Signal Distortion1:
Open or 5 REN Load, 100 Ω Loop
5 REN (Ringing Equivalency Number) is equivalent of 1380 Ω in series with 40 µF
Differential Gain RINGINP/N to PT/PR
RLOAD = Open,
VBAT1 = –75 V (Le9500A), VRINGINP/N = 0.51 VPP;
VBAT1 = –85 V (Le9500B), VRINGINP/N = 0.59 VPP;
VBAT1 = –100 V (Le9500C), VRINGINP/N = 0.70 VPP;
VBAT1 = –145 V (Le9500D), VRINGINP/N = 1.04 VPP.
V/V
124
130
136
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 6. Ring Trip
Parameter
Min
Typ
Max
Unit
Ring Trip (NSTAT = 0):
Loop Resistance (total) VBAT1 Applied
100
—
600
Ω
Ring Trip (NSTAT = 1):
Loop Resistance (total) VBAT1 Applied
Trip Time (f = 20 Hz)1
Hysteresis1
—
—
—
—
—
10
10
100
—
kΩ
ms
mA
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
11
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Pre-trip immunity
Ringing will not be tripped by the following loads across Tip and Ring as shown in the reference schematic in the this document.
Ringing frequency = 17 Hz to 23 Hz otherwise specified.
•
•
10-kΩ resistor in parallel with 5 Ringer Equivalency Number (REN) (equivalent of 1386-Ω + 40-µF) per GR-909 Issue 2,
December 2004
10-kΩ resistor in parallel with a 2-µF capacitor in parallel with 5 Ringer Equivalency Number (REN) (equivalent of 1386-Ω +
40-µF) per GR 57 Issue 1 October 2001.
OPERATING STATES
Table 7. Control States
B0
0
0
B1
0
1
B2
1
1
Operating State
Forward active
Reverse active
0
0
0
On-hook transmission forward battery
0
1
0
On-hook transmission reverse battery
1
1
0
Ground start
1
0
0
Scan
1
1
1
Disconnect (default device power up state)
1
0
1
Ring
Table 8. Supervision Coding
NSTAT
0 = off-hook or ring trip or thermal shutdown or ring ground.
1 = on-hook and no ring trip and no thermal shutdown and no ring ground.
Operating State Definitions
Forward Active
•
•
•
•
•
Pin PT is positive with respect to PR.
VBAT2 is applied to tip/ring drive amplifiers.
Loop closure and common-mode detect are active.
Ring trip detector is turned off to conserve power.
Overhead is set to nominal 7.2 V for undistorted transmission of 3.14 dBm into 900 Ω with 500 mVrms of PPM.
Reverse Active
•
•
•
•
•
Pin PR is positive with respect to PT.
VBAT2 is applied to tip/ring drive amplifiers.
Loop closure and common-mode detect are active.
Ring trip detector is turned off to conserve power.
Overhead is set to nominal 7.2 V for undistorted transmission of 3.14 dBm into 900 Ω with 500 mVrms of PPM.
Scan
•
•
•
•
Except for loop closure, all circuits (including ring trip and common-mode detector) are powered down.
On-hook transmission is disabled.
Pin PT is positive with respect to PR and VBAT1 is applied to tip/ring.
The tip to ring on-hook differential voltage will be typically between –44 V and –51 V with a –51 V to –100 V primary battery.
On-Hook Transmission—Forward Battery
•
•
•
•
Pin PT is positive with respect to PR.
VBAT1 is applied to tip/ring drive amplifiers.
Supervision circuits, loop closure, and common-mode detect are active.
Ring trip detector is turned off to conserve power.
12
Zarlink Semiconductor Inc.
Le9500
Data Sheet
•
•
On-hook transmission is allowed.
The tip to ring on-hook differential voltage will be typically between –41 V and –49 V with a –51 V to –100 V primary battery.
On-Hook Transmission—Reverse Battery
•
•
•
•
•
•
Pin PR is positive with respect to PT.
VBAT1 is applied to tip/ring drive amplifiers.
Supervision circuits, loop closure, and common-mode detect are active.
Ring trip detector is turned off to conserve power.
On-hook transmission is allowed.
The tip to ring on-hook differential voltage will be typically between –41 V and –49 V with a –51 V to –100 V primary battery.
Disconnect
•
•
•
•
The tip/ring amplifiers and all supervision are turned off.
The SLIC device goes into a high-impedance state.
NSTAT is forced high (on-hook).
Due to internal pull-ups, device will power up in this state.
Ring
•
•
•
•
Power ring signal is applied to tip and ring.
Input wave form at RINGINN/P is amplified.
Ring trip supervision and common-mode current supervision are active; loop closure is inactive.
Overhead voltage is reduced to typically 4 V.
Ground Start
•
•
•
Tip drive amplifier is turned off.
Device presents a high impedance (>100 kΩ) to pin PT.
Device presents a clamped (amplitude <56.5 V) current-limited battery (VBAT1) to PR.
Thermal Shutdown
•
•
Not controlled via truth table inputs.
This mode is caused by excessive heating of the device, such as may be encountered in an extended power cross
situation. NSTAT output is forced low or off hook during a thermal shutdown event.
13
Zarlink Semiconductor Inc.
Le9500
Data Sheet
TEST CIRCUIT
Figure 2. Le9500 Device Basic Test Circuit
RINGINN
RINGINN
RTFLT
0.1 µF
RINGINP
RINGINP
VITR
383 kΩ
VITR
RCV
DCOUT
PR
0.1 µF
69.8 kΩ
60.4 kΩ
30 Ω
TIP
RLOOP
100 Ω/600 Ω
RCVP
RCVN
30 Ω
26.7 kΩ
RING
PT
Le9500
BASIC
TEST
0.1 µF
VPROG
VREF
FB2
CIRCUIT
TXI
VTX
4750 Ω
ITR
FB1
CF1
B0
B1
B2
B0
B1
B2
0.1 µF
0.1 µF
CF2
VBAT2
VBAT2
VBAT1
VBAT1
BGND VCC
AGND
NSTAT
0.1 µF
0.1 µF
0.1 µF
VCC
Figure 3. Metallic PSRR
VBAT or Vcc
100
4.7
Ω
Disconnect
Bypass Capacitor
µ
F
VS
VBAT or Vcc
TIP
+
BASIC
TEST CIRCUIT
600
Ω
VT/R
–
RING
VS
VT/R
PSRR = 20log
14
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Figure 4. Longitudinal PSRR
VBAT or Vcc
Disconnect
Bypass Capacitor
100
4.7
Ω
µ
F
VS
VBAT or Vcc
67.5
Ω
TIP
10 µF
BASIC
TEST CIRCUIT
RING
67.5
Ω
Ω
+
VM 56.3
–
10 µF
VS
PSRR = 20log
VM
Figure 5. Longitudinal Balance
100 µF
TIP
VS
368
368
Ω
+
BASIC
TEST CIRCUIT
VM
–
Ω
RING
100
µF
VS
VM
LONGITUDINAL BALANCE = 20log
Figure 6. AC Gains
VITR
PT
+
BASIC
TEST CIRCUIT
VT/R
600
Ω
–
RCV
VS
PR
RCV
VVITR
VT/R
GXMT =
GRCV =
VT/R
VRCV
15
Zarlink Semiconductor Inc.
Le9500
Data Sheet
APPLICATIONS
DC Loop Current Limit
Current limit may be chosen from two discrete values, 25 mA or 40 mA, depending on if VPROG is grounded (25 mA) or left floating
(40 mA). Note that there is a 12.5 kΩ slope to the I/V characteristic in the current-limit region; thus, once in current limit, the actual
loop current will increase slightly, as loop length decreases.
The above describes the active state steady-state current-limit response. There will be a transient response of the current-limit
circuit upon an on- to off-hook transition. Typical active state transient current-limit response is given in Table 10.
Table 9. Typical Active state On-Hook to Off-Hook Tip/Ring Current-Limit Transient Response
Parameter
Value
Unit
DC Loop Current:
Active state
RLOOP = 100 Ω On- to Off-hook Transition t < 5 ms
ILIM + 60
mA
DC Loop Current:
Active state
RLOOP = 100 Ω On- to Off-hook Transition t < 50 ms
DC Loop Current:
ILIM + 20
ILIM
mA
mA
Active state
RLOOP = 100 Ω On- to Off-hook Transition t < 300 ms
Overhead Voltage
Active state
Overhead is fixed to a nominal 7.2 V, which is adequate for an on-hook transmission of 3.14 dBm into 900 Ω with additional head
room for a 500-mV PPM signal.
Scan state
If the magnitude of the primary battery is greater than 51 V (but no more than 100 V), the magnitude of the open loop tip-to-ring
open loop voltage is clamped typically between 44 V and 51 V. If the magnitude of the primary battery is less than a nominal 51
V, the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage
will be about 4V less than battery.
On-Hook Transmission state
If the magnitude of the primary battery is greater than 51 V (but no more than 100 V), the magnitude of the open loop tip-to-ring
open loop voltage is clamped typically between 41 and 49 V. If the magnitude of the primary battery is less than a nominal 51 V,
the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage will
be 6 to 8 V less than battery.
Ring state
In the ring state, to maximize ringing loop length, the overhead is decreased to the saturation of the tip ring drive amplifiers, a
nominal 4 V.
During the ring state, to conserve power, the receive input at RCVN/RCVP is deactivated. During the ring state, to conserve
power, the AAC amplifier in the transmit direction at VITR is deactivated. However, the AX amplifier at VTX is active during the
ring state; differential ring current may be sensed at VTX during the ring state.
DC Loop Range
The DC loop range can be calculated by using the following equation:
VBAT2 – VOH
-------------------------------------
RLOOP =
– 2RP – RDC
ILOOP
where:
VBAT2 is applied under off-hook conditions for power conservation and SLIC device thermal considerations.
VOH is overhead voltage, typically 7.2V.
RDC is DC feed impedance, typically 40 Ω.
RP is protection resistor, typically 50 Ω.
16
Zarlink Semiconductor Inc.
Le9500
Data Sheet
ILOOP is the loop DC current, no more than DC current limit.
If the minimum loop current allowed is 22 mA and VBAT2 is –21V then the maximum loop resistance by the equation is 487 Ω.
This includes telephone set at the end of the loop.
The Le9500 device is intended for short-loop applications and, therefore, could always be in current limit during off-hook
conditions. The above equation does not apply when the DC current is in the current limit region.
The actual maximum loop length the device can support, however, is often limited by the ringing loop length rather than the DC
loop length (with adequate amplitude of VBAT2).
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by capacitors CFB1 and CFB2. A chart showing CFB1 and CFB2 values versus
typical ramp time is given below. Leave FB1 and FB2 open if it is not desired to ramp the rate of battery reversal. Use with 0.47
µF for CTX.
The voltage seen on FB1 and FB2 pins on the SLIC can be close to VBAT1. The value of CFB1 and CFB2 being greater than 0.22
µF is not recommended.
Table 10. CFB1 and CFB2 Values versus Typical Ramp Time
CFB1 and CFB2
0.001 µF
0.01 µF
Transition Time
2 ms
20 ms
0.022 µF
0.047 µF
0.1 µF
50 ms
100 ms
220 ms
320 ms
0.15 µF
Supervision
The Le9500 device offers the loop closure and ring trip supervision functions. Internal to the device, the outputs of these detectors
are multiplexed into a single package output, NSTAT. The ring trip detector is valid on NSTAT during the ring state, and loop
closure detector is valid on NSTAT during active and on-hook transmission states. Additionally, common-mode current is detected
for ground start applications. This status is output onto NSTAT and is valid during ground start mode.
Loop Closure
The loop closure has a fixed on-hook to off-hook threshold in Scan/Active/OHT states with hysteresis.
Ring Trip
The ring trip detector requires only a single-pole filter at the input, minimizing external components. An R/C combination of
383 kΩ and 0.1 µF, for a filter pole at 5.15 Hz, is recommended.
The ring trip threshold is internally fixed as a function of battery voltage and is given by the following:
RT (mA) = 67 * {(0.0045 * VBAT1) + 0.317}
where:
RT is ring trip current in mA.
VBAT1 is the magnitude of the ring battery in V.
There is a typical 10 mA hysteresis.
Ground Start
In the ground start applications, the loop closure detector is also used to indicate ring-ground has occurred. During ground start
mode, loop current will be common mode, rather than differential as in loop start mode. Thus, in ground start the threshold of the
loop closure detector is reduced by one half the threshold seen in the loop start mode. This output is seen at the NSTAT output
pin.
Power Ring
The device offers a ring state, in which a balanced power ring signal is provided to the tip/ring pair. During the ring state, a user-
supplied low-voltage ring signals are input to the device’s RINGINP/N inputs. These signals are amplified to produce the balanced
power ring signals. The user may supply a sine wave input, PWM input, or a square wave to produce sinusoidal or trapezoidal
ringing at tip and ring.
17
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Sine Wave Input Signal and Sine Wave Power Ring Signal Output
The low-voltage sine wave input is applied differentially or single ended to the Le9500 device at pins RINGINP and RINGINN.
During the ring state, the signals at pins RINGINP and RINGINN are amplified and presented to the subscriber loop. The differential
gain from RINGINP/N to tip and ring is specified in the device specifications.
When the device enters the Ring state, the clamp circuit is disabled, allowing the voltage magnitude of the power ring signal to
be maximized. Additionally, in the Ring state, the loop current limit is increased and is not limited by DC loop current limit.
The magnitude of the power ring voltage will be a function of the gain of the ring amplifier, the high-voltage battery, and the input
signal level at RINGINP/N. The input range of the signal at RINGINP/N is 0 V to Vcc. As the input voltage at RINGINP/N is increased,
the magnitude of the power ring voltage at tip and ring will increase linearly, until the tip and ring drive amplifiers begin to saturate.
Once the tip and ring amplifiers reach saturation, further increases of the input signal will cause clipping distortion of the power
ring signal at tip and ring. The ring signal will appear balanced on tip and ring. That is, the power ring signal is applied to both tip
and ring, with the signal on tip 180-degree out of phase from the signal on ring.
The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the input capacitor
at RINGINP/N, and the input signal at RINGINP/N and VCC. During non-ringing states, the sinusoidal ringing waveform may be left
on at RINGINP/N. Via the state table, the ring signal will be removed from tip and ring, even if the low voltage input is still present
at RINGINP/N.
Power Ringing with Le9500D
For operation of the Le9500D device with a high magnitude on VBAT1 greater than -100 V, special attention must be given to the
following areas at system level.
Ringing Cadence
Scan or On Hook transmission state must be used during the silent period of ringing. Do not use Active state.
VBAT1 supply
VBAT1 may be more negative than -100 V only during the actual power ringing. The amplitude of VBAT1 should not exceed 100 V
when the SLIC device is not in the Ringing mode. The amplitude of VBAT1 may not exceed 100 V during the silent period of ringing
or any other non-ringing mode of operation.
Pre-Trip Immunity
The Le9500D device pre-trip immunity is specified as 2 µF. With battery voltages more negative than -100 V, ringing into a heavy
pre trip load will generate excessive power. Depending on system and ambient conditions, ringing into a load heavier than 2 µF
could force the device into thermal shutdown. Under these conditions, as the device goes into and out of thermal shutdown a
glitch will appear on NSTAT. Proper operation may require the system to filter out these glitches.
Robust Ring Trip Indication
Upon ring trip, there will be large current going through the SLIC device which may cause the SLIC to go into thermal shutdown.
Upon thermal shutdown, NSTAT remains Low, which is still consistent with the Ring Trip state. During thermal shutdown, the net
voltage on RTFLT will go up because the Tip Ring amplifiers are off. When the voltage on RTFLT passes a certain limit (ring trip
threshold), until a SLIC state change, NSTAT will toggle between the thermal shutdown inducted low indication and the RTFLT
voltage high indication.
There are several ways to help remedy this situation. Limit the current on VBAT1 supply such that VBAT1 will move up towards
ground upon off hook, add a 100-Ω power resistor in the VBAT1, or add a 2-MΩ resistor from RTFLT to ground to lower ring trip
threshold.
For more details, please contact Zarlink field/customer applications.
18
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Design Examples
The following reference schematics show the complete Le9500 SLIC schematic for interfaces to Broadcom codecs.
®
Le9500/Broadcom Reference Schematic A
The following reference circuit shows the complete Le9500 SLIC device schematic for interface to the Broadcom BCM3352 as
designed on the Broadcom BCM93352SV application reference design and board. This circuit has a 600-Ω AC termination. The
BCM3351, BCM3352, and BCM6352 have programmable registers to modify the external 600-Ω termination to achieve
worldwide real or complex terminations. For complex terminations with BCM1101, the external circuit must be changed to set the
complex termination. Other resistive terminations require a change to this circuit. Contact your Zarlink account representative
for assistance with modifications to this circuit.
VCC = 3.3 V
VBAT1ext
VBAT2
L
600 Ω
CCC
CVBAT1
CVBAT2
DVBAT1
0.1 µF 0.1 µF
BGND VBAT2
0.1 µF
VBAT1
AGND
VCC
VDDCORE
VDDI/O
CRT
CMLEVEL
RTFLT
C4
R9
0.1 µF
100 kΩ
VREF_IO
RRT
R10
383 kΩ
100 kΩ
C5
CC2
R1
DCOUT
PT
0.1 µF
150 pF
20 kΩ
VTXP
VTXN
C6
R
CC1
0.1 µF
TIP
PT
R2
150 pF
20 kΩ
50 Ω
VBAT1ext
VITR
C7
Protector
150 pF
BROADCOM
R5
174 kΩ
CP
BCM3351
BCM3352
R6
C1
0.1 µF
88.7 kΩ
3.3 nF
Le9500
VRXP BCM6352
BCM1101
RCVP
VREF
PR
R
RING
PR
R4
50 Ω
78.7 kΩ
BCM3341
C2
VPROG
3.3 nF
R7
54.9 kΩ
TXI
R8
88.7 kΩ
CTX
0.47 µF
VRXN
RCVN
VTX
ITR
C3
RGX
3.3 nF
4.75 kΩ
RINGINN
RINGINP
RINGREFN
C10
68 nF
RINGREFP
D0 D1 D2 DET
CF1
CF1
CF2
NSTAT B2 B1 B0
C9
68 nF
0.22 µF
CF2
0.1 µF
RNSTAT
10 kΩ
VCC
19
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Application Circuit Parts List A
The following parts list is for the Zarlink Le9500 SLIC device and Broadcom BCM3352 codec (per Broadcom BCM93552SV
application board daughter board components), fully programmable.
Item
RPT
Type
Value
Tolerance
Rating
Comments
Protection resistor.
Fault Protection
Resistor
Resistor
50 Ω
50 Ω
1%
1%
Fusible or PTC
Fusible or PTC
RPR
Protection resistor.
Battery
referenced
thyristor
Secondary protection. Reference to most
negative power supply (VBAT1ext).
Protector
—
—
Consult protector vendor for recommended
value.
100 V1
CP
Capacitor
0.1 µF
20%
Power Supply
100 V1
50 V2
CVBAT1
CVBAT2
DVBAT1
CCC
Capacitor
Capacitor
Diode
0.1 µF
0.1 µF
20%
20%
—
VBAT1 filter capacitor.
VBAT2 filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
1N4004
0.47 µF
—
Capacitor
20%
10 V
Ceramic bypass capacitor.
600 Ω, Murata®
BLM11A601SPB
Ferrite
Bead
L
—
—
Filtering.
CF1
CF2
Capacitor
Capacitor
0.22 µF
0.1 µF
20%
20%
Filter capacitor.
Filter capacitor.
100 V
100 V
Ring Trip
CRT
RRT
Capacitor
Resistor
0.1 µF
20%
1%
10 V
Ring trip filter capacitor.
Ring trip filter resistor.
383 kΩ
1/16 W
AC Interface
RGX
CTX
CC1
R4
Resistor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
4.75 kΩ
0.47 µF
0.1 µF
1%
20%
20%
1%
1/16 W
10 V
Sets T/R to VITR transimpedance.
AC/DC separation.
DC blocking capacitor
AC interface.
10 V
78.7 kΩ
174 kΩ
88.7 kΩ
54.9 kΩ
88.7 kΩ
10 kΩ
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
R5
1%
AC interface.
R6
1%
AC interface.
R7
1%
AC interface.
R8
1%
AC interface.
RNSTAT
1%
Control.
SLIC
device
Le9500
—
—
—
Note:
1. Increase to 200 V for Le9500C and Le9500D.
2. Assume |VBAT2|<50V.
20
Zarlink Semiconductor Inc.
Le9500
Data Sheet
®
Le9500/Broadcom Reference Schematic B
The following reference schematic shows the complete Le9500 SLIC device schematic for interface to the Broadcom BCM3367/
3368. This circuit has a natural 700-Ω AC termination impedance. The BCM3367 or MCB3368 has programmable registers to
modify the external 700-Ω termination to achieve worldwide real or complex terminations, as well as to set transmit and receive
gains, and other AC parameters. The BCM3367/3368 codec also drives ringing inputs, sets SLIC operation state, and monitors
NSTAT. The voltage of the battery supply to VBAT1 is expected to be properly set and may vary depending upon SLIC operational
states.
Contact your Zarlink account representative for assistance with other applications.
VCC = 3.3 V
VBAT1ext
VBAT2
VBAT2
L
600 Ω
CVCC
CVBAT1
CVBAT2
0.1 µF
0.1 µF
0.1 µF
DVBAT1
VBAT1
BGND
AGND
VCC
VDDCORE
VDDI/O
CVTXP
0.1 µF
CRT
VTXP
RTFLT
0.1 µF
RVTXP
RRT
383 kΩ
301 kΩ
APM_LAVDD_1P2
RVTXN
DCOUT
PT
301 kΩ
C
VITR
0.1
µ
F
R
PT
TIP
VITR
VTXN
50
Ω
VBAT1ext
BROADCOM
BCM3367
VRXP BCM3368
RVITR
Protector
162 kΩ
CP
RCIP
0.1 µF
100 kΩ
Le9500
RCVP
VREF
R
PR
PR
RRCVP
RING
50 Ω
100 kΩ
VPROG
TXI
RRCVN
RCIN
61.9 kΩ
CTX
100 kΩ
0.47 µF
VRXN
RCVN
VTX
ITR
RGX
4.75 kΩ
RINGINN
RINGINP
RINGREFN
CINGN
68 nF
RINGREFP
D0 D1 D2 DET
CF1
CF2
NSTAT B2 B1 B0
CINGP
68 nF
CF1
CF2
0.22 µF
0.1 µF
RNSTAT
10 kΩ
VCC
21
Zarlink Semiconductor Inc.
Le9500
Data Sheet
Application Circuit Parts List B
The following parts list is for the Zarlink Le9500 SLIC device and Broadcom BCM3367/3368 codec.
Item
RPT
Type
Value
Tolerance
Rating
Comments
Fault Protection
Resistor
Resistor
50 Ω
50 Ω
1%
1%
Fusible or PTC
Fusible or PTC
Protection resistor.
Protection resistor.
RPR
Battery
referenced
thyristor
Secondary protection. Reference to most
negative power supply (VBAT1ext).
Protector
—
—
Consult protector vendor for recommended
value.
100 V1
C
P
Capacitor
0.1 µF
20%
Power Supply
100 V1
50 V2
CVBAT1
CVBAT2
DVBAT1
CVCC
Capacitor
Capacitor
Diode
0.1 µF
0.1 µF
20%
20%
—
VBAT1 filter capacitor.
VBAT2 filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
1N4004
0.47 µF
—
Capacitor
20%
10 V
Ceramic bypass capacitor.
600 Ω, Murata®
BLM11A601SPB
Ferrite
Bead
L
—
—
Filtering.
CF1
CF2
Capacitor
Capacitor
0.22 µF
0.1 µF
20%
20%
Filter capacitor.
Filter capacitor.
100 V
100 V
Ring Trip
CRT
RRT
Capacitor
Resistor
0.1 µF
20%
1%
10 V
Ring trip filter capacitor.
Ring trip filter resistor.
383 kΩ
1/16 W
AC Interface
RGX
Resistor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Resistor
4.75 kΩ
0.47 µF
0.1 µF
1%
20%
20%
20%
1%
1/16 W
10 V
Sets T/R to VITR transimpedance.
AC/DC separation.
DC blocking capacitor.
DC blocking capacitor.
AC interface.
CTX
CVITR
CVTXP
RVITR
RVTXP
RVTXN
RCIP
10 V
0.1 µF
10 V
162 kΩ
301 kΩ
301 kΩ
100 kΩ
100 kΩ
100 kΩ
61.9 kΩ
0.068 µF
0.068 µF
10 kΩ
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
10 V
1%
AC interface.
1%
AC interface.
1%
AC interface.
RCIN
1%
AC interface.
RRCVP
RRCVN
CINGP
CINGN
RNSTAT
1%
AC interface.
1%
AC interface.
20%
20%
1%
Ringing interface.
Ringing interface.
Control.
10 V
1/16 W
SLIC
device
Le9500
—
—
—
Note:
1. Increase to 200 V for Le9500C and Le9500D.
2. Assume |VBAT2|<50V.
22
Zarlink Semiconductor Inc.
Le9500
Data Sheet
PHYSICAL DIMENSIONS
28-Pin PLCC
Dwg rev. AN; 8/00
28-Pin PLCC
23
Zarlink Semiconductor Inc.
Le9500
Data Sheet
REVISION HISTORY
Revision A1 to B1
•
•
•
•
•
•
•
Added Note 1 to 5V Supply Currents and Power Dissipation tables.
Updated typical values for 3.3V and 5V Supply Currents and Power Dissipation tables.
Added Le9500C section with "TBD" values.
Removed "150V" from "150V HV7 Technology", page 1.
Corrected Battery Supply and Office Battery Supply specifications for absolute and electrical ranges, page 6.
Fixed "5-V" and "5 V" formatting on power dissipation tables, page10.
Corrected typical values for Table 1, added "Note 2" to Longitudinal to Metallic Balance, and "Note 3" to metallic to Longitu-
dinal Balance, page 11.
•
•
•
Applied "Note 2" to Psophometric and 3-kHz Flat ICN, page 12.
Combined Ground Start Hysteresis to one line, and added "Note 1" to Differential Gain on Table 6, page 13.
Corrected wording "(-65V to 105V)" to be "(-65V to -100V)" under the power control section, page 18.
Revision B1 to C1
•
•
Removed standard OPNs and added green package OPNs in Ordering Information, on page 1
Added Package Assembly, on page 6
Revision C1 to D1
•
Added Le9500D device information.
Revision D1 to E1
•
•
In Ordering Information, on page 1, added column for packing; added Note 2 for instructions on tape/reel ordering.
In Electrical Characteristics, on page 7,changed the Active State /PT-PR/-/Vbat2/ maximum from 7.75 V to 8.5 V.
Revision E1 to F1
•
•
•
In Absolute Maximum Ratings, on page 6, separated ratings for VBAT1 in non-ringing and ringing states.
In Ring Trip, on page 11, added pre-trip condition for the Le9500D device.
Added Power Ringing with Le9500D, on page 18
Revision F1 to F2
•
Added a note (the new note 1) under the Thermal Characteristics table on page 7 and removed the corresponding state-
ment about TSD in the note under the ABSOLUTE MAXIMUM RATINGS table on page 6.
Revision F2 to G1
•
•
•
•
•
•
•
•
Removed descriptions and specifications related to Vcc = 5 V.
Added BCM3367/3368 to Applications, on page 1.
Updated Thermal Characteristics, on page 7.
Added test conditions to Line Characteristics, on page 9.
Updated Loop Closure Thresholds and Hysteresis in Table 1, Two-Wire Port, on page 9.
Updated PSRR for VCC to reflect VCC= 3.3 V in Table 1, Two-Wire Port, on page 9.
Corrected the DCOUT gain in Table 2, Analog Pin Characteristics, on page 10
Updated Ring Signal Distortion and Differential Gain RINGINP/N to PT/PR in Table 5, Ringing Specifications, on
page 11
•
•
Updated descriptions to DC Loop Current Limit, on page 16.
Updated descriptions to Battery Reversal Rate, on page 17 and Table 10, CFB1 and CFB2 Values versus Typical
Ramp Time, on page 17.
•
•
•
Updated descriptions to Power Ring, on page 17.
Added Reference Schematic B, on page 21.
Added Parts List B, on page 22.
Revision G1 to G2
•
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
24
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
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