LX1661CD-TR [MICROSEMI]
Switching Controller, Current-mode, 1.5A, PDIP16, LEAD FREE, PLASTIC, DIP-16;
| 型号： | LX1661CD-TR |
| 厂家： | 
Microsemi |
| 描述： | Switching Controller, Current-mode, 1.5A, PDIP16, LEAD FREE, PLASTIC, DIP-16 开关 光电二极管 |
| 文件： | 总15页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not Recommended For New Design
LX1660 / 1661
ADVANCED PWM CONTROLLER
P
R O D U C T I O N D A T A S H E E T
T
H E
I
N F I N I T E
P
O W E R O F
I N N O V A T I O N
KEY FEATURES
DESCRIPTION
The LX1660 and LX1661 Are Monolithic Short-Circuit Current Limiting Without
Switching Regulator Controller ICs designed to Expensive Current Sense Resistors. The
provide low-cost, high performance adjustable current sensing mechanism can use a PCB trace
power supply for microprocessors and other resistance or the parasitic resistance of the main
applications requiring a fast transient response and inductor. For applications requiring a high degree
a high degree of accuracy. They provide an of accuracy, a conventional sense resistor can be
adjustable synchronous Pulse Width Modulator used.
Designed To Drive A
Synchronous Rectifier Stage —
Can Also Be Used In Non-
Synchronous Applications
Soft-Start Capability
Hiccup-Mode Fault Protection
No Current-Sense Resistor
Required For Current Limiting
ModulaConstant Off-Time
Conism For Fast
Tponse And Simple
Ssign
output suitable for a power supply for Pentium
other microprocessors.
Synchronous Rectifier Driver For CPU Core.
®
or Hiccup Mode Fault Protection. The hiccup
mode is programmable and with pulse-by-pulse
current limiting will help protect the power
The devices can drive dual MOSFETs resulting in supply system and load in the even of a short
typical efficiencies of 85 - 90%, even with loads in circuit.
2InternVoltage
Refe Brht Out
excess of 10A. Synchronous shutdown results in
increased efficiency in light load applications.
Ultra-Fast Transient Response Reduce
System Cost. The fixed frequency modulated
off-time architecture results in the fastest
transient response for a given inductor. Adaptive
voltage positioning (LX1661 only) requi
low-ESR capacitors to meet stringen
over and under-shoot spections.
PLICATIONS
Pentium Processor Supplies
AMD-K6TM Supplies
Cyrix® 6x86TM Supplies
Voltage Regulator Modules
General Purpose DC:DC
Supplies
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.memi.com
PRODUCT HIGGHT
OUTEN
V
5V
LX1661 I
N
SOCKET
7
IN
PROCESSOR
SUPPLY
APPLICATION
C2
C7
Q1
IRL3103
16V, 1000µF
Sanyo MV-GX or equivalent
R14, 1%
See Table 5
VOUT
U1
61
L1
C9
1µF
R1, 5m
R15
2.0k
1%
4
5
6
7
8
16
5µH Toroid
D1
VC1
TDRV
PGND
BDRV
VCC
C5
C6
15
14
13
12
11
10
9
R16
10k
VRE
16V, 1000µF
Sanyo MV-GX or
equivalent
INV
NINV
HICCUP
CT
SYNCEN
CS+
R5, 1k
C1
390pF
CS-
C3
0.1µF
390pF
16-pin SOIC
R6, 1k
PACKAGE ORDER INFO
Plastic DIP
16-Pin
RoHS Compliant / Pb-free
Transition DC: 0503
Plastic SOIC
16-Pin
RoHS Compliant / Pb-free
Transition DC: 0440
N
D
TA (°C)
0 to 70
LX166xCN
LX166xCD
Note: Available in Tape & Reel. Append the letters “TR” to the part number.
(i.e. :LX1661CD-TR)
L
I N
F
I N I T Y
M
I C R O E L E C T R O N I C S
I N C .
Copyright © 1998
Rev. 1.1a,2005-03-09
1
11861 WESTERN
A
VENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS (Note 1)
PACKAGE PIN OUTS
Supply Voltage ............................................................................................................. 25V
Output Peak Current Source (500ns)......................................................................... 1.5A
Output Peak Current Sink (500ns) ............................................................................. 1.5A
Analog Inputs ................................................................................................... -0.3 to +6V
Power Dissipation at TA = 25°C
N Package............................................................................................................... 1.5W
D Package........................................................................................................... 830mW
Operating Junction Temperature
EN
OTADJ
SGND
VREF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VC1
TDRV
PGND
BDRV
VCC
SYNCEN
CS+
INV
NINV/SS
HICCUP
CS-
CKAGE
Top w)
Plastic (N, D Packages)......................................................................................... 150°C
Storage Temperature Range .................................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds)............................................................. 300°C
Peak Package Solder Reflow Temp. (40 second max. exposure)..........................................260°C (+0, -5)
1
16
15
14
13
12
11
10
9
EN
OTJ
G
REF
INV
NINV/SS
VC1
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect
to Ground. Currents are positive into, negative out of the specified terminal. Pin
numbers refer to DIL packages only.
2
3
4
5
6
7
8
TDRV
PGND
BDRV
VCC
SYNCEN
CS+
THERMAL DATA
HICCUP
CT
N PACKAGE:
CS-
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
D PACKAGE:
W
D PACKAGE
(Top View)
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Junction Temperature Calculation: TJ = TA + (PD x θJA).
0°C/W
RoHS / Pb-free 100% Matte Tin Lead Finish
The θJA numbers are guidelines for the thermal performance of the ystem.
All of the above assume no ambient airflow
Copyright © 1998
Rev. 1.1a 10/25/2004
2
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, 10.8 < VCC < 13.2, 0°C ≤ TA ≤ 85°C. Test conditions: VCC = 12V, T = 25°C.)
LX1660
LX1661
Units
Parameter
Symbol
Test Conditions
Min. Typ. Max. Min. Typ. Max.
Reference Section
Initial Output Voltage
Load Regulation
VCC = 12V, IL = 100µA
1.98
2
2
24
2.02 1.98
2
2
24
2.02
V
VCC = 12V, IL = 10µA to 5mA
VREF = 1.96V
mV
mA
Short Circuit Current ISH
Timing Section
Off Time Initial
OT
IDIS
OTADJ = 1.8V, CT = 390pF
OTADJ = 3.5V, CT = 390pF
OTADJ = 1.8V to 3.5V
2
1
2
2
µS
µS
%
µA
µA
V
Off Time Temp Stability
Discharging Current
10 240 210 240
180 240 180 210 240
VNINV = 1.8V, VCT = 1.5V
VNINV = 3.5V, VCT = 1.75V
2
2
Ramp Peak
VP
0.9 1.0 0.8 0.9 1.0
.475 0.5 0.525 0.475 0.5 0.525
100 100
00.9 1.2 0.6 0.9 1.2
V
Ramp Peak-Valley
VRPP
OTADJ = 1.8V
V
nS
V
OTADJ = 3.5V
Ramp Valley Delay to Output
Turn Off Threshold
10% Overdrive
(Voltage at OTADJ Pin)
VOFF
Error Comparator Section
Input Bias Current
Input Offset Voltage
EC Delay to Output
IB
VIO
VFB = VSET
0.1 1.0
2
0.1 1.0
µA
mV
nS
36
42
48
10% Overdrive
150
150
Synchronous Control Section
Synchronous Enable Threshold
SYCEN
0.5 0.7 0.9 0.5 0.7 0.9
V
Current Sense Section
Input Bias Current
Pulse By Pulse CL
IB
VCLP
1.8VCS+ = V3.5V
IniAc
0.1 0.1
1
1
µA
mV
nS
80
90 100 80
150
90 100
150
CS Delay to Output
10% drive
Output Drivers Section
Output Rise Time
Output Fall Time
VC2 = 12V, CL = 3000pF
2 = 12V, CL = 3000pF
= 0, IPULL UP = 2mA
= 500ns
70
70
1
70
70
1
nSec
nSec
V
Output Pull Down
Peak Current
1.0
1.0
A
UVLO and S.S.
Start-Up Thresh
Hysteresis
VST
VHYST
ISD
VOL
VEN
IEN
9.85 10.15 10.45 9.85 10.15 10.45
V
V
mA
V
0.31
0.31
2
3
2
3
S.S. Sink Current
S.S. Sat Voltage
VCL = 10.1V
VCL = 9V, ISD = 20µA
0.2 0.6
0.2 0.6
1.3 1.4 1.5 1.3 1.4 1.5
V
Enable Shutdown Thre
Enable Bias Current
-0.5
0.5
-1
1
-0.5
0.5
-1
1
µA
µA
V
IEN (Low), VEN = 0V
IEN (High), VEN = 2V
0.14 0.16 0.18 0.14 0.16 0.18
Enable Hysteresis
Supply Current Section
Dynamic Operating Current
Start-Up Current
ICD
IST
VCC = VC = 12V, Out Freq = 200kHz, CL = 0
VCL = 10V
25
25
mA
µA
500 1000
500 1000
Hiccup Section
Hiccup Factor “ON” Time
Hiccup Duty Cycle
(CHICCUP = 0.1µF typ.)
100
10
100
10
mS/µF
%
Copyright © 1998
Rev. 1.1a 10/25/2004
3
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
BLOCK DIAGRAM
VCC
2V OUT
ENABLE
2V REF
EN
1
V
C1
16
15
UVLO
10.6/10.1
PWM LATCH
TDRV
S
Q
1.4V
EN
INTERNAL
VCC
R DOM
VREG 5V
R
Q
OTADJ
2
3
PGND
BDRV
14
13
BREAK
E
E
SGND
VREF
INV
4
5
VREG GOOD
40mV (1661 only)
ERROR
COMP
V
12
11
CC
SYNC EN
COMP
OTADJ
NINV/SS
6
VPEAK = 2V
VVAL = 1V
SYNCEN
OFFTIME CONTROL
HICCUP
CT
7
8
UPGRADE
IMAX
CS+
CS-
10
9
0.7V
90mV
HICCUP
R
I
1.5V
CCUP LATCH
FIGURE 1 — Block Diagram
Copyright © 1998
Rev. 1.1a 10/25/2004
4
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
FUNCTIONAL PIN DESCRIPTION
Pin
#
Description
EN
1
A low voltage at this pin puts the IC in sleep-mode.
OTADJ
2
The purpose of this pin is to allow modulation of the OFF-time relative to the reference voltage. The OFF-time is
inversely proportional to the reference voltage. The inverting input of the upgrade voltage comparator is also
connected to this pin, when the voltage at this pin is below 0.7V, the controller shuts down.
SGND
VREF
3
4
5
6
This pin is the signal ground of the IC.
2V reference.
INV
This pin is the inverting input of the error comparator.
NINV/SS
This pin is the non-inverting input of the error comparator (LX1661 omV offsen this pin and error
comparator). This pin is pulled low during sleep-mode to allow sion during start up.
HICCUP
CT
7
8
9
A hiccup-mode capacitor connected to this pin adjustty cycle.
The OFF-time is programmed by connecting a capacitor frhis pin tund.
This is the inverting input of the pulse-by-pulse cmparat
CS-
CS+
10 This is the non-inverting input of the pulse-bymparator.
SYNCEN 11 This pin enables the synchronous (bottom) drivltage at this pin disables the synchronous driver.
VCC
BDRV
PGND
TDRV
VC1
12 This is the IC supply voltage as ll as the ply to the bottom MOSFET.
13 This is the gate drive to the bottoOSFET
14 This is a seate ge top bottom MOSFET.
15 This is the gate SFET.
16 parate supply input for the top drive.
Copyright © 1998
Rev. 1.1a 10/25/2004
5
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
THEORY OF OPERATION
IC OPERATION
Referring to the block diagram and typical application circuit, the
output turns ON the top MOSFET, allowing the inductor current
to increase. At the error comparator threshold, the PWM latch is
reset, the top MOSFET turns OFF and the synchronous MOSFET
turnsON. The OFF-timecapacitorCT isnowallowedtodischarge.
At the valley voltage, the synchronous MOSFET turns OFF and the
top MOSFET turns on. A special break-before-make circuit
prevents simultaneous conduction of the two MOSFETs.
To minimize frequency variation with varying output voltage,
the OFF-time is modulated as a function of the voltage at the OTADJ
pin. The OTADJ pin is also being monitored for a minimum voltage
of 0.7V. Below 0.7V the controller will shut down. A low voltage
at the EN pin or the OTADJ pin will put the controller in a sleep
mode. During the sleep mode the NINV pin is pulled low. This
dischargestheexternalbypasscapacitoronthispinandallowsfor
a soft-start.
■ The peak voltage at the VFB pin is 40mV higher than the set
voltage and its average is the peak voltage minus the ripple volt-
age at VFB pin.
■ The output voltage is the voltage at the VFB pin minus the voltage
drop across the current sensing resistor (I
RSENSE).
*
■ At light loads, the voltage drop acensing resistor is small;
hence, the output voltage is aphe voltage at the VFB
pin (approximately 40mV hignomnal set-point volt-
age, VSET).
■ At heavy loads, lrrent fin the nse resistor, there-
fore, the voltage digher and tput voltage is lower.
This adaptive positioninthe output voltage as the load
changes allows er outpuge excursion during a fast
step-load traquires fewer output capacitors to meet
ttransienspefication.
+V
Q1
Regulation
C
VFB
(LX1661)
VFB
(LX1660)
LX1660 Only: The INV pin is connected to the negative side
of the sense resistor (i.e. the actual voltage supplied to the
load) — See Figure 2. The LX1660 will achieve a high DC se
point accuracy, since it regulates at the load, but it will ha
greater transient voltage over- and under-shoots than the LX16
L
RS
A
B
E
LOAD
TDRV
INV
NINV
Q2
COUT
BDRV
VREF
CS+
CS-
HICCUP
2V
CT
CS-
LX1661 Only: The INV pin is connected to the positive side o
the sense resistor (between the inductor and the sresistor)
— See Figure 2. The LX1661 has a 40mV offset the NIn
to enhance transient response, as shown in Fiw.
CS+
C
CHICCUP
CT
R
R
To RS
Figure 2 — LX1660 / 1661 General Circuit Configuration
Steady
Load current
Nominal set-point
voltage, VSET
Output voltage
(VOUT
)
Voltage drop (mainly) due
to current change and ESR
of capacitors, ∆V = ∆I * ESR
Steady-state voltage at
high current is approximately
VSET + 40mV - I * RSENSE
(Effects of ESL ignored
in this analysis)
Figure 3 — Adaptive Voltage Positioning
Copyright © 1998
Rev. 1.1a 10/25/2004
6
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
THEORY OF OPERATION (continued)
ERROR VOLTAGE COMPARATOR
OFF TIME CONTROL TIMING SECTION (continued)
The error voltage comparator compares the feedback voltage at
the positive side of the sense resistor to the set voltage (set voltage
plus40mVinLX1661). Anexternalfilterisrecommendedforhigh-
frequency noise.
In order to minimize frequency variations while providing
different supply voltages, the discharge current is modulated by
the voltage at the OTADJ pin. The OFF-time is inversely propor-
tional to the OTADJ voltage. If the OTADJ voltage drops below 0.7V,
the IC shuts down into a low quiescent current mode.
CURRENT LIMIT AND HICCUP SECTIONS
UNDER VOLTAGE LOCKOUT AND N SECTION
Current limiting is performed by sensing the inductor current
across the sense resistor. Exceeding this threshold turns the
output drive OFF and latches it OFF until the PWM latch set input
goes high again. To reduce stress on the external MOSFET and
SCR during output shorts or heavy-load conditions, a hiccup
circuit is incorporated, which provides 10% duty cycle. The
hiccup time is programmed via a capacitor at the HICCUP pin. A
low voltage at this pin disables the hiccup function.
The purpose of the UVLO is to kutpdrive off and to
maintain low quiesceurrnt uninput age reaches the
start-up threshold. At ges belrt-up voltage, the
UVLO comparator disaeinternal biasing, and turns off the
output drives. The NINV pipulled low.
SYNCHRONOOL SECTION
synchrontrol ction incorporates a unique break-
bemake fon to ure that the primary switch and the
synchus swit turned on at the same time. Approxi-
mately 1anoseconds of deadtime is provided by the break-
ore-makcuitry to protect the MOSFET switches.
OFF TIME CONTROL TIMING SECTION
ThetimingcapacitorCT allowsprogrammingoftheOFF-time. The
timing capacitor is quickly charged during the ON time of the top
MOSFET and allowed to discharge when the top MOSFET is OFF.
APPLICATIOMATION
Fuse (F1)
is optional
VIN 5V
See Note 1
C2 x 3
F1
6.3V, 1500µF
Sanyo MV-GX
or equivalent
VOUT = VREF (1 + R14/R15)
*
(VREF = 2.0V)
VOUT 3.3V
Q1
R14
IRL3103
1.3k (See Table 5)
L1
See Note 2
C9
1µF
R1, 5m
R15
2.0k
LX1660
2
3
4
5
6
7
8
16
5µH Toroid
EN
VC1
TDRV
PGND
BDRV
VCC
C5 x 6
15
14
13
12
11
10
9
OTADJ
SGND
VREF
D1
See Note 4
6.3V, 1500µF
Sanyo MV-GX or
equivalent
INV
NINV
HICCUP
CT
SYNCEN
CS+
R5, 1k
C1
390pF
CS-
C7
C3
0.1µF
0.1µF
16-pin SOIC
C8
680pF
R6, 1k
See Note 3
Notes 1. The number of capacitors within this bank may be reduced for cost savings at a penalty of increased ripple on the input bus.
2. The number of capacitors in the output filter bank may be reduced by two in a typical application; more may be removed for systems
with lesser transient requirements.
3. If pulse-by-pulse current limiting is desired, remove C7 and short LX1660 pin 7 to ground.
4. D1 is Motorola MBR1035 for 10A capability; downsize as per required current.
Figure 4 — LX1660 Controller Used In A Typical Stand-Alone High-Current 5V To 3.3V Regulator Application
Copyright © 1998
Rev. 1.1a 10/25/2004
7
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
APPLICATION INFORMATION
See Note 1
JP1
D1
1N4148
12VIN
5VIN
F1
JP2
D2
1N4148
C20
0.1µF
16A 32V
R13
10
C2
C11
See Note 1
JP4
1500µF
6.3V
1500µF
6.3V
JP3
Q1
IRL3
C9
1µF
R4
1K
VRM
CONTROLLER
See Note 1
C19
0.1µF
L1
R1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
VC1
EN
C10
R7 10
TDRV
PGND
BDRV
VCC
OROID
5µH
5mΩ
OTADJ
SGND
VVREF
0.1µF
C5
C12
C13
C4
390µF
Q2
IRL3103
R
LX1670
INV
R2
R3
1K
1
2
3
4
5
6
7
14
13
12
11
10
9
NINV/SS
HICCUP
CT
VCC
D4B
D4
D3
D2
VIDO
VSENSE
PGOOD
OVOUT
ENABLE
BLKEN
GND
10K
C
VID4
VID3
VID2
VID1
VID0
PWRGD
OUTEN
C1
390pF
C7
0.1µF
C8
680pF
C3
0.1µF
LX1661
R6
1K
D1
D0
8
Q3
2N6504
SUPPLY OUTPUT CLAMP
Note 1. Setup shown is for 5V application. For 12V inange the f
-
-
-
-
Close JP1 and JP4
Open JP2 and JP3
For C2 and C11, use 16V/850µF capacitors instead
Inductor L1 = 10µH
Figure 5 — Full Featured Voltator Usi661 Controller And LX1670 Programmable Reference / DAC Chip
FoProcessor Or Pentium II Processor Applications
Copyright © 1998
Rev. 1.1a 10/25/2004
8
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
APPLICATION INFORMATION
OUTEN
12V
VIN 5V
C2
C7
16V, 1000µF
Sanyo MV-GX or equivalent
VOUT
Q1
IRL3103
R4
1k
U2 1/2 LM358
3
8
U1
LX1661
1
C9
1µF
1
2
3
4
5
6
7
8
16
5roid
D1
2
EN
VC1
TDRV
PGND
BDRV
4
C5
C6
15
14
13
12
11
OTADJ
SGND
VREF
R24
R16
10k
16V, 1000µF
Sanyo MV-GX or
equivalent
C4
390pF
1k, 1%
INV
Jumper
VID0
NINV
HICCUP
CT
SYN
CS
R23, 20k 1%
R5, 1k
R22, 10k 1%
R21, 5k 1%
C3
0.1µF
390pF
CS-
VID1
VID2
VID3
16-pin SOIC
R6, 1k
C8
680pF
R20, 2.5k 1%
Figure 6 — Low Cost Programmabpply For Socket 7 Processors
TABLE 1 - Voltage Identification Co(VID)
Setting The Output Voltage
VID3
VID2
VID1
VID0
Ouge
The output voltage is set by means of a 4-bit digital VID code.
For processors that do not have VID coded into the package, the
VID code can be set by means of a jumper or DIP switch. For
low or ‘0’ signal, connect the VID pin to ground (DIP switch
ON). For high or ‘1’, leave open (DIP switch OFF).
1
1
1
1
1
1
1
1
0
1
0
1
2.0V
2.1V
2.2V
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
.3V
2.4V
2.5V
2.6V
2.7V
2.8V
2.9V
3.0V
3.1V
3.2V
3.3V
3.4V
3.5V
Note: Costs are estimates only. Check with suppliers for exact
quotation.
Copyright © 1998
Rev. 1.1a 10/25/2004
9
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
The LX1660/61 devices are very easy to design with, requiring
only a few simple calculations to implement a given design. The
followingproceduresandconsiderationsshouldprovideeffective
operation for virtually all applications. Refer to theApplication
Information section for component reference designators.
INPUT INDUCTOR
In order to supply faster transient load changes, a smaller output
inductor is needed. However, reducing the size of the output
inductor will result in a higher ripple voltage on the input supply.
Thisnoiseonthe5Vrailcanaffectothersystemcomponents, such
as graphic cards. In this case, it is recommended that a 1 - 1.5µH
inductor is used on the input to the rtor, to filter the ripple
on the 5V supply. Ensure that this s the same current
rating as the output inductor.
SELECTING BETWEEN THE LX1660 AND THE LX1661
In order to provide maximum user versatility, the Advanced PWM
Controller is offered in two versions: the LX1660 and the LX1661.
The LX1661 has a 40mV offset built-in which compensates for
the current sense resistor voltage drop. This allows optimal
transient response for high-speed systems, such as Pentium Pro
processor power supplies. Overall system design could be more
economical with the LX1661, since output capacitance require-
ments could be eased.
The LX1660 provides a very accurate DC set-point, since the
40mV offset is not included in the device. This device is good for
critical DC applications, such as core power in slower micropro-
cessors and related systems.
OUTPUT CAPACITOR
The output capacitor s d to meet ripple and transient
performance specifications. tive Series Resistance (ESR) is a
critical parametn a stecurrent occurs, the output
voltage will hat equals the product of the ESR and the
crent step,advae microprocessor power supply, the
ot capacsually ected for ESR instead of capacitance
or RcurrenabilA capacitor that satisfies the ESR
requiret usually s a larger capacitance and current capabil-
ity than stneeded. The allowed ESR can be found by:
See "Theory Of Operation" section earlier in this data sheet.
OUTPUT INDUCTOR
R (IRIPPLE + ∆I) < VEX
*
The output inductor should be selected to meet the requireme
of the output voltage ripple in steady-state operation and t
inductor current slew-rate during transient.
IRIPPLE is the inductor ripple current, ∆I is the maximum
rrent step change, and VEX is the allowed output voltage
ursion in the transient. Adaptive voltage positioning increases
the value ofVEX, allowingahigherESRvalueandreducingthecost
of the output capacitor.
The peak-to-peak output voltage ripple is:
VRIPPLE = ESR
I
RIPPLE
*
Typically, the positioning voltage is 40mV, using the LX1661,
and the transient tolerance is 100mV, resulting in a VEX of 140mV
(See Figure 3). The LX1660 does not have the positioning voltage
offset, so VEX is 100mV maximum.
where,
VIN - VOUT
VIN
IRIPPLE
=
*
fSW
L
*
Electrolytic capacitors can be used for the output capacitor, but
arelessstablewithagethantantalumcapacitors. Astheyage,their
ESR degrades, reducing the system performance and increasing
the risk of failure. It is recommended that multiple parallel
capacitors be used, so that, as ESR increases with age, overall
performance will still meet the processor's requirements.
There is frequently strong pressure to use the least expensive
components possible, however, this could lead to degraded long-
termreliability,especiallyinthecaseoffiltercapacitors. Linfinity's
demonstration boards use Sanyo MV-GX filter capacitors, which
are aluminum electrolytic, and have demonstrated reliability. The
Oscon series from Sanyo generally provides the very best
performance in terms of long term ESR stability and general
reliability, but at a substantial cost penalty. The MV-GX series
provides excellent ESR performance at a reasonable cost. Beware
of off-brand, very low-cost filter capacitors, which have been
shown to degrade in both ESR and general electrolytic character-
istics over time.
IRIPPLE is the indue curretput inductor
value and ESR ieries nce of the output
capacitor.
IRIPPLE shouange of 20% to 40% of the
maximum ounductance results in lower
output voltage tly higher ESR to satisfy the
transient specificactance also slows the inductor
current slew rate in rthe load-current step change, ∆I,
resulting in more output-capacitor voltage droop. The inductor-
current slew rates at rise and fall edges are:
TRISE = L ∆I / (V - V
)
OUT
*
IN
and,
TFALL = L ∆I / V
*
OUT
When using electrolytic capacitors, the capacitor voltage
droop is usually negligible, due to the large capacitance.
Copyright © 1998
Rev. 1.1a 10/25/2004
10
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
INPUT CAPACITOR
CURRENT LIMIT (continued)
The input capacitor and the input inductor are to filter the
pulsating current generated by the buck converter to reduce
interference to other circuits connected to the same 5V rail. In
addition, the input capacitor provides local de-coupling of the
buck converter. The capacitor should be rated to handle the RMS
current requirement. The RMS current is:
parasitic resistance of the inductor. One should include an RC
filter at the CS+ and CS- inputs, as shown in the Application
Information section, to eliminate jitter and noise.
For most applications, the resistors R5, R6 can be set at 1kΩ,
and C1 can be in the 300-500pF range as a starting point. If a fine
trim or adjustment of the current trip s required, C1 may be
shunted by a resistor. C1 will inmall delay into the
current limit trip point, which efises he threshold.
I
RMS = IL √ d(1-d)
where IL is the inductor current and d is the duty cycle. The
maximum value, when d = 50%, IRMS = 0.5IL . For 5V input and
output in the range of 2 to 3V, the required RMS current is very
close to 0.5IL .
Sense Resistor
The current sense resi1) is seleccording to the for-
mula:
R1 = VTRIP / I
A high-frequency (ceramic) capacitor should be placed across
the drain of the top MOSFET and the source of the bottom one to
avoidringingduetotheparasiticinductorbeingswitchedONand
OFF. See capacitor C7 in the Product Highlight on the first page
of this data sheet.
Where VTent sense comparator threshold (100mV)
ITRIP is thcunt limit. Typical choices are shown
be
E 2 - CSense Resistor Selection Guide
Load
Sense Resistor Value
TIMING CAPACITOR SELECTION
-Class cessor (<10A)
Class (>10A)
5mΩ
2.5mΩ
The frequency of operation of the LX1660 / 1661 is a function
the duty cycle and OFF-time. The OFF-time is proportional to
timing capacitor (connected to Pin 8, CT ), and is modulated
minimize frequency variations with duty cycle. The frequency i
constant, during steady-state operation, due to the lation of
the OFF-time.
r sense resistor will result in lower heat dissipation (I²R)
lso a smaller output voltage droop at higher currents.
There are several alternative types of sense resistor. The sur-
face-mount metal “staple” form of resistor has the advantage of
exposure to free air to dissipate heat and its value can be con-
trolled very tightly. Its main drawback, however, is cost. An alter-
native is to construct the sense resistor using a copper PCB trace.
Although the resistance cannot be controlled as tightly, the PCB
trace is very low cost.
The timing capacitor (CT) should be selected g llo
ing equation:
(1 - VOUT / V ) I
IN
DIS
CT =
f (1.52 - 0.29 V
)
*
S
where IDIS is fixed at 200µA ang frequency
(recommended to b200kHperation and
component sele
Whenusingeswitcgfrequency(fS)can
be approxima
PCB Sense Resistor
A PCB sense resistor should be constructed as shown in Figure
7. By attaching directly to the large pads for the capacitor and
inductor, heat is dissipated efficiently by the larger copper masses.
Connect the current sense lines as shown to avoid any errors.
C = 0.62
T
2.5mΩ Sense Resistor
100mil Wide, 850mil Long
Choosing a 680pF pacitor will result in an operating
frequency of 183kHz at VOUT = 2.8V. When a 12V power input is
used, the capacitor value must be changed (the optimal timing
capacitor for 12V input will be in the range of 1000 - 1500pF).
2.5mm x 22mm (2 oz/ft2 copper)
Inductor
CURRENT LIMIT
Output
Capacitor Pad
Current limiting occurs when a sensed voltage, proportional to
load current, exceeds the current-sense comparator threshold
value (90mV). The current can be sensed either by using a fixed
sense resistor in series with the inductor to cause a voltage drop
proportional to current, or by using a resistor and capacitor in
parallel with the inductor to sense the voltage drop across the
Sense Lines
FIGURE 7 — Sense Resistor Construction Diagram
Copyright © 1998
Rev. 1.1a 10/25/2004
11
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
CURRENT LIMIT (continued)
CURRENT LIMIT (continued)
Recommended sense resistor sizes are given in the following
table:
The dc/static tripping current Itrip,S satisfies:
Vtrip
RL
TABLE 3 - PCB Sense Resistor Selection Guide
Itrip,S
=
Copper
Copper Desired Resistor
Value
Dimensions (w x l)
Weight Thickness
mm
inches
Select L/RSCS ≤ RL to have higher dynamic tripping current
than the static one. The dynamic tricurrent Itrip,d satisfies:
2 oz/ft2
68µm
2.5m
5m
Ω
2.5 x 22
2.5 x 43
0.1 x 0.85
0.1 x 1.7
Vtrip
Ω
Itrip,d
=
L/(RSCS)
Loss-Less Current Sensing Using Resistance of Inductor
Any inductor has a parasitic resistance, RL, which causes a DC
voltage drop when current flows through the inductor. Figure 8
shows a sensor circuit comprising of a surface mount resistor, RS,
and capacitor, CS, in parallel with the inductor, eliminating the
current sense resistor.
General Guidelines focting RS , d RL
Vtrip
RL =
Se≤ 10 kΩ
Itri
Ln
and CS ac
CS n
=
RL RS
L
RL
Load
above tion taken into account the current-de-
pendeof the ce. Typical values are: RL = 3mΩ, RS =
9kΩ, CS µF, and L is 2.5µH at 0A current.
RS
n cases re RL is so large that the trip point current would
r than desired short-circuit current limit, a resistor (RS2)
t in parallel withCS, as shown in Figure 8. The selection
nents is as follows:
CS
RS2
Current
Sense
Comparator
VCS
RL (Required)
RS2
=
RL (Actual)
RS2 + RS
FIGURE 8 — Current Sense Circui
L
L
RS + RS2
The current flowing through the inductor is iawa
If the sensor components are selected such that:
CS =
=
*
RL (Actual) (R // R )
RL (Actual)
RS2 R
*
S
*
S2
S
L/RL = RS CS
*
Again, select (RS2//RS) < 10kΩ.
C4 ERROR COMPARATOR INPUT BYPASS CAPACITOR
The voltage across the capao the current
flowing through the resistor, i.e.
VCS = ILRL
The LX1660/61 device has a unique topology which results in
extremely fast response to transient disturbances. Actual loop
closure is around a comparator. A capacitor should be placed
between the INV and NINV Error Comparator inputs to eliminate
jitter and noise. This capacitor value should be: C = ½ CT, where
CT is the timing capacitor. Refer to Capacitor C4 in the Applica-
tion Information section.
Since VCS rerrent, belecting the appro-
priate RS and e to reach the comparator
voltage at the
Design Example
(Pentium II circuit, wum static current of 14.2A)
The gain of the sensor can be characterized as:
C7 HICCUP CAPACITOR SELECTION
|T(jω)|
The hiccup capacitor controls two time periods; the ON time
duration of 10% duty cycle mode, and the OFF-time duration
before re-try. The ON:OFF-time ratios will always be 1:10 due to
the current sources which charge (10I) and discharge (I) the
hiccup capacitor. Select CHICCUP by using:
RL
L/RSCS
Duration of reduced D operation = 100ms/µF
ω
1/RSCS RL/L
FIGURE 9 — Sensor Gain
Copyright © 1998
Rev. 1.1a 10/25/2004
12
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
C7 HICCUP CAPACITOR SELECTION (continued)
FET SELECTION (continued)
The resulting time is the duration allowed for the 10% duty
cycle drive to be applied to the bottom switch (the top switch is
OFF during current limit). The OFF-time will be fixed at ten times
(10x) this number, and determines the time interval the supply
remains completely OFF until re-try. If the short has been
removed, the supply will resume normal operation. No power
cycling is necessary to reset the VRM module after a current limit
event.
For the IRL3102 (13mΩ RDS(ON)), converting 5V to 2.8V at 14A
will result in typical heat dissipation of 1.48W.
Synchronous Rectification – Lower MOSFET
The lower pass element can be either a MOSFET or a Schottky
diode. The use of a MOSFET (synus rectification) will
result in higher efficiency, but at hin using a Schottky
diode (non-synchronous).
As an example, if a 0.1µF hiccup capacitor is chosen, the
bottomswitchdrivewillpulseat(approximately)a10%dutycycle
for 10mA, when current limit is reached. It will then shut OFF for
100ms, at which time a re-try cycle is attempted, which will result
in either normal operation or another 10% duty cycle burst.
Power dissipated ithe bottoFET wbe:
PD = I2
R
ty Cycle] W
*
*
DS(ON)
[IRL3303 or 1.12W foIRL3102]
Non-Synchrotion - Sottky Diode
FET SELECTION
A typical Sche, with a forward drop of 0.6V will dissi-
0.6 14 .8/5] 3.7W (compared to the 1.1 to 2.2W
*
To insure reliable operation, the operating junction temperature
of the FET switches must be kept below certain limits. The Intel
specification states that 115°C maximum junction temperature
should be maintained with an ambient of 50°C. This is achieved
by properly derating the part, and by adequate heat sinking. One
of the most critical parameters for FET selection is the RDS(
resistance. This parameter directly contributes to the pow
dissipation of the FET devices, and thus impacts heat sink desig
mechanical layout, and reliability. In general, the larger the
current handling capability of the FET, the lower tDS(ON) will
be, since more die area is available.
dised by SFET er the same conditions). This power
loss bes musignificant at lower duty cycles – syn-
chronoutification is recommended especially when a 12V-
er inpused. The use of a dual Schottky diode in a single
packa(e.g. the MBR2535) helps improve thermal dis-
GATE BIAS
e power MOSFETs can be biased by one of two methods:
charge pump or 12V supply connected to VC1.
TABLE 4 - FET Selection Guide
This table gives selection of suitable FETs from International Rectifi
1) Charge Pump (Bootstrap)
When 12V is supplied to the drain of the MOSFET, as in
Figure5(option), thegatedriveneedstobehigherthan12V
in order to turn the MOSFET on. Capacitor C20 and diodes
D1 & D2 are used as a charge pump voltage doubling circuit
to raise the voltage of VC1 so that the TDRV pin always
provides a high enough voltage to turn on Q1. The 12V
supply must always be connected to VCC to provide power
fortheICitself, aswellasgatedriveforthebottomMOSFET.
Device
RDS(ON)
@
I
Max. k-
10V (mΩ)
=
own Voltage
IRL3803
IRL22203N
IRL3103
IRL3102
IRL3303
IRL2703
6
40
56
24
17
30
30
30
20
30
30
2) 12V Supply
When5VissuppliedtothedrainofQ1, a12Vsupplyshould
be connected to both VCC and VC1.
All devices in TOrface mount devices (TO-263 /
D2-Pak), add 'S' to . IRL3103S.
The recommended solution is to use IRL3102 for the high side
and IRL3303 for the low side FET, for the best combination of
cost and performance. Alternative FET’s from any manufacturer
CURRENT SHARE APPLICATION
Synchronous rectifier stages should not be paralleled unless they
are locked in at the same frequency, or undesirable current
sourcing/sinking could occur. If synchronization is not practical,
the next best alternative is to disable the synchronous (bottom)
switch. This is easilyaccomplished with theLX1660/61bypulling
the SYNCEN pin HIGH. In most applications, a 5 to 6% reduction
in efficiency will result when the synchronous driver is disabled.
A Schottky diode of the proper voltage and current ratings should
be installed across the inactive FET to conduct the inductor
current.
could be used, provided they meet the same criteria for RDS(ON)
.
Heat Dissipated In Upper MOSFET
The heat dissipated in the top MOSFET will be:
PD = (I2
R
Duty Cycle) + (0.5 I V
t
f )
*
S
*
*
*
*
*
DS(ON)
IN
SW
where tSW is switching transition line for body diode (~100ns)
and fS is the switching frequency.
Copyright © 1998
Rev. 1.1a 10/25/2004
13
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
USING THE LX1660/1661 IN PROGRAMMABLE APPLICATIONS
LAYOUT GUIDELINES - THERMAL DESIGN (continued)
The LX1660/61 device may be used in conjunction with the
LX1670 Programmable Reference to implement a high-perfor-
mance,digitally-controlledswitched-modepowersupplysuitable
for Pentium Pro Processors and other advanced microprocessor-
based designs. The LX1670 incorporates a 5-bit equivalent DAC,
which can be programmed by the microprocessor’s Voltage
Identification Code (VID). The LX1670 then commands the
LX1660/61 to provide the required output voltage. System
protection functions such as over voltage, SCR drive, and power-
good detection are embedded within the LX1670 device. See
Figure 5.
cases are well suited for this application, and are the preferred
packages. Remember to remove any conformal coating from all
exposed PC traces which are involved in heatsinking.
General Notes
As always, be sure to provide local cive de-coupling close
to the chip. Be sure use ground uction for all high-
frequency work. Use low ESR chere justified, but be
alert for damping and nging proHighquency designs
demand careful routlayond mrequire several
iterations to achieve dperformavels.
PROGRAMMING THE OUTPUT VOLTAGE
Power Traces
To reduce poue to oc resistance, careful consid-
eration shoun to the layout of traces that carry high
nts. Thaths consider are:
SelectthevoltagedividerR14andR15valuesasshowninthetable
below, using 1% metal film resistors:
TABLE 5
■ t powV supply to drain of top MOSFET.
■ Traetween top MOSFET and lower MOSFET or Schottky
diode
ace bween lower MOSFET or Schottky diode and
und.
Desired Converter VOUT
R14 Value
R15 Value
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
806Ω
909Ω
1.0kΩ
1.10kΩ
1.21kΩ
1.30kΩ
1.40kΩ
1.50kΩ
2kΩ
2kΩ
2kΩ
2kΩ
2kΩ
2kΩ
2kΩ
ce between source of top MOSFET and inductor, sense
istor and load.
All of these traces should be made as wide and thick as pos-
sible, in order to minimize resistance and hence power losses. It
is also recommended that, whenever possible, the ground, input
and output power signals should be on separate planes (PCB
layers). See Figure 10 – bold traces are power traces.
If other VOUT values are needed, the divider vs may
calculated as follows:
VOUT = VREF (1 + R14/R15)
5V Input
where VREF = 2.that reart of a filter
element, and dothe caions.
Please refer Infortion schematic for
the reference ocations.
LAYOUT GUIDSIGN
LX166x
A great deal of timre spent optimizing the thermal
design of the demo boarAny user who intends to implement
an embedded motherboard would be well advised to carefully
read and follow these guidelines. If the FET switches have been
carefully selected, external heatsinking is generally not required.
However, this means that copper trace on the PC board must now
be used. This is a potential trouble spot;as much copper area as
possible must be dedicated to heatsinking the FET switches, and
the diode as well if a non-synchronous solution is used.
Output
FIGURE 10 — Power Traces
In our VRM module, heatsink area was taken from internal
ground and VCC planes which were actually split and connected
with VIAS to the power device tabs. The TO-220 and TO-263
Copyright © 1998
Rev. 1.1a 10/25/2004
14
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX1660/1661
A
D V A N C E D P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
USING THE LX1660/61 DEVICES
C9 Input De-coupling (VCC) Capacitor
Ensure that this 1µF capacitor is placed as close to the IC as
possible to minimize the effects of noise on the device.
Layout Assistance
Please contact Linfinity’s Applications Engineers for assistance
with any layout or component selection issues. A Gerber file
with layout for the most popular devices is available upon re-
quest.
Evaluation boards are also available upon request. Please
check Linfinity's web site for further application notes.
RELATED DECES
LX1662/1663
Single-Chip Programmable PWM Controw/ 5-Bit DAC
LX16
Dual Output PWM fApplications
L
Triple Output PWM foor Applications
X1553
WM 5V 3.3V Conversion
X1670
mmabeference & Voltage Monitor
Pentium is a registered trademark of Intel Corporation.
Cyrix is a registered trademark and 6x86 is a trademark of Cyrix Corporation. K6 is a trademark of AMD.
PRODUCTIONDATA-InformationcontainedinthisdocumentisproprietarytoLinFinity, andiscurrentasofpublicationdate. Thisdocument
may not be modified in any way without the express written consent of LinFinity. Product processing does not necessarily include testing of
all parameters. Linfinity reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright © 1998
Rev. 1.1a 10/25/2004
15
相关型号：
LX1662CD-TR
Switching Controller, Current-mode, 1.5A, 200kHz Switching Freq-Max, PDSO14, ROHS COMPLIANT, PLASTIC, SOIC-14
MICROSEMI
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