LX1752CLQ [MICROSEMI]
Dual Interleaving PWM Controller; 双路交错PWM控制器
| 型号： | LX1752CLQ |
| 厂家： | 
Microsemi |
| 描述： | Dual Interleaving PWM Controller |
| 文件： | 总28页 (文件大小：653K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
KEY FEATURES
GENERAL DESCRIPTION
The LX1752 is
a
dual output
Internal gate drive circuitry provides 5V
Dual PWM Controller,
Synchronous Operation
Voltage Mode PWM with
External Compensation
Single Input Supply, wide
range 4.5V to 22V
synchronous buck controller using voltage for the external upper and lower N channel
mode PWM architecture.
The single input voltage supply feature
simplifies the design and offers a wide currents up to 15A per phase and efficiency
range of operation from 4.5 to 22 volts. of 93% can be achieved with the flexible
MOSFETS.
Output voltages as low as 700mV, load
Each PWM has
programming the output sequencing and
serves as the shutdown control.
Current limit threshold is set with a options are available: two PWM channels
single external resistor and protects the with 180° separation; three PWM channels
high-side and low-side MOSFETs by at 120° or four PWM channels at 90°. This
sensing the voltage drop generated from phasing is set by the tri-state input pin
a Soft-Start pin for controller.
Precision Reference
Outputs as low as 700mV
Selectable PWM Frequency up
to 1.5Mhz
Synchronization Pin for PWM
Frequency
Operating alone or with other LX1752’s
on a bus, three multi-phase interleaving
Independent and
RDSON
.
PSET. This architecture minimizes the
Programmable Soft
Each PWM channel has its own input capacitor requirements.
Start/Enable for Power
Sequencing
Integrated High Current
MOSFET Drivers
Programmable Current Limit
Lossless Current Sensing for
Current Limit and Short Circuit
Protection
external feedback compensation for
performance optimization.
The entire power supply design occupies
a small footprint with the LX1752’s low
profile 28 pin, MLP package of 4x5x1mm
(JEDEC MO-220).
Pb-free, RoHS Compliant
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
APPLICATIONS
Multi-Output Power Supplies
Video Card Power Supplies
PC Peripherals
Set Top Boxes
Point of Load DC-DC
Converters
PACKAGE ORDER INFO
PRODUCT HIGHLIGHT
Plastic MLPQ
VIN 4.5V to 22V
LQ
TA (°C)
0 to 85
28 pin
RoHS Compliant / Pb-free
VSX
LX1752CLQ
VIN
HOX
VCX
HRX
CSX
LOX
PGX
EAX-
VCCL
Note: Available in Tape & Reel. Append the letters “TR” to
the part number. (i.e. LX1752CLQ-TR)
PSET
SSENX
AGND
VOUT
LX1752
SYNC
SHDN
SYNC
SHDNX
RFREQ
EAOX
ONE OF 2 PWM SECTIONS
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 1
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Input Voltage(VIN) .............................................................. -0.3V to 22V
Supply Voltage (VCCL) .................................................................. -0.3V to 6.0V
Topside Driver Supply Input Voltage (VCX).................................... -0.3V to 28V
Topside Current Sense Input (VSx) .................................................. -0.3V to 28V
Current Sense Input (CSX) .................................. -0.3V(-2.0V for ≤ 50ns), to 28V
Topside Driver Return Input Voltage (VHRX).... -0.3V(-2.0V for ≤ 50ns), to 28V
Error Amplifier Inputs (EAX-) ........................................................ -0.3V to 5.5V
Logic Inputs (SYNC, PSET, SHDNX).............................................-0.3 to VCCL
Differential Voltage: VHOX-VHRX (High Side Return)......................... -0.3V to 6V
Soft Start Input (SSENX)..................................................................-0.3V to VREF
Maximum LDO Output Current (VCCL) ...................................................100mA
Maximum Operating Junction Temperature ................................................ 150°C
Operating Temperature ....................................................................-20°C to 85°C
Storage Temperature Range...........................................................-65°C to 150°C
Peak Package Solder Reflow Temp (40 seconds max exposure).... 260°C (+0, -5)
28
27 26 25 24 23
22
1
2
3
4
5
6
7
8
GND
SYNC
SHDN2
SSEN2
EA2-
SHDN1
CS1
21
20
19
18
17
16
15
VS1
VC1
H01
EO2
VIN
HR1
L01
PGND
CS2
9
10 11 12 13 14
LQ PACKAGE
(Top View)
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
x denotes respective pin designator (1 or 2).
MSC
1752
XXXX
THERMAL DATA
Plastic MLPQ 28-Pin
LQ
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
27°C/W
LQ PACKAGE MARKINGS
“xxxx” Denote Date Code and Lot Identification
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the
above assume no ambient airflow.
RoHS / Pb-free 100% matte Tin Pin Finish
FUNCTIONAL PIN DESCRIPTION
Name
Pin
Description
Analog Ground. Connect this pin to a local analog ground plane. All low level signals are referenced to this
ground and should return to this pin.
GND
1
SYNC Control Line used on the multi-channel bus. Wire OR’d negative going pulse with a common pull-up
resistor.
SYNC
2
The Shutdown pin is an I/O pin which connects to an internal open drain transistor and an external pull up
resistor. During a fault, this pin will be low during the discharge portion of hiccup mode, and high during the
recovery (soft start) portion of hiccup mode.. Used primarily for test purposes. May be used as a system
level fault monitor. Each SHDN pin requires a pull-up resistor of 500Ω to 4.7K tied to VCCL.
SHDNX 3, 22
SSENX 4, 25
Soft Start Enable input. Connect a capacitor from SSENx to GND to set the soft-start time, the rise time of
the output voltage during start up. If grounded the PWM is disabled.
Error Amplifier Inverting Input for the corresponding PWM channel denoted by “X”. Connect to the output
via external network to regulate the output voltage.
EAX -
5, 24
Error Amplifier Output – Connect to external loop compensation network for the corresponding PWM
channel denoted by “X” to provide an error signal to the internal PWM comparator for duty cycle control.
EOX
VIN
6, 23
7
Controller Supply Voltage. This is the input to the internal 5V LDO.
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 2
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
FUNCTIONAL PIN DESCRIPTION
Over-Current Limit Set – connecting a resistor between CSX pin and the junction of the drain of the low-side
NMOSFET and the Source of the high-side MOSFET sets the current limit threshold for the corresponding
PWM channel denoted by “X”. A minimum of 200 ohms must be in series with this input. Whenever the
current limit threshold is reached for 4 consecutive clock cycles the shutdown latch is set and the Soft Start
capacitor is discharged through an internal resistor initiating Shutdown and then a Soft Start to generate a
hiccup mode current limit.
CSX
VSX
8, 21
Voltage reference for high side current sense. “X” denotes corresponding phase. Connect this pin directly
to the high-side MOSFET’s drain.
9, 20
PWM channel High-Side MOSFET Gate Driver Supply. Connect to the flying capacitor bootstrap supply to
ensure proper high-side gate driver supply voltage. “X” denotes the corresponding PWM channel.
VCX
HOX
HRX
10, 19
11, 18
12, 17
High Side MOSFET Gate Driver – “X” denotes corresponding PWM channel.
High Side driver return, connect this pin to the High Side MOSFET source. “X” denotes the corresponding
PWM channel.
Output of the +5V LDO regulator. Supplies the internal circuit and the external MOSFETs gate drivers.
For 4.5V < VIN < 5.5V, this pin is connected externally to VIN. For VIN >
6V this pin supplies +5V to the internal circuit and the external MOSFETs gate drivers Connect a minimum
of 4.7µF ceramic capacitor from this pin to GND.
VCCL
13
LOX
14, 16
15
Low Side MOSFET Gate Driver – “X” denotes corresponding PWM channel.
Power ground pin for the low-side MOSFET drivers. Connect low-side MOSFETs’ source directly to this pin,
which connects to power ground plane
PGND
RFREQ
26
The resistor value from this pin to GND sets the PWM frequency.
A Tri-State logic level input that selects the phase position of the two PWM channels from the SYNC pulse.
A logic low, GND, will set the PWM phases at 0 and 180 degrees. An open pin, Tri-State, will set the PWM
phases at 90 and 270 degrees. A logic high, VCCL, will set the PWM phases at 120 and 240 degrees.
PSET
VREF
27
28
An internally generated voltage reference of 0.8V that is buffered and brought out on this pin. If used,
connect a 470pF ceramic capacitor to GND.
Note: X Denotes the PWM Channel: 1 or 2
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Analog Mixed Signal Group
Page 3
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where
otherwise noted and the following test conditions: VIN = 12V, VCX = 17V, HOX = 1000pF load to HRX, LOX =1000pF load to GND,
VHRX = 12V, (f = 800kHz).
LX1752
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
`
IC ELECTRICAL CHARACTERISTICS
VIN
6.0
4.5
22
5.5
Input Voltage
V
Connect VCCL to VIN externally
Operation Current
Feedback Voltage
IVIN
EAx-
No Switching
Initial Accuracy; TA = 25°C
4.5V ≤ VIN ≤ 22V
6
mA
V
0.691
0.689
0.700
0.709
0.711
Switching Frequency = 800kHz to1.5Mhz
Measured between 1.5V rise to 1.5V fall of HOX
– HRX.
High Side Minimum Pulse Width
(NOTE 3, NOTE 5)
PWMIN
80
ns
Measured between HOX-HRX 1.5V rise to HOX-
HRX 1.5V fall.
0mA ≤ IVREF ≤ 1.0mA
Maximum Duty Cycle
PWMDC
VREF
88
92
%
V
Buffered Reference Voltage
0.784
0.800
0.816
`
ERROR AMPLIFIER
DC Open Loop Gain,
Unity gain bandwidth (NOTE 2)
High Output Voltage
Low Output Voltage
Input Common Mode Range
Input Bias Current
70
10
dB
MHz
V
mV
V
AVUGBW
VOH
VOL
I Source = 2mA
I Sink = 100µA
3.5
0.2
100
1.0
30
IIN
nA
`
`
CURRENT SENSE
VCSx to VHRX = 0.2V; VPGND = 0V, Vcx to Vhrx =
5.0V
Referenced to VCSX, VPGND = 0V
(NOTE 5)
CS Bias Current (Source)
ISET
44
50
57
20
µA
CS Trip Threshold Offset
CS Delay (Blanking)
VTRIP
TCSD
-20
0
150
mV
ns
OUTPUT DRIVERS – N Channel MOSFETS
Drive Rise and Fall Time
Dead Time – High Side to Low Side
or Low Side to High Side
TR/F
CL = 1000pF
measured between 1.5V crossings of HOX-HRX
and LOX.
40
ns
ns
TDEAD
40
High Side Driver RDSON
Drive High
HOX_RDSON IHOX = 100mA (NOTE 5)
IHOX = -100mA
4.8
3.3
Ohm
Ohm
Drive Low
Low Side Driver RDSON
Drive High
LOX_RDSON
ILOX = 100mA
LOX = -100mA
4.4
3.3
Drive Low
I
`
SYNC-FREQUENCY GENERATOR
Maximum Clock Frequency
Minimum Clock Frequency
Ramp Amplitude
FMAX
FMIN
VRAMP
RFREQ = 19.1kΩ
RFREQ = 178kΩ
1.4
180
1.5
200
1.2
±5
1.6
220
MHz
kHz
VPP
%
Frequency Stability
4.5V ≤ VIN ≤22V
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 4
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where
otherwise noted and the following test conditions: VIN = 12V, VCX = 17V, HOX = 1000pF load to HRX, LOX =1000pF load to GND,
VHRX = 12V, (f = 800kHz).
LX1752
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
`
UVLO AND SOFT-START (SS)
Start-Up Threshold
(VCCL)
VCCL Rising
3.75
0.2
4.35
V
Hysteresis (NOTE 2)
SS Input Resistance
SS Shutdown Threshold
0.30
20
V
kΩ
mV
RSS
VSHDN
85
130
CSS = 0.1uF; VOUT rise time from 0V to 90% of
output voltage set by feedback (NOTE 2)
CSS = 0.1µF; 100% * On time/Off time + On time
Soft Start Time
4.30
4
ms
%
Hiccup Mode Duty Cycle
`
`
`
INTERNAL LDO REGULATOR
Internal + External Load: 0mA < IVCCL < 100mA;
6V < VIN<22V.
Regulated Output
VCCL
PSET
4.5
5.5
V
PSET TRI-STATE INPUT
Logic Level Low Threshold
Logic Level Open Threshold
Logic Level High Threshold
Percentage of VCCL (NOTE 4)
Percentage of VCCL (NOTE 4)
Percentage of VCCL (NOTE 4)
22
60
%
%
%
40
84
50
LOGIC INPUT / OUTPUT – OPEN DRAIN EXTERNAL PULL UP RESISTOR
Threshold Logic Low
External Pull-up Resistance = 500 ohms to
VCCL
Input Pulse Width measured at 50% of VCCL;
Fall time < 5ns, Rise time < 20ns
Threshold Logic Low; Falling Edge
1.0
1.5
V
SYNC
SHDN
Sync Bus
30
100
1.5
ns
V
Shutdown
0.8
`
`
SWITCHING REGULATORS
Phase to Phase Position
PSET = VCCL; Measured HO1 to HO2
PSET = Open; Measured HO1 to HO2
PSET = GND; Measured HO1 to HO2
80
140
160
102
165
180
120 Degrees
190 Degrees
210 Degrees
Thermal Shutdown
Rising temperature; Hiccup Mode Operation at
Limit
Rising temperature; Hiccup Mode Operation at
Limit
Die Temperature
TSD
TSD
165
10
°C
°C
Die Temperature Hysteresis
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 5
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
SYSTEM CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where
otherwise noted and the following test conditions: VIN = 12V; f = 800kHz; tested using the application circuit referenced in Figure 2.
LX1752
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
`
SWITCHING REGULATORS SYSTEM CHARACTERISTICS
Line Regulation
Load Regulation
VIN = 6V to 22V
0 to 5 Amps Output Load
0.5
-0.2
0.5
0.2
%
%
Note 1: X denotes the PWM Channel: 1 or 2.
Note 2: Assured by design and characterization. Not ATE tested.
Note 3: For switching frequencies less than 800kHz, minimum pulse width is defined by the formula PWMIN = 0.064 X 1/Fsw
Note 4: PSET Logic Threshold specifications are dependent on VCCL voltage level. The following formulas apply:
PSET Logic High min. threshold = 0.81 X VCCL + 0.140 (rising)
PSET Logic Low max. threshold = 0.19 X VCCL + 0.028 (rising)
Note 5: Guaranteed by design. Not ATE tested.
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Analog Mixed Signal Group
Page 6
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2)
LX1752 Line Regulation - 1 Amp Load
LX1752 Load Regulation @ VIN = 12V
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
Vout1
Vout2
% Change V1
% Change V2
5
10
15
20
25
0
1
2
3
4
5
6
Input Voltage (V)
Output Current
Line Regulation
Load Regulation
Line Regulation - VCCL
IVCCL = 20mA
LX1752 Efficiency Vs. Output Current
800kHz; Vin = 12V; Vout1 = 5.0V; Vout2 = 3.3V
100.0%
90.0%
80.0%
70.0%
60.0%
50.0%
40.0%
30.0%
20.0%
10.0%
0.0%
1.0%
0.8%
0.6%
0.4%
0.2%
0.0%
-0.2%
-0.4%
-0.6%
-0.8%
-1.0%
Vout1
Vout2
% Change
5
10
15
20
25
0
1
2
3
4
5
6
Input Voltage (V)
Output Current
VCCL Line Regulation
Efficiency Vs. Output Current
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 7
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2)
VOUT1
VOUT1
Load
Current
Load
Current
Output Load Step Response
Output Load Release Response
VOUT2
PWM
VOUT2
PWM
Inductor
Current
Inductor
Current
Short Circuit Current Limit During Hiccup Mode
Overcurrent Protection Limit - I limit set for 6.5A
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 8
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2)
VOUT1
PWM
UNIT#1
VOUT1
PWM
VOUT2
PWM
UNIT#2
VOUT1
PWM
SS1
UNIT#1
VOUT2
PWM
SS2
UNIT#2
VOUT2
PWM
Fault Hiccup Mode – VOUT2 Shorted
Dual 1752s Synchronized and Interleaved at 90° Intervals
VOUT2
VOUT2
PWM
VOUT2
PWM
Inductor
Current
EO2
EO2
Inductor
Current
VOUT2
Soft Start at Power-up
Zoom In Soft Start at Power-up
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 9
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
SIMPLIFIED BLOCK DIAGRAM
RSET
VSx
+
CSx
+5V
VIN
VCx
CIN
-
ISET
CS Comp
50uA
CS Comp
-
PWM
HOx
HRx
LOx
R
S
Q
OUT X
+
LX
CLKx
EAOx
ESR
COUT
4 CYCLE
COUNTER
PGx
VIN
Error Comp
VIN
+
-
+
Hiccup
Vref
BG
-
RAMPx
EA-x
SSx
+5V
+
Amplifier/
+5V
Regulator
+
SS COMP
Compensation
100mv
-
VCCL
+
4.7K
20K
CSS
VREF
SHDNx
F
S
UVLO
500k
FAULT
AGND
R
SSMSK
TSD
VCCL
PHASE SHIFT FROM SYNC
PSET PWM1 PWM2
CLK1
RAMP1
RAMP2
PSET
TRI - STATE
INPUT
HIGH
TRI
120
90
0
240
270
180
PSET MUX
+5V
LOW
CLK2
IRAMP
RFREQ
500
SYNC BUSS
SYNC
FREQ RAMP
HIGH &
LOW LIMIT
DETECTOR
CFREQ
Figure 1 – Simplified Block Diagram
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 10
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION CIRCUIT
E O 1
2
L O
2 3
2 4
2 5
2 6
2 7
2 8
1 4
1 3
1 2
1 1
1 0
9
- 1 E A
C L V C
S S E N 1
Q E R R F
P S E
F E V R
2
H R
H O 2
V C
T
2
2
V S
Figure 2 – LX1752 Application Schematic
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 11
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
DETAIL DESCRIPTION
An externally generated clock pulse may be used to
The LX1752 is an independent dual-output, voltage-mode,
Synchronous Buck controller integrated circuit. Output
current sensing is through RDSON measurement of the
external power MOSFETs, and is set by a single user-
programmable resistor for each output. The internal PWM
clock frequency is user programmable from 200kHz to
1.5MHz, via a single programming resistor. Synchronizing
of the internal PWM clock is possible for multiple LX1752
ICs using either an internally generated sync pulse, or a sync
signal from an external source. Synchronized LX1752 IC’s
PWM outputs can be phase positioned relative to each other
via a single pin configuration, allowing 90°, 120°, or 180°
phase separation between outputs. Each of the two LX1752
outputs has external feedback compensation, for flexibility of
output filter component selection.
synchronize multiple LX1752 ICs.
The LX1752
synchronizes to an external signal by resetting the PWM
ramp on the falling edge of the signal input at the SYNC pin.
When using an external clock for synchronizing, the external
clock should be provided through an open drain or open
collector connection, with an external pull-up resistor
between the SYNC and VCCL pins. . For proper operation,
the external clock frequency must be at least 15% higher than
the LX1752 internal PWM frequency set by RFREQ, and
external clock widths should be less than ½ the nominal
period set by RFREQ. Figure 3 and 4 are an example of an
external sync circuit and the resultant waveforms at the
moment of sync clock capture.
VCCL (LX1752 PIN 13)
OSCILLATOR FREQUENCY
The LX1752 IC’s internal PWM oscillator is user-
programmable from 200kHz to 1.5MHz. Programming is
provided by a single resistor, RFREQ, connected between the
RFREQ and GND pins. The value of this resistor is based on
the following formula:
1K
TO LX1752 SYNC PIN (PIN 2)
EXTERNAL SYNC CLOCK
1
2N7002
RFREQ(KΩ) =
−5.156
27.56E−9 ×FOSC
10K
EXTERNAL CLOCK SYNCHRONIZATION
The LX1752 provides external clock synchronization of the
PWM clock, for multiple LX1752 ICs. This feature is
implemented via a common buss connected to the LX1752
IC’s SYNC pin. The SYNC pin is an I/O pin, with an open
drain switch to ground providing the internally-generated
output sync pulse. This allows each LX1752 SYNC pin to
connect to a common buss in a wired-OR configuration. For
proper operation, a pull-up resistor between the LX1752 IC’s
VCCL and SYNC pins must be provided. The total parallel
pull-up resistance must be greater than 500 Ohms for all ICs
connected to the common buss. The total pull-up resistance
on the SYNC pins is sized such that the sync pulse rise time
is (at maximum) less than ½ the PWM clock period. Under
synchronized operation, each LX1752 is synchronized to the
falling edge of the sync pulse. Multiple LX1752 ICs will
synchronize to the controller with the highest PWM clock
frequency. For proper operation, it is advised to set one
controller’s PWM frequency 15% higher than the others to
insure it will always provide the master clock frequency.
Figure 3. External Sync Circuit
LX1752 HR1
PIN
EXTERNAL
SYNC
CLOCK
LX1752
SYNC PIN
Figure 4. LX1752 External Sync Waveforms
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LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
off, and the soft-start capacitor (CSS) is discharged at a rate
OUTPUT PHASE POSITIONING
1/25 of the soft-start rate. When the SS pin voltage decreases
to the 0.1V PWM enable threshold, the hiccup mode cycle
“off time” finishes, the output PWM is switched on, and the
circuit soft-starts again. During the soft start period, Hiccup
mode is disabled, however, cycle by cycle current limit is
functional, insuring output current is kept at the current limit
setting. Once SSENX reaches 720 mV (90% of the 800mV
SSENX pin reference voltage), if an over current condition
still exists, hiccup mode will again be initiated, the SS
capacitor will discharge, and the PWM output will be
switched off until the SS voltage decreases to 0.1V. The low
duty cycle of hiccup mode, in combination with cycle by
cycle current limiting, reduces the power dissipation of the
output MOSFETs during a fault condition, thus providing a
very reliable and robust overload and short circuit protection
The LX1752 offers phase positioning of the output PWMs.
Using two synchronized LX1752 controllers, up to four
PWM outputs may be interleaved at 90° intervals or 3 PWM
outputs at 120° intervals. Output phase positioning relative
to the SYNC pin signal can be configured via the LX1752’s
PSET pin. The PSET pin is a tri-mode input pin, whose state
determines the PWM output’s phase relationship.
PSET PIN SETTINGS
PSET
Connection
PWM 1 Position
(Relative to SYNC
pin signal)
PWM 2 Position
(Relative to SYNC
pin signal)
VCCL
OPEN
GND
120°
90°
0°
240°
270°
180°
INTERNAL LDO REGULATOR
The LX1752 contains a +5V LDO regulator for providing
power to internal circuits, external flying bootstrap
capacitors, MOSFET gate drives, and pull-up resistors for the
SYNC and SHDN pins. The +5V LDO output is available at
the VCCL pin. For proper operation, a minimum 4.7uF
capacitor is required between the VCCL and GND pins.
Total continuous LDO current should be limited to 100mA.
OVER-CURRENT PROTECTION AND HICCUP MODE
The LX1752 senses the RDS(ON) of both the upper (Control)
and the lower (Synchronous) MOSFET for current limit
detection. RDSON Sensing is done via three pins: CSX,
VSX, and PGND. The upper (Control) FET RDSON is sensed
via the CSX and VSX pins. The lower (Synchronous) FET
RDSON is sensed via the CSX and PGND pins. Current limit
is set by the resistor on the CSX pin, and is based on the
following calculation:
UNDER VOLTAGE LOCKOUT (UVLO)
At power up, the LX1752 monitors the internal LDO voltage
at the VCCL pin. The VIN supply voltage has to be
sufficient to produce a voltage greater than the UVLO
threshold at the VCCL pin before the controller will come out
of the under-voltage lock-out state. At VCCL voltages below
the UVLO threshold, Both soft-start (SS) pins are held low,
the internal PWM oscillator is disabled, and all MOSFETs
are held off.
ILIM ×RDSON(max)
RCS
=
Ics(min)
Where ICS (min) = minimum CS pin programming current
The upper and lower MOSFET current sense contain an
internal blanking circuit which delays current sensing for
150ns after their respective MOSFET is switched on. This
reduces possible false current limit detection due to ringing.
RCS values should be chosen such that delays created by the
CSX resistor and any PCB capacitance on the CSX pin are
less than 100ns; this is to insure the CSX pin voltage rises
faster than the current sense blanking time.
For best operation of the LX1752 current sense circuit, the
VSX pin and CSX resistor must be Kelvin-connected to their
respective output MOSFET Drain and Source pins. When an
over current limit is detected, a signal to reset the PWM latch
is generated, and the output PWM is truncated on a cycle by
cycle basis. After 4 continuous PWM cycles of current limit
detection, hiccup mode is started. At the initial start of
hiccup mode, the HOX output MOSFET for that phase is held
SOFT-START
Once the VCCL output is above the UVLO threshold, a
capacitor connected between the SSX and GND pins begins
charging by a 20kΩ internal resistor connected to an 800mV
reference. The capacitor voltage at the SS pin rises as a
simple RC circuit. The voltage at the SS pin controls its
respective output voltage through the error amplifier’s non-
inverting input. The output voltage will follow the SS pin
voltage if sufficient charging current is provided to the output
capacitor. Due to the exponential rise of the SSX pin voltage,
the fastest output voltage rate of rise occurs during the first
time constant of the SSX capacitor, and the internal 20KΩ
resistor. During this period, the feedback reference voltage
will reach 63% of its nominal setting. This rate of rise can be
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LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
used to calculate the average startup current seen by the and soft start can be controlled through an external signal.
inductor:
This method is useful for controlled power-up sequencing.
BUFFERED VREF OUTPUT
.63× VOUT
ISTARTUP = COUT
+ ILOAD
The LX1752 provides a buffered output of the internal
800mV reference. This output may be used as a reference for
an external LDO or any application where an 800mV
reference is required. Current is limited to a maximum of
1mA from this output.
20E3 × CSS
For lowest in-rush currents, soft start capacitors should be
sized such that the output voltage rise is slower than the input
voltage (VIN) rise during power-up.
EXTERNAL FEEDBACK AND COMPENSATION COMPONENTS
EXTERNAL PWM ENABLE
The LX1752 has pin access to each output’s respective error
amplifier inverting and output signals. This topology offers
full freedom for output filter component selection and control
loop optimization for stable high bandwidth operation. See
compensation section below.
The LX1752’s PWM outputs can be disabled externally by
holding the SSX pin below 0.1V with an open drain transistor
connected to ground. At SSX pin ≤ 0.1V, both output
MOSFETS are held off. Using this method, PWM enable
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LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
High output current may require paralleling multiple
OUTPUT INDUCTOR SELECTION
capacitors to meet output ripple requirement, as it reduces
ESR and ESL, which are the major contributors to output
ripple voltage.
The Output Inductor value is selected based on the desired
ripple current. Inductor Ripple current should be in the range
of 20% to 40% of the maximum output current. Higher
inductance values result in lower peak to peak ripple current,
at the expense of slower transient response. Lower inductor
values provide a higher current slew rate in response to a step
change in load current, however peak to peak ripple current
increases, requiring an output filter capacitor with a smaller
ESR specification to meet output ripple voltage requirements.
For step load conditions, capacitor ESR will be the dominant
factor determining the size of the initial output voltage
excursion. Capacitor ESR should be selected such that:
ESR×(IRIPPLE + ΔI) < VTRANSIENT
The Inductor value can be calculated by:
Where IRIPPLE = peak to peak inductor ripple current
VIN − VOUT
IRIPPLE
D
L =
×
ΔI is the maximum load current step change
TRANSIENT is the maximum allowed output voltage excursion
during a load step change
FSW
V
Where D = Operating Duty Cycle
FSW = PWM Switching Frequency
RIPPLE = Desired Peak to Peak Ripple Current
A second consideration when determining the output
capacitor is the minimum capacitance value required to limit
voltage overshoot during a large load release, such as a
transient from full load to no load. In this case, the output
capacitor must be large enough to absorb the excess energy
present in the inductor. Minimum output capacitance is
based on the desired maximum overshoot and output
inductor value, and is calculated by the following formula:
I
OUTPUT CAPACITOR SELECTION
The key selection parameters for the output capacitor are the
actual capacitance value, the equivalent series resistance
(ESR), the equivalent series inductance (ESL), and the
voltage rating requirements, which affect overall stability,
output ripple voltage, and step load transient response.
(ITRAN )2 × L
CMIN
=
2
2
(
VOUT + VOVERSHOOT
)
− VOUT
The output ripple has three components: variation in the
charge stored in the output capacitor, the voltage drop across
the ESR, and the voltage drop across the ESL, caused by the
current into and out of the capacitor. The following
Where ITRAN = specified maximum load transient (full load to
no load)
equations estimate the worst-case output ripple voltage:
L = output inductor value
V
OVERSHOOT = maximum allowable voltage overshoot
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL)
INPUT CAPACITOR SELECTION
RMS ripple current is the primary factor when selecting the
input capacitor. Input RMS ripple current is based on
operating duty cycle (D), and is at a maximum at D = 50%.
Where:
VRIPPLE(ESR) = IRIPPLE × ESR
The following formula is used for calculating the input RMS
current for each output:
IRIPPLE
VRIPPLE(C)
=
8×C×FSW
V ×ESL
L + ESL
IN
VOUT (VIN − VOUT
)
VRIPPLE(ESL)
=
IINRMS = IOUT(MAX)
×
VIN
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LX1752
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Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
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Supply Rail
Input (VIN
)
Input capacitance is largely dependent on the source
impedance of the power source; however, for most cases the
general rule of thumb is to use a total minimum capacitance
of 10uF for every ampere of input ripple current. This is best
achieved through a combination of ceramic capacitors placed
as close to the output FETS as possible, and an electrolytic
capacitor placed in close proximity to the LX1752 and it’s
associated circuit components.
Control to Output Section
Loop Gain
(Must = 1 at
Crossover
Frequency)
Output LC
Filter
PWM Modulator
Error Amplifier
Figure 6. Separating the Loop Components
FEEDBACK AND COMPENSATION COMPONENT SELECTION
To achieve a proper closed loop system, first the crossover
frequency is determined, after which the Control To Output
Section is analyzed for it’s gain and rolloff response at that
frequency. Once the response at the crossover frequency is
known, the error amplifier compensation components are
chosen such that the overall gain of the two sections is equal
to 1 (or 0dB) at the crossover frequency:
The LX1752 is a voltage mode controller that uses external
feedback components to establish output DC voltage and
closed-loop bandwidth. This control scheme consists of an
error amplifier, whose output controls a PWM modulator,
which in turn drives an LC filter to produce the DC output
(See Figure 5). A simple way to analyze the closed loop
system is to break the loop and separate the elements into two
sections: first, the combined PWM modulator and output LC
filter, called the Control To Output section, and second, the
Error Amplifier section (See Figure 6). Once separated, the
total gain through the two sections is analyzed.
GFC = GCTO ×GEAXO = 1
Where GFC = loop gain at crossover frequency
G
CTO = Control To Output Section Gain at crossover
frequency
G
EAXO = Error Amplifier Section Gain at crossover frequency
The LC filter creates a complex pole (-2 Slope) in the
Control To Output Section’s response, along with a zero
created by the output capacitor ESR. So, in addition to the
Gain of 1 at the crossover frequency, the phase response of
the Error Amplifier Section must be designed such that the
response of the Control To Output Section is compensated to
achieve a first order response (-1 slope) at the crossover
frequency (See Figure 7). This will insure that the phase
margin at the crossover frequency is greater than 45°. This is
accomplished by designing the Error Amplifier’s response to
counteract the pole and zero created by the output LC filter.
Supply Rail
Input (VIN
)
Output LC
Filter
Output Voltage
(VOUT
PWM Modulator
)
10
L-C Corner
Frequency
5
0
Error Amplifier
-5
-2 Slope
-10
-15
Figure 5. Voltage Mode Control Scheme
ESR-C
Corner
Frequency
-20
-25
-30
-35
-40
-1 Slope
10
100
1000
Frequency (Hz)
10000
100000
Figure 7. Output Filter Gain Vs. Frequency
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LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
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regulator output
When selecting feedback and compensation components, the
following steps are required:
1) Determine the input resistor value.
2) Determine the output voltage setting resistor.
3) Determine the Control-To-Output gain at the desired
crossover frequency.
4) Determine the Error Amplifier gain at the desired
crossover frequency.
5) Decide if Type Two or Type Three compensation is
used
6) Calculate the feedback components for the desired
compensation type.
RINPUT
Closed-loop
output voltage
will drive this
node to 0.7V
ERRAMP
_
+
Error
Vref
+
RSET
1. DETERMINE THE INPUT RESISTOR VALUE:
0.7
The input resistor is sized based on the error amplifier input
bias current specification. High bias currents can create
output voltage errors in large-value input resistors due to the
IR drop created by this current. The LX1752 has a specified
input bias current of 30nA (max.). This will generate a 30uV
Figure 8. Output DC Setting Resistors
(max.) output voltage error for every 1k ꢀ of input resistance. 3. DETERMINE THE CONTROL TO OUTPUT GAIN AT THE
This error is small enough to neglect in most cases. For this DESIRED CROSSOVER FREQUENCY:
example, use 21kꢀ (See Figure 8).
The first step in determining the control to output gain is to
decide on the closed-loop bandwidth, or crossover frequency
of the system. Bandwidths that are too wide (high crossover
frequency) can amplify switching noise. Bandwidths that are
too low will have poor transient response times.
2. DETERMINE THE OUTPUT VOLTAGE SETTING RESISTOR:
The voltage setting resistor is the resistor connected between
the error amplifier’s inverting input and ground. This
resistor, in conjunction with the input resistor, forms a DC
voltage divider that determines the output voltage level (see
Figure 8). Because the voltage divider is connected to the
input of the error amplifier, the control loop will force the DC
output voltage such that the voltage developed across the
setting resistor will equal the feedback voltage reference,
VFB. VFB for the LX1752 is specified at a nominal 0.7V at
The general rule-of-thumb is that the crossover frequency
(FC) should be no greater than 1/5th the switching frequency,
or :
FSW
room temperature. The following equation determines the (Equation 2)
voltage setting resistor:
FC ≤
5
RINPUT × 0.7
VOUT − 0.7
(Equation 1)
RSET
=
The error amplifier gain will limit the maximum crossover
frequency. The total bandwidth capable will be based on the
output filter components, the DC input voltage, and the error
amplifier gain. A good rule of thumb would be to limit the
bandwidth to 100kHz or less.
For our example, If RINPUT = 21kꢀ, and desired VOUT = 5V,
then RSET = 3.42kꢀ.
Once the crossover frequency has been determined, the next
step is to determine the total input to output gain of the
Control to Output Section at the crossover frequency. The
input to output gain expression for the Control to Output
Section is:
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LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
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2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
FP
FC
(Equation 8)
GLC
=
;FZ > FC
(Equation 3)
GCTO = V ×GPWM ×GLC
IN
Where VIN = DC input voltage to the output Mosfets
PWM = PWM Modulator Gain
LC = Output LC filter Gain
Example Calculations:
G
G
Using the application circuit:
VIN = 12V
L = 3.3uH
C= 820uF
ESR = 21mꢀ
The PWM Modulator Gain is based on the peak to peak
PWM ramp voltage, and is simply:
1
(Equation 4)
GPWM =
VRAMP
Ramp Amplitude = 1.2V
Where VRAMP = the peak to peak ramp amplitude
The LX1752 has a nominal ramp amplitude = 1.2V
Crossover Frequency = 80kHz
Using equations 5 and 6, find the pole and zero frequency
corners:
1
FP =
FZ =
= 3.06kHz
= 9.25kHz
The output LC filter creates two frequency corners in the
output response: First, a complex pole with -2 slope
(40dB/Decade) rolloff and 180° phase shift is created at the
LC resonance frequency. Second, a zero, is created at the
output capacitor and its respective Equivalent Series
Resistance (ESR) corner frequency.
2π 3.3E−6 ×820E−6
1
2π× 21E−3 ×820E−6
The ESR-capacitor zero frequency of our example is less
than the crossover frequency. Use equation 7 to determine
the LC filter gain at the crossover frequency:
These two frequency corners are found by the following
equations:
1
(Equation 5)
FP
=
3.06kHz2
= 12.65E−3
2π LC
GLC
=
9.25kHz×80kHz
And
1
The PWM Modulator gain is found using equation 4:
1
(Equation 6)
FZ
=
2π(RC)
GPWM
=
= 833E−3
Where L = Output Filter Inductor
C = Output Filter Capacitor
1.2
R = Output Filter Capacitor ESR
Using Equation 3, the total Control to Output Section gain at
the crossover can be determined:
At the crossover frequency, the LC filter’s response can be
found using the calculated pole and zero. This method of
calculating the response will depend on the relationship of the
output capacitor-ESR zero corner frequency to the chosen
crossover frequency:
GCTO = 12×833E−3 ×12.65E−3 = 126.45E−3
4. DETERMINE THE ERROR AMPLIFIER GAIN AT THE DESIRED
CROSSOVER FREQUENCY:
2
FP
Our example Control to Output Section gain is 0.12645 at the
crossover frequency. The error amplifier gain required for
unity gain at the crossover frequency will be:
(Equation 7)
GLC
=
;FZ ≤ FC
(FZ ×FC )
Or
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LX1752
®
Dual Interleaving PWM Controller
TM
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1
1
(Equation 9)
GEAXO
=
=
= 7.908
available phase margin present in the Control to Output
Section at the crossover frequency. Because Type Two
compensation does not provide an extra phase boost after the
complex LC pole, the phase boost provided by the output
capacitor – ESR combination is critical when using Type
Two compensation. Therefore, the relationship of the
complex LC pole, FP, to the ESR-capacitor zero, FZ,. becomes
126.45E−3
GCTO
Once the required Error Amplifier gain is determined, the
Error Amplifier open loop gain should be examined to assure
the Error Amplifier has enough open-loop gain at the
crossover frequency to satisfy the above gain requirement:
important:
if Fz/Fp is 5 or less, then Type Two
GEAOL
Compensation may be used. Type Three compensation
should be used otherwise.
(Equation 10) GEAXO
≤
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
GEAOL × 2π⋅FC
2π⋅FEAOL
+1
Where GEAOL = Error Amplifier Open Loop Gain
FEAOL = Error Amplifier Open Loop Bandwidth
regulator output
C3
Using the LX1752 Error Amplifier as an example:
GEAOL = 70dB, gain magnitude = 3162
R3
C1
R2
R1
F
EAOL = 10MHz
C2
ERRAMP
_
3162
3162× 2π×80kHz
2π×10MHz
= 120.24
Error
⎛
⎜
⎞
⎟
+1
+
Vref
⎝
⎠
+
R4
0.7
The above equation shows there is ample Error Amplifier
open-loop gain available at the crossover frequency.
Figure 9. Type 3 Compensation
regulator output
5. DECIDE IF TYPE TWO OR TYPE THREE COMPENSATION IS
USED.
C2
At this point, the compensation type can be decided. The two
standard methods for compensating a Voltage Mode Buck
converter are Type Two and Type Three compensation (the
name references the number of compensating slopes in the
response; Type Two has two, Type Three has three). See
C1
R2
R1
ERRAMP
Figures 9 & 10.
Both Type Two and Type Three
_
compensation are identical in that they are designed to offset
the complex pole and ESR zero of the output LC filter.
Where they differ is in the number of compensating poles and
zeros provided. Type Two compensation is known as a
“single pole-zero” compensation, in that it supplies a single
compensating zero, and a single compensating pole in the
Error Amplifier’s response. The Type Three compensation is
known as “pole-zero pair” compensation, in that it supplies
two compensating poles and two compensating zeros. The
deciding factor for which of the two methods of
compensating the loop can be used is based on the amount of
Error
+
Vref
+
R3
0.7
Figure 10. Type 2 Compensation
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LX1752
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Dual Interleaving PWM Controller
TM
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TYPE THREE COMPENSATION COMPONENT SELECTION.
4. Finally, the last compensation pole (fP2) is set equal
to 1/2 the switching frequency:
Type Three compensation contains 2 poles and 2 zeros in
the feedback loop to counteract the complex pole created by
the L-C output filter, and the zero created by the ESR -
output capacitor. Type 3 compensation should be used
when the desired crossover frequency is lower than the ESR
zero frequency, or when it is higher than the ESR zero
frequency and the ESR zero frequency is higher than 4 to 5
times the output LC filter corner frequency. Typical
feedback response is shown in Figure 11.
FSW
(Equation 14)
fP 2 =
2
In order for the feedback response to be correct, the feedback
loop must be set to two gain levels, GFB1, and GFB2
GFB2 is the highest gain value of the two levels, and is the
gain required to boost the control to output gain to 1 at the
crossover frequency. GFB2 is established after the first
compensation pole frequency (fP1), and is the complement of
the total control to output gain (GCTO) at the selected
crossover frequency:
100
90
80
70
60
50
40
30
1
(Equation 15)
GFB 2 =
GCTO
GFB1 is the gain level established after the first compensation
zero frequency (fz1). GFB1 gain is derived from the crossover
frequency gain (GFB2). The method for calculating GFB1 is
dependent on whether the output capacitor – ESR zero corner
frequency is greater or less than the crossover frequency.
G
FB2
fp1
fp2
20
10
0
G
FB1
fz1
fz2
1
10
100
1000
Frequency (Hz)
10000
100000
1000000
Crossover
Frequency (FC)
Condition 1; FZ ≤ FC
Figure 11. Typical Type 3 Feedback Response
⎛
⎞
fZ 2
fP1
⎜
⎜
⎟
⎟
(Equation 16)
GFB1= GFB 2×
⎝
⎠
To calculate the values, first the two compensation zeros and
two compensation poles must be set.
Condition 2; FC ≤ FZ
The two compensation zeros are set to counteract the
complex L-C pole at two locations, both multiples of the
complex L-C pole:
This condition occurs when the capacitor-ESR zero
frequency corner is greater than the chosen cutoff frequency.
This is a common condition with ceramic output capacitors.
For this condition, GFB1 is found by:
1. Set the first compensation zero frequency (fz1) to
the L-C pole/4:
F
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
P
fZ 2
FC
(Equation 11)
fZ1=
(Equation 17)
GFB1= GFB 2×
4
2. Set the second compensation zero frequency (fZ2)
equal to the L-C pole frequency:
To calculate the compensation component values (Reference
Figure 9):
(Equation 12)
fZ 2 = F
P
First, select resistor R1. This topic is covered under
“Determine the Input Resistor Value” on page 17. Resistor
R4 may be selected at this time; however it is for setting the
output DC level only, and is not used in the compensation
calculations. R4 is covered under “Determine the Output
Voltage Setting Resistor” on page 17.
3. Next, the first compensation pole (fP1) is set equal to
the ESR - capacitor zero frequency:
(Equation 13)
fP1= FZ
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LX1752
®
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Next, calculate the value of R2; R1 & R2 will set the gain for
GFB1:
•
•
Capacitor ESR = 5.5mꢀ (2 capacitor ESR values of
11mꢀ in parallel)
Crossover Frequency = 80kHz
(Equation 18)
R2 = R1× GFB1
Calculate the value for C1; C1 & R2 set the first zero Referencing Figure 7:
frequency:
Step 1 – Determine the input resistor (R1) value:
1
(Equation 19)
C1=
Keep the input resistor value as low as practical to
reduce input bias errors. For this example, choose
10.7kꢀ 1% (1% part for DC output voltage
accuracy).
2π(fZ1)R2
The next value is for R3; R3||R1 & R2 set the gain for GFB2:
Step 2 – Determine the DC output “setting” resistor (R4):
Using Equation 1, and the values chosen for RINPUT
R1×R2
(Equation 20)
R3 =
(
R1× GFB 2 − R2
)
and VOUT
:
RSET (R4) = 13.6kꢀ. Use 13.7kꢀ 1% (1% part for
DC output voltage accuracy).
Calculate C2; C2 & R1 + R3 set the second zero frequency:
1
Step 3 – Determine the Control to Output Section Gain:
Using Equation 5, and the values chosen for L and C:
FP = 1.96kHz
(Equation 21)
C2 =
2π(fZ 2)(R1+ R3)
Finally, the value for C3 + C1 & R2 sets the second pole
frequency:
Using Equation 6, and the values chosen for ESR and
C:
FZ = 9.65kHz
C1
(Equation 22) C3 =
The ESR – Capacitor zero frequency is less than the
chosen crossover frequency. Use Equation 7 to
calculate the gain of the LC filter section:
GLC = 4.974E-3
Using Equation 4, PWM modulator gain is:
GPWM = 0.833
(2π(fP 2)⋅ C1⋅R2) −1
The first pole frequency, fP1, will be correct with the values
chosen. To verify:
1
Finally, using Equation 3 and the chosen VIN value
of 3.4V:
(Equation 23) fP1=
2π(R3C2)
GCTO = 14.086E-3
Example Calculations:
Step 4 - Determine required Error Amplifier Gain:
Using Equation 9, the required Error Amplifier Gain:
GEAXO = 71
Assume the following design parameters and component
values:
Use Equation 10 to determine the Error Amplifier
open-loop gain at the crossover frequency:
GEAXO ≤ 120.2
•
•
•
•
•
•
•
•
VIN = 3.4V
VOUT = 1.24V
Based on equation 10, there is enough gain available.
Step 5 – Determine Type Two or Type Three compensation:
For this example, FZ/FP is greater than 4. We will use
Type Three Compensation.
Step 6 – Select Type Three components (reference Figure 9):
VRAMP = 1.2V
PWM frequency = 800kHz
Error Amplifier Gain = 3162 (70dB)
Error Amplifier Bandwidth = 10MHz
Output Inductor (L) = 2.2uH
Using Equations 11 through 14, determine the
compensation frequency components:
fz1 = 490Hz
Output Capacitor (C) = 3000uF (2 X 1500uF
capacitors in parallel)
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
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Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
fz2 = 1.96kHz
fp1 = 9.65kHz
fp2 = 400kHz
Figure 13 is the Bode Plot of the closed loop response of our
example.
Overall Loop Gain & Phase
Calculate the highest of the two feedback gains using
Equation 15:
GFB2 = 71
The ESR – Capacitor zero frequency is less than the
chosen crossover frequency. Use Equation 16 to
calculate the lower of the two feedback gains:
150
100
50
GFB1 = 14.4
Using Equations 18 through 22, calculate the values
for the compensation components:
0
R2 = 154kꢀ; use 150kꢀ 5%
R3 = 2.72kꢀ; use 2.7kꢀ 5%
C1 = 2.11nF; use 2.2nF
50
100
C2 = 6.05nF; use 5.6nF
C3 = 2.6pF; too small; omit this capacitor.
150
In this example, C3 value of 2.6pF is far too small to be of
practical use. In this case it may be omitted without any
consequence. If the additional roll off provided by C3 is still
desired, the value of RINPUT (R1) may be set lower, and the
feedback components recalculated. This will raise the value
of C3. As an alternative, set FP2 to a lower frequency,
however do not set lower than 1.5 X the crossover frequency
(FC). Figure 12 is the schematic of the example feedback
compensation.
3
4
5
6
.
.
.
.
1 10
10
100
1 10
1 10
1 10
Frequency
Gain
Phase
Figure 13. Bode Plot of Example Circuit
regulator output
Not
Used
C3
R3
2.7k
5%
R2
R1
2.2n
C1
10.7k
1%
C2
150k
5%
5.6n
ERRAMP
_
+
Error
R4
13.7k
1%
Vref
+
0.7
Figure 12. Example Circuit Feedback and
Compensation
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
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Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
As in Type 3 Compensation, establish the frequency corners:
TYPE TWO COMPENSATION COMPONENT SELECTION.
1. Set the first compensation zero frequency (fz1) to
the L-C pole/4:
Type Two compensation contains a single zero and pole in
the feedback loop to counteract the complex pole created by
the L-C output filter. This type of compensation does not
provide an extra phase boost after the complex LC pole
frequency, which is provided by Type 3 compensation. This
type of compensation is used when the phase margin of the
Control to Output section is greater than the minimum closed
loop phase margin desired at the crossover frequency.
Typical frequency response is shown in Figure 14.
F
P
(Equation 24)
fZ1=
4
2. Set the compensation pole (fP1) equal to 1/2 the
switching frequency:
FSW
(Equation 25)
fP1=
2
100
90
80
70
60
50
40
30
Type Two compensation has only one gain level to be
concerned with. This is the gain required to boost the control
to output gain to 1 at the crossover frequency:
1
(Equation 26)
GFB =
GCTO
To calculate the compensation component values (Reference
Figure 8):
GFB
First, select resistor R1. This topic is covered under
“Determine the Input Resistor Value” on page 15. Resistor
R3 may be selected at this time; however it is for setting the
output DC level only, and is not used in the compensation
calculations. R3 is covered under “Determine the Output
Voltage Setting Resistor” on page 16.
fp1
20
10
fz1
0
1
10
100
1000
10000
100000
Crossover
Frequency (FC)
1000000
Frequency (Hz)
Figure 14. Typical Type 2 Feedback Response
Next, calculate the value of R2; R1 & R2 will set the gain for
GFB:
The component values for Type 2 compensation are found
using identical equations and methods as in Type 3. The
main differences are that Type 2 has only one gain level, one
compensating zero, and one compensating pole to calculate.
(Equation 27)
R2 = R1× GFB
Calculate the value for C1; C1 & R2 set the compensating
zero frequency:
1
(Equation 28)
C1=
2π(fZ1)R2
Finally, the value for C2 + C1 & R2 sets the compensating
pole frequency:
C1
(Equation 29)
C2 =
(2π(fP1)⋅ C1⋅R2) −1
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
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Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
OUTPUT MOSFET SELECTION
For conduction losses in the Control (Upper) FET, channel
loss is the only concern (under normal operation the body
diode does not conduct). Channel loss is due to the IR drop
When selecting output MOSFETs, There are five important
parameters to be concerned with: Maximum VDS rating,
Maximum Drain Current rating, RDSON, Total Gate Charge,
and Maximum Power Dissipation.
across the MOSFET’s RDSON
. When calculating channel
loss, RDSON should be specified at the maximum junction
temperature of the FET. Most datasheets specify RDSON at
25°C, and provide a graph for estimating the RDSON at a
specific junction temperature. Channel loss for the upper
FET (PDRDS(CONTROL)) can be calculated with the following
formula:
The upper and lower MOSFET positions, in many cases, can
be satisfied with the same part value FET, making the use of
dual MOSFET packages attractive. However, in cases where
output current and switching frequency are high, the
MOSFET chosen for the upper (Control) FET may differ
from the lower (Synchronous) FET.
(Equation 30)
2
ILOAD
)
×RDS0N × VOUT
PDRDS(CONTROL) (W) =
VIN
For example, in a high frequency switcher application, the
power dissipated in the Control FET may be more dependent
on switching losses, in which case a FET with a lower total
gate charge (Qg) should be considered. The opposite is true
for the Synchronous FET, where conduction losses may be
the dominating factor in the total power dissipation. In this
case a FET with a lower RDSON would be considered.
Note: specify RDSON at maximum junction temperature.
For conduction losses in the Synchronous (Lower) FET, both
channel and body diode losses must be considered. As in the
Control FET calculations, channel loss is a function of
RDSON, and should be evaluated using the specified RDSON
at the part’s specified maximum junction temperature:
The maximum VDS rating of the MOSFET should exceed by
at least 10% the maximum DC input voltage, plus any
voltage transients that might be present on the DC line, over
all operating temperatures.
The maximum drain current rating of the MOSFET should be
chosen to cover all operating current conditions, at all
operating temperatures. Overcurrent limits, and current
spikes should all be considered before selecting a MOSFET.
(Equation 31)
⎛
⎞
VOUT
VIN
2
⎜
⎟
⎟
PDRDS(SYNC) (W) =
(
ILOAD
)
×RDS0N × 1−
⎜
⎝
⎠
Note: specify RDSON at maximum junction temperature.
In addition to channel loss, body diode conduction loss must
be considered. Body diode conduction loss (PDBD) is found
using the following equation:
RDSON and total gate charge should always be as small as
possible. RDSON and total gate charge (Qg) will vary
inversely with each other; ie. lower gate charges typically are
at the expense of higher RDSON ratings.
(Equation 32)
PDBD(SYNC)(W) = 2×ILOAD × VF × TDT ×FSW
Where VF = Body Diode Forward Voltage
TDT = PWM output dead time
MOSFETs must be chosen such that their maximum power
dissipation is not exceeded at any time in the application, and
that the junction temperature for the device does not exceed
the maximum rating for the part under all conditions. The
power dissipation of the MOSFET will depend largely on two
principle factors affecting loss: conduction losses, and
switching losses.
FSW = PWM output switching frequency
Switching losses for the Synchronous FET are limited to the
gate input losses due to the input capacitance (CISS). PDCISS
is found by:
(Equation 33)
2
At lower frequency switching, conduction losses make up the
bulk of the total power dissipation in the MOSFETs. Two
factors determine conduction losses: channel conduction
losses (for both Control and Synchronous FETs), and body
diode conduction losses (Synchronous FET only).
PDCISS(SYNC) (W) = 0.5 × CISS
×
(
VGS
)
× FSW
Where VGS = peak gate drive voltage
Most datasheets specify CISS in a graph of capacitance vs.
VDS. Due to the zero voltage switching of the Synchronous
FET, CISS should be chosen at VDS = 0 for this calculation.
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
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Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
Total power loss in the Synchronous FET will be the sum of
the conduction and the switching losses:
Where:
F
SW = PWM switching frequency
RGATE = gate input resistance
(Equation 34)
Where QG = total gate charge (datasheet value)
VGS = peak gate drive voltage
PD(SYNC)(W) = PDRDS(SYNC) +PDBD(SYNC) + PDCISS(SYNC)
RDRIVE = high side driver on resistance
Switching losses in the Control FET are due to overlap
switching loss, gate input loss, losses due to MOSFET
capacitances, and Synchronous FET body diode reverse
recovery charge.
Losses due to Synchronous FET reverse body diode recovery
are based on QRR, a parameter not clearly defined in most
datasheets. A good rule of thumb would be to increase the
total power dissipation due to switching loss by 20% to
account for losses due to QRR and MOSFET capacitances.
The total Control FET switching loss would be the sum of
the losses, increased by 20%:
To calculate overlap switching loss, first the average gate
current must be calculated. This is found through by the
average of the upper and lower drive RDSON, added to the
MOSFET internal gate resistance, which is specified on most
datasheets. If not specified, 2.0 Ohms may be substituted. In
the LX1752, the average drive on-resistance is 3.0ꢀ.
Average gate current can now be found by:
(Equation 39)
PDSW(CONTROL)
=
PDOLS + PDGATE ×1.2
)
Total power dissipation in the Control FET can now be
calculated:
VGS
(Equation 35) IG = 0.5 ×
RDRIVE + RGATE
Where RDRIVE = average controller gate drive On resistance
RGATE = MOSFET gate resistance
(Equation 40)
PDCONTROL (W) = PDSW(CONTROL) + PDRDS(CONTROL)
Once average gate current is known, the next step is to
calculate the average gate switching time:
Once the power dissipations of both MOSFETS are known,
the operating junction temperatures can be calculated using
thermal resistance specifications contained in the MOSFET
datasheet.
QGS2 + QGD
(Equation 36) TS =
IG
Where QGS2 is the portion of gate to source gate charge after
the gate reaches Vth to the plateau of the gate charge curve,
and QGD is MOSFET gate-drain charge. Refer to the
MOSFET datasheet for more detail.
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Careful attention to PCB layout is necessary to insure proper
operation with minimal noise generation. When laying out
the PCB, these guidelines should be followed:
1) Keep the input capacitor, output capacitor, output
inductor and output MOSFETs (upper and lower), close
together, and tie all high current output returns directly
to a suitable power ground plane.
With switching time (TS), load current, PWM frequency, and
maximum VIN known, overlap switching loss can be
calculated by:
2) Keep the high current ground return paths separate from
the signal return paths. It is recommended that a
separate signal ground plane be used, with a common tie
point between the power ground plane and the signal
ground plane established at the IC signal ground pin.
(Equation 37) PDOLS = IOUT × TS × VIN ×FSW
Gate input loss (PDGATE) is found by:
3) Place the input decoupling capacitor has close to the
upper and lower MOSFETs as practical. Connections
between this capacitor and the upper and lower
MOSFET’s Drain and Source connections should be as
(Equation 38)
RGATE
PDGATE = QG × VGS ×FSW
×
RDRIVE + RGATE
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 25
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
short as practical.
9) Stray capacitance to ground on CSx pins should be
minimized. If possible, remove ground and power
planes in the area directly below CSX pins, and place
each respective CSX resistor as close to the LX1752 as
practical; preferably on the same PCB side as the
LX1752.
4) The LDO filter capacitor should be placed as close to the
VCCL pin as practical.
5) PGND connection to the Source pin of the Lower
MOSFET should be as short as practical, and should be
established with a direct connection (using no vias) if
possible.
6) VSX Pin connections should be Kelvin connected
directly at the Upper MOSFET’s drain pin(s).
7) HRX connection to the Upper MOSFET’s Source pin
should be as short as practical, and should be established
with a direct connection (using no vias) if possible.
10) Place all compensation and feedback components as
close to their respective error amplifier pins as practical.
Keep the error amplifier input connections (EAX-) as
short as possible.
11) Place the frequency programming resistor, RFREQ as
close to the RFREQ and GND pins as practical.
12) Refer to the Evaluation Board for an example of the
PCB layout.
8) LOX and HOX should be connected to their respective
MOSFET gate pins with as short a trace as practical, and
should be established with a direct connection (using no
vias) if possible.
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
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Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
PACKAGE DIMENSIONS
28-Pin 4x5mm
LQ
D
MILLIMETERS
INCHES
Dim
MIN
0.80
0.00
0.20 REF
0.20 REF
0.50 BSC
MAX
1.00
0.02
MIN
0.031
0
0.008 REF
0.008 REF
0.02 BSC
MAX
0.039
0.008
A
L
D2
A1
A3
K
E
E2
K
e
L
b
D2
E2
D
0.30
0.50
0.30
2.75
3.75
0.012
0.02
0.012
0.108
0.148
0.18
2.50
3.50
4.00 BSC
5.00 BSC
0.007
0.098
0.138
0.158 BSC
0.197 BSC
b
e
A3
A
E
A1
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Page 27
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1752
®
Dual Interleaving PWM Controller
TM
PRODUCTION DATA SHEET
NOTES
PRELIMINARY DATA – Information contained in this document is pre-production data
and is proprietary to Microsemi. It may not be modified in any way without the express
written consent of Microsemi. Product referred to herein is offered in pre-production form
only and may not have completed Microsemi’s Quality Assurance process for Release to
Production. Microsemi reserves the right to change or discontinue this proposed product
at any time.
Copyright © 2007
Rev. 1.0, 2008-07-31
Microsemi
Analog Mixed Signal Group
Page 28
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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