M1A3P1000L-1PQ208I [MICROSEMI]

Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, 24576-Cell, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208;


型号：	M1A3P1000L-1PQ208I
厂家：	Microsemi
描述：	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, 24576-Cell, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208 栅
文件：	总242页 (文件大小：11392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Revision 13

ProASIC3L Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

•

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os Programmable Output

Slew Rate and Drive Strength

Low Power

•

Dramatic Reduction in Dynamic and Static Power Savings

1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry to / Exit from Low-Power Flash*Freeze

Mode

•

Supports Single-Voltage System Operation

Low-Impedance Switches

High Capacity

•

250,000 to 3,000,000 System Gates

Up to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

•

Reprogrammable Flash Technology

•

Programmable Input Delay (A3PE3000L only)

Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

Weak Pull-Up/-Down

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

•

Instant On Level 0 Support

IEEE 1149.1 (JTAG) Boundary Scan Test

Single-Chip Solution

Retains Programmed Design when Powered Off

Pin-Compatible Packages across the ProASIC 3L Family

(except PQ208)

High Performance

Clock Conditioning Circuit (CCC) and PLL

•

350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

•

Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All

with Integrated PLL (ProASIC3EL)

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems))

•

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

SRAMs and FIFOs

•

FlashLock to Secure FPGA Contents

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

High-Performance Routing Hierarchy

•

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous

Operation:

•

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

– 250 MHz: For 1.2 V systems

Advanced and Pro (Professional) I/Os

– 350 MHz: For 1.5 V systems

•

700 Mbps DDR, LVDS-Capable I/Os

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

ARM^®Processor Support in ProASIC3L FPGAs

•

ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1 • ProASIC3 Low-Power Product Family

ProASIC3L Devices

A3P250L

A3P600L

A3P1000L

A3PE3000L

ARM Cortex-M1

Devices ¹

M1A3P600L

M1A3P1000L

M1A3PE3000L

System Gates

250,000

600,000

13,824

108

1,000,000

3,000,000

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

6,144

24,576

144

75,264

504

112

FlashROM Kbits

Secure (AES) ISP

Yes

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

157

235

300

620

Package Pins

VQFP

VQ100

PQ208

FG144, FG256

PQFP

PQ208

FG144, FG256, FG484

PQ208

FG144, FG256, FG484

PQ208

FBGA

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM Cortex-M1 ProASIC3L devices.

3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

January 2013

ProASIC3L Low Power Flash FPGAs

I/Os Per Package

ProASIC3L

Low-Power

Devices

A3P250L ²

A3P600L

A3P1000L

A3PE3000L

ARM

Cortex-M1

Devices

M1A3P600L

M1A3P1000L

M1A3PE3000L ³

I/O Type

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Package

VQ100

PQ208

FG144

FG256

FG324

FG484

FG896

Notes:

Ended I/O ⁴

151

157

–

154

177

–

154

177

–

147

–

221

341

620

110

168

310

–

235

–

300

–

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure

you are complying with design and board migration requirements.

2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.

3. ARM Cortex-M1 support is TBD on this device.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. FG256 and FG484 are footprint-compatible packages.

6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the part

number.

7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user

I/Os available is reduced by one.

Table 2 • ProASIC3L FPGAs Package Sizes Dimensions

Package

VQ100

PQ208

FG144

FG256

FG324

FG484

FG896

Length × Width

(mm\mm)

14 × 14

28 × 28

13 × 13

17 × 17

19 × 19

23 × 23

31 × 31

Nominal Area

(mm²)

196

784

169

289

361

529

961

Pitch (mm)

0.5

1.0

Height (mm)

1.00

3.40

1.45

1.60

1.63

2.23

Revision 13

ProASIC3L Low Power Flash FPGAs

ProASIC3L Ordering Information

A3P1000L

144

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

Package Type

Very Thin Quad Flat Pack (0.5 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

Part Number

ProASIC3L Devices

A3P250L = 250,000 System Gates

A3P600L = 600,000 System Gates

A3P1000L = 1,000,000 System Gates

A3PE3000L= 3,000,000 System Gates

ProASIC3L Devices with Cortex-M1

M1A3P600L = 600,000 System Gates

M1A3P1000L = 1,000,000 System Gates

M1A3PE3000L = 3,000,000 System Gates

Revision 13

III

ProASIC3L Low Power Flash FPGAs

Temperature Grade Offerings

Package

ARM Cortex-M1 Devices

VQ100

A3P250L

A3P600L

A3P1000L

A3PE3000L

M1A3P600L

M1A3P1000L

M1A3PE3000L

C, I

–

PQ208

C, I

–

C, I

–

C, I

FG144

FG256

FG324

C, I

FG484

–

C, I

–

C, I

–

FG896

–

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

Speed Grade and Temperature Grade Matrix

Temperature Grade

Std.

–1

C ¹

I ²

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

ProASIC3L Device Status

ProASIC3L Devices

Status

M1 ProASIC3L Devices

Status

A3P250L

Production

A3P600L

A3P1000L

A3P3000L

M1A3P600L

M1A3P1000L

M1A3P3000L

Production

Contact your local Microsemi SoC Products Group representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Revision 13

ProASIC3L Low Power Flash FPGAs

Table of Contents

ProASIC3L Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3L DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Package Pin Assignments

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Revision 13

1 – ProASIC3L Device Family Overview

General Description

The ProASIC3L family of Microsemi flash FPGAs dramatically reduces dynamic power consumption by

40% and static power by 50% compared to the equivalent ProASIC3 device. These power savings are

coupled with performance, density, true single-chip, 1.2 V to 1.5 V core and I/O operation as low as

1.2 V, reprogrammability, and advanced features.

Using Microsemi's proven Flash*Freeze technology enables users to shut off dynamic power

instantaneously and switch the device to static mode without the need to switch off clocks or power

supplies while retaining internal states of the device. This greatly simplifies power management on a

board done through I/Os and clocks. In addition, optimized software tools using power-driven layout

provide instant push-button power reduction.

Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power,

single-chip solution that is Instant On. ProASIC3L offers dramatic dynamic power savings giving the

FPGA users flexibility to combine low power with high performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). ProASIC3L devices

support devices from 250 k system gates to 3 million system gates with up to 504 kbits of true dual-port

SRAM and 620 user I/Os.

M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and

speed when implemented in an M1 ProASIC3L device. The processor runs the ARMv6-M instruction set,

has a configurable nested interrupt controller, and can be implemented with or without the debug block.

ARM Cortex-M1 is available for free from Microsemi for use in M1 ProASIC3L FPGAs.

The ARM-enabled devices have Microsemi SoC Products Group ordering numbers that begin with M1

and do not support AES decryption.

Flash*Freeze Technology

The ProASIC3L devices offer Microsemi's proven Flash*Freeze technology, which allows instantaneous

switching from an active state to a static state. ProASIC3L devices do not need additional components to

turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V) allows for an even greater

reduction in power consumption, which enables low total system power.

When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is

retained.

The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in portable

media, secure communications, radio applications as well as high performance portable, industrial, test,

scientific, and medical applications.

Revision 13

1-1

ProASIC3L Device Family Overview

Flash Advantages

Low Power

The ProASIC3L family of Microsemi flash-based FPGAs provide a low-power advantage, and when

coupled with high performance, enables designers to make power-smart choices using a single-chip,

reprogrammable, and Instant On device.

ProASIC3L devices offer 40% dynamic power and 50% static power savings compared to the equivalent

ProASIC3 device by reducing the core operating voltage to 1.2 V. In addition, the Power Driven Layout

(PDL) feature in Libero^®System-on-Chip (SoC) offers up to 30% additional power reduction over the

standard timing-driven place-and-route (TDPR). With Flash*Freeze technology, ProASIC3L devices are

able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to

stop clock or power supplies. Combining these features provides a low-power, feature-rich and high-

performance solution.

Security

Nonvolatile, flash-based ProASIC3L devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which provides

a unique combination of reprogrammability and design security without external overhead, advantages

that only an FPGA with nonvolatile flash programming can offer.

ProASIC3L devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level

of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in ProASIC3L devices can be encrypted prior to loading, using the industry-

leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National

Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3L

devices have a built-in AES decryption engine and a flash-based AES key that make them the most

comprehensive programmable logic device security solution available today. ProASIC3L devices with

AES-based security provide a high level of protection for remote field updates over public networks such

as the Internet, and are designed to ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3L family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. The ProASIC3L family, with FlashLock and AES security, is

unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected

with industry-standard security, making remote ISP possible. A ProASIC3L device provides the best

available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3L FPGAs

do not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

Instant On

Flash-based ProASIC3L devices support Level 0 of the Instant On classification standard. This feature

helps in system component initialization, execution of critical tasks before the processor wakes up, setup

and configuration of memory blocks, clock generation, and bus activity management. The Instant On

feature of flash-based ProASIC3L devices greatly simplifies total system design and reduces total

system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and

brownouts in system power will not corrupt the ProASIC3L device's flash configuration, and unlike

SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This

enables the reduction or complete removal of the configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3L devices

simplify total system design and reduce cost and design risk while increasing system reliability and

improving system initialization time.

1-2

Revision 13

ProASIC3L Low Power Flash FPGAs

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3L devices allow all functionality to be Instant On; no external boot

PROM is required. On-board security mechanisms prevent access to all the programming information

and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

reprogramming to support future design iterations and field upgrades with confidence that valuable

intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-

standard AES algorithm. The ProASIC3L family device architecture mitigates the need for ASIC

migration at higher user volumes. This makes the ProASIC3L family a cost-effective ASIC replacement

solution, manipulation in portable media and secure communications, radio applications as well as high

performance portable Industrial, test, scientific and medical applications.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-based

FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs cannot be

altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and

correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The ProASIC3L family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3L architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3L device consists of five distinct and programmable architectural features (Figure 1-1 on

page 1-4 and Figure 1-2 on page 1-4):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT)

equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric.

The VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs.

VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

Revision 13

1-3

ProASIC3L Device Family Overview

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600L and A3P1000L)

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 2

Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L,

and A3P1000L)

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Figure 1-2 • ProASIC3EL Device Architecture Overview

1-4

Revision 13

ProASIC3L Low Power Flash FPGAs

Flash*Freeze Technology

The ProASIC3L devices offer Microsemi's proven Flash*Freeze technology, which enables designers to

instantaneously shut off dynamic power consumption while retaining all SRAM and register information.

Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by

activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition,

I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks

can still be driven or can be toggling without impact on power consumption; and the device retains all

core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can

be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is

consumed by the I/O banks, clocks, JTAG pins, or PLL. Flash*Freeze technology allows the user to

switch to active mode on demand, thus simplifying the power management of the device.

The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is

safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode

usage is not planned, which is advantageous because of the inherent low-power static and dynamic

capabilities of the ProASIC3L device. Refer to Figure 1-3 for an illustration of entering/exiting

Flash*Freeze mode.

ProASIC3L

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-3 • ProASIC3L Flash*Freeze Mode

VersaTiles

The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The ProASIC3L VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

Data

CLK

CLR

LUT-3

D-FF

CLK

D-FF

Enable

CLR

Figure 1-4 • VersaTile Configurations

Revision 13

1-5

ProASIC3L Device Family Overview

User Nonvolatile FlashROM

ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can

be used in diverse system applications:

•

Internet Protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard ProASIC3L IEEE 1532 JTAG programming interface.The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3L development software solutions, Libero SoC and Designer, have extensive support for

the FlashROM. One such feature is auto-generation of sequential programming files for applications

requiring a unique serial number in each part. Another feature allows the inclusion of static data for

system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC

and Designer software tools. Comprehensive programming file support is also included to allow for easy

programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit port and

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each

member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC

(center west side) has a PLL.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

1-6

Revision 13

ProASIC3L Low Power Flash FPGAs

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time is 300 µs

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}

Global Clocking

ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The ProASIC3L family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O standards,

including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized

into banks, with two, four, or eight (ProASIC3EL only) banks per device. The configuration of these banks

determines the I/O standards supported (Table 1-1). For ProASIC3EL, each I/O bank is subdivided into

VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All

the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank

is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference

voltage.

Table 1-1 • I/O Standards Supported

I/O Standards Supported

Device and

Bank

GTL+ 2.5 V/3.3 V, GTL

2.5 V/3.3 V, HSTL I and II,

LVTTL/

PCI/

LVPECL, LVDS,

I/O Bank Type

Pro I/Os

Location

LVCMOS PCI-X B-LVDS, M-LVDS SSTL2 I and II, SSTL3 I and II

A3PE3000L

Advanced I/Os

A3P250L,

A3P600L,

A3P1000L

Not supported

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up

to 20 loads.

Revision 13

1-7

ProASIC3L Device Family Overview

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support both

the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to

3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States

During Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-5 on page 1-9).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States during programming are saved to the ADB and resulting programming files after

completing programming file generation.

1-8

Revision 13

ProASIC3L Low Power Flash FPGAs

Figure 1-5 • I/O States During Programming Window

Revision 13

1-9

2 – ProASIC3L DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

VJTAG

VPUMP

Programming voltage

VCCPLL Analog power supply (PLL)

VCCI and DC I/O buffer supply voltage

VMV ²

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

T_STG

Storage temperature

Junction temperature

–65 to +150

+125

°C

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

Revision 13

2-1

ProASIC3L DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_A

Parameter

Commercial

0 to +70

Industrial

–40 to +85

–40 to +100

1.14 to 1.575

1.4 to 3.6

Units

°C

Ambient temperature

Junction Temperature

T_J

0 to + 85

VCC ²

VJTAG

VPUMP ⁵

1.2 V–1.5 V wide range core voltage ³

1.14 to 1.575

1.4 to 3.6

3.15 to 3.45

0 to 3.6

JTAG DC voltage

Programming voltage

Programming Mode ⁴

Operation ⁵

3.15 to 3.45

0 to 3.6

VCCPLL ⁶

Analog power supply (PLL)

1.2 V–1.5 V wide range 1.14 to 1.575

core voltage ³

1.14 to 1.575

VCCI

and 1.2 V DC supply voltage⁸

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V wide range DC supply voltage⁹

3.3 V DC supply voltage

LVDS differential I/O

1.14 to 1.26

VMV ⁷

1.425 to 1.575 1.425 to 1.575

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

2.375 to 2.625 2.375 to 2.625

3.0 to 3.6 3.0 to 3.6

LVPECL differential I/O

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-14 on page 2-10. VCCI should be at the same voltage within a given I/O bank.

3. All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V.

4. The programming temperature range supported is T

= 0°C to 85°C.

ambient

5. VPUMP can be left floating during normal operation (not programming mode).

6. VCCPLL pins should be tied to VCC pins. See the "VCCPLA/B/C/D/E/F PLL Supply Voltage" section on page 3-1 for

further information.

7. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

8. For ProASIC 3L devices, VCCI VCC.

9. 3.3 V wide range is compliant to the JESD8-A specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature¹

Product

Grade

Programming Program Retention

Maximum Storage

Maximum Operating

Cycles

(biased/unbiased) Temperature T_STG(°C) ²Junction Temperature T_J(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

500

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

2-2

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot²

VCCI

2.7 V or less

10%

1.4 V

1.49 V

1.1 V

3 V

10%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of

two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI_.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Revision 13

2-3

ProASIC3L DC and Switching Characteristics

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup

behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-

2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low-Power Flash Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

VCCI

Activation trip point:

= 0.9 V ± 0.3 V

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Deactivation trip point:

= 0.8 V ± 0.3 V

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 13

ProASIC3L Low Power Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Activation trip point:

= 0.85 V ± 0.2 V

Deactivation trip point:

Region 1: I/O buffers are OFF

= 0.75 V ± 0.2 V

VCCI

Activation trip point:

= 0.9 V ± 0.15 V

Deactivation trip point:

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

= 0.8 V ± 0.15 V

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Revision 13

2-5

ProASIC3L DC and Switching Characteristics

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction temperature to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C

------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------

= 1.463 W

Maximum Power Allowed =

_ja(C/W)

20.5C/W

EQ 2

Table 2-5 • Package Thermal Resistivities

_ja

Package Type

Device

Pin Count _jcStill Air 200 ft./min. 500 ft./min. Units

Very Thin Quad Flat Pack (VQFP)

Plastic Quad Flat Pack (PQFP)

PQFP with embedded heatspreader

Fine Pitch Ball Grid Array (FBGA)

All devices

A3P250L

100

208

144

256

324

484

896

10.0

8.0

35.3

26.1

16.2

43.8

35.8

31.6

38.6

32.0

28.1

TBD

27.5

23.3

20.6

13.6

29.4

22.5

13.3

37.7

30.2

26.2

34.7

27.5

24.4

TBD

21.9

19.0

15.7

10.4

27.1

20.8

11.9

35.8

28.3

24.2

33.0

25.8

22.7

TBD

20.2

16.7

14.0

9.4

C/W

3.8

12.2

8.3

A3P600L

A3P1000L

A3P250L

6.3

12.0

8.5

A3P600L

A3P1000L

AGLE3000

A3P600L

6.6

TBD

9.5

A3P1000L

A3PE3000L

8.0

4.7

2.4

2-6

Revision 13

ProASIC3L Low Power Flash FPGAs

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, VCC = 1.14 V)

Junction Temperature (°C)

Array Voltage VCC (V)

–40°C

0.90

0.87

0.83

0.81

0.78

0.75

0.74

0.70

0.67

0°C

0.94

0.90

0.86

0.84

0.81

0.78

0.77

0.72

0.70

25°C

0.96

0.92

0.88

0.86

0.83

0.80

0.78

0.74

0.72

70°C

1.00

0.96

0.92

0.90

0.87

0.83

0.82

0.77

0.75

85°C

1.01

0.97

0.93

0.91

0.88

0.84

0.83

0.79

0.76

110°C

1.03

0.99

0.85

0.93

0.89

0.86

0.85

0.80

0.77

1.14

1.2

1.26

1.3

1.35

1.4

1.425

1.5

1.575

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (I_DD) calculation depends on multiple factors, including operating voltages

(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage.

Microsemi recommends using the Power Calculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage, operating

voltage, and temperature.

Table 2-7 • Power Supply State per Mode

Power Supply Configurations

Modes/Power Supplies

Flash*Freeze

Sleep

VCC

VCCPLL

VCCI

VJTAG

VPUMP

On/off/floating

Off

Shutdown

Off

No Flash*Freeze

On/off/floating

Note: Off: Power Supply level = 0 V

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode*

Core Voltage

1.2 V

A3P250L

0.33

A3P600L

0.55

A3P1000L

0.88

A3PE3000L Units

Typical (25°C)

2.75

4.2

1.5 V

0.5

0.83

1.33

Note: * IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.

Revision 13

2-7

ProASIC3L DC and Switching Characteristics

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode*

ICCI Current

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V/1.5 V

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI/VJTAG = 3.3 V (per bank)

Typical (25°C)

Note: *IDD = N_BANKS* ICCI

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode

Core Voltage

A3PE3000L

Units

Typical (25°C)

1.2 V/1.5 V

µA

Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode¹

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

ICCA Current²

Typical (25°C)

1.2 V

1.5 V

0.33

0.5

0.55

0.83

0.88

1.33

2.75

4.2

ICCI or IJTAG Current

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V/1.5 V

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI/VJTAG = 3.3 V (per bank)

Typical (25°C)

Notes:

1. *IDD = N_BANKS* ICCI+ICCA. JTAG counts as one bank when powered.

2. Includes VCC and VPUMP and VCCPLL currents.

2-8

Revision 13

ProASIC3L Low Power Flash FPGAs

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Pro I/O Banks

Static Power

PDC6 (mW)¹

Dynamic Power

VCCI (V)

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.34

24.49

4.71

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

6.13

1.66

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

1.2 V LVCMOS

1.78

1.01

0.97

0.60

1.2 V LVCMOS – Schmitt trigger

3.3 V PCI

0.53

17.76

19.10

17.76

19.10

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

7.07

3.62

2.97

2.55

0.85

3.30

8.08

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

0.95

1.62

LVPECL

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

Revision 13

2-9

ProASIC3L DC and Switching Characteristics

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

PDC6 (mW)²

Dynamic Power

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

3.3

2.5

1.8

1.5

1.2

3.3

–

16.22

4.65

1.65

0.98

0.61

17.64

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

0.95

1.63

LVPECL

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

is the static power (where applicable) measured on VCCI.

DC6

is the total dynamic power measured on VCCI.

AC10

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Static Power

PDC6 (mW)¹

Dynamic Power

VCCI (V)

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL /

3.3

–

16.23

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

2.5

1.8

1.5

1.2

3.3

–

4.66

1.64

0.99

0.58

17.64

3.3 V PCI-X

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

2-10

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings ¹

Applicable to Pro I/Os

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

3.3

2.5

1.8

1.5

1.2

3.3

–

148.00

83.23

54.58

37.05

17.94

204.61

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.22

105.56

116.60

114.87

131.76

2.5 V GTL

–

3.3 V GTL+

2.5 V GTL+

HSTL (I)

–

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.62

LVPECL

19.42

168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Revision 13

2-11

ProASIC3L DC and Switching Characteristics

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings ¹

Applicable to Advanced I/O Banks

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

3.3

2.5

1.8

1.5

1.2

3.3

–

141.97

79.98

52.26

35.62

21.29

201.02

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

89.71

LVPECL

19.54

167.54

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings ¹

Applicable to Standard Plus I/O Banks

Static Power

PDC7 (mW)²

Dynamic Power

_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

3.3

2.5

1.8

1.5

1.2

3.3

–

125.97

70.82

36.39

25.34

16.24

184.92

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

2-12

Revision 13

ProASIC3L Low Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.2 V VCC

Device Specific Dynamic Power (µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE3000L A3P1000L A3P600L A3P250L

12.61

2.66

0.56

9.28

1.59

8.19

1.19

0.52

7.07

1.01

PAC2

PAC3

PAC4

Clock contribution of a VersaTile used as a sequential

module

0.07

0.05

0.19

0.11

PAC5

PAC6

PAC7

First contribution of a VersaTile used as a sequential

module

Second contribution of a VersaTile used as a sequential

module

Contribution of a VersaTile used as a combinatorial

Module

PAC8

PAC9

Average contribution of a routing net

0.45

Contribution of an I/O input pin (standard-dependent)

See Table 2-12 on page 2-9. through

Table 2-14 on page 2-10.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin (standard-dependent)

See Table 2-15 on page 2-11 through

Table 2-17 on page 2-12.

Average contribution of a RAM block during a read

operation

25.00

30.00

1.74

Average contribution of a RAM block during a write

operation

Dynamic contribution for PLL

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Revision 13

2-13

ProASIC3L DC and Switching Characteristics

Table 2-19 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.5 V VCC

Device Specific Dynamic Power (µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE3000L A3P1000L A3P600L A3P250L

19.7

4.16

0.88

14.50

2.48

12.80

1.85

0.81

11.00

1.58

PAC2

PAC3

PAC4

Clock contribution of a VersaTile used as a sequential

module

0.12

PAC5

PAC6

PAC7

First contribution of a VersaTile used as a sequential

module

0.07

0.29

0.70

Second contribution of a VersaTile used as a sequential

module

Contribution of a VersaTile used as a combinatorial

Module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin (standard-dependent)

See Table 2-12 on page 2-9. through

Table 2-14 on page 2-10.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin (standard-dependent)

See Table 2-15 on page 2-11 through

Table 2-17 on page 2-12.

Average contribution of a RAM block during a read

operation

25.00

30.00

2.60

Average contribution of a RAM block during a write

operation

Dynamic contribution for PLL

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Table 2-20 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices

Device Specific Dynamic Power (µW)

Parameter

PDC1

Definition

A3PE3000L A3P1000L A3P600L A3P250L

See Table 2-11 on page 2-8.

See Table 2-9 on page 2-8.

See Table 2-8 on page 2-7.

1.42 mW

Array static power in Active mode

Array static power in Static (Idle) mode

Array static power in Flash*Freeze mode

PDC2

PDC3

PDC4

Static PLL contribution at 1.2 V core (operating mode

only)

Static PLL contribution at 1.5 V core (operating mode

only)

2.55 mW

PDC5

PDC6

PDC7

Bank quiescent power (VCCI-dependent)

See Table 2-8 on page 2-7, Table 2-9 on

page 2-8, Table 2-11 on page 2-8.

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-12 on page 2-9 through

Table 2-14 on page 2-10.

See Table 2-15 on page 2-11 through

Table 2-17 on page 2-12.

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

2-14

Revision 13

ProASIC3L Low Power Flash FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-21 on

page 2-17.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-22 on

page 2-17.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-22 on page 2-17. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

P_STAT= (PDC1 or PDC2 or PDC3) + N_BANKS* PDC5 + N_INPUTS* PDC6 + N_OUTPUTS* PDC7

N_INPUTSis the number of I/O input buffers used in the design.

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the ProASIC3L FPGA Fabric User’s Guide.

_ROWis the number of VersaTile rows used in the design—guidelines are provided in the

"Spine Architecture" section of the ProASIC3L FPGA Fabric User’s Guide.

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + ₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-17.

F_CLKis the global clock signal frequency.

Revision 13

2-15

ProASIC3L DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-17.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-17.

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-17.

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-17.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-22 on page 2-17.

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* ₂+ PAC12 * N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-22 on

page 2-17.

PLL Contribution—P

PLL

P_PLL= PDC4 + PAC13 * F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

2-16

Revision 13

ProASIC3L Low Power Flash FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-21 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-22 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

Revision 13

2-17

ProASIC3L DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

LVPECL (Applicable to

Advanced I/O Banks Only)L

t_PD= 0.56 ns

t_PD= 0.49 ns

t_DP= 1.34 ns

I/O Module

(Non-Registered)

Combinational Cell

Output drive strength = 12 mA

High slew rate

LVTTL

t_DP= 2.64 ns (Advanced I/O Banks)

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Output drive strength = 8 mA

High slew rate

LVTTL

_PY= 1.05 ns

t_DP= 3.66 ns (Advanced I/O Banks)

LVPECL

(Applicable

to Advanced

I/O Banks only)

t_PD= 0.47 ns

I/O Module

(Non-Registered)

Combinational Cell

Output drive strength = 4 mA

LVCMOS 1.5 V

High slew rate

_ICLKQ= 0.24 ns

_DP= 3.97 ns (Advanced I/O Banks)

t_PD= 0.47 ns

t_ISUD= 0.26 ns

Input LVTTL

Clock

I/O Module

(Registered)

Combinational Cell

_PY= 0.76 ns (Advanced I/O Banks)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

(Non-Registered)

t_PD= 0.47 ns

t_DP= 2.64 ns

(Advanced I/O Banks)

t_CLKQ= 0.55 ns

_SUD= 0.43 ns

_OCLKQ= 0.59 ns

_OSUD= 0.31 ns

_CLKQ= 0.55 ns

LVDS,

BLVDS,

M-LVDS

t_SUD= 0.43 ns

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t_PY= 1.20 ns

t_PY= 0.76 ns

(Advanced I/O Banks)

Figure 2-3 • Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

V_CC= 1.14 V

2-18

Revision 13

ProASIC3L Low Power Flash FPGAs

t_PY

t_DIN

PAD

DIN

CLK

To Array

I/O Interface

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

V_trip

VIL

PAD

VCC

50%

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

Revision 13

2-19

ProASIC3L DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

2-20

Revision 13

ProASIC3L Low Power Flash FPGAs

EOUT

CLK

, t , t , t , t , t

ZL ZH HZ LZ ZLS ZHS

EOUT

PAD

DOUT

CLK

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

50%

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

50%

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

ZHS

ZLS

Vtrip

VOL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

Revision 13

2-21

ProASIC3L DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Pro I/O Banks

Equiv.

Software

Default

Drive

VIL

VIH

VOL

VOH

IOL³IOH³

Drive

Strength Strength Slew Min.

Max.

Min.

Max.²

Max.

Min.

I/O Standard (mA)

Option¹Rate

12 mA High –0.3

mA mA

3.3 V LVTTL / 12 mA

3.3 V

0.8

3.6

2.7

0.4

2.4

12 12

LVCMOS

3.3 V

100 µA 12 mA High –0.3

0.8

0.7

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide Range⁴

2.5 V

LVCMOS

12 mA

2 mA

12 mA High –0.3

1.7

0.7

1.7

12 12

1.8 V

LVCMOS

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12 12

1.5 V

LVCMOS

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

1.2 V

LVCMOS

1.2 V

100 µA

2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide Range⁵

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Per PCI Specification

Per PCI-X Specification

20 mA⁶20 mA⁶High –0.3 VREF – 0.05 VREF + 0.05 3.6

20 mA⁶20 mA⁶High –0.3 VREF – 0.05 VREF + 0.05 2.7

0.4

0.6

0.4

0.54

0.35

0.7

0.5

–

20 20

35 35

33 33

–

35 mA

33 mA

8 mA

35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

33 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7

8 mA High –0.3 VREF – 0.1 VREF + 0.1 1.575

–

VCCI – 0.4

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA⁶15 mA⁶High –0.3 VREF – 0.1 VREF + 0.1 1.575

VCCI – 0.4 15 15

VCCI – 0.62 15 15

VCCI – 0.43 18 18

VCCI – 1.1 14 14

VCCI – 0.9 21 21

15 mA

18 mA

14 mA

21 mA

15 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7

18 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7

14 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

21 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100uA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Maximum VIH is 3.6 V for all I/O standards with hot-insertion is enabled.

3. Currents are measured at 85°C junction temperature.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

6. Output drive strength is below JEDEC specification.

7. Output slew rate can be extracted using the IBIS models.

2-22

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

Equiv.

Software

VIL

VIH

VOL

VOH

IOL²IOH²

Default

Drive

Drive Strength Slew Min.

Max.

Min.

Max.

Min.

I/O Standard Strength Option¹Rate

mA mA

3.3 V LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High –0.3

0.8

3.6

2.7

0.4

2.4

12 12

3.3 V

100 µA 12 mA High –0.3

12 mA 12 mA High –0.3

0.8

0.7

0.2

VCCI – 0.2 0.1 0.1

LVCMOS Wide

Range³

2.5 V

1.7

0.7

1.7

12 12

LVCMOS

1.8 V

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12 12

LVCMOS

1.5 V

12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

LVCMOS

1.2 V

2 mA

2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

LVCMOS

1.2 V

100 µA

2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide Range^4,5

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Currents are measured at 85°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Applicable to devices operating at VCCI ≥ VCC.

6. Output slew rate can be extracted using the IBIS models.

Revision 13

2-23

ProASIC3L DC and Switching Characteristics

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

Equiv.

Software

VIL

VIH

VOL

VOH

IOL²IOH²

Default

Drive

Drive Strength Slew Min.

Max.

Min.

Max.

Min.

I/O Standard Strength Option¹Rate

mA mA

12 12

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High –0.3

0.8

3.6

2.7

0.4

2.4

3.3 V LVCMOS 100 µA 12 mA High –0.3

Wide Range³

0.8

0.2

VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA

1.8 V LVCMOS 8 mA

1.5 V LVCMOS 4 mA

12 mA High –0.3

0.7

1.7

0.7

1.7

8 mA High –0.3 0.35*VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

4 mA High –0.3 0.35*VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2 mA High –0.3 0.35*VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

1.2 V

2 mA

LVCMOS⁴

1.2 V

100 µA

2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide Range^4,5

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Currents are measured at 85°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Applicable to devices operating at VCCI ≥ VCC.

6. Output slew rate can be extracted using the IBIS models.

2-24

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-26 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

Industrial²

IIL

IIH

µA

IIL³

µA

IIH⁴

µA

DC I/O Standard

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS⁵

1.2 V LVCMOS Wide Range⁵

3.3 V PCI

µA

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Commercial range (0°C < T < 70°C)

2. Industrial range (–40°C < T < 85°C)

3. IIL is the input leakage current per I/O pin over recommended operation conditions where

–0.3V < VIN <VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

5. Applicable to devices operating at VCCI  VCC.

Revision 13

2-25

ProASIC3L DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-27 • Summary of AC Measuring Points

Input Reference Voltage

(VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip Point

(Vtrip)

Standard

3.3 V LVTTL /

–

1.4 V

3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

–

1.4 V

1.2 V

1.8 V LVCMOS

0.90 V

1.5 V LVCMOS

0.75 V

1.2 V LVCMOS *

0.6 V

1.2 V LVCMOS Wide Range*

3.3 V PCI

0.6 V

0.285 * VCCI (RR)

0.615 * VCCI (FF))

0.285 * VCCI (RR)

0.615 * VCCI (FF)

VREF

3.3 V PCI-X

–

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Note: *Applicable only to devices operating in the 1.2 V core range.

Table 2-28 • I/O AC Parameter Definitions

Parameter

t_DP

Parameter Definition

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer

t_DOUT

t_EOUT

t_DIN

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—High to Z

Enable to Pad delay through the Output Buffer—Z to High

Enable to Pad delay through the Output Buffer—Low to Z

Enable to Pad delay through the Output Buffer—Z to Low

t_HZ

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

2-26

Revision 13

ProASIC3L Low Power Flash FPGAs

1.5 V DC Core Voltage

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425V,

Worst Case VCCI

Pro I/O Banks

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

– 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS 100 µA 12 mA High

Wide Range^1,2

–

2.5 V LVCMOS 12 mA 12 mA High

1.8 V LVCMOS 12 mA 12 mA High

1.5 V LVCMOS 12 mA 12 mA High

– 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns

– 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

– 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

25³0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI

Per

PCI

–

High

spec.

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 25³0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20mA⁵20 mA⁵High 10 25 0.50 1.59 0.03 1.80

20mA⁵20 mA⁵High 10 25 0.50 1.63 0.03 1.75

35 mA 35 mA High 10 25 0.50 1.57 0.03 1.80

33 mA 33 mA High 10 25 0.50 1.69 0.03 1.75

8 mA 8 mA High 20 25 0.50 2.43 0.03 2.12

–

0.33 1.56 1.59

0.33 1.66 1.63

0.33 1.60 1.57

0.33 1.72 1.61

0.33 2.48 2.41

0.33 2.36 2.08

0.33 1.66 1.41

0.33 1.69 1.36

0.33 1.80 1.41

0.33 1.61 1.28

–

3.27 3.30 ns

3.37 3.34 ns

3.31 3.29 ns

3.43 3.32 ns

4.19 4.12 ns

4.07 3.79 ns

1.66 1.41 ns

1.69 1.36 ns

1.80 1.41 ns

1.61 1.28 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15 mA 15 mA High 20 50 0.50 2.32 0.03 2.12

15 mA 15 mA High 30 25 0.50 1.63 0.03 1.61

18 mA 18 mA High 30 50 0.50 1.66 0.03 1.61

14 mA 14 mA High 30 25 0.50 1.77 0.03 1.54

21 mA 21 mA High 30 50 0.50 1.58 0.03 1.54

24 mA 24 mA High

–

– 0.50 1.40 0.03 1.85

– 0.50 1.40 0.03 1.67

–

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

5. Output drive strength is below JEDEC specification.

Revision 13

2-27

ProASIC3L DC and Switching Characteristics

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V, Worst

Case VCCI

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

–

0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

3.3 V LVCMOS 100 µA 12 mA High

Wide Range^1,2

–

2.5 V LVCMOS 12 mA 12 mA High

1.8 V LVCMOS 12 mA 12 mA High

1.5 V LVCMOS 12 mA 12 mA High

–

0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns

0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns

3.3 V PCI

Per

PCI

–

High

25 ³0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

spec.

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 25³0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS

24 mA

–

High

–

0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns

0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-28

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.425 V, Worst

Case VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

–

0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS 100 µA 12 mA High

Wide Range^1,2

–

2.5 V LVCMOS 12 mA 12 mA High

1.8 V LVCMOS 8 mA 8 mA High

1.5 V LVCMOS 4 mA 4 mA High

–

0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns

3.3 V PCI

3.3 V PCI-X

Notes:

Per

PCI

spec.

–

High 10 25 ³0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

Per

PCI-X

spec.

–

High 10 25 ³0.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-29

ProASIC3L DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.14 V,

Worst Case VCCI

Pro I/O Banks

Standard

3.3 V LVTTL / 12 mA 12 mA High 5

3.3 V LVCMOS

–

0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS 100 µA 12 mA High 5

Wide Range^1,2

–

2.5 V LVCMOS 12 mA 12 mA High 5

1.8 V LVCMOS 12 mA 12 mA High 5

1.5 V LVCMOS 12 mA 12 mA High 5

1.2 V LVCMOS 2 mA 2 mA High 5

–

0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns

0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns

0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns

1.2 V LVCMOS 100 µA 2 mA High 5

Wide Range^1,3

–

3.3 V PCI

Per

PCI

–

High 10 25⁴0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

spec.

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 25⁴0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20mA⁶

35 mA

33 mA

8 mA

15mA⁶

15 mA

18 mA

14 mA

21 mA

–

High 10 25 0.66 1.59 0.04 1.80

High 10 25 0.66 1.63 0.04 1.75

High 10 25 0.66 1.57 0.04 1.80

High 10 25 0.66 1.69 0.04 1.75

High 20 25 0.66 2.43 0.04 2.12

High 20 50 0.66 2.32 0.04 2.12

High 30 25 0.66 1.63 0.04 1.61

High 30 50 0.66 1.66 0.04 1.61

High 30 25 0.66 1.77 0.04 1.54

High 30 50 0.66 1.58 0.04 1.54

–

0.43 1.56 1.59

0.43 1.66 1.63

0.43 1.60 1.57

0.43 1.72 1.61

0.43 2.48 2.41

0.43 2.36 2.08

0.43 1.66 1.41

0.43 1.69 1.36

0.43 1.80 1.41

0.43 1.61 1.28

–

3.27 3.30 ns

3.37 3.34 ns

3.31 3.29 ns

3.43 3.32 ns

4.19 4.12 ns

4.07 3.79 ns

1.66 1.41 ns

1.69 1.36 ns

1.80 1.41 ns

1.61 1.28 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

6. Output drive strength is below JEDEC specification.

2-30

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.14 V,

Worst Case VCCI

Pro I/O Banks

Standard

LVDS

24 mA

–

High –

–

0.66 1.43 0.04 1.85

0.66 1.37 0.04 1.67

–

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

6. Output drive strength is below JEDEC specification.

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 5 pF

–

0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns

3.3 V LVCMOS 100 µA 12 mA High 5 pF

Wide Range_1,2

–

2.5 V LVCMOS 12 mA 12 mA High 5 pF

1.8 V LVCMOS 12 mA 12 mA High 5 pF

1.5 V LVCMOS 12 mA 12 mA High 5 pF

–

0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns

0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns

0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns

0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns

1.2 V LVCMOS

2 mA 2 mA High 5pF

1.2 V LVCMOS 100 µA 2 mA High 5 pF

Wide Range^1,3

–

3.3 V PCI

Per

PCI

–

High 10 25 ⁴0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

spec.

Revision 13

2-31

ProASIC3L DC and Switching Characteristics

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI

Advanced I/O Banks

I/O Standard

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 25 ⁴0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS

24 mA

–

High

–

0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns

0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-32

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 5 pF

–

0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS 100 µA 12 mA High 5 pF

Wide Range^1,2

–

2.5 V LVCMOS 12 mA 12 mA High 5 pF

–

0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns

0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns

1.8 V LVCMOS

1.5 V LVCMOS

8 mA 8 mA High 5 pF

4 mA 4 mA High 5 pF

1.2 V LVCMOS 2 mA 2 mA High 5 pF

1.2 V LVCMOS 100 µA 2 mA High 5 pF

Wide Range^1,3

–

3.3 V PCI

3.3 V PCI-X

Notes:

Per

PCI

spec.

–

High 10 pF 25 ⁴0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

Per

PCI-X

spec.

–

High 10 pF 25 ⁴0.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Detailed I/O DC Characteristics

Table 2-35 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

Input capacitance

Input capacitance on the clock pin

V_IN= 0, f = 1.0 MHz

C_INCLK

Revision 13

2-33

ProASIC3L DC and Switching Characteristics

Table 2-36 • I/O Output Buffer Maximum Resistances¹

Applicable to Pro I/Os

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

4 mA

() ²

() ³

3.3 V LVTTL / 3.3 V LVCMOS

100

300

150

8 mA

12 mA

16 mA

24 mA

100 µA

4 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

200

100

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

200

100

225

112

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

200

100

224

112

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

158

164

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

100 µA

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

Per PCI/PCI-X

specification

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁴

35 mA

33 mA

8 mA

15 mA⁴

15 mA

18 mA

14 mA

21 mA

–

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Output drive strength is below JEDEC specification.

2-34

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-37 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

Drive

Strength

R_PULL-DOWN

R_PULL-UP

Standard

() ²

() ³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

100

300

150

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

100 µA

2 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

300

150

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

100

200

100

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

200

100

224

112

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

158

164

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

100 µA

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

25 75

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on V , drive strength selection, temperature, and process. For board design considerations and detailed output buffer

CCI

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

Revision 13

2-35

ProASIC3L DC and Switching Characteristics

Table 2-38 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard Plus I/O Banks

Drive

Strength

R_PULL-DOWN

R_PULL-UP

Standard

() ²

() ³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

100

300

150

4 mA

6 mA

8 mA

12 mA

16 mA

100 µA

2 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

200

100

4 mA

6 mA

8 mA

12 mA

2 mA

1.8 V LVCMOS

1.5 V LVCMOS

200

100

225

112

4 mA

6 mA

8 mA

2 mA

200

100

158

224

112

164

4 mA

1.2 V LVCMOS

2 mA

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

100 µA

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

25 75

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

2-36

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-39 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCI

Min.

Max.

45 k

55 k

70 k

90 k

110 k

Min.

10 k

12 k

17 k

19 k

25 k

19 k

Max.

45 k

3.3 V

10 k

11 k

18 k

19 k

25 k

19 k

3.3 V (wide range I/Os)

45 k

2.5 V

74 k

1.8 V

110 k

140 k

150 k

1.5 V

1.2 V LVCMOS

1.2 V (wide range I/Os)

Notes:

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN)

= (VOLspec) / I

(WEAK PULL-DOWN-MAX)

(WEAK PULL-DOWN-MIN)

Revision 13

2-37

ProASIC3L DC and Switching Characteristics

Table 2-40 • I/O Short Currents IOSH/IOSL

Applicable to Pro I/Os

Standard

Drive Strength

4 mA

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

8 mA

12 mA

16 mA

24 mA

100 µA

4 mA

103

132

268

109

127

181

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

169

124

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCIX

100 µA

Per PCI/PCI-X

Specification

Per PCI Curves

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA²

35 mA

33 mA

8 mA

268

169

268

169

181

124

181

124

HSTL (II)

15 mA²

15 mA

18 mA

14 mA

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

169

124

Notes:

1. *TJ = 100°C

2. Output drive strength is below JEDEC specification.

2-38

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-41 • I/O Short Currents IOSH/IOS_L

Applicable to Advanced I/O Banks

Standard

Drive Strength

2 mA

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

100 µA

2 mA

103

132

268

109

127

181

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

169

124

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

4 mA

103

109

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

100 µA

Per PCI/PCI-X

specification

Note: *T_J= 100°C

Revision 13

2-39

ProASIC3L DC and Switching Characteristics

Table 2-42 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3

LVCMOS

LVTTL

3.3

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

100 µA

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100 µA

103

109

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

103

109

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Note: T_J= 100°C

Table 2-43 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers

Input Buffer Configuration

Hysteresis Value (typ.)

240 mV

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

1.2 V LVCMOS (Schmitt trigger mode)

140 mV

80 mV

60 mV

40 mV

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

2-40

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-44 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-45 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

No requirement

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/

No requirement

M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal

integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input

signals.

Revision 13

2-41

ProASIC3L DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all

LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8-A

specification.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL IIH

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

Drive Strength

4 mA

mA mA

µA²µA²

10 10

–0.3

0.8

3.6

0.4

2.4

6 mA

8 mA

12 12

16 16

24 24

103

132

268

109

127

181

12 mA

16 mA

24 mA

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH

IIL IIH

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

Drive Strength

2 mA

mA mA

µA²µA²

10 10

–0.3

0.8

3.6

0.4

2.4

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

103

132

268

109

127

181

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-42

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL IIH

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

Drive Strength

2 mA

mA mA

µA²µA²

10 10

–0.3

0.8

3.6

0.4

2.4

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

12 12

16 16

103

109

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_LOAD(pF)

3.3

1.4

Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-43

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60

6.42

5.46

5.78

4.91

5.29

4.50

5.19

4.41

5.20

4.42

0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46

0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57

0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59

0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85

0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98

0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64

0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80

0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54

0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15

4.38

3.72

3.90

3.32

3.68

3.13

3.64

3.09

3.58

3.05

0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38

0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59

0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91

0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28

0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64

0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23

0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59

0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25

0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-44

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.22

6.14

6.39

5.44

6.39

5.44

5.76

4.90

5.57

4.74

5.47

4.65

t_ZHS

6.34

5.40

5.76

4.90

5.76

4.90

5.33

4.53

5.23

4.45

5.26

4.48

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

5.11 0.04 0.91

4.35 0.03 0.78

4.30 0.04 0.91

3.66 0.03 0.78

4.30 0.04 0.91

3.66 0.03 0.78

3.68 0.04 0.91

3.13 0.03 0.78

3.50 0.04 0.91

2.97 0.03 0.78

3.39 0.04 0.91

2.88 0.03 0.78

5.21 4.33 2.38 2.21

4.43 3.68 2.02 1.88

4.38 3.75 2.68 2.74

3.73 3.19 2.28 2.33

4.38 3.75 2.68 2.74

3.73 3.19 2.28 2.33

3.75 3.32 2.89 3.07

3.19 2.82 2.45 2.62

3.56 3.21 2.93 3.16

3.03 2.73 2.49 2.69

3.45 3.25 2.99 3.50

2.94 2.76 2.54 2.97

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.97

4.23

4.47

3.80

4.47

3.80

4.21

3.58

4.17

3.54

4.19

3.56

t_ZHS

4.29

3.65

3.85

3.28

3.85

3.28

3.64

3.10

3.61

3.07

3.56

3.03

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

2.90 0.04 0.91

2.47 0.03 0.78

2.41 0.04 0.91

2.05 0.03 0.78

2.41 0.04 0.91

2.05 0.03 0.78

2.16 0.04 0.91

1.83 0.03 0.78

2.11 0.04 0.91

1.80 0.03 0.78

2.14 0.04 0.91

1.82 0.03 0.78

2.96 2.28 2.38 2.35

2.52 1.94 2.03 2.00

2.46 1.84 2.69 2.88

2.09 1.57 2.29 2.45

2.46 1.84 2.69 2.88

2.09 1.57 2.29 2.45

2.20 1.63 2.89 3.22

1.87 1.39 2.46 2.74

2.15 1.59 2.94 3.31

1.83 1.36 2.50 2.82

2.17 1.55 2.99 3.65

1.85 1.32 2.54 3.11

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–-1

Std.

–-1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-45

ProASIC3L DC and Switching Characteristics

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.71

5.71

5.88

5.00

5.88

5.00

5.30

4.51

5.30

4.51

t_ZHS

5.92

5.04

5.41

4.60

5.41

4.60

5.01

4.27

5.01

4.27

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

4.61 0.04 0.90

3.92 0.03 0.77

3.80 0.04 0.90

3.23 0.03 0.77

3.80 0.04 0.90

3.23 0.03 0.77

3.22 0.04 0.90

2.74 0.03 0.77

3.22 0.04 0.90

2.74 0.03 0.77

4.70 3.91 2.05 1.99

4.00 3.32 1.74 1.69

3.87 3.40 2.32 2.47

3.29 2.89 1.98 2.10

3.87 3.40 2.32 2.47

3.29 2.89 1.98 2.10

3.28 3.00 2.51 2.77

2.79 2.55 2.14 2.36

3.28 3.00 2.51 2.77

2.79 2.55 2.14 2.36

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.57

3.89

4.10

3.49

4.10

3.49

3.88

3.30

3.88

3.30

t_ZHS

4.02

3.42

3.62

3.08

3.62

3.08

3.42

2.91

3.42

2.91

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

2.51 0.04 0.90

2.14 0.03 0.77

2.05 0.04 0.90

1.74 0.03 0.77

2.05 0.04 0.90

1.74 0.03 0.77

1.83 0.04 0.90

1.56 0.03 0.77

1.83 0.04 0.90

1.56 0.03 0.77

2.56 2.01 2.05 2.10

2.18 1.71 1.74 1.79

2.09 1.61 2.32 2.59

1.78 1.37 1.97 2.20

2.09 1.61 2.32 2.59

1.78 1.37 1.97 2.20

1.86 1.41 2.51 2.90

1.59 1.20 2.14 2.47

1.86 1.41 2.51 2.90

1.59 1.20 2.14 2.47

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-46

Revision 13

ProASIC3L Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.77 5.48 0.05 1.58 2.17 0.50 5.58 4.40 2.42 2.20 7.60

6.42

5.46

5.78

4.91

5.29

4.50

5.19

4.41

5.20

4.42

0.66 4.66 0.04 1.34 1.85 0.43 4.75 3.75 2.06 1.87 6.46

0.77 4.48 0.05 1.58 2.17 0.50 4.56 3.76 2.73 2.76 6.57

0.66 3.81 0.04 1.34 1.85 0.43 3.88 3.20 2.33 2.35 5.59

0.77 3.77 0.05 1.58 2.17 0.50 3.84 3.28 2.95 3.12 5.85

0.66 3.21 0.04 1.34 1.85 0.43 3.27 2.79 2.51 2.65 4.98

0.77 3.57 0.05 1.58 2.17 0.50 3.63 3.18 2.99 3.22 5.64

0.66 3.03 0.04 1.34 1.85 0.43 3.09 2.70 2.54 2.74 4.80

0.77 3.46 0.05 1.58 2.17 0.50 3.52 3.19 3.05 3.57 5.54

0.66 2.94 0.04 1.34 1.85 0.43 3.00 2.71 2.59 3.03 4.71

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15

4.38

3.72

3.90

3.32

3.68

3.13

3.64

3.09

3.58

3.05

0.66 2.62 0.04 1.34 1.85 0.43 2.67 2.01 2.06 1.98 4.38

0.77 2.53 0.05 1.58 2.17 0.50 2.58 1.89 2.74 2.89 4.59

0.66 2.16 0.04 1.34 1.85 0.43 2.20 1.61 2.33 2.46 3.91

0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28

0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64

0.77 2.17 0.05 1.58 2.17 0.50 2.21 1.63 3.00 3.35 4.23

0.66 1.85 0.04 1.34 1.85 0.43 1.88 1.38 2.55 2.85 3.59

0.77 2.19 0.05 1.58 2.17 0.50 2.24 1.57 3.05 3.71 4.25

0.66 1.87 0.04 1.34 1.85 0.43 1.90 1.33 2.59 3.16 3.61

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-47

ProASIC3L DC and Switching Characteristics

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.22

6.14

6.39

5.44

6.39

5.44

5.76

4.90

5.57

4.74

5.47

4.65

t_ZHS

6.34

5.40

5.76

4.90

5.76

4.90

5.33

4.53

5.23

4.45

5.26

4.48

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

5.11 0.05 0.91

4.35 0.04 0.78

4.30 0.05 0.91

3.66 0.04 0.78

4.30 0.05 0.91

3.66 0.04 0.78

3.68 0.05 0.91

3.13 0.04 0.78

3.50 0.05 0.91

2.97 0.04 0.78

3.39 0.05 0.91

2.88 0.04 0.78

5.21 4.33 2.38 2.21

4.43 3.68 2.02 1.88

4.38 3.75 2.68 2.74

3.73 3.19 2.28 2.33

4.38 3.75 2.68 2.74

3.73 3.19 2.28 2.33

3.75 3.32 2.89 3.07

3.19 2.82 2.45 2.62

3.56 3.21 2.93 3.16

3.03 2.73 2.49 2.69

3.45 3.25 2.99 3.50

2.94 2.76 2.54 2.97

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.97

4.23

4.47

3.80

4.47

3.80

4.21

3.58

4.17

3.54

4.19

3.56

t_ZHS

4.29

3.65

3.85

3.28

3.85

3.28

3.64

3.10

3.61

3.07

3.56

3.03

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

2.90 0.05 0.91

2.47 0.04 0.78

2.41 0.05 0.91

2.05 0.04 0.78

2.41 0.05 0.91

2.05 0.04 0.78

2.16 0.05 0.91

1.83 0.04 0.78

2.11 0.05 0.91

1.80 0.04 0.78

2.14 0.05 0.91

1.82 0.04 0.78

2.96 2.28 2.38 2.35

2.52 1.94 2.03 2.00

2.46 1.84 2.69 2.88

2.09 1.57 2.29 2.45

2.46 1.84 2.69 2.88

2.09 1.57 2.29 2.45

2.20 1.63 2.89 3.22

1.87 1.39 2.46 2.74

2.15 1.59 2.94 3.31

1.83 1.36 2.50 2.82

2.17 1.55 2.99 3.65

1.85 1.32 2.54 3.11

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–-1

Std.

–-1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-48

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.71

5.71

5.88

5.00

5.88

5.00

5.30

4.51

5.30

4.51

t_ZHS

5.92

5.04

5.41

4.60

5.41

4.60

5.01

4.27

5.01

4.27

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

4.61 0.05 0.90

3.92 0.04 0.77

3.80 0.05 0.90

3.23 0.04 0.77

3.80 0.05 0.90

3.23 0.04 0.77

3.22 0.05 0.90

2.74 0.04 0.77

3.22 0.05 0.90

2.74 0.04 0.77

4.70 3.91 2.05 1.99

4.00 3.32 1.74 1.69

3.87 3.40 2.32 2.47

3.29 2.89 1.98 2.10

3.87 3.40 2.32 2.47

3.29 2.89 1.98 2.10

3.28 3.00 2.51 2.77

2.79 2.55 2.14 2.36

3.28 3.00 2.51 2.77

2.79 2.55 2.14 2.36

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.57

3.89

4.10

3.49

4.10

3.49

3.88

3.30

3.88

3.30

t_ZHS

4.02

3.42

3.62

3.08

3.62

3.08

3.42

2.91

3.42

2.91

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

2.51 0.05 0.90

2.14 0.04 0.77

2.05 0.05 0.90

1.74 0.04 0.77

2.05 0.05 0.90

1.74 0.04 0.77

1.83 0.05 0.90

1.56 0.04 0.77

1.83 0.05 0.90

1.56 0.04 0.77

2.56 2.01 2.05 2.10

2.18 1.71 1.74 1.79

2.09 1.61 2.32 2.59

1.78 1.37 1.97 2.20

2.09 1.61 2.32 2.59

1.78 1.37 1.97 2.20

1.86 1.41 2.51 2.90

1.59 1.20 2.14 2.47

1.86 1.41 2.51 2.90

1.59 1.20 2.14 2.47

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-49

ProASIC3L DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Pro I/O Banks

3.3 V

Equivalent

LVCMOS

Software

Wide

Default

Drive

Range

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL

Max. Max.

µA

IIH

Drive

Strength

Min.

Max. Min.

Max. Max.

Min.

Option¹

µA mA²mA²µA

µA

100 µA

Notes:

2 mA

4 mA

–0.3

0.8

3.6

0.2 VDD – 0.2 100 100 25

0.2 VDD – 0.2 100 100 51

6 mA

8 mA

12 mA

16 mA

24 mA

0.2 VDD – 0.2 100 100 103 109

0.2 VDD – 0.2 100 100 132 127

0.2 VDD – 0.2 100 100 268 181

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification

4. Software default selection highlighted in gray.

Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Advanced I/O Banks

3.3 V

Equivalent

LVCMOS

Software

Wide

Default

Drive

Range

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL

Max. Max.

µA

IIH

Drive

Strength

Min.

Max. Min.

Max. Max.

Min.

Option¹

µA mA²mA²µA

µA

100 µA

Notes:

2 mA

4 mA

–0.3

0.8

3.6

0.2 VDD – 0.2 100 100 25

0.2 VDD – 0.2 100 100 51

6 mA

8 mA

12 mA

16 mA

24 mA

0.2 VDD – 0.2 100 100 103 109

0.2 VDD – 0.2 100 100 132 127

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification

4. Software default selection highlighted in gray.

2-50

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Standard Plus I/O Banks

3.3 V

LVCMOS

Wide

Equivalent

Software

Default

Range

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL

Max. Max.

µA

IIH

Drive

Strength

Min.

Max. Min.

Max. Max.

Min.

Option¹

µA mA²mA²µA

µA

100 µA

Notes:

2 mA

4 mA

–0.3

0.8

3.6

0.2 VDD – 0.2 100 100 25

0.2 VDD – 0.2 100 100 51

6 mA

8 mA

12 mA

16 mA

0.2 VDD – 0.2 100 100 103 109

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification

4. Software default selection highlighted in gray.

Revision 13

2-51

ProASIC3L DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-65 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

2.5 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH IIL IIH

Min.

Max.

Min.

Max.

Min.

Max.

Drive Strength

4 mA

mA mA mA¹

mA¹µA²µA²

–0.3

0.7

1.7

2.7

0.7

1.7

10 10

8 mA

12 mA

12 12

16 16

24 24

16 mA

24 mA

169

124

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-66 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

Drive Strength

2 mA

mA mA

µA²µA²

10 10

–0.3

0.7

1.7

2.7

0.7

1.7

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

169

124

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-52

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-67 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

10 10

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.7

1.7

2.7

0.7

1.7

12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-68 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_LOAD(pF)

2.5

1.2

Note: *Measuring point = Vtrip_.See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-53

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-69 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.59 6.24 0.04 1.86 2.31 0.38 6.36 5.30 2.45 1.98 8.37

7.31

6.22

6.50

5.53

5.92

5.04

5.79

4.93

5.81

4.94

0.50 5.31 0.03 1.58 1.97 0.33 5.41 4.51 2.08 1.68 7.12

0.59 5.10 0.04 1.86 2.31 0.38 5.20 4.49 2.79 2.64 7.21

0.50 4.34 0.03 1.58 1.97 0.33 4.42 3.82 2.37 2.24 6.13

0.59 4.29 0.04 1.86 2.31 0.38 4.37 3.91 3.03 3.05 6.39

0.50 3.65 0.03 1.58 1.97 0.33 3.72 3.32 2.58 2.60 5.43

0.59 4.05 0.04 1.86 2.31 0.38 4.12 3.78 3.08 3.17 6.13

0.50 3.44 0.03 1.58 1.97 0.33 3.51 3.22 2.62 2.70 5.22

0.59 3.94 0.04 1.86 2.31 0.38 4.01 3.80 3.15 3.60 6.03

0.50 3.35 0.03 1.58 1.97 0.33 3.41 3.23 2.68 3.06 5.13

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-70 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.59 3.18 0.04 1.86 2.31 0.38 3.24 2.84 2.45 2.06 5.25

4.85

4.13

4.20

3.57

3.88

3.30

3.82

3.25

3.74

3.18

0.50 2.71 0.03 1.58 1.97 0.33 2.76 2.42 2.08 1.75 4.47

0.59 2.61 0.04 1.86 2.31 0.38 2.65 2.19 2.79 2.73 4.67

0.50 2.22 0.03 1.58 1.97 0.33 2.26 1.86 2.37 2.32 3.97

0.59 2.26 0.04 1.86 2.31 0.38 2.30 1.86 3.03 3.15 4.32

0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67

0.59 2.20 0.04 1.86 2.31 0.38 2.24 1.80 3.08 3.26 4.26

0.50 1.87 0.03 1.58 1.97 0.33 1.91 1.54 2.62 2.77 3.62

0.59 2.21 0.04 1.86 2.31 0.38 2.25 1.73 3.15 3.70 4.27

0.50 1.88 0.03 1.58 1.97 0.33 1.92 1.47 2.68 3.14 3.63

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-54

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-71 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.91

6.73

6.94

5.90

6.94

5.90

6.22

5.29

5.99

5.10

5.88

5.01

t_ZHS

7.19

6.11

6.44

5.48

6.44

5.48

5.93

5.04

5.81

4.94

5.87

4.99

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

5.79 0.04 1.18

4.92 0.03 1.00

4.84 0.04 1.18

4.11 0.03 1.00

4.84 0.04 1.18

4.11 0.03 1.00

4.13 0.04 1.18

3.52 0.03 1.00

3.91 0.04 1.18

3.32 0.03 1.00

3.85 0.04 1.18

3.28 0.03 1.00

5.90 5.18 2.41 1.98

5.01 4.40 2.05 1.69

4.93 4.43 2.74 2.60

4.19 3.77 2.33 2.21

4.93 4.43 2.74 2.60

4.19 3.77 2.33 2.21

4.21 3.92 2.97 2.99

3.58 3.33 2.53 2.54

3.98 3.80 3.02 3.09

3.39 3.23 2.57 2.63

3.87 3.85 3.09 3.48

3.29 3.28 2.63 2.96

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-72 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.04

4.29

4.50

3.83

4.50

3.83

4.22

3.59

4.17

3.55

4.19

3.56

t_ZHS

4.75

4.04

4.13

3.51

4.13

3.51

3.83

3.26

3.78

3.21

3.72

3.16

Units

4 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

2.97 0.04 1.18

2.53 0.03 1.00

2.44 0.04 1.18

2.08 0.03 1.00

2.44 0.04 1.18

2.08 0.03 1.00

2.17 0.04 1.18

1.85 0.03 1.00

2.12 0.04 1.18

1.81 0.03 1.00

2.13 0.04 1.18

1.81 0.03 1.00

3.03 2.74 2.41 2.07

2.58 2.33 2.05 1.76

2.49 2.12 2.74 2.70

2.12 1.80 2.33 2.30

2.49 2.12 2.74 2.70

2.12 1.80 2.33 2.30

2.21 1.82 2.97 3.09

1.88 1.55 2.53 2.63

2.16 1.76 3.03 3.19

1.84 1.50 2.57 2.72

2.17 1.71 3.09 3.60

1.85 1.45 2.63 3.06

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-55

ProASIC3L DC and Switching Characteristics

Table 2-73 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.38

6.28

6.42

5.46

6.42

5.46

5.74

4.89

t_ZHS

6.69

5.69

6.04

5.14

6.04

5.14

5.57

4.74

Units

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

5.27 0.04 1.17

4.49 0.03 0.99

4.32 0.04 1.17

3.68 0.03 0.99

4.32 0.04 1.17

3.68 0.03 0.99

3.66 0.04 1.17

3.12 0.03 0.99

5.37 4.68 2.03 1.79

4.57 3.98 1.73 1.52

4.40 4.03 2.33 2.35

3.75 3.43 1.98 2.00

4.40 4.03 2.33 2.35

3.75 3.43 1.98 2.00

3.73 3.56 2.54 2.71

3.17 3.03 2.16 2.30

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-74 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.66

3.96

4.16

3.54

4.16

3.54

3.91

3.33

t_ZHS

4.40

3.74

3.84

3.27

3.84

3.27

3.57

3.03

Units

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

2.60 0.04 1.17

2.21 0.03 0.99

2.10 0.04 1.17

1.79 0.03 0.99

2.10 0.04 1.17

1.79 0.03 0.99

1.86 0.04 1.17

1.59 0.03 0.99

2.65 2.39 2.03 1.87

2.25 2.03 1.72 1.59

2.14 1.83 2.33 2.44

1.82 1.56 1.98 2.07

2.14 1.83 2.33 2.44

1.82 1.56 1.98 2.07

1.90 1.55 2.54 2.80

1.61 1.32 2.16 2.38

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-56

Revision 13

ProASIC3L Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-75 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.77 6.24 0.05 1.86 2.31 0.50 6.36 5.30 2.45 1.98 8.37

7.31

6.22

6.50

5.53

5.92

5.04

5.79

4.93

5.81

4.94

0.66 5.31 0.04 1.58 1.97 0.43 5.41 4.51 2.08 1.68 7.12

0.77 5.10 0.05 1.86 2.31 0.50 5.20 4.49 2.79 2.64 7.21

0.66 4.34 0.04 1.58 1.97 0.43 4.42 3.82 2.37 2.24 6.13

0.77 4.29 0.05 1.86 2.31 0.50 4.37 3.91 3.03 3.05 6.39

0.66 3.65 0.04 1.58 1.97 0.43 3.72 3.32 2.58 2.60 5.43

0.77 4.05 0.05 1.86 2.31 0.50 4.12 3.78 3.08 3.17 6.13

0.66 3.44 0.04 1.58 1.97 0.43 3.51 3.22 2.62 2.70 5.22

0.77 3.94 0.05 1.86 2.31 0.50 4.01 3.80 3.15 3.60 6.03

0.66 3.35 0.04 1.58 1.97 0.43 3.41 3.23 2.68 3.06 5.13

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-76 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/Os

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.77 3.18 0.05 1.86 2.31 0.50 3.24 2.84 2.45 2.06 5.25

4.85

4.13

4.20

3.57

3.88

3.30

3.82

3.25

3.74

3.18

0.66 2.71 0.04 1.58 1.97 0.43 2.76 2.42 2.08 1.75 4.47

0.77 2.61 0.05 1.86 2.31 0.50 2.65 2.19 2.79 2.73 4.67

0.66 2.22 0.04 1.58 1.97 0.43 2.26 1.86 2.37 2.32 3.97

0.77 2.26 0.05 1.86 2.31 0.50 2.30 1.86 3.03 3.15 4.32

0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67

0.77 2.20 0.05 1.86 2.31 0.50 2.24 1.80 3.08 3.26 4.26

0.66 1.87 0.04 1.58 1.97 0.43 1.91 1.54 2.62 2.77 3.62

0.77 2.21 0.05 1.86 2.31 0.50 2.25 1.73 3.15 3.70 4.27

0.66 1.88 0.04 1.58 1.97 0.43 1.92 1.47 2.68 3.14 3.63

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-57

ProASIC3L DC and Switching Characteristics

Table 2-77 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.91

6.73

6.94

5.90

6.94

5.90

6.22

5.29

5.99

5.10

5.88

5.01

t_ZHS

7.19

6.11

6.44

5.48

6.44

5.48

5.93

5.04

5.81

4.94

5.87

4.99

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

5.79 0.05 1.18

4.92 0.04 1.00

4.84 0.05 1.18

4.11 0.04 1.00

4.84 0.05 1.18

4.11 0.04 1.00

4.13 0.05 1.18

3.52 0.04 1.00

3.91 0.05 1.18

3.32 0.04 1.00

3.85 0.05 1.18

3.28 0.04 1.00

5.90 5.18 2.41 1.98

5.01 4.40 2.05 1.69

4.93 4.43 2.74 2.60

4.19 3.77 2.33 2.21

4.93 4.43 2.74 2.60

4.19 3.77 2.33 2.21

4.21 3.92 2.97 2.99

3.58 3.33 2.53 2.54

3.98 3.80 3.02 3.09

3.39 3.23 2.57 2.63

3.87 3.85 3.09 3.48

3.29 3.28 2.63 2.96

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-78 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.04

4.29

4.50

3.83

4.50

3.83

4.22

3.59

4.17

3.55

4.19

3.56

t_ZHS

4.75

4.04

4.13

3.51

4.13

3.51

3.83

3.26

3.78

3.21

3.72

3.16

Units

4 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

2.97 0.05 1.18

2.53 0.04 1.00

2.44 0.05 1.18

2.08 0.04 1.00

2.44 0.05 1.18

2.08 0.04 1.00

2.17 0.05 1.18

1.85 0.04 1.00

2.12 0.05 1.18

1.81 0.04 1.00

2.13 0.05 1.18

1.81 0.04 1.00

3.03 2.74 2.41 2.07

2.58 2.33 2.05 1.76

2.49 2.12 2.74 2.70

2.12 1.80 2.33 2.30

2.49 2.12 2.74 2.70

2.12 1.80 2.33 2.30

2.21 1.82 2.97 3.09

1.88 1.55 2.53 2.63

2.16 1.76 3.03 3.19

1.84 1.50 2.57 2.72

2.17 1.71 3.09 3.60

1.85 1.45 2.63 3.06

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-58

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-79 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

7.38

6.28

6.42

5.46

6.42

5.46

5.74

4.89

t_ZHS

6.69

5.69

6.04

5.14

6.04

5.14

5.57

4.74

Units

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

5.27 0.05 1.17

4.49 0.04 0.99

4.32 0.05 1.17

3.68 0.04 0.99

4.32 0.05 1.17

3.68 0.04 0.99

3.66 0.05 1.17

3.12 0.04 0.99

5.37 4.68 2.03 1.79

4.57 3.98 1.73 1.52

4.40 4.03 2.33 2.35

3.75 3.43 1.98 2.00

4.40 4.03 2.33 2.35

3.75 3.43 1.98 2.00

3.73 3.56 2.54 2.71

3.17 3.03 2.16 2.30

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-80 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.66

3.96

4.16

3.54

4.16

3.54

3.91

3.33

t_ZHS

4.40

3.74

3.84

3.27

3.84

3.27

3.57

3.03

Units

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

2.60 0.05 1.17

2.21 0.04 0.99

2.10 0.05 1.17

1.79 0.04 0.99

2.10 0.05 1.17

1.79 0.04 0.99

1.86 0.05 1.17

1.59 0.04 0.99

2.65 2.39 2.03 1.87

2.25 2.03 1.72 1.59

2.14 1.83 2.33 2.44

1.82 1.56 1.98 2.07

2.14 1.83 2.33 2.44

1.82 1.56 1.98 2.07

1.90 1.55 2.54 2.80

1.61 1.32 2.16 2.38

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-59

ProASIC3L DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-81 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

1.8 V

LVCMOS

VIL

Max.

VIH

Min. V

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

10 10

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

VCCI – 0.45 12 12

VCCI – 0.45 16 16

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-82 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

mA¹

mA mA mA¹

µA²µA²

10 10

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI

–0.3 0.35 * VCCI 0.65 * V_CCI

–0.3 0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-60

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-83 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Max. Max.

Drive

Strength

Min.

Max.

Min.

mA mA mA¹

mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI

–0.3 0.35 * VCCI 0.65 * V_CCI

–0.3 0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45

10 10

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-84 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_LOAD(pF)

1.8

0.9

Note: *Measuring point = V_trip.See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-61

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-85 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.59 8.32 0.04 1.80 2.55 0.38 8.48 6.99 2.50 1.42 10.49 9.00

0.50 7.08 0.03 1.53 2.17 0.33 7.21 5.95 2.13 1.21 8.92

0.59 6.85 0.04 1.80 2.55 0.38 6.98 5.89 2.93 2.50 8.99

0.50 5.83 0.03 1.53 2.17 0.33 5.94 5.01 2.49 2.12 7.65

0.59 5.81 0.04 1.80 2.55 0.38 5.92 5.13 3.21 3.02 7.93

0.50 4.94 0.03 1.53 2.17 0.33 5.03 4.37 2.73 2.57 6.75

0.59 5.46 0.04 1.80 2.55 0.38 5.56 4.99 3.28 3.17 7.57

0.50 4.64 0.03 1.53 2.17 0.33 4.73 4.24 2.79 2.70 6.44

0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47

0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35

0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47

0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35

7.66

7.90

6.72

7.15

6.08

7.00

5.95

7.01

5.96

7.01

5.96

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-86 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.59 3.76 0.04 1.80 2.55 0.38 3.83 3.68 2.50 1.47 5.84

5.70

4.85

4.75

4.04

4.28

3.64

4.19

3.57

4.08

3.47

4.08

3.47

0.50 3.20 0.03 1.53 2.17 0.33 3.26 3.13 2.13 1.25 4.97

0.59 3.05 0.04 1.80 2.55 0.38 3.11 2.73 2.92 2.58 5.12

0.50 2.59 0.03 1.53 2.17 0.33 2.64 2.33 2.49 2.19 4.35

0.59 2.61 0.04 1.80 2.55 0.38 2.66 2.27 3.21 3.12 4.67

0.50 2.22 0.03 1.53 2.17 0.33 2.26 1.93 2.73 2.65 3.98

0.59 2.53 0.04 1.80 2.55 0.38 2.58 2.18 3.27 3.26 4.59

0.50 2.15 0.03 1.53 2.17 0.33 2.19 1.85 2.78 2.77 3.90

0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58

0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89

0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58

0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-62

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-87 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.93

8.45

8.51

7.24

7.59

6.46

7.27

6.19

7.17

6.10

7.17

6.10

t_ZHS

8.81

7.49

7.79

6.63

7.12

6.06

6.98

5.94

7.04

5.99

7.04

5.99

Units

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

7.77 0.04 1.18

6.61 0.03 1.00

6.38 0.04 1.18

5.43 0.03 1.00

5.48 0.04 1.18

4.66 0.03 1.00

5.17 0.04 1.18

4.40 0.03 1.00

5.06 0.04 1.18

4.30 0.03 1.00

5.06 0.04 1.18

4.30 0.03 1.00

7.92 6.80 2.50 1.44

6.73 5.78 2.13 1.22

6.50 5.78 2.91 2.46

5.53 4.91 2.47 2.09

5.58 5.11 3.18 2.94

4.75 4.35 2.71 2.51

5.26 4.97 3.24 3.07

4.48 4.23 2.76 2.61

5.15 5.03 3.34 3.55

4.38 4.28 2.84 3.02

5.15 5.03 3.34 3.55

4.38 4.28 2.84 3.02

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-88 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.68

4.83

4.88

4.15

4.53

3.85

4.46

3.79

4.45

3.79

4.45

3.79

t_ZHS

5.53

4.71

4.65

3.96

4.22

3.59

4.14

3.52

4.05

3.45

4.05

3.45

Units

2 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

3.60 0.04 1.10

3.06 0.03 0.93

2.81 0.04 1.10

2.39 0.03 0.93

2.47 0.04 1.10

2.10 0.03 0.93

2.40 0.04 1.10

2.04 0.03 0.93

2.39 0.04 1.10

2.04 0.03 0.93

2.39 0.04 1.10

2.04 0.03 0.93

3.66 3.52 2.49 1.49

3.12 3.00 2.12 1.27

2.87 2.64 2.90 2.55

2.44 2.25 2.47 2.17

2.51 2.21 3.18 3.04

2.14 1.88 2.70 2.59

2.45 2.13 3.24 3.17

2.08 1.81 2.76 2.70

2.44 2.04 3.33 3.67

2.08 1.73 2.83 3.12

2.44 2.04 3.33 3.67

2.08 1.73 2.83 3.12

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-63

ProASIC3L DC and Switching Characteristics

Table 2-89 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.36

7.96

7.93

6.74

7.06

6.01

7.06

6.01

t_ZHS

8.16

6.94

7.27

6.19

6.66

5.67

6.66

5.67

Units

2 mA

4 mA

6 mA

8 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

7.21 0.04 1.17

6.13 0.03 0.99

5.81 0.04 1.17

4.94 0.03 0.99

4.96 0.04 1.17

4.22 0.03 0.99

4.96 0.04 1.17

4.22 0.03 0.99

7.35 6.14 2.03 1.32

6.25 5.23 1.72 1.12

5.92 5.26 2.39 2.25

5.03 4.47 2.03 1.91

5.05 4.65 2.64 2.69

4.30 3.96 2.25 2.29

5.05 4.65 2.64 2.69

4.30 3.96 2.25 2.29

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-90 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.30

4.50

4.54

3.86

4.22

3.59

4.22

3.59

t_ZHS

5.06

4.30

4.26

3.63

3.87

3.29

3.87

3.29

Units

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

3.22 0.04 1.08

2.74 0.03 0.92

2.48 0.04 1.08

2.11 0.03 0.92

2.17 0.04 1.08

1.85 0.03 0.92

2.17 0.04 1.08

1.85 0.03 0.92

3.28 3.04 2.02 1.37

2.79 2.59 1.72 1.17

2.53 2.25 2.38 2.34

2.15 1.92 2.03 1.99

2.21 1.86 2.64 2.79

1.88 1.58 2.24 2.37

2.21 1.86 2.64 2.79

1.88 1.58 2.24 2.37

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-64

Revision 13

ProASIC3L Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-91 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.77 8.32 0.05 1.80 2.55 0.50 8.48 6.99 2.50 1.42 10.49 9.00

0.66 7.08 0.04 1.53 2.17 0.43 7.21 5.95 2.13 1.21 8.92

0.77 6.85 0.05 1.80 2.55 0.50 6.98 5.89 2.93 2.50 8.99

0.66 5.83 0.04 1.53 2.17 0.43 5.94 5.01 2.49 2.12 7.65

0.77 5.81 0.05 1.80 2.55 0.50 5.92 5.13 3.21 3.02 7.93

0.66 4.94 0.04 1.53 2.17 0.43 5.03 4.37 2.73 2.57 6.75

0.77 5.46 0.05 1.80 2.55 0.50 5.56 4.99 3.28 3.17 7.57

0.66 4.64 0.04 1.53 2.17 0.43 4.73 4.24 2.79 2.70 6.44

0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47

0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35

0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47

0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35

7.66

7.90

6.72

7.15

6.08

7.00

5.95

7.01

5.96

7.01

5.96

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-92 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.77 3.76 0.05 1.80 2.55 0.50 3.83 3.68 2.50 1.47 5.84

5.70

4.85

4.75

4.04

4.28

3.64

4.19

3.57

4.08

3.47

4.08

3.47

0.66 3.20 0.04 1.53 2.17 0.43 3.26 3.13 2.13 1.25 4.97

0.77 3.05 0.05 1.80 2.55 0.50 3.11 2.73 2.92 2.58 5.12

0.66 2.59 0.04 1.53 2.17 0.43 2.64 2.33 2.49 2.19 4.35

0.77 2.61 0.05 1.80 2.55 0.50 2.66 2.27 3.21 3.12 4.67

0.66 2.22 0.04 1.53 2.17 0.43 2.26 1.93 2.73 2.65 3.98

0.77 2.53 0.05 1.80 2.55 0.50 2.58 2.18 3.27 3.26 4.59

0.66 2.15 0.04 1.53 2.17 0.43 2.19 1.85 2.78 2.77 3.90

0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58

0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89

0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58

0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-65

ProASIC3L DC and Switching Characteristics

Table 2-93 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.93

8.45

8.51

7.24

7.59

6.46

7.27

6.19

7.17

6.10

7.17

6.10

t_ZHS

8.81

7.49

7.79

6.63

7.12

6.06

6.98

5.94

7.04

5.99

7.04

5.99

Units

2 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

7.77 0.05 1.18

6.61 0.04 1.00

6.38 0.05 1.18

5.43 0.04 1.00

5.48 0.05 1.18

4.66 0.04 1.00

5.17 0.05 1.18

4.40 0.04 1.00

5.06 0.05 1.18

4.30 0.04 1.00

5.06 0.05 1.18

4.30 0.04 1.00

7.92 6.80 2.50 1.44

6.73 5.78 2.13 1.22

6.50 5.78 2.91 2.46

5.53 4.91 2.47 2.09

5.58 5.11 3.18 2.94

4.75 4.35 2.71 2.51

5.26 4.97 3.24 3.07

4.48 4.23 2.76 2.61

5.15 5.03 3.34 3.55

4.38 4.28 2.84 3.02

5.15 5.03 3.34 3.55

4.38 4.28 2.84 3.02

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-94 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.68

4.83

4.88

4.15

4.53

3.85

4.46

3.79

4.45

3.79

4.45

3.79

t_ZHS

5.53

4.71

4.65

3.96

4.22

3.59

4.14

3.52

4.05

3.45

4.05

3.45

Units

2 mA

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

3.60 0.05 1.10

3.06 0.04 0.93

2.81 0.05 1.10

2.39 0.04 0.93

2.47 0.05 1.10

2.10 0.04 0.93

2.40 0.05 1.10

2.04 0.04 0.93

2.39 0.05 1.10

2.04 0.04 0.93

2.39 0.05 1.10

2.04 0.04 0.93

3.66 3.52 2.49 1.49

3.12 3.00 2.12 1.27

2.87 2.64 2.90 2.55

2.44 2.25 2.47 2.17

2.51 2.21 3.18 3.04

2.14 1.88 2.70 2.59

2.45 2.13 3.24 3.17

2.08 1.81 2.76 2.70

2.44 2.04 3.33 3.67

2.08 1.73 2.83 3.12

2.44 2.04 3.33 3.67

2.08 1.73 2.83 3.12

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-66

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-95 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.36

7.96

7.93

6.74

7.06

6.01

7.06

6.01

t_ZHS

8.16

6.94

7.27

6.19

6.66

5.67

6.66

5.67

Units

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

7.21 0.05 1.17

6.13 0.04 0.99

5.81 0.05 1.17

4.94 0.04 0.99

4.96 0.05 1.17

4.22 0.04 0.99

4.96 0.05 1.17

4.22 0.04 0.99

7.35 6.14 2.03 1.32

6.25 5.23 1.72 1.12

5.92 5.26 2.39 2.25

5.03 4.47 2.03 1.91

5.05 4.65 2.64 2.69

4.30 3.96 2.25 2.29

5.05 4.65 2.64 2.69

4.30 3.96 2.25 2.29

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-96 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.30

4.50

4.54

3.86

4.22

3.59

4.22

3.59

t_ZHS

5.06

4.30

4.26

3.63

3.87

3.29

3.87

3.29

Units

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

3.22 0.05 1.08

2.74 0.04 0.92

2.48 0.05 1.08

2.11 0.04 0.92

2.17 0.05 1.08

1.85 0.04 0.92

2.17 0.05 1.08

1.85 0.04 0.92

3.28 3.04 2.02 1.37

2.79 2.59 1.72 1.17

2.53 2.25 2.38 2.34

2.15 1.92 2.03 1.99

2.21 1.86 2.64 2.79

1.88 1.58 2.24 2.37

2.21 1.86 2.64 2.79

1.88 1.58 2.24 2.37

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-67

ProASIC3L DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-97 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os

1.5 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Max. Max.

Drive

Strength

Min.

Max.

Min.

mA mA mA¹

mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

–0.3 0.35 * VCCI 0.65 * V_CCI1.575 0.25 * VCCI 0.75 * V_CCI

10 10

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-98 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max. Max.

mA mA mA¹mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

10 10

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-68

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-99 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

10 10

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-100 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_LOAD(pF)

1.5

0.75

Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-69

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-101 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.59 8.65 0.04 1.99 2.77 0.38 8.81 7.17 3.06 2.41 10.83 9.18

0.50 7.36 0.03 1.69 2.36 0.33 7.50 6.10 2.61 2.05 9.21

0.59 7.40 0.04 1.99 2.77 0.38 7.53 6.26 3.39 3.02 9.55

0.50 6.29 0.03 1.69 2.36 0.33 6.41 5.33 2.89 2.57 8.12

0.59 6.94 0.04 1.99 2.77 0.38 7.07 6.09 3.46 3.19 9.08

0.50 5.91 0.03 1.69 2.36 0.33 6.01 5.18 2.94 2.72 7.73

0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99

0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65

0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99

0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65

7.81

8.27

7.04

8.11

6.90

8.11

6.90

8.11

6.90

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-102 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.59 3.55 0.04 1.99 2.77 0.38 3.62 3.22 3.05 2.51 5.63

5.23

4.45

4.65

3.96

4.54

3.86

4.41

3.75

4.41

3.75

0.50 3.02 0.03 1.69 2.36 0.33 3.08 2.74 2.60 2.14 4.79

0.59 3.03 0.04 1.99 2.77 0.38 3.08 2.64 3.38 3.13 5.10

0.50 2.58 0.03 1.69 2.36 0.33 2.62 2.25 2.87 2.66 4.34

0.59 2.93 0.04 1.99 2.77 0.38 2.98 2.53 3.45 3.30 4.99

0.50 2.49 0.03 1.69 2.36 0.33 2.54 2.15 2.93 2.81 4.25

0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96

0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22

0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96

0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-70

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-103 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

9.02

7.68

8.22

7.00

8.06

6.86

8.12

6.91

8.12

6.91

Units

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

8.00 0.04 1.18

6.80 0.03 1.00

6.91 0.04 1.18

5.88 0.03 1.00

6.51 0.04 1.18

5.54 0.03 1.00

6.41 0.04 1.18

5.45 0.03 1.00

6.41 0.04 1.18

5.45 0.03 1.00

8.15 7.01 3.06 2.38 10.16

6.93 5.96 2.60 2.02

7.04 6.21 3.37 2.94

5.99 5.28 2.87 2.50

6.63 6.05 3.45 3.09

5.64 5.15 2.93 2.63

6.53 6.11 3.56 3.64

5.56 5.20 3.03 3.10

6.53 6.11 3.56 3.64

5.56 5.20 3.03 3.10

8.64

9.05

7.70

8.64

7.35

8.54

7.27

8.54

7.27

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-104 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.68

4.83

4.88

4.15

4.53

3.85

4.46

3.79

4.45

3.79

t_ZHS

5.53

4.71

4.65

3.96

4.22

3.59

4.14

3.52

4.05

3.45

Units

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

0.54

0.46

3.60 0.04 1.10

3.06 0.03 0.93

2.81 0.04 1.10

2.39 0.03 0.93

2.47 0.04 1.10

2.10 0.03 0.93

2.40 0.04 1.10

2.04 0.03 0.93

2.39 0.04 1.10

2.04 0.03 0.93

3.66 3.52 2.49 1.49

3.12 3.00 2.12 1.27

2.87 2.64 2.90 2.55

2.44 2.25 2.47 2.17

2.51 2.21 3.18 3.04

2.14 1.88 2.70 2.59

2.45 2.13 3.24 3.17

2.08 1.81 2.76 2.70

2.44 2.04 3.33 3.67

2.08 1.73 2.83 3.12

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-71

ProASIC3L DC and Switching Characteristics

Table 2-105 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.46

8.05

8.42

7.16

t_ZHS

8.40

7.14

7.67

6.52

Units

2 mA

4 mA

Std.

–1

0.54

0.46

0.54

0.46

7.32 0.04 1.17

6.22 0.03 0.99

6.29 0.04 1.17

5.35 0.03 0.99

7.45 6.38 2.44 2.18

6.34 5.43 2.08 1.86

6.40 5.65 2.73 2.70

5.45 4.81 2.33 2.29

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-106 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.38

0.33

0.38

0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.97

4.23

4.58

3.90

t_ZHS

4.64

3.95

4.15

3.53

Units

2 mA

4 mA

Notes:

Std.

–1

0.54

0.46

0.54

0.46

2.90 0.04 1.28

2.47 0.03 1.09

2.52 0.04 1.28

2.15 0.03 1.09

2.95 2.63 2.44 2.29

2.51 2.24 2.07 1.95

2.57 2.14 2.73 2.82

2.19 1.82 2.32 2.40

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-72

Revision 13

ProASIC3L Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-107 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.77 8.65 0.05 1.99 2.77 0.50 8.81 7.17 3.06 2.41 10.83 9.18

0.66 7.36 0.04 1.69 2.36 0.43 7.50 6.10 2.61 2.05 9.21

0.77 7.40 0.05 1.99 2.77 0.50 7.53 6.26 3.39 3.02 9.55

0.66 6.29 0.04 1.69 2.36 0.43 6.41 5.33 2.89 2.57 8.12

0.77 6.94 0.05 1.99 2.77 0.50 7.07 6.09 3.46 3.19 9.08

0.66 5.91 0.04 1.69 2.36 0.43 6.01 5.18 2.94 2.72 7.73

0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99

0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65

0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99

0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65

7.81

8.27

7.04

8.11

6.90

8.11

6.90

8.11

6.90

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-108 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.77 3.55 0.05 1.99 2.77 0.50 3.62 3.22 3.05 2.51 5.63

5.23

4.45

4.65

3.96

4.54

3.86

4.41

3.75

4.41

3.75

0.66 3.02 0.04 1.69 2.36 0.43 3.08 2.74 2.60 2.14 4.79

0.77 3.03 0.05 1.99 2.77 0.50 3.08 2.64 3.38 3.13 5.10

0.66 2.58 0.04 1.69 2.36 0.43 2.62 2.25 2.87 2.66 4.34

0.77 2.93 0.05 1.99 2.77 0.50 2.98 2.53 3.45 3.30 4.99

0.66 2.49 0.04 1.69 2.36 0.43 2.54 2.15 2.93 2.81 4.25

0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96

0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22

0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96

0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-73

ProASIC3L DC and Switching Characteristics

Table 2-109 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

9.02

7.68

8.22

7.00

8.06

6.86

8.12

6.91

8.12

6.91

Units

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

8.00 0.05 1.18

6.80 0.04 1.00

6.91 0.05 1.18

5.88 0.04 1.00

6.51 0.05 1.18

5.54 0.04 1.00

6.41 0.05 1.18

5.45 0.04 1.00

6.41 0.05 1.18

5.45 0.04 1.00

8.15 7.01 3.06 2.38 10.16

6.93 5.96 2.60 2.02

7.04 6.21 3.37 2.94

5.99 5.28 2.87 2.50

6.63 6.05 3.45 3.09

5.64 5.15 2.93 2.63

6.53 6.11 3.56 3.64

5.56 5.20 3.03 3.10

6.53 6.11 3.56 3.64

5.56 5.20 3.03 3.10

8.64

9.05

7.70

8.64

7.35

8.54

7.27

8.54

7.27

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-110 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.33

4.53

4.90

4.17

4.82

4.10

4.80

4.08

4.80

4.08

t_ZHS

5.12

4.36

4.59

3.90

4.48

3.81

4.37

3.72

4.37

3.72

Units

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

0.70

0.60

3.26 0.05 1.30

2.77 0.04 1.10

2.84 0.05 1.30

2.41 0.04 1.10

2.76 0.05 1.30

2.35 0.04 1.10

2.74 0.05 1.30

2.33 0.04 1.10

2.74 0.05 1.30

2.33 0.04 1.10

3.32 3.11 3.05 2.49

2.82 2.64 2.59 2.12

2.89 2.57 3.37 3.06

2.46 2.19 2.86 2.60

2.81 2.47 3.44 3.21

2.39 2.10 2.92 2.73

2.79 2.36 3.55 3.78

2.37 2.01 3.02 3.22

2.79 2.36 3.55 3.78

2.37 2.01 3.02 3.22

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-74

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-111 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.46

8.05

8.42

7.16

t_ZHS

8.40

7.14

7.67

6.52

Units

2 mA

4 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

7.32 0.05 1.17

6.22 0.04 0.99

6.29 0.05 1.17

5.35 0.04 0.99

7.45 6.38 2.44 2.18

6.34 5.43 2.08 1.86

6.40 5.65 2.73 2.70

5.45 4.81 2.33 2.29

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-112 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.50

0.43

0.50

0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.97

4.23

4.58

3.90

t_ZHS

4.64

3.95

4.15

3.53

Units

2 mA

4 mA

Notes:

Std.

–1

0.70

0.60

0.70

0.60

2.90 0.05 1.28

2.47 0.04 1.09

2.52 0.05 1.28

2.15 0.04 1.09

2.95 2.63 2.44 2.29

2.51 2.24 2.07 1.95

2.57 2.14 2.73 2.82

2.19 1.82 2.32 2.40

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-75

ProASIC3L DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V

applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-113 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS

VIL

VIH

Min.

VOL

VOH

IOL IOH IOSH¹IOSL¹IIL²IIH²

Drive

Strength

Min.

Max.

Min.

Max.

mA mA

µA µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2

TBD

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-114 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.2 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH¹IOSL¹IIL²IIH²

Max. Max.

Drive

Strength

Min.

Max.

Min.

mA mA mA

mA µA µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

TBD

TBD 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-115 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.2 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH¹IOSL¹IIL²IIH²

Drive

Strength

Min.

Max.

Min.

Max.

mA mA mA

Max.

µA µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

TBD

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-76

Revision 13

ProASIC3L Low Power Flash FPGAs

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

Table 2-116 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_LOAD(pF)

1.2

0.6

Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-77

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-117 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade t_DOUTt_DP

Unit

t_DINt_PYt_PYSt_EOUT

0.77 11.80 0.05 2.38 3.52 0.50 10.97 8.61 4.79 4.38 12.91 10.55

0.66 10.04 0.04 2.02 2.99 0.43 9.33 7.32 4.08 3.72 10.98 8.97

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

2 mA

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-118 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Pro I/O Banks

Drive

Strength

Speed

Grade t_DOUTt_DP

Unit

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

5.90

5.02

2 mA

Std.

–1

0.77

0.66

4.84 0.05 2.38 3.52 0.50

4.12 0.04 2.02 2.99 0.43

4.50 3.96 4.78 4.51 6.44

3.83 3.37 4.06 3.84 5.48

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-119 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

–1

0.70 8.77 0.05 1.82 0.50 6.17 5.45 2.80 2.77 8.11 7.39

0.60 7.46 0.04 1.55 0.43 5.25 4.63 2.39 2.35 6.90 6.28

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-120 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

–1

0.70 3.73 0.05 1.82 0.50 2.48 2.06 2.80 2.89 4.42 4.00

0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-121 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

–1

0.70 9.67 0.05 1.83 0.50 6.78 5.99 4.08 4.57 8.72 7.93

0.60 8.23 0.04 1.56 0.43 5.77 5.09 3.47 3.88 7.42 6.74

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-78

Revision 13

ProASIC3L Low Power Flash FPGAs

Table 2-122 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

–1

0.70 4.17 0.05 1.83 0.50 2.79 2.48 4.23 4.55 4.73 4.42

0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-79

ProASIC3L DC and Switching Characteristics

1.2 V LVCMOS Wide Range

Table 2-123 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Pro I/O Banks

1.2 V

Equivalent

LVCMOS

Software

Wide

Default

Drive

Range

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min.

Max.

Min.

Max. Max.

Strength Option¹

µA µA mA²mA²µA µA

100 µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20

26 10 10

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification

4. Software default selection highlighted in gray.

Table 2-124 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 Wide Range

Applicable to Advanced I/O Banks

1.2 V

Equivalent

LVCMOS

Software

Wide

Default

Drive

Range

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min.

Max.

Min.

Max. Max.

Strength Option¹

µA µA mA²mA²µA µA

100 µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20

26 10 10

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification

4. Software default selection highlighted in gray.

Table 2-125 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Standard Plus I/O Banks

1.2 V

LVCMOS

Wide

Range

Equivalent

Software

Default

Drive

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min.

Max.

Min.

Max. Max.

Strength Option¹

µA µA mA²mA²µA µA

100 µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20

26 10 10

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Currents are measured at 85°C junction temperature.

3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification

4. Software default selection highlighted in gray.

2-80

Revision 13

ProASIC3L Low Power Flash FPGAs

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-126 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

Max.

VIH

Max.

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL IIH

Min.

Max.

mA¹

Max.

mA¹

Drive Strength

Per PCI specification

Notes:

mA mA

µA²µA²

Per PCI curves

10 10

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the database; Microsemi loadings for

enable path characterization are described in Figure 2-12.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

10 pF for t_HZ/ t_LZ

Figure 2-12 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-127.

Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C_LOAD(pF)

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-128 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.33 0.38

2.84 0.33

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.59 2.52

0.50 2.15

0.04 2.47

0.03 2.10

2.57 1.80

2.19 1.53

2.95 3.25

2.51 2.77

4.58 3.81

3.90 3.24

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-81

ProASIC3L DC and Switching Characteristics

Table 2-129 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.38 2.46

0.33 2.09

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.77

3.21

t_ZHSUnits

Std.

–1

0.54 2.41

0.46 2.05

0.04 0.78

0.03 0.66

1.76 2.89

1.49 2.46

3.22 4.47

2.74 3.80

0.54

0.46

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-130 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.38 2.12

0.33 1.80

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.55

3.02

t_ZHSUnits

Std.

–1

0.54 2.08

0.46 1.77

0.04 0.77

0.03 0.65

1.53 2.51

1.31 2.14

2.90 4.13

2.47 3.51

0.54

0.46

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-131 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.33 0.50

2.84 0.43

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.77 2.52

0.66 2.15

0.05 2.47

0.04 2.10

2.57 1.80

2.19 1.53

2.95 3.25

2.51 2.77

4.58 3.81

3.90 3.24

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-132 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.50 2.46

0.43 2.09

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.70 2.41

0.60 2.05

0.05 0.78

0.04 0.66

1.76 2.89

1.49 2.46

3.22 4.47

2.74 3.80

3.77 0.73

3.21 0.62

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-133 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.50 2.12

0.43 1.80

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.70 2.08

0.60 1.77

0.05 0.77

0.04 0.65

1.53 2.51

1.31 2.14

2.90 4.13

2.47 3.51

3.55 0.73

3.02 0.62

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-82

Revision 13

ProASIC3L Low Power Flash FPGAs

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V.

Table 2-134 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

268

181

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

Test Point

10 pF

Figure 2-13 • AC Loading

Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

Note: *Measuring point = Vtrip_.See Table 2-16 on page 2-12 for a complete table of trip points.

Revision 13

2-83

ProASIC3L DC and Switching Characteristics

Timing Characteristics

Table 2-136 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.87

1.59

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.85

3.27

t_ZHS

3.88

3.30

Units

Std.

2.12

1.80

1.83

1.56

1.87

1.59

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-137 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Applicable to Pro I/Os

Speed

Grade

t_DOUT

0.77

t_DP

1.87

1.59

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.85

3.27

t_ZHS

3.88

3.30

Units

Std.

2.12

1.80

1.83

1.56

1.87

1.59

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-84

Revision 13

ProASIC3L Low Power Flash FPGAs

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The V_CCIpin should be connected to 2.5 V

Table 2-138 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

2.7

0.4

–

20 20

169

124

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

Test Point

10 pF

Figure 2-14 • AC Loading

Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

Revision 13

2-85

ProASIC3L DC and Switching Characteristics

Timing Characteristics

Table 2-140 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.92

1.63

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.96

3.37

t_ZHS

3.93

3.34

Units

Std.

2.05

1.75

1.95

1.66

1.92

1.63

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-141 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.92

1.63

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.96

3.37

t_ZHS

3.93

3.34

Units

Std.

2.05

1.75

1.95

1.66

1.92

1.63

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-86

Revision 13

ProASIC3L Low Power Flash FPGAs

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V

Table 2-142 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

35 mA

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.6

–

35 35

268

181

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

GTL+

Test Point

10 pF

Figure 2-15 • AC Loading

Table 2-143 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

Timing Characteristics

Table 2-144 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.85

1.57

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.90

3.31

t_ZHS

3.86

3.29

Units

Std.

2.12

1.80

1.88

1.60

1.85

1.57

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-145 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.85

1.57

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.90

3.31

t_ZHS

3.86

3.29

Units

Std.

2.12

1.80

1.88

1.60

1.85

1.57

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-87

ProASIC3L DC and Switching Characteristics

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 2.5 V.

Table 2-146 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

mA mA mA¹

µA²µA²

33 mA

–0.3 VREF – 0.1 VREF + 0.1

2.7

0.6

–

33 33

169

124

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

GTL+

Test Point

10 pF

Figure 2-16 • AC Loading

Table 2-147 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

2-88

Revision 13

ProASIC3L Low Power Flash FPGAs

Timing Characteristics

Table 2-148 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.99

1.69

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.03

3.43

t_ZHS

3.90

3.32

Units

Std.

–1

2.05

1.75

2.02

1.72

1.89

1.61

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-16 on page 2-12 for derating

values.

Table 2-149 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.99

1.69

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.03

3.43

t_ZHS

3.90

3.32

Units

Std.

2.05

1.75

2.02

1.72

1.89

1.61

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-16 on page 2-12 for derating

values.

Revision 13

2-89

ProASIC3L DC and Switching Characteristics

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-150 • Minimum and Maximum DC Input and Output Levels

HSTL

Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

mA mA mA¹

µA²µA²

8 mA

–0.3 VREF – 0.1 VREF + 0.1 1.575

0.4

VCCI – 0.4

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

HSTL

Class I

Test Point

20 pF

Figure 2-17 • AC Loading

Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring Point*

Input Low (V)

Input High (V)

(V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

Note: *Measuring point = Vtrip_.See Table 2-16 on page 2-12 for a complete table of trip points.

2-90

Revision 13

ProASIC3L Low Power Flash FPGAs

Timing Characteristics

Table 2-152 • HSTL Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

2.86

2.43

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.93

4.19

t_ZHS

4.84

4.12

Units

Std.

–1

2.50

2.12

2.91

2.48

2.83

2.41

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-153 • HSTL Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

2.86

2.43

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.93

4.19

t_ZHS

4.84

4.12

Units

Std.

2.50

2.12

2.91

2.48

2.83

2.41

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-91

ProASIC3L DC and Switching Characteristics

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-154 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max. Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

15 mA³

–0.3 VREF – 0.1 VREF + 0.1 1.575

0.4

VCCI – 0.4 15 15

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

HSTL

Class II

Test Point

20 pF

Figure 2-18 • AC Loading

Table 2-155 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

2-92

Revision 13

ProASIC3L Low Power Flash FPGAs

Timing Characteristics

Table 2-156 • HSTL Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

2.72

2.32

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.78

4.07

t_ZHS

4.45

3.79

Units

Std.

–1

2.50

2.12

2.77

2.36

2.44

2.08

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-157 • HSTL Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

2.72

2.32

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.78

4.07

t_ZHS

4.45

3.79

Units

Std.

2.50

2.12

2.77

2.36

2.44

2.08

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-93

ProASIC3L DC and Switching Characteristics

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-158 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

15 mA

–0.3 VREF – 0.2 VREF + 0.2

2.7

0.54 VCCI – 0.62 15 15

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

SSTL2

Class I

Test Point

30 pF

Figure 2-19 • AC Loading

Table 2-159 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

1.25

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

2-94

Revision 13

ProASIC3L Low Power Flash FPGAs

Timing Characteristics

Table 2-160 • SSTL2 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Applicable to Pro I/Os

Speed

Grade

t_DOUT

0.59

t_DP

1.91

1.63

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.95

1.66

t_ZHS

1.66

1.41

Units

Std.

–1

1.89

1.61

1.95

1.66

1.41

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-161 • SSTL2 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.91

1.63

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.95

1.66

t_ZHS

1.66

1.41

Units

Std.

1.89

1.61

1.95

1.66

1.41

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-95

ProASIC3L DC and Switching Characteristics

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-162 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max. Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

18 mA

–0.3 VREF – 0.2 VREF + 0.2 2.7

0.35

VCCI – 0.43 18 18

169

124

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

SSTL2

Class II

Test Point

30 pF

Figure 2-20 • AC Loading

Table 2-163 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

1.25

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

Timing Characteristics

Table 2-164 • SSTL2 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.95

1.66

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.99

1.69

t_ZHS

1.59

1.36

Units

Std.

1.89

1.61

1.99

1.69

1.59

1.36

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-165 • SSTL2 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case V_CCI= 2.3 V VREF = 1.25 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.95

1.66

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.99

1.69

t_ZHS

1.59

1.36

Units

Std.

1.89

1.61

1.99

1.69

1.59

1.36

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-96

Revision 13

ProASIC3L Low Power Flash FPGAs

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-166 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

14 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.7

VCCI – 1.1 14 14

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

SSTL3

Class I

Test Point

30 pF

Figure 2-21 • AC Loading

Table 2-167 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

1.485

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points.

Timing Characteristics

Table 2-168 • SSTL3 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

2.08

1.77

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.11

1.80

t_ZHS

1.65

1.41

Units

Std.

1.81

1.54

2.11

1.80

1.65

1.41

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-169 • SSTL3 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

2.08

1.77

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.11

1.80

t_ZHS

1.65

1.41

Units

Std.

1.81

1.54

2.11

1.80

1.65

1.41

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-97

ProASIC3L DC and Switching Characteristics

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-170 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

21 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.5

VCCI – 0.9 21 21

103

109

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

SSTL3

Class II

Test Point

30 pF

Figure 2-22 • AC Loading

Table 2-171 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

1.485

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

Note: *Measuring point = Vtrip_.See Table 2-16 on page 2-12 for a complete table of trip points.

Timing Characteristics

Table 2-172 • SSTL3 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.59

t_DP

1.86

1.58

t_DIN

0.04

0.03

t_PY

t_EOUT

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.89

1.61

t_ZHS

1.50

1.28

Units

Std.

1.81

1.54

1.89

1.61

1.50

1.28

–1

0.50

0.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-173 • SSTL3 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Applicable to Pro I/O Banks

Speed

Grade

t_DOUT

0.77

t_DP

1.86

1.58

t_DIN

0.05

0.04

t_PY

t_EOUT

0.50

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.89

1.61

t_ZHS

1.50

1.28

Units

Std.

1.81

1.54

1.89

1.61

1.50

1.28

–1

0.66

0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-98

Revision 13

ProASIC3L Low Power Flash FPGAs

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Designer software when the user

instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

–

100 

Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation

Revision 13

2-99

ProASIC3L DC and Switching Characteristics

Table 2-174 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

Output Low Voltage

VOL

1.075

1.425

0.91

Output High Voltage

VOH

1.25

0.65

IOL ¹

1.16

2.925

Output Lower Current

Output High Current

IOH ¹

Input Voltage

V_I

IIH ²

µA

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

IIL ²

VODIFF

VOCM

VICM

VIDIFF

Notes:

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

1. Currents are measured at 85°C junction temperature.

2. IOL/IOH is defined by VODIFF/(Resistor Network).

Table 2-175 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.075

1.325

Cross point

Note: *Measuring point = V_trip.See Table 2-27 on page 2-26 for a complete table of trip points.

2-100

Revision 13

ProASIC3L Low Power Flash FPGAs

Timing Characteristics

1.5 V DC Core Voltage

Table 2-176 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Speed Grade

t_DOUT

0.59

t_DP

1.65

1.40

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

2.18

1.85

0.50

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-177 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.54

t_DP

1.65

1.40

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

1.44

1.23

0.46

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-178 • LVDS – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Pro I/O Banks

Speed Grade

t_DOUT

0.77

t_DP

1.68

1.43

t_DIN

0.05

0.04

t_PY

Units

Std.

–1

2.18

1.85

0.66

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-179 • LVDS – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.70

t_DP

1.65

1.40

t_DIN

0.05

0.04

t_PY

Units

Std.

–1

1.44

1.23

0.60

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 13

2-101

ProASIC3L DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in

the LVDS section in Table 2-174 on page 2-100.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

Receiver

Transceiver

BIBUF_LVDS

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-102

Revision 13

ProASIC3L Low Power Flash FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

OUTBUF_LVPECL

100 

Z₀= 50 

187 W

INBUF_LVPECL

–

100 

Z₀= 50 

Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-180 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

3.3

Min.

Max.

Units

3.0

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

1.43

2.28

3.6

1.30

2.13

1.57

2.41

3.6

VOH

Output High Voltage

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0.625

1.762

1.01

300

0.97 0.625

1.98 1.762

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

1.01

300

VIDIFF

Table 2-181 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.64

1.94

Cross point

Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

Revision 13

2-103

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-182 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Speed Grade

t_DOUT

0.59

t_DP

1.64

1.40

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

1.97

1.67

0.50

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-183 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.54

t_DP

1.62

1.38

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

1.26

1.08

0.46

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-184 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Speed Grade

t_DOUT

0.77

t_DP

1.62

1.37

t_DIN

0.05

0.04

t_PY

Units

Std.

–1

1.97

1.67

0.66

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-185 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.70

t_DP

1.62

1.38

t_DIN

0.05

0.04

t_PY

Units

Std.

–1

1.26

1.08

0.60

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-104

Revision 13

ProASIC3L Low Power Flash FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

DOUT

Data_out

PRE

Core

Array

Data

Enable

CLK

DFN1E1P1

EOUT

PRE

DFN1E1P1

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Revision 13

2-105

ProASIC3L DC and Switching Characteristics

Table 2-186 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

Note: *See Figure 2-26 on page 2-105 for more information.

2-106

Revision 13

ProASIC3L Low Power Flash FPGAs

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

Data_out

Core

Data

Array

DFN1E1C1

EOUT

Enable

CLK

CLR

DFN1E1C1

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Revision 13

2-107

ProASIC3L DC and Switching Characteristics

Table 2-187 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

GG, HH

LL, DOUT

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-27 on page 2-107 for more information.

2-108

Revision 13

ProASIC3L Low Power Flash FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

CLK

Data

t_IHD

50%

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-28 • Input Register Timing Diagram

Revision 13

2-109

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-188 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Description

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

–1 Std. Units

0.24 0.29 ns

0.27 0.31 ns

0.00 0.00 ns

0.38 0.45 ns

0.00 0.00 ns

0.46 0.54 ns

0.00 0.00 ns

0.23 0.27 ns

0.00 0.00 ns

0.23 0.27 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-189 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_ICLKQ

Description

Clock-to-Q of the Input Data Register

–1 Std. Units

0.32 0.37 ns

0.35 0.41 ns

0.00 0.00 ns

0.50 0.58 ns

0.00 0.00 ns

0.60 0.71 ns

0.00 0.00 ns

0.30 0.35 ns

0.00 0.00 ns

0.30 0.35 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-110

Revision 13

ProASIC3L Low Power Flash FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-29 • Output Register Timing Diagram

Revision 13

2-111

ProASIC3L DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-190 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.60 0.71

0.32 0.37

0.00 0.00

0.45 0.53

0.00 0.00

0.82 0.96

0.00 0.00

0.23 0.27

0.00 0.00

0.23 0.27

0.19 0.22

0.31 0.36

0.28 0.32

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width High for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-191 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.78 0.92

0.42 0.49

0.00 0.00

0.58 0.69

0.00 0.00

1.07 1.26

0.00 0.00

0.30 0.35