M1AGL250V2-CSG196YI_技术文档

2 – IGLOO DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-

2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits¹

Units

–0.3 to 1.65

V

VJTAG

VPUMP

VCCPLL

–0.3 to 3.75

Programming voltage

–0.3 to 3.75

–0.3 to 1.65

Analog power supply (PLL)

VCCI and VMV ²DC I/O buffer supply voltage

–0.3 to 3.75

VI

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

3

T_STG

Storage Temperature

Junction Temperature

–65 to +150

+125

°C

3

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA

Fabric User’s Guide for further information.

3. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-3, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

Revision 24

2-1

IGLOO DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_A

Parameter

Commercial

0 to +70

Industrial

–40 to +85

–40 to +100

Units

°C

V

Ambient Temperature

Junction Temperature ²

T_J

VCC³

0 to +85

1.5 V DC core supply voltage⁵

1.425 to 1.575 1.425 to 1.575

1.14 to 1.575 1.14 to 1.575

1.2 V–1.5 V wide range DC

core supply voltage ^4,6

V

VJTAG

JTAG DC voltage

1.4 to 3.6

3.15 to 3.45

0 to 3.6

1.4 to 3.6

3.15 to 3.45

0 to 3.6

V

VPUMP

Programming voltage

Programming Mode

Operation ⁷

VCCPLL⁸Analog power supply (PLL)

1.5 V DC core supply voltage⁵1.425 to 1.575 1.425 to 1.575

1.2 V – 1.5 V DC core supply 1.14 to 1.575 1.14 to 1.575

voltage^4,6

VCCI and 1.2 V DC core supply voltage⁶

1.14 to 1.26

V

VMV ⁹

1.2 V DC wide range DC

1.14 to 1.575 1.14 to 1.575

supply voltage⁶

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.0 V DC supply voltage ¹⁰

3.3 V DC supply voltage

LVDS differential I/O

LVPECL differential I/O

Notes:

1.425 to 1.575 1.425 to 1.575

V

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

2.375 to 2.625 2.375 to 2.625

3.0 to 3.6 3.0 to 3.6

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-25 on page 2-24. VCCI should be at the same voltage within a given I/O bank.

4. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2

devices powered by 1.2 V supply must switch the core supply to 1.5 V for in-system programming.

®

5. For IGLOO V5 devices

6. For IGLOO V2 devices only, operating at VCCI  VCC.

7. VPUMP can be left floating during operation (not programming mode).

8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User Guide for

further information.

9. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA

Fabric User Guide for further information.

10. 3.3 V wide range is compliant to the JESD-8B specification and supports 3.0 V VCCI operation.

2-2

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature¹

Product

Grade

Programming

Cycles

Program Retention

Maximum Storage

Maximum Operating Junction

Temperature T_J(°C) ²

(biased/unbiased) Temperature T_STG(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

Table 2-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or Undershoot Duration

as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot²

VCCI

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

IGLOO I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V

Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V

Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V

VCC Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V

Revision 24

2-3

IGLOO DC and Switching Characteristics

Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the

output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low

Power Flash Devices" chapter of the ProASIC^®3 and ProASIC3E FPGA fabric user guides for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

To make sure the transition from input buffers to output buffers is clean, ensure that there is no path

longer than 100 ns from input buffer to output buffer in your design.

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential inputs)

but slower because VCCI

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

but I/Os are slower because

the VCC is below specification.

Activation trip point:

V_a= 0.85 V ± 0.25 V

Deactivation trip point:

V_d= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

VCCI

Activation trip point:

Min VCCI datasheet specification

V_a= 0.9 V ± 0.3 V

Deactivation trip point:

V_d= 0.8 V ± 0.3 V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 24

IGLOO Low Power Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

Region 4: I/O

Region 1: I/O Buffers are OFF

and power supplies are within

specification.

buffers are ON.

I/Os are functional

(except differential inputs)

I/Os meet the entire datasheet

and timer specifications for

but slower because VCCI is

speed, VIH / VIL , VOH / VOL , etc.

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

but I/Os are slower because

the VCC is below specification.

Activation trip point:

V_a= 0.85 V ± 0.2 V

Deactivation trip point:

V_d= 0.75 V ± 0.2 V

Region 1: I/O buffers are OFF

Activation trip point:

V_a= 0.9 V ± 0.15 V

Deactivation trip point:

V_d= 0.8 V ± 0.15 V

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

VCCI

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5 on page 2-6.

P = Power dissipation

Revision 24

2-5

IGLOO DC and Switching Characteristics

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for the AGL1000-FG484 package at commercial temperature and in still air.

100C – 70C

23.3°C/W

Max. junction temp. (C) – Max. ambient temp. (C)

------------------------------------

Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ =

= 1.28 W

EQ 2

_ja(C/W)

Table 2-5 • Package Thermal Resistivities

_ja

Package Type

Device

AGL030

AGL060

AGL125

AGL250

AGL030

Pin Count

132

68

j_c

13.1

11.0

9.2

Still Air

21.4

21.2

21.1

21.0

68.4

35.3

28.0

37.1

38.3

39.5

32.8

28.8

26.9

40.6

55.2

31.6

37.6

38.6

28.1

23.3

1 m/s

16.8

16.6

16.5

16.4

45.8

29.4

22.8

31.1

32.2

33.4

28.5

24.8

22.3

35.2

49.4

26.2

31.2

34.7

24.4

19.0

2.5 m/s

Unit

Quad Flat No Lead (QN)

15.3

15.0

14.9

14.8

43.1

27.1

21.5

28.9

30.0

31.1

27.2

23.5

20.9

33.7

47.2

24.2

29.0

33.0

22.7

16.7

C/W

8.9

13.4

10.0

6.0

Very Thin Quad Flat Pack (VQ)*

Chip Scale Package (CS)

100

281

196

81

AGL1000

AGL400

AGL250

AGL125

AGL030

AGL060

AGL250

AGL030

AGL060

AGL1000

AGL400

AGL250

AGL1000

7.2

7.6

8.0

12.4

11.1

10.4

16.9

18.6

6.3

81

Micro Chip Scale Package (UC)

Fine Pitch Ball Grid Array (FG)

81

144

256

484

6.8

12.0

6.6

8.0

Note: *Thermal resistances for other device-package combinations will be posted in a later revision.

Disclaimer:

The simulation for determining the junction-to-air thermal resistance is based on JEDEC standards

(JESD51) and assumptions made in building the model. Junction-to-case is based on SEMI G38-88.

JESD51 is only used for comparing one package to another package, provided the two tests uses the

same condition. They have little relevance in actual application and therefore should be used with a

degree of caution.

2-6

Revision 24

IGLOO Low Power Flash FPGAs

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

VCC = 1.425 V)

For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0.934

0.855

0.799

0°C

25°C

0.971

0.891

0.832

70°C

1.000

0.917

0.857

85°C

1.007

0.924

0.864

100°C

1.013

0.929

0.868

1.425

0.953

0.874

0.816

1.500

1.575

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

VCC = 1.14 V)

For IGLOO V2, 1.2 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0.967

0.864

0.794

0°C

25°C

0.991

0.885

0.814

70°C

1.000

0.894

0.821

85°C

1.006

0.899

0.827

100°C

1.010

0.902

0.830

1.14

0.978

0.874

0.803

1.20

1.26

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages

(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage.

Microsemi recommends using the PowerCalculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage, operating

voltage, and temperature.

Table 2-8 • Power Supply State per Mode

Power Supply Configurations

Modes/power supplies

Flash*Freeze

VCC

On

VCCPLL

VCCI

On

VJTAG

VPUMP

On/off/floating

Off

On

Off

On

Off

On

Sleep

Off

On

Shutdown

Off

No Flash*Freeze

Note: Off: Power supply level = 0 V

On

On/off/floating

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

Typical

(25°C)

1.2 V

1.5 V

4

6

8

13

18

20

34

27

51

30

72

44

µA

6

10

127

Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution,

which is shown in Table 2-13 on page 2-10 through Table 2-15 on page 2-11 and Table 2-16 on page 2-11

through Table 2-18 on page 2-12 (PDC6 and PDC7).

Revision 24

2-7

IGLOO DC and Switching Characteristics

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

VCCI/ VJTAG = 1.2 V

(per bank) Typical

(25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.5 V 1.2 V /

(per bank) Typical

(25°C)

1.5 V

VCCI/VJTAG = 1.8 V 1.2 V /

(per bank) Typical

(25°C)

1.5 V

VCCI/VJTAG = 2.5 V 1.2 V /

(per bank) Typical

(25°C)

1.5 V

VCCI/VJTAG = 3.3 V 1.2 V /

(per bank) Typical

(25°C)

1.5 V

Note: IDD = N_BANKS× ICCI. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-10

through Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12 (PDC6 and

PDC7).

Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode

Core Voltage

AGL015

AGL030

Units

Typical (25°C)

1.2 V / 1.5 V

0

µA

2-8

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-12 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode¹

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

ICCA Current²

Typical (25°C)

1.2 V

1.5 V

5

6

10

20

13

28

18

44

25

66

28

82

42

µA

14

16

137

ICCI or IJTAG Current³

VCCI/VJTAG = 1.2 V

(per bank) Typical

(25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.5 V

(per bank) Typical

(25°C)

1.2 V /

1.5 V

VCCI/VJTAG = 1.8 V

(per bank) Typical

(25°C)

1.2 V /

1.5 V

VCCI/VJTAG = 2.5 V

(per bank) Typical

(25°C)

1.2 V /

1.5 V

VCCI/VJTAG = 3.3 V

(per bank) Typical

(25°C)

1.2 V /

1.5 V

Notes:

1. IDD = N

× ICCI + ICCA. JTAG counts as one bank when powered.

BANKS

2. Includes VCC, VPUMP, and VCCPLL currents.

3. Values do not include I/O static contribution (PDC6 and PDC7).

Revision 24

2-9

IGLOO DC and Switching Characteristics

Power per I/O Pin

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

Static Power

PDC6 (mW)¹

Dynamic Power

VCCI (V)

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range³

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

1.2 V LVCMOS Wide Range⁴

3.3 V PCI

3.3

2.5

1.8

1.5

1.2

3.3

–

16.27

4.65

1.61

0.96

0.58

17.67

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

23.39

59.05

LVPECL

Notes:

1.

2.

P

is the static power (where applicable) measured on VCCI.

is the total dynamic power measured on VCCI.

DC6

AC9

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable for IGLOO V2 devices only

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Static Power

PDC6 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

VCCI (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.41

4.75

1.8 V LVCMOS

1.66

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

1.2 V LVCMOS Wide Range⁴

1.00

0.61

3.3 V PCI

17.78

3.3 V PCI-X

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. Applicable for IGLOO V2 devices only.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

2-10

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

Static Power

PDC6 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

VCCI (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

–

17.24

5.64

2.63

1.97

0.57

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

1.2 V LVCMOS Wide Range⁴

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable for IGLOO V2 devices only.

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range⁴

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁵

1.2 V LVCMOS Wide Range⁵

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

136.95

76.84

49.31

33.36

16.24

194.05

5

10

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

156.22

339.35

LVPECL

19.54

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. Applicable for IGLOO V2 devices only.

Revision 24

2-11

IGLOO DC and Switching Characteristics

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range⁴

2.5 V LVCMOS

5

3.3

2.5

1.8

1.5

1.2

3.3

–

122.16

68.37

34.53

23.66

14.90

181.06

5

1.8 V LVCMOS

5

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁵

1.2 V LVCMOS Wide Range⁵

5

3.3 V PCI

10

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2.

3.

P

is the static power (where applicable) measured on VCCI.

DC7

is the total dynamic power measured on VCCI.

AC10

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. Applicable for IGLOO V2 devices only.

Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard I/O Banks

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range⁴

2.5 V LVCMOS

5

3.3

2.5

1.8

1.5

1.2

–

104.38

59.86

31.26

21.96

13.49

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁵

1.2 V LVCMOS Wide Range⁵

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. Applicable for IGLOO V2 devices only.

2-12

Revision 24

IGLOO Low Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-19 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1

Clock contribution of a

Global Rib

7.778

4.334

1.379

0.151

6.221

3.512

1.445

0.149

6.082

2.759

1.377

0.151

4.460

2.718

1.483

0.149

4.446

1.753

1.467

0.149

2.736

1.971

1.503

0.151

0.000

3.483

1.472

0.146

0.000

3.483

1.472

0.146

PAC2

PAC3

PAC4

Clock contribution of a

Global Spine

Clock contribution of a

VersaTile row

Clock contribution of a

VersaTile used as a

sequential module

PAC5

PAC6

PAC7

First contribution of a

VersaTile used as a

sequential module

0.057

Second contribution of a

VersaTile used as a

sequential module

0.207

Contribution of a

VersaTile used as a

combinatorial module

0.276

1.161

0.262

1.147

0.279

1.193

0.277

0.280

1.076

0.300

1.088

0.281

1.134

0.273

1.153

PAC8

PAC9

Average contribution of a

routing net

1.273

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

Average contribution of a

RAM block during a read

operation

25.00

30.00

2.70

Average contribution of a

RAM block during a write

operation

Dynamic PLL

contribution

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Revision 24

2-13

IGLOO DC and Switching Characteristics

Table 2-20 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device-Specific Static Power (mW)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PDC1

Array static power in Active

mode

See Table 2-12 on page 2-9.

PDC2

PDC3

Array static power in Static

(Idle) mode

See Table 2-11 on page 2-8.

See Table 2-9 on page 2-7.

Array static power in

Flash*Freeze mode

PDC4

PDC5

Static PLL contribution

1.84

Bank quiescent power

(V_CCI-dependent)

See Table 2-12 on page 2-9.

PDC6

PDC7

I/O input pin static power

(standard-dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

I/O output pin static power

(standard-dependent)

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

2-14

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-21 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PAC1

Clock contribution of a

Global Rib

4.978

2.773

0.883

0.096

3.982

2.248

0.924

0.095

3.892

1.765

0.881

0.096

2.854

1.740

0.949

0.095

2.845

1.122

0.939

0.095

1.751

1.261

0.962

0.096

0.000

2.229

0.942

0.094

0.000

2.229

0.942

0.094

PAC2

PAC3

PAC4

Clock contribution of a

Global Spine

Clock contribution of a

VersaTile row

Clock contribution of a

VersaTile used as a

sequential module

PAC5

PAC6

PAC7

First contribution of a

VersaTile used as a

sequential module

0.045

Second contribution of a

VersaTile used as a

sequential module

0.186

Contribution of a

VersaTile used as a

combinatorial module

0.158

0.756

0.149

0.729

0.158

0.753

0.157

0.160

0.678

0.170

0.692

0.160

0.738

0.155

0.721

PAC8

PAC9

Average contribution of a

routing net

0.817

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

Average contribution of a

RAM block during a read

operation

25.00

30.00

2.10

Average contribution of a

RAM block during a write

operation

Dynamic PLL contribution

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Revision 24

2-15

IGLOO DC and Switching Characteristics

Table 2-22 • Different Components Contributing to the Static Power Consumption in IGLOO Device

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Static Power (mW)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

PDC1

Array static power in

Active mode

See Table 2-12 on page 2-9.

PDC2

PDC3

Array static power in Static

(Idle) mode

See Table 2-11 on page 2-8.

See Table 2-9 on page 2-7.

Array static power in

Flash*Freeze mode

PDC4

PDC5

Static PLL contribution

0.90

Bank quiescent power

(VCCI-Dependent)

See Table 2-12 on page 2-9.

PDC6

PDC7

I/O input pin static power

(standard-dependent)

See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.

See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.

I/O output pin static

power (standard-

dependent)

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

2-16

Revision 24

IGLOO Low Power Flash FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Microsemi Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-23 on

page 2-19.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-24 on

page 2-19.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-24 on page 2-19. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (P_DC1or P_DC2or P_DC3) + N_BANKS* P_DC5+ N_INPUTS* P_DC6+ N_OUTPUTS* P_DC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE* P_AC2+ N_ROW* P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the IGLOO FPGA Fabric User’s Guide.

N

_ROWis the number of VersaTile rows used in the design—guidelines are provided in the

"Spine Architecture" section of the IGLOO FPGA Fabric User’s Guide.

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

F

N

P

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ ₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-19.

F_CLKis the global clock signal frequency.

Revision 24

2-17

IGLOO DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-19.

F

_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on

page 2-19.

F_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-24 on page 2-19.

F

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* ₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-24 on

page 2-19.

PLL Contribution—P

PLL

P_PLL= P_DC4+ P_AC13*F_CLKOUT

F_CLKOUTis the output clock frequency.^†

† If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

2-18

Revision 24

IGLOO Low Power Flash FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-23 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-24 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

Revision 24

2-19

IGLOO DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

LVPECL (Applicable to

Advanced I/O Banks Only)L

Y

t_PD= 1.22 ns

t_PD= 1.20 ns

t_DP= 1.72 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

Output drive strength = 12 mA

High slew rate

LVTTL

t_DP= 3.05 ns (Advanced I/O Banks)

t_PD= 1.80 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Y

Output drive strength = 8 mA

High slew rate

LVTTL

t

_PY= 1.20 ns

t_DP= 4.12 ns (Advanced I/O Banks)

LVPECL

(Applicable

to Advanced

I/O Banks only)

t_PD= 1.49 ns

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

Output drive strength = 4 mA

LVCMOS 1.5 V

High slew rate

t

_ICLKQ= 0.43 ns

t

_DP= 4.42 ns (Advanced I/O Banks)

t_PD= 0.86 ns

t_ISUD= 0.47 ns

Input LVTTL

Clock

I/O Module

(Registered)

Register Cell

Combinational Cell

t

_PY= 0.87 ns (Advanced I/O Banks)

Y

D

Q

D

Q

D

Q

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

(Non-Registered)

t_PD= 0.92 ns

t_DP= 3.05 ns

(Advanced I/O Banks)

t_CLKQ= 0.90 ns

t_SUD= 0.82 ns

t

_OCLKQ= 1.02 ns

_OSUD= 0.52 ns

t

_CLKQ= 0.90 ns

LVDS,

BLVDS,

M-LVDS

t_SUD= 0.82 ns

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t_PY= 1.35 ns

t_PY= 0.87 ns

(Advanced I/O Banks)

Figure 2-3 • Timing Model

Operating Conditions: Std. Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices

2-20

Revision 24

IGLOO Low Power Flash FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

V_trip

VIL

PAD

VCC

50%

Y

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

Revision 24

2-21

IGLOO DC and Switching Characteristics

t_DOUT

t_DP

D Q

CLK

PAD

DOUT

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

2-22

Revision 24

IGLOO Low Power Flash FPGAs

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% VCCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

Revision 24

2-23

IGLOO DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

Equivalent

Software

Default

VIL

VIH

VOL

VOH

IOL¹IOH¹

Drive

I/O

Drive

Strength Slew

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Standard Strength Option²Rate Min.V

mA mA

3.3 V

LVTTL /

3.3 V

12 mA

High –0.3

0.8

2

3.6

2.7

0.4

2.4

12

LVCMOS

3.3 V

100 µA

0.8

2

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide

Range³

2.5 V

LVCMOS

12 mA

2 mA

12 mA

2 mA

0.7

1.7

0.7

1.7

12

2

1.8 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12

1.5 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12

High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

1.2 V

2

LVCMOS⁴

1.2 V

100 µA

2 mA

High –0.3 0.3 * VCCI 0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide

Range^4,5

3.3 V PCI

Per PCI specifications

3.3 V

Per PCI-X specifications

PCI-X

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable to V2 Devices operating at VCCI VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

2-24

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

Equivalent

Software

VIL

VIH

VOL

VOH

I_OLI_OH

Default

Drive

I/O

Drive

Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Standard Strength Option²Rate

V

mA mA

12 12

3.3 V

LVTTL /

3.3 V

12 mA

High –0.3

0.8

2

3.6

2.7

0.4

2.4

LVCMOS

3.3 V

100 µA

12 mA

0.8

2

0.2

VDD-0.2

0.1 0.1

LVCMOS

Wide

Range³

2.5 V

LVCMOS

12 mA

8 mA

12 mA

8 mA

4 mA

2 mA

0.7

1.7

0.7

1.7

12

8

12

8

1.8 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45

1.5 V

LVCMOS

4 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

4

1.2 V

2 mA

2

LVCMOS⁴

1.2 V

100 µA

High –0.3 0.3 * VCCI 0.7 * VCCI 1.575

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide

Range⁴

3.3 V PCI

Per PCI specifications

3.3 V

Per PCI-X specifications

PCI-X

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable to V2 Devices operating at VCCI  VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

Revision 24

2-25

IGLOO DC and Switching Characteristics

Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

1

Equivalent

Software

VIL

V_IH

VOL

V_OH

I_OLI_OH

Default

Drive

I/O

Drive

Strength Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Standard Strength Option²Rate

V

mA mA

3.3 V

LVTTL /

3.3 V

8 mA

High –0.3

0.8

0.7

2

3.6

0.4

2.4

8

LVCMOS

3.3 V

100 µA

8 mA

2

0.2

VDD-0.2

0.1 0.1

LVCMOS

Wide

Range³

2.5 V

LVCMOS

8 mA

4 mA

8 mA

4 mA

2 mA

1 mA

1.7

0.7

1.7

8

4

2

1

8

4

2

1

1.8 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45

1.5 V

LVCMOS

2 mA

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

1.2 V

1 mA

LVCMOS⁴

1.2 V

100 µA

High –0.3 0.3 * VCCI 0.7 * VCCI 3.6

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide

Range^4,5

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable to V2 Devices operating at VCCI  VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

2-26

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-28 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

IIL⁴

Industrial²

IIH⁵

µA

10

IIL⁴

µA

15

IIH⁵

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

µA

10

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS³

1.2 V LVCMOS Wide Range³

3.3 V PCI

3.3 V PCI-X

Notes:

1. Commercial range (0°C < T < 70°C)

A

2. Industrial range (–40°C < T < 85°C)

A

3. Applicable to V2 Devices operating at VCCI VCC.

4. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

5. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

Revision 24

2-27

IGLOO DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-29 • Summary of AC Measuring Points

Standard

Measuring Trip Point (Vtrip)

1.4 V

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V VCMOS Wide Range

2.5 V LVCMOS

1.4 V

1.2 V

1.8 V LVCMOS

0.90 V

1.5 V LVCMOS

0.75 V

1.2 V LVCMOS

0.60 V

1.2 V LVCMOS Wide Range

3.3 V PCI

0.60 V

0.285 * VCCI (RR)

0.615 * VCCI (FF)

0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V PCI-X

Table 2-30 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data to Pad delay through the Output Buffer

Pad to Data delay through the Input Buffer

Data to Output Buffer delay through the I/O interface

t_DP

t_PY

t_DOUT

t_EOUT

t_DIN

t_HZ

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—High to Z

Enable to Pad delay through the Output Buffer—Z to High

Enable to Pad delay through the Output Buffer—Low to Z

t_ZH

t_LZ

t_ZL

Enable to Pad delay through the Output Buffer—Z to Low

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

2-28

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per

standard)

Applicable to Advanced I/O Banks

3.3 V

LVTTL /

3.3 V

12 mA

12

High

5

–

0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns

0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns

LVCMOS

3.3 V

100 µA

LVCMOS

Wide

Range²

2.5 V

LVCMOS

12 mA

12

–

High

5

–

0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns

0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns

0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns

1.8 V

LVCMOS

1.5 V

LVCMOS

3.3 V PCI Per PCI

spec

High 10 25 ²0.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns

High 10 25 ²0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns

3.3 V

PCI-X

Per

PCI-X

spec

–

LVDS

24 mA

–

High

–

0.97 1.74 0.19 1.35

0.97 1.68 0.19 1.16

–

ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-29

IGLOO DC and Switching Characteristics

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per

standard)

Applicable to Standard Plus I/O Banks

3.3 V

LVTTL /

3.3 V

12 mA

12 High

5

–

0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns

0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns

LVCMOS

3.3 V

100 µA

LVCMOS

Wide

Range²

2.5 V

LVCMOS

12 mA

8 mA

4 mA

5

–

0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns

0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns

0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns

1.8 V

LVCMOS

8

4

–

High

1.5 V

LVCMOS

3.3 V PCI Per PCI

spec

High 10 25 ²0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns

High 10 25 ²0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns

3.3 V

PCI-X

Per PCI-

X spec

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-30

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per

standard)

Applicable to Standard I/O Banks

3.3 V

LVTTL /

3.3 V

8 mA

8

High

5

–

0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26 ns

0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17 ns

LVCMOS

3.3 V

100 µA

LVCMOS

Wide

Range²

2.5 V

LVCMOS

8 mA

4 mA

2 mA

8

4

2

High

5

–

0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15 ns

0.97 2.18 0.18 0.98 0.66 2.22 1.93 1.97 2.06 ns

0.97 2.51 0.18 1.14 0.66 2.56 2.21 1.99 2.03 ns

1.8 V

LVCMOS

1.5 V

LVCMOS

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-31

IGLOO DC and Switching Characteristics

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per

standard)

Applicable to Advanced I/O Banks

3.3 V

LVTTL /

3.3 V

12 mA 12 mA High

100 µA 12 mA High

5

–

1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns

1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns

LVCMOS

3.3 V

LVCMOS

Wide

Range²

2.5 V

LVCMOS

12 mA 12 mA High

5

–

1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns

1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns

1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns

1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns

1.8 V

LVCMOS

1.5 V

LVCMOS

1.2 V

LVCMOS

2 mA

2 mA High

1.2 V

100 µA 2 mA High

LVCMOS

Wide

Range³

3.3 V PCI Per PCI

spec

–

High 10 25²1.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns

High 10 25²1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns

3.3 V

Per

PCI-X

spec

PCI-X

LVDS

24 mA

–

High

–

1.55 2.27 0.25 1.57

1.55 2.24 0.25 1.38

–

ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-32

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per

standard)

Applicable to Standard Plus I/O Banks

3.3 V

LVTTL /

3.3 V

12 mA

12

High

5

–

1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns

1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns

LVCMOS

3.3 V

100 µA

LVCMOS

Wide

Range²

2.5 V

LVCMOS

12 mA

8 mA

12

8

High

5

–

1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns

1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns

1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns

1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns

1.8 V

LVCMOS

1.5 V

LVCMOS

4 mA

4

1.2 V

LVCMOS

2 mA

2

1.2 V

100 µA

2

LVCMOS

Wide

Range³

3.3 V PCI

Per

PCI

spec

–

High 10 25²1.55 2.53 0.26 0.84 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns

High 10 25²1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns

3.3 V

PCI-X

Per

PCI-X

spec

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to

the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78

for connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-33

IGLOO DC and Switching Characteristics

Table 2-36 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case VCCI (per

standard)

Applicable to Standard I/O Banks

3.3 V

LVTTL /

3.3 V

8 mA

8

High

5

–

1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns

1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns

LVCMOS

3.3 V

100 µA

LVCMOS

Wide

Range³

2.5 V

LVCMOS

8 mA

4 mA

8

4

2

1

High

5

–

1.55 2.39 0.26 1.15 1.10 2.42 2.05 2.38 2.80 ns

1.55 2.60 0.26 1.08 1.10 2.64 2.33 2.38 2.62 ns

1.55 2.92 0.26 1.22 1.10 2.96 2.60 2.40 2.56 ns

1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns

1.8 V

LVCMOS

1.5 V

LVCMOS

2 mA

1.2 V

LVCMOS

1 mA

1.2 V

100 µA

LVCMOS

Wide

Range³

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to

the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-34

Revision 24

IGLOO Low Power Flash FPGAs

Detailed I/O DC Characteristics

Table 2-37 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

Input capacitance on the clock pin

VIN = 0, f = 1.0 MHz

8

C_INCLK

pF

Table 2-38 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

()²

100

50

()³

3.3 V LVTTL / 3.3 V LVCMOS

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

24 mA

100 A

2 mA

25

17

50

11

33

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

16 mA

2 mA

25

20

40

1.5 V LVCMOS

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

2 mA

33

37

1.2 V LVCMOS⁴

158

164

1.2 V LVCMOS Wide Range⁴

100 A

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

25 75

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

R

= (VOLspec) / I

(PULL-DOWN-MAX) OLspec

3.

R

= (VCCImax – VOHspec) / I

(PULL-UP-MAX)

OHspec

4. Applicable to IGLOO V2 Devices operating at VCCI  VCC

Revision 24

2-35

IGLOO DC and Switching Characteristics

Table 2-39 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard Plus I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

()²

()³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

100 A

2 mA

25

75

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

2 mA

25

1.8 V LVCMOS

1.5 V LVCMOS

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

2 mA

200

100

158

224

112

164

4 mA

1.2 V LVCMOS⁴

2 mA

1.2 V LVCMOS Wide Range⁴

100 A

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

25 75

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

3.

R

= (VOLspec) / I

(PULL-DOWN-MAX) OLspec

= (VCCImax – VOHspec) / I

(PULL-UP-MAX)

OHspec

4. Applicable to IGLOO V2 Devices operating at VCCI VCC

2-36

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-40 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

()²

()³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

4 mA

6 mA

8 mA

50

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 A

2 mA

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

100

50

200

100

225

112

224

164

4 mA

6 mA

8 mA

50

1.8 V LVCMOS

2 mA

200

100

200

158

4 mA

1.5 V LVCMOS

1.2 V LVCMOS

1.2 V LVCMOS Wide Range⁴

Notes:

2 mA

1 mA

100 A

Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

3.

R

= (VOLspec) / I

(PULL-DOWN-MAX) OLspec

= (VCCImax – VOHspec) / I

(PULL-UP-MAX)

OHspec

Table 2-41 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCI

Min.

10 K

11 K

18 K

19 K

25 K

19 K

Max.

45 K

55 K

70 K

90 K

110 K

Min.

10 K

12 K

17 K

19 K

25 K

19 K

Max.

45 K

3.3 V

3.3 V Wide Range I/Os

45 K

2.5 V

74 K

1.8 V

110 K

140 K

150 K

1.5 V

1.2 V

1.2 V Wide Range I/Os

Notes:

1.

2.

R

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX) (WEAK PULL-UP-MIN)

= (VOLspec) / I

(WEAK PULLDOWN-MAX)

(WEAK PULLDOWN-MIN)

Revision 24

2-37

IGLOO DC and Switching Characteristics

Table 2-42 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

100 A

2 mA

103

132

268

109

127

181

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

16

32

65

83

169

9

18

37

74

87

124

11

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

4 mA

17

35

45

91

13

25

32

66

20

103

22

44

51

74

16

33

39

55

26

109

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

100 A

Per PCI/PCI-X

specification

Note: *T_J= 100°C

2-38

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-43 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

100 A

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100 A

25

27

51

54

51

54

103

109

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

16

32

65

9

18

37

74

11

1.8 V LVCMOS

1.5 V LVCMOS

17

35

13

25

20

103

22

44

16

33

26

109

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Note: *T_J= 100°C

Revision 24

2-39

IGLOO DC and Switching Characteristics

Table 2-44 • I/O Short Currents IOSH/IOSL

Applicable to Standard I/O Banks

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

100 A

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

1 mA

100 A

25

51

27

54

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

16

32

9

18

37

11

22

16

26

1.8 V LVCMOS

17

13

20

1.5 V LVCMOS

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

Note: *T_J= 100°C

The length of time an I/O can withstand I_{OSH OSL}

/I

events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-45 • Duration of Short Circuit Event before Failure

Temperature

–40°C

–20°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability1

Input Rise/Fall Time

(min.)

Input Rise/Fall Time

(max.)

Input Buffer

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (100°C)

10 years (100°C)

LVDS/B-LVDS/M-LVDS/

LVPECL

Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Microsemi recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

2-40

Revision 24

IGLOO Low Power Flash FPGAs

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V

software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

25

27

4 mA

4

6 mA

6

51

54

8 mA

8

51

54

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

103

132

268

109

127

181

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

V_OL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

2

25

27

4 mA

4

6 mA

6

51

54

8 mA

8

51

54

12 mA

16 mA

Notes:

12 12

16 16

103

109

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Revision 24

2-41

IGLOO DC and Switching Characteristics

Table 2-49 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

V_OL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

25

51

27

54

4

6

8

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

3.3

1.4

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

2-42

Revision 24

IGLOO Low Power Flash FPGAs

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

0.97 4.47 0.18 0.85 0.66 4.56 3.89 2.24 2.19 8.15 7.48

0.97 3.74 0.18 0.85 0.66 3.82 3.37 2.49 2.63 7.42 6.96

0.97 3.23 0.18 0.85 0.66 3.30 2.98 2.66 2.91 6.89 6.57

0.97 3.08 0.18 0.85 0.66 3.14 2.89 2.70 2.99 6.74 6.48

0.97 3.00 0.18 0.85 0.66 3.06 2.91 2.74 3.27 6.66 6.50

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength

4 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.73 0.18 0.85 0.66 2.79 2.22 2.25 2.32 6.38 5.82

0.97 2.32 0.18 0.85 0.66 2.37 1.85 2.50 2.76 5.96 5.45

0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27

0.97 2.05 0.18 0.85 0.66 2.10 1.64 2.70 3.12 5.69 5.24

0.97 2.07 0.18 0.85 0.66 2.12 1.60 2.75 3.41 5.71 5.20

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

0.97 3.94 0.18 0.85 0.66 4.02 3.46 1.98 2.03 7.62 7.05

0.97 3.24 0.18 0.85 0.66 3.31 2.99 2.21 2.42 6.90 6.59

0.97 2.76 0.18 0.85 0.66 2.82 2.63 2.36 2.68 6.42 6.22

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-43

IGLOO DC and Switching Characteristics

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength

4 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.32 0.18 0.85 0.66 2.37 1.90 1.98 2.13 5.96 5.49

0.97 1.94 0.18 0.85 0.66 1.99 1.57 2.20 2.53 5.58 5.16

0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99

ns

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

3.80 0.18 0.83

3.15 0.18 0.83

3.88 3.41 1.74 1.78

3.21 2.94 1.96 2.17

4 mA

ns

6 mA

ns

8 mA

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

2.19 0.18 0.83

1.85 0.18 0.83

2.24 1.79 1.74 1.87

1.89 1.46 1.96 2.26

4 mA

ns

6 mA

ns

8 mA

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-44

Revision 24

IGLOO Low Power Flash FPGAs

Applies to 1.2 V DC Core Voltage

Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 5.12 0.26 0.98 1.10 5.20 4.46 2.81 3.02 10.99 10.25

1.55 4.38 0.26 0.98 1.10 4.45 3.93 3.07 3.48 10.23 9.72

1.55 3.85 0.26 0.98 1.10 3.91 3.53 3.24 3.77 9.69 9.32

1.55 3.69 0.26 0.98 1.10 3.75 3.44 3.28 3.84 9.54 9.23

1.55 3.61 0.26 0.98 1.10 3.67 3.46 3.33 4.13 9.45 9.24

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 3.33 0.26 0.98 1.10 3.38 2.75 2.82 3.18 9.17 8.54

1.55 2.91 0.26 0.98 1.10 2.95 2.37 3.07 3.64 8.73 8.15

1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97

1.55 2.63 0.26 0.98 1.10 2.67 2.14 3.28 4.01 8.45 7.93

1.55 2.65 0.26 0.98 1.10 2.69 2.10 3.33 4.31 8.47 7.89

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

1.55 4.56 0.26 0.97 1.10 4.63 3.98 2.54 2.83 10.42 9.76

1.55 3.84 0.26 0.97 1.10 3.90 3.50 2.77 3.24 9.69 9.29

1.55 3.35 0.26 0.97 1.10 3.40 3.13 2.93 3.51 9.19 8.91

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Revision 24

2-45

IGLOO DC and Switching Characteristics

Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 2.89 0.26 0.97 1.10 2.93 2.38 2.53 2.96 8.72 8.17

1.55 2.50 0.26 0.97 1.10 2.54 2.04 2.77 3.37 8.33 7.82

1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65

ns

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

4.39 0.26 0.94

3.72 0.26 0.94

4.46 3.91 2.17 2.44

3.78 3.43 2.40 2.85

4 mA

ns

6 mA

ns

8 mA

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

2.74 0.26 0.94

2.38 0.26 0.94

2.78 2.26 2.17 2.55

2.41 1.92 2.40 2.96

4 mA

ns

6 mA

ns

8 mA

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-46

Revision 24

IGLOO Low Power Flash FPGAs

3.3 V LVCMOS Wide Range

Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Advanced I/O Banks

3.3 V LVCMOS Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL²IIH³

Equivalent

Software

Default Drive

Drive

Strength

Min. Max. Min. Max. Max.

Min.

V

Max.

Option¹

V

2

V

µA µA

mA⁴

mA⁴µA⁵µA⁵

100 µA

Notes:

2 mA

4 mA

–0.3 0.8

3.6

0.2 VDD – 0.2 100 100

25

27

10 10

25

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

103

132

268

109

127

181

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Revision 24

2-47

IGLOO DC and Switching Characteristics

Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Standard Plus I/O Banks

3.3 V LVCMOS Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL²IIH³

Equivalent

Software

Default Drive

Drive

Strength

Min. Max. Min. Max. Max.

Min.

V

Max.

Option¹

V

2

V

µA µA

mA⁴

mA⁴µA⁵µA⁵

100 µA

Notes:

2 mA

4 mA

–0.3 0.8

3.6

0.2 VDD – 0.2 100 100

25

27

10 10

25

6 mA

51

54

8 mA

51

54

12 mA

16 mA

103

109

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

2-48

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-65 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Standard I/O Banks

3.3 V LVCMOS Wide Range VIL VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL²IIH³

Equivalent

Software

DefaultDrive

Strength

Drive

Strength

Min. Max. Min. Max. Max.

Min.

V

Max.

Option¹

V

2

V

µA µA

mA⁴

mA⁴µA⁵µA⁵

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

–0.3

0.8

3.6

0.2 VDD – 0.2 100 100

25

27

54

10 10

25

51

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-66 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

3.3

1.4

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Revision 24

2-49

IGLOO DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-67 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

0.97 6.61 0.18 1.19 0.66 6.63 5.63 3.15 2.98 10.22 9.23

ns

0.97 5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66 9.10 8.44

0.97 4.69 0.18 1.19 0.66 4.71 4.25 3.80 4.10 8.31 7.85

0.97 4.46 0.18 1.19 0.66 4.48 4.11 3.86 4.21 8.07 7.71

0.97 4.34 0.18 1.19 0.66 4.36 4.14 3.93 4.64 7.95 7.74

8 mA

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-68 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

0.97 3.92 0.18 1.19 0.66 3.94 3.10 3.16 3.17 7.54 6.70

ns

0.97 3.28 0.18 1.19 0.66 3.30 2.54 3.54 3.86 6.90 6.14

0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87

0.97 2.87 0.18 1.19 0.66 2.89 2.22 3.86 4.41 6.49 5.82

0.97 2.90 0.18 1.19 0.66 2.92 2.16 3.94 4.86 6.51 5.75

8 mA

12 mA

16 mA

24 mA

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2. Software default selection highlighted in gray.

3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2-50

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-69 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Plus Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

0.97 5.84 0.18 1.20 0.66 5.86 5.04 2.74 2.71 9.46 8.64

ns

0.97 4.76 0.18 1.20 0.66 4.78 4.33 3.09 3.33 8.37 7.93

0.97 4.02 0.18 1.20 0.66 4.04 3.78 3.33 3.73 7.64 7.37

8 mA

12 mA

16 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-70 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Plus Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

0.97 3.33 0.18 1.20 0.66 3.35 2.68 2.73 2.88 6.94 6.27

ns

0.97 2.75 0.18 1.20 0.66 2.77 2.17 3.08 3.50 6.36 5.77

0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51

8 mA

12 mA

16 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

Revision 24

2-51

IGLOO DC and Switching Characteristics

Table 2-71 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Banks

Equivalent

Software

Default

Drive

Strength

Speed

Grade t_DOUT

Option¹

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

Std.

0.97

5.64 0.18

4.63 0.18

1.17

5.65

4.64

4.98

4.26

2.45

2.80

2.42

3.02

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-72 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Applicable to Standard Banks

Equivalent

Software

Default

Drive

Strength

Speed

Grade t_DOUT

Option¹

t_DP

t_DIN

1.17

t_PY

t_EOUT

3.17

2.63

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

0.97

3.16

2.62

0.18

0.66

2.53

2.02

2.45

2.79

2.56

3.17

0.97

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

2-52

Revision 24

IGLOO Low Power Flash FPGAs

Applies to 1.2 V DC Core Voltage

Table 2-73 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Applicable to Advanced Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

1.55 7.52 0.26 1.32 1.10 7.52 6.38 3.84 4.02 13.31 12.16

1.55 6.37 0.26 1.32 1.10 6.37 5.57 4.23 4.73 12.16 11.35

1.55 5.55 0.26 1.32 1.10 5.55 4.96 4.50 5.18 11.34 10.75

1.55 5.32 0.26 1.32 1.10 5.32 4.82 4.56 5.29 11.10 10.61

1.55 5.19 0.26 1.32 1.10 5.19 4.85 4.63 5.74 10.98 10.63

ns

8 mA

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-74 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Advanced Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

1.55 4.75 0.26 1.32 1.10 4.75 3.77 3.84 4.27 10.54 9.56

ns

1.55 4.10 0.26 1.32 1.10 4.10 3.19 4.24 4.98 9.88 8.98

1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69

1.55 3.67 0.26 1.32 1.10 3.67 2.85 4.57 5.55 9.46 8.64

1.55 3.70 0.26 1.32 1.10 3.70 2.79 4.65 6.01 9.49 8.58

8 mA

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

Revision 24

2-53

IGLOO DC and Switching Characteristics

Table 2-75 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Plus Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

1.55 6.69 0.26 1.32 1.10 6.69 5.73 3.41 3.72 12.48 11.52

ns

1.55 5.58 0.26 1.32 1.10 5.58 5.01 3.77 4.35 11.36 10.79

1.55 4.82 0.26 1.32 1.10 4.82 4.44 4.02 4.76 10.61 10.23

8 mA

12 mA

16 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-76 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Plus Banks

Equivalent

Software

Default

Drive

Strength

Speed

Option¹

Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

6 mA

Std.

1.55 4.10 0.26 1.32 1.10 4.10 3.30 3.40 3.92 9.89 9.09

ns

1.55 3.51 0.26 1.32 1.10 3.51 2.79 3.76 4.56 9.30 8.57

1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31

8 mA

12 mA

16 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

2-54

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-77 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Banks

Equivalent

Software

Default

Drive

Strength

Speed

Grade t_DOUT

Option¹

t_DP

t_DIN

0.26

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

Std.

1.55

6.44

5.41

1.29

6.44

5.41

5.64

4.91

2.99

3.35

3.28

3.89

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-78 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7

Applicable to Standard Banks

Equivalent

Software

Default

Drive

Strength

Speed

Grade t_DOUT

Option¹

t_DP

t_DIN

0.26

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

Std.

1.55

3.89

3.33

1.29

3.89

3.33

3.13

2.62

2.99

3.34

3.45

4.07

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive

strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

Revision 24

2-55

IGLOO DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-79 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

18

4 mA

6 mA

32

37

8 mA

32

37

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

65

74

83

87

169

124

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-80 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

32

65

18

37

74

12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-56

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-81 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

2

4

6

8

2

16

32

18

37

4

6

8

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

2.5

1.2

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Revision 24

2-57

IGLOO DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-83 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

0.97 4.96 0.18 1.08 0.66 5.06 4.59 2.26 2.00 8.66 8.19

0.97 4.15 0.18 1.08 0.66 4.24 3.94 2.54 2.51 7.83 7.53

0.97 3.57 0.18 1.08 0.66 3.65 3.47 2.73 2.84 7.24 7.06

0.97 3.39 0.18 1.08 0.66 3.46 3.36 2.78 2.92 7.06 6.95

0.97 3.38 0.18 1.08 0.66 3.38 3.38 2.83 3.25 6.98 6.98

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-84 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

0.97 2.77 0.18 1.08 0.66 2.83 2.60 2.26 2.08 6.42 6.19

0.97 2.34 0.18 1.08 0.66 2.39 2.08 2.54 2.60 5.99 5.68

0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43

0.97 2.05 0.18 1.08 0.66 2.09 1.78 2.78 3.02 5.69 5.38

0.97 2.06 0.18 1.08 0.66 2.10 1.72 2.83 3.35 5.70 5.32

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-85 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Std.

0.97 4.42 0.18 1.08 0.66 4.51 4.10 1.96 1.85 8.10 7.69

0.97 3.62 0.18 1.08 0.66 3.70 3.52 2.21 2.32 7.29 7.11

0.97 3.09 0.18 1.08 0.66 3.15 3.09 2.39 2.61 6.74 6.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-58

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-86 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

0.97 2.36 0.18 1.08 0.66 2.41 2.21 1.96 1.92 6.01 5.81

0.97 1.97 0.18 1.08 0.66 2.01 1.75 2.21 2.40 5.61 5.34

0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-87 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

4.27 0.18 1.04

3.54 0.18 1.04

4.36 4.06 1.71 1.62

3.61 3.48 1.95 2.08

4 mA

ns

6 mA

ns

8 mA

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-88 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

2.24 0.18 1.04

1.88 0.18 1.04

2.29 2.09 1.71 1.68

1.92 1.63 1.95 2.15

4 mA

ns

6 mA

ns

8 mA

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-59

IGLOO DC and Switching Characteristics

Applies to 1.2 V Core Voltage

Table 2-89 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 5.59 0.26 1.20 1.10 5.68 5.14 2.82 2.80 11.47 10.93

1.55 4.76 0.26 1.20 1.10 4.84 4.47 3.10 3.33 10.62 10.26

1.55 4.17 0.26 1.20 1.10 4.23 3.99 3.30 3.67 10.02 9.77

1.55 3.98 0.26 1.20 1.10 4.04 3.88 3.34 3.76 9.83 9.66

1.55 3.90 0.26 1.20 1.10 3.96 3.90 3.40 4.09 9.75 9.68

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-90 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 3.33 0.26 1.20 1.10 3.38 3.09 2.82 2.91 9.17 8.88

1.55 2.89 0.26 1.20 1.10 2.93 2.56 3.10 3.45 8.72 8.34

1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08

1.55 2.59 0.26 1.20 1.10 2.63 2.24 3.34 3.88 8.41 8.03

1.55 2.60 0.26 1.20 1.10 2.64 2.18 3.40 4.22 8.42 7.97

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-91 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Std.

1.55 5.02 0.26 1.19 1.10 5.11 4.60 2.50 2.62 10.89 10.38

1.55 4.21 0.26 1.19 1.10 4.27 4.00 2.76 3.10 10.06 9.79

1.55 3.66 0.26 1.19 1.10 3.71 3.55 2.94 3.41 9.50 9.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-60

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-92 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

1.55 2.91 0.26 1.19 1.10 2.95 2.66 2.50 2.72 8.74 8.45

1.55 2.51 0.26 1.19 1.10 2.54 2.18 2.75 3.21 8.33 7.97

1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-93 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

4.85 0.26 1.15

4.09 0.26 1.15

4.93 4.55 2.13 2.24

4.16 3.95 2.38 2.71

4 mA

ns

6 mA

ns

8 mA

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-94 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

2.76 0.26 1.15

2.39 0.26 1.15

2.80 2.52 2.13 2.32

2.42 2.05 2.38 2.80

4 mA

ns

6 mA

ns

8 mA

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Revision 24

2-61

IGLOO DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-95 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

V

mA mA

mA³

µA⁴µA⁴

10 10

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45

2

4

6

8

2

4

9

11

22

44

51

74

4 mA

17

35

45

91

6 mA

6

8 mA

8

12 mA

16 mA

Notes:

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-96 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH

mA mA

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

Max.

mA³

V

µA⁴µA⁴

10 10

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45

2

4

2

4

9

11

22

44

17

35

–0.3 0.35 * VCCI 0.65 * VCCI 1.9

6

8

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-62

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-97 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

V

mA mA

mA³

µA⁴µA⁴

10 10

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45

2

4

2

4

9

11

22

17

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-99 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

0.97 6.38 0.18 1.01 0.66 6.51 5.93 2.33 1.56 10.10 9.53

0.97 5.35 0.18 1.01 0.66 5.46 5.04 2.67 2.38 9.05 8.64

0.97 4.62 0.18 1.01 0.66 4.71 4.44 2.90 2.79 8.31 8.04

0.97 4.37 0.18 1.01 0.66 4.46 4.31 2.95 2.89 8.05 7.90

0.97 4.32 0.18 1.01 0.66 4.37 4.32 3.03 3.30 7.97 7.92

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-63

IGLOO DC and Switching Characteristics

Table 2-100 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

0.97 3.25 0.18 1.01 0.66 3.21 3.25 2.33 1.61 6.80 6.85

0.97 2.62 0.18 1.01 0.66 2.68 2.51 2.66 2.46 6.27 6.11

0.97 2.31 0.18 1.01 0.66 2.36 2.15 2.90 2.87 5.95 5.75

0.97 2.25 0.18 1.01 0.66 2.30 2.08 2.95 2.98 5.89 5.68

0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60

ns

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-101 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Std.

0.97 5.78 0.18 1.01 0.66 5.90 5.32 1.95 1.47 9.49 8.91

0.97 4.75 0.18 1.01 0.66 4.85 4.54 2.25 2.21 8.44 8.13

0.97 4.07 0.18 1.01 0.66 4.15 3.98 2.46 2.58 7.75 7.57

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-102 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

0.97 2.76 0.18 1.01 0.66 2.79 2.76 1.94 1.51 6.39 6.35

0.97 2.25 0.18 1.01 0.66 2.30 2.09 2.24 2.29 5.89 5.69

0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-103 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

0.97

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

5.63 0.18 0.98 0.66

4.69 0.18 0.98 0.66

5.74

4.79

5.30 1.68 1.24

4.52 1.97 1.98

4 mA

0.97

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-64

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-104 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

2.62

t_DP

t_DIN

t_PY

t_EOUT

2.67

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

0.18 0.98 0.66

2.59 1.67 1.29 2.62

1.93 1.97 2.06 2.18

4 mA

2.18

2.22

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-65

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-105 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

1.55 6.97 0.26 1.11 1.10 7.08 6.48 2.87 2.29 12.87 12.27

1.55 5.91 0.26 1.11 1.10 6.01 5.57 3.21 3.14 11.79 11.36

1.55 5.16 0.26 1.11 1.10 5.24 4.95 3.45 3.55 11.03 10.74

1.55 4.90 0.26 1.11 1.10 4.98 4.81 3.50 3.66 10.77 10.60

1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.58 4.08 10.68 10.61

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-106 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

1.55 3.73 0.26 1.11 1.10 3.71 3.73 2.86 2.34 9.49 9.51

1.55 3.12 0.26 1.11 1.10 3.16 2.97 3.21 3.22 8.95 8.75

1.55 2.79 0.26 1.11 1.10 2.83 2.59 3.45 3.65 8.62 8.38

1.55 2.73 0.26 1.11 1.10 2.77 2.52 3.50 3.75 8.56 8.30

1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22

ns

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-107 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Std.

1.55 6.32 0.26 1.11 1.10 6.43 5.81 2.47 2.16 12.22 11.60

1.55 5.27 0.26 1.11 1.10 5.35 5.01 2.78 2.92 11.14 10.79

1.55 4.56 0.26 1.11 1.10 4.64 4.44 3.00 3.30 10.42 10.22

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-66

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-108 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

1.55 3.22 0.26 1.11 1.10 3.26 3.18 2.47 2.20 9.05 8.97

1.55 2.72 0.26 1.11 1.10 2.75 2.50 2.78 3.01 8.54 8.29

1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-109 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

1.55

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

6.13 0.26 1.08 1.10

5.17 0.26 1.08 1.10

6.24

5.26

5.79 2.08 1.78

4.98 2.38 2.54

4 mA

1.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-110 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

3.06

t_DP

t_DIN

t_PY

t_EOUT

3.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

Std.

0.26 1.08 1.10

3.01 2.08 1.83 3.06

2.33 2.38 2.62 2.60

4 mA

2.60

2.64

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Revision 24

2-67

IGLOO DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-111 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2

4

2

4

13

25

32

66

16

33

39

55

10 10

6

8

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-112 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Max. Max.

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2

4

2

4

13

25

16

33

10 10

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-68

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-113 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.25 * VCCI 0.75 * VCCI

2

13

16

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Revision 24

2-69

IGLOO DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-115 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

0.97 6.62 0.18 1.17 0.66 6.75 6.06 2.79 2.31 10.35 9.66

0.97 5.75 0.18 1.17 0.66 5.86 5.34 3.06 2.78 9.46 8.93

0.97 5.43 0.18 1.17 0.66 5.54 5.19 3.12 2.90 9.13 8.78

0.97 5.35 0.18 1.17 0.66 5.46 5.20 2.63 3.36 9.06 8.79

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-116 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

0.97 2.97 0.18 1.17 0.66 3.04 2.90 2.78 2.40 6.63 6.50

0.97 2.60 0.18 1.17 0.66 2.65 2.45 3.05 2.88 6.25 6.05

0.97 2.53 0.18 1.17 0.66 2.58 2.37 3.11 3.00 6.18 5.96

0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-117 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

Std.

0.97 5.93 0.18 1.18 0.66 6.04 5.46 2.30 2.15 9.64 9.06

0.97 5.11 0.18 1.18 0.66 5.21 4.80 2.54 2.58 8.80 8.39

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-118 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.58 0.18 1.18 0.66 2.64 2.41 2.29 2.24 6.23 6.01

0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59

ns

4 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-70

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-119 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

Std.

0.97

5.88 0.18 1.14

0.66

6.00 5.45 2.00 1.94

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-120 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

0.97

2.51 0.18 1.14

0.66

2.56 2.21 1.99 2.03

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-71

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-121 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

1.55 7.17 0.26 1.27 1.10 7.29 6.60 3.33 3.03 13.07 12.39

1.55 6.27 0.26 1.27 1.10 6.37 5.86 3.61 3.51 12.16 11.64

1.55 5.94 0.26 1.27 1.10 6.04 5.70 3.67 3.64 11.82 11.48

1.55 5.86 0.26 1.27 1.10 5.96 5.71 2.83 4.11 11.74 11.50

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-122 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

1.55 3.44 0.26 1.27 1.10 3.49 3.35 3.32 3.12 9.28 9.14

1.55 3.06 0.26 1.27 1.10 3.10 2.89 3.60 3.61 8.89 8.67

1.55 2.98 0.26 1.27 1.10 3.02 2.80 3.66 3.74 8.81 8.58

1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-123 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

Std.

1.55 6.43 0.26 1.27 1.10 6.54 5.95 2.82 2.83 12.32 11.74

1.55 5.59 0.26 1.27 1.10 5.68 5.27 3.07 3.27 11.47 11.05

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-124 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

Notes:

Std.

1.55 3.02 0.26 1.27 1.10 3.07 2.81 2.82 2.92 8.85 8.59

1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-72

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-125 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

Std.

1.55

6.35 0.26 1.22

1.10

6.46 5.93 2.40 2.46

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-126 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

1.55

2.92 0.26 1.22

1.10

2.96 2.60 2.40 2.56

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Revision 24

2-73

IGLOO DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V

applications. It uses a 1.2 V input buffer and a push-pull output buffer. Furthermore, all LVCMOS 1.2 V

software macros comply with LVCMOS 1.2 V wide range as specified in the JESD8-12A

specification.

Table 2-127 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

2

20

26

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-128 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.2 V

LVCMOS

VIL

VIH

VOL

VOH

I_OLIOH IOSH IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI

2

20

26

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Table 2-129 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.2 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

1 mA

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.25 * VCCI 0.75 * VCCI

1

20

26

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

2-74

Revision 24

IGLOO Low Power Flash FPGAs

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

Table 2-130 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.2

0.6

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Timing Characteristics

1.2 V DC Core Voltage

Table 2-131 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

ns

2 mA Std. 1.55 8.37 0.26 1.60 1.10 8.04 7.17 3.94 3.52 13.82 12.95

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-132 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

9.14 ns

2 mA

Std.

1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-133 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

ns

2 mA Std. 1.55 7.59 0.26 1.59 1.10 7.29 6.54 3.30 3.35 13.08 12.33

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-134 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-75

IGLOO DC and Switching Characteristics

Table 2-135 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

1 mA

Std.

1.55

8.57 0.26 1.53

1.10

8.23 7.38 2.51 2.39

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-136 • 1.2 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Applicable to Standard Banks

Drive Strength

1 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

1.55

3.59 0.26 1.53

1.10

3.47 3.06 2.51 2.49

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

1.2 V LVCMOS Wide Range

Table 2-137 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Advanced I/O Banks

1.2 V LVCMOS

Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL²IIH³

Equivalent

Software

Default

Drive

Strength Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

Strength Option¹

V

mA mA mA⁴mA⁴µA⁵µA⁵

100 µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20

26

10 10

Notes:

1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.

The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS

models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

2-76

Revision 24

IGLOO Low Power Flash FPGAs

Table 2-138 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Standard Plus I/O Banks

1.2 V LVCMOS

Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL²IIH³

Equivalent

Software

Default

Drive

Strength Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

Strength Option¹

V

mA mA mA⁴mA⁴µA⁵µA⁵

100 µA

2mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20

26 10 10

Notes:

1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.

The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS

models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-139 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range

Applicable to Standard I/O Banks

1.2 V LVCMOS

Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL²IIH³

Equivalent

Software

Default

Drive

Strength Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

Strength Option¹

V

mA mA mA⁴mA⁴µA⁵µA⁵

100 µA

1 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20

26

10 10

Notes:

1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.

The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS

models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 100°C junction temperature and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

Table 2-140 • 1.2 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.2

0.6

5

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Timing Characteristics

Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-75 for worst-case timing.

Revision 24

2-77

IGLOO DC and Switching Characteristics

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-141 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced and Standard Plus I/Os

3.3 V PCI/PCI-X

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSH

IOSL

IIL IIH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA¹

Max.

mA¹

Drive Strength

V

mA mA

µA²µA²

Per PCI

Per PCI curves

10 10

specification

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable

path characterization are described in Figure 2-12.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-12 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-142.

Table 2-142 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

C_LOAD(pF)

0

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

10

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-143 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHS

Units

Std.

0.97

2.32 0.19 0.70

0.66

2.37 1.78 2.67 3.05 5.96 5.38

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-144 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHS

Units

Std.

0.97

1.97 0.19 0.70

0.66

2.01 1.50 2.36 2.79 5.61 5.10

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-78

Revision 24

IGLOO Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-145 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHS

Units

Std.

1.55

2.91 0.25 0.86

1.10

2.95 2.29 3.25 3.93 8.74 8.08

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Table 2-146 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHS

Units

Std.

1.55

2.53 0.25 0.85

1.10

2.57 1.98 2.93 3.64 8.35 7.76

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

P

N

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

+

–

100 

Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation

Revision 24

2-79

IGLOO DC and Switching Characteristics

Table 2-147 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

Supply Voltage

VOL

Output Low Voltage

1.075

1.425

0.91

V

VOH

Output High Voltage

1.25

0.65

0

V

IOL¹

Output Lower Current

Output High Current

1.16

2.925

10

mA

V

IOH¹

VI

Input Voltage

IIH²

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

µA

mV

V

IIL²

10

VODIFF

VOCM

VICM

VIDIFF⁴

Notes:

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

mV

1. IOL/IOH is defined by VODIFF/(resistor network)

2. Currents are measured at 85°C junction temperature.

Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.075

1.325

Cross point

Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-149 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

0.97

1.67

0.19

1.31

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7 on

page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-150 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.19

0.25

1.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7 on

page 2-7 for derating values.

2-80

Revision 24

IGLOO Low Power Flash FPGAs

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-14. The input and output buffer delays are available in

the LVDS section in Table 2-149 on page 2-80 and Table 2-150 on page 2-80.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-15. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

N

OUTBUF_LVPECL

100 

Z = 50 

0

INBUF_LVPECL

+

–

187 W

Z = 50 

100 

0

N

Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation

Revision 24

2-81

IGLOO DC and Switching Characteristics

Table 2-151 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max. Units

3.0

3.3

3.6

V

VOL

Output Low Voltage

0.96

1.8

0

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

VIL, VIH

V_ODIFF

V_OCM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

V

0.625 0.97 0.625 0.97 0.625 0.97

1.762 1.98 1.762 1.98 1.762 1.98

V

V_ICM

1.01

300

2.57

1.01

300

2.57

1.01

300

2.57

V

V_IDIFF

mV

Table 2-152 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.64

1.94

Cross point

Note: *Measuring point = Vtrip. See Table 2-28 on page 2-102 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-153 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

0.97

1.67

0.19

1.16

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-154 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.24

0.25

1.37

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-82

Revision 24

IGLOO Low Power Flash FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

DFN1E1P1

G

E

EOUT

B

A

H

I

PRE

J

D

Q

DFN1E1P1

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

CLKBUF

INBUF

Postive-Edge Triggered

Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Revision 24

2-83

IGLOO DC and Switching Characteristics

Table 2-155 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

Note: *See Figure 2-16 on page 2-83 for more information.

2-84

Revision 24

IGLOO Low Power Flash FPGAs

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

AA

DD

CLR

LL

HH

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Revision 24

2-85

IGLOO DC and Switching Characteristics

Table 2-156 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

GG, HH

LL, DOUT

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-17 on page 2-85 for more information.

2-86

Revision 24

IGLOO Low Power Flash FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

CLK

Data

t_IHD

50%

1

0

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-18 • Input Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-157 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

Std. Units

Clock-to-Q of the Input Data Register

0.42

0.47

0.00

0.67

0.00

0.79

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Revision 24

2-87

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-158 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Description

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

Std. Units

0.68

0.97

0.00

1.02

0.00

1.19

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Output Register

t_OCKMPWHt_OCKMPWL

50%

1

CLK

t_OSUDt_OHD

50%

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-19 • Output Register Timing Diagram

2-88

Revision 24

IGLOO Low Power Flash FPGAs

Timing Characteristics

1.5 V DC Core Voltage

Table 2-159 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

Std. Units

Clock-to-Q of the Output Data Register

1.00

0.51

0.00

0.70

0.00

1.34

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width High for the Output Data Register

Clock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-160 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

Std. Units

1.52

1.15

0.00

1.11

0.00

1.96

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width High for the Output Data Register

Clock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

Revision 24

2-89

IGLOO DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_{OESUD OEHD}

t

50% 50%

1

0

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

EOUT

Figure 2-20 • Output Enable Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-161 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

Std. Units

Clock-to-Q of the Output Enable Register

0.75

0.51

0.00

0.73

0.00

1.13

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OESUE

Enable Setup Time for the Output Enable Register

t_OEHE

Enable Hold Time for the Output Enable Register

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

t_OEWPRE

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register

t_OECKMPWHClock Minimum Pulse Width High for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width Low for the Output Enable Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

2-90

Revision 24

IGLOO Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-162 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OECLKQ

t_OESUD

Description

Clock-to-Q of the Output Enable Register

Std. Units

1.10

1.15

0.00

1.22

0.00

1.65