M1AGL250V2-FG144YC [MICROSEMI]
Field Programmable Gate Array;型号: | M1AGL250V2-FG144YC |
厂家: | Microsemi |
描述: | Field Programmable Gate Array 栅 可编程逻辑 |
文件: | 总246页 (文件大小:11503K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 20
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
•
Single-Ended I/O Standards: LVTTL, LVCMOS
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
†
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X ,
†
and LVCMOS 2.5 V / 5.0 V Input
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
•
•
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
•
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
High Capacity
•
•
•
15K to 1 Million System Gates
Up to 144 Kbits of True Dual-Port SRAM
Up to 300 User I/Os
•
•
•
•
•
•
‡
Hot-Swappable and Cold-Sparing I/Os
†
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
Reprogrammable Flash Technology
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO Family
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Clock Conditioning Circuit (CCC) and PLL†
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
In-System Programming (ISP) and Security
Embedded Memory
•
•
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
®
®
(AES) Decryption (except ARM -enabled IGLOO devices) via
1 kbit of FlashROM User Nonvolatile Memory
†
†
JTAG (IEEE 1532–compliant)
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
®
•
FlashLock Designed to Secure FPGA Contents
†
•
True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
ARM Processor Support in IGLOO FPGAs
•
•
Segmented, Hierarchical Routing and Clock Structure
M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
Advanced I/O
•
•
700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
IGLOO Devices
AGL0151 AGL030
AGL060 AGL125
AGL250
AGL400
AGL600
AGL1000
2
ARM-Enabled IGLOO Devices
System Gates
M1AGL250
M1AGL600 M1AGL1000
15,000
30,000
60,000 125,000
250,000
2,048
6,144
24
400,000
600,000
1,000,000
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
128
384
5
256
768
5
512
1,536
10
18
4
1,024
3,072
16
–
9,216
32
54
12
1
–
13,824
36
–
24,576
53
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
–
–
36
36
108
24
144
32
4,608-Bit Blocks
–
–
8
8
FlashROM Kbits (1,024 bits)
1
1
1
1
1
1
1
2
AES-Protected ISP
–
–
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
3
Integrated PLL in CCCs
–
–
4
VersaNet Globals
6
6
18
2
18
18
18
4
18
18
I/O Banks
2
2
2
4
4
4
Maximum User I/Os
49
81
96
133
143
194
235
300
Package Pins
UC/CS
3
5
UC81
CS81
CS121
CS121, CS81, CS196
CS196
CS196
CS281
CS281
5,6
QFN
QN68 QN48, QN68, QN132
QN132
QN132
QN132
VQFP
FBGA
VQ100
VQ100
VQ100
FG144
VQ100
FG144
6
FG144
FG144, FG256, FG144, FG256, FG144, FG256,
FG484 FG484 FG484
Notes:
1. AGL015 is not recommended for new designs
2. AES is not available for ARM-enabled IGLOO devices.
3. AGL060 in CS121 does not support the PLL.
4. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
5. The M1AGL250 device does not support this package.
6. Device/package support TBD.
7. The IGLOOe datasheet and IGLOOe FPGA Fabric User’s Guide provide information on higher densities and additional features.
† AGL015 and AGL030 devices do not support this feature. ‡ Supported only by AGL015 and AGL030 devices.
March 2012
© 2012 Microsemi Corporation
I
IGLOO Low Power Flash FPGAs
1
I/Os Per Package
IGLOO Devices
AGL0152 AGL030 AGL060 AGL125
AGL250
AGL600
AGL1000
AGL400
ARM-Enabled
IGLOO Devices
M1AGL250
I/O Type3
M1AGL600 M1AGL1000
Package
QN48
–
49
–
34
49
66
66
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
QN68
–
–
UC81
–
–
–
–
–
–
–
–
–
CS81
–
–
–
60
–
7
–
–
–
–
–
–
CS121
VQ100
QN132
CS196
FG144
FG2567
CS281
FG4847
Notes:
–
96
71
80
–
96
71
84
133
97
–
–
–
–
–
–
–
–
–
77
81
–
68
87 5,6
143 5
97
–
13
19 5,6
35 5
24
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
143
97
178
–
35
25
38
–
–
–
–
–
–
–
96 7
97
177
215
235
25
43
53
60
97
177
215
300
25
44
53
74
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
194
38
1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO FPGA Fabric User’s Guide to
ensure compliance with design and board migration requirements.
2. AGL015 is not recommended for new designs.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1AGL250 device does not support QN132 or CS196 packages.
6. Device/package support TBD.
7. FG256 and FG484 are footprint-compatible packages.
Table 1 • IGLOO FPGAs Package Sizes Dimensions
Package
UC81 CS81 CS121 QN48 QN68 QN132 CS196 CS281 FG144 VQ100 FG256 FG484
Length × Width
(mm\mm)
4 × 4
5 × 5
6 × 6
6 × 6 8 × 8
8 × 8
8 × 8 10 × 10 13 × 13 14 × 14 17 × 17 23 × 23
Nominal Area
(mm2)
16
25
36
36
64
64
64
100
169
196
289
529
Pitch (mm)
0.4
0.5
0.5
0.4
0.4
0.5
0.5
0.5
1.0
0.5
1.0
1.0
Height (mm)
0.80
0.80
0.99
0.90
0.90
0.75
1.20
1.05
1.45
1.00
1.60
2.23
II
Revision 20
IGLOO Low Power Flash FPGAs
IGLOO Ordering Information
_
AGL1000
V2
FG
G
144
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging (some packages also halogen-free)
Package Type
=
=
=
=
=
UC
CS
QN
VQ
FG
Micro Chip Scale Package (0.4 mm pitch)
Chip Scale Package (0.4 mm and 0.5 mm pitches)
Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)
Very Thin Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO Devices
AGL015 = 15,000 System Gates (AGL015 is not recommended for new designs)
AGL030 = 30,000 System Gates
AGL060 = 60,000 System Gates
AGL125 = 125,000 System Gates
AGL250 = 250,000 System Gates
AGL400 = 400,000 System Gates
AGL600 = 600,000 System Gates
AGL1000 = 1,000,000 System Gates
IGLOO Devices with Cortex-M1
M1AGL250 = 250,000 System Gates
M1AGL600 = 600,000 System Gates
M1AGL1000 = 1,000,000 System Gates
Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
Revision 20
III
IGLOO Low Power Flash FPGAs
Temperature Grade Offerings
AGL015 1
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
Package
QN48
M1AGL250
M1AGL600 M1AGL1000
–
C, I
–
C, I
–
–
–
–
–
–
–
–
–
–
–
–
–
QN68
UC81
C, I
C, I
–
–
–
–
–
–
–
CS81
–
–
–
C, I
–
–
–
–
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
Notes:
–
C, I
C, I
C, I 2
–
C, I
C, I
C, I
C, I
C, I
–
–
–
–
–
C, I
C, I
–
C, I
C, I 2
C, I
C, I
–
–
–
–
–
–
–
–
–
C, I
C, I
C, I
–
–
–
–
–
C, I 2
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
–
–
–
–
–
–
–
–
–
–
–
–
–
C, I
1. AGL015 is not recommended for new designs.
2. Device/package support TBD.
C = Commercial temperature range: 0°C to 70°C ambient temperature.
I = Industrial temperature range: –40°C to 85°C ambient temperature.
IGLOO Device Status
IGLOO Devices
Status
Not recommended for new designs.
Production
M1 IGLOO Devices
Status
AGL015
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
Production
Production
Production
M1AGL250
Production
Production
Production
M1AGL600
Production
Production
Production
M1AGL1000
References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1
(Cortex-M1).
Contact your local Microsemi SoC Products Group representative for device availability:
www.microsemi.com/soc/contact/default.aspx.
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
AGL015 is not recommended for new designs.
IV
Revision 20
IGLOO Low Power Flash FPGAs
Table of Contents
IGLOO Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-128
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Package Pin Assignments
UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Revision 20
V
1 – IGLOO Device Family Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low power
mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze technology
simplifies power management through I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low power consumption (from 12 µW) while
the IGLOO device is completely functional in the system. This allows the IGLOO device to control system
power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming
minimal power.
Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, single-
chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-market
benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock
conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030
devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with
up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for
implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It
has a three-stage pipeline that offers a good balance between low power consumption and speed when
implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a
configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-
M1 is available for free from Microsemi for use in M1 IGLOO FPGAs.
The ARM-enabled devices have ordering numbers that begin with M1AGL and do not support AES
decryption.
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low
power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks
while retaining the design information, SRAM content, and registers. Flash*Freeze technology is
combined with in-system programmability, which enables users to quickly and easily upgrade and update
their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to
support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus
achieving the lowest total system power.
When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and
inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is
retained.
The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage
solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for
portable electronics.
Revision 20
1-1
IGLOO Device Family Overview
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an
ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings; power is
even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique
combination of reprogrammability and design security without external overhead, advantages that only
an FPGA with nonvolatile flash programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of
protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM
data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192)
bit block cipher encryption standard. AES was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES
decryption engine and a flash-based AES key that make them the most comprehensive programmable
logic device security solution available today. IGLOO devices with AES-based security provide a high
level of protection for remote field updates over public networks such as the Internet, and are designed to
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.
The contents of a programmed IGLOO device cannot be read back, although secure design verification
is possible.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique
in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with
industry-standard security, making remote ISP possible. An IGLOO device provides the best available
security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do
not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Live at Power-Up
Flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature helps in
system component initialization, execution of critical tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of
flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often
eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system
power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the
device will not have to be reloaded when system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock
generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and
reduce cost and design risk while increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost
instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike SRAM-
based FPGAs the device does not need to reload configuration and design state from external memory
components; instead it retains all necessary information to resume operation immediately.
1-2
Revision 20
IGLOO Low Power Flash FPGAs
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-
standard AES algorithm. The IGLOO family device architecture mitigates the need for ASIC migration at
higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution,
especially for applications in the consumer, networking/communications, computing, and avionics
markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-based
FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot be altered
by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user
data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all modes
of operation.
Advanced Architecture
The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO
device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and
Figure 1-2 on page 1-4):
•
•
•
•
•
•
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory†
Extensive CCCs and PLLs†
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the IGLOO core tile as either a three-input lookup table (LUT)
equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs.
† The AGL015 and AGL030 do not support PLL or SRAM.
Revision 20
1-3
IGLOO Device Family Overview
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 1
Note: *Not supported by AGL015 and AGL030 devices
Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and
AGL125)
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
(AGL600 and AGL1000)
Bank 2
Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and
AGL1000)
1-4
Revision 20
IGLOO Low Power Flash FPGAs
Flash*Freeze Technology
The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a
certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the
I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if
Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power
static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to Figure 1-3 for an
illustration of entering/exiting Flash*Freeze mode.
IGLOO FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-3 • IGLOO Flash*Freeze Mode
VersaTiles
The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The IGLOO VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-4 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-4 • VersaTile Configurations
Revision 20
1-5
IGLOO Device Family Overview
User Nonvolatile FlashROM
IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be
used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core
can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the AGL015 and AGL030 devices), as in
security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Microsemi development software solutions, Libero® Integrated Design Environment (IDE) and
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential
programming files for applications requiring a unique serial number in each part. Another feature allows
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly
and easily using Libero IDE and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their
north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent
read and write ports that can be configured with different bit widths on each port. For example, data can
be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be
initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the
AGL015 and AGL030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each
member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL015
and AGL030 do not have a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
1-6
Revision 20
IGLOO Low Power Flash FPGAs
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
•
•
•
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
OUT_CCC (for PLL only)
Global Clocking
IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V,
1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-
ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported (Table 1-1).
Table 1-1 • I/O Standards Supported
I/O Standards Supported
LVTTL/
LVCMOS
PCI/PCI-X
LVPECL, LVDS,
B-LVDS, M-LVDS
I/O Bank Type
Device and Bank Location
Advanced
East and west banks of AGL250 and larger
devices
3
3
3
3
3
Standard Plus North and south banks of AGL250 and
larger devices
Not supported
All banks of AGL060 and AGL125K
Standard
All banks of AGL015 and AGL030
Not supported Not supported
3
Revision 20
1-7
IGLOO Device Family Overview
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS
and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the
JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to
3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-5 on page 1-9).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
1-8
Revision 20
IGLOO Low Power Flash FPGAs
Figure 1-5 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
Revision 20
1-9
2 – IGLOO DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-
2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits1
Units
–0.3 to 1.65
V
V
V
V
V
V
VJTAG
VPUMP
VCCPLL
–0.3 to 3.75
Programming voltage
–0.3 to 3.75
–0.3 to 1.65
Analog power supply (PLL)
VCCI and VMV 2 DC I/O buffer supply voltage
–0.3 to 3.75
VI
I/O input voltage
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
3
TSTG
Storage Temperature
Junction Temperature
–65 to +150
+125
°C
°C
3
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA
Fabric User’s Guide for further information.
3. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 20
2-1
IGLOO DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 1
Symbol
TA
Parameter
Commercial
0 to +70
Industrial
–40 to +85
–40 to +100
Units
°C
°C
V
Ambient Temperature
Junction Temperature 2
TJ
VCC3
0 to +85
1.5 V DC core supply voltage5
1.425 to 1.575 1.425 to 1.575
1.14 to 1.575 1.14 to 1.575
1.2 V–1.5 V wide range DC
core supply voltage 4,6
V
VJTAG
JTAG DC voltage
1.4 to 3.6
3.15 to 3.45
0 to 3.6
1.4 to 3.6
3.15 to 3.45
0 to 3.6
V
V
V
V
V
VPUMP
Programming voltage
Programming Mode
Operation 7
VCCPLL8 Analog power supply (PLL)
1.5 V DC core supply voltage5 1.425 to 1.575 1.425 to 1.575
1.2 V – 1.5 V DC core supply 1.14 to 1.575 1.14 to 1.575
voltage4,6
VCCI and 1.2 V DC core supply voltage6
1.14 to 1.26
1.14 to 1.26
V
V
VMV 9
1.2 V DC wide range DC
1.14 to 1.575 1.14 to 1.575
supply voltage6
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.0 V DC supply voltage 10
3.3 V DC supply voltage
LVDS differential I/O
LVPECL differential I/O
Notes:
1.425 to 1.575 1.425 to 1.575
V
V
V
V
V
V
V
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
2.375 to 2.625 2.375 to 2.625
3.0 to 3.6 3.0 to 3.6
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-25 on page 2-24. VCCI should be at the same voltage within a given I/O bank.
4. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2
devices powered by 1.2 V supply must switch the core supply to 1.5 V for in-system programming.
®
5. For IGLOO V5 devices
6. For IGLOO V2 devices only, operating at VCCI ≥ VCC.
7. VPUMP can be left floating during operation (not programming mode).
8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User’s Guide
for further information.
9. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA
Fabric User’s Guide for further information.
10. 3.3 V wide range is compliant to the JESD-8B specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
Maximum Storage
Maximum Operating Junction
Temperature TJ (°C) 2
(biased/unbiased) Temperature TSTG (°C) 2
Commercial
Industrial
Notes:
500
500
20 years
20 years
110
110
100
100
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or
Undershoot Duration
Maximum Overshoot/
Undershoot2
VCCI
as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at junction temperature at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4 and Figure 2-2 on page 2-5.
There are five regions to consider during power-up.
IGLOO I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and
Figure 2-2 on page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
VCC Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Revision 20
2-3
IGLOO DC and Switching Characteristics
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the
output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the ProASIC®3 and ProASIC3E FPGA fabric user’s guides for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential inputs)
but slower because VCCI
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
but I/Os are slower because
the VCC is below specification.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
VCCI
Activation trip point:
Min VCCI datasheet specification
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Revision 20
IGLOO Low Power Flash FPGAs
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
Region 4: I/O
Region 1: I/O Buffers are OFF
and power supplies are within
specification.
buffers are ON.
I/Os are functional
(except differential inputs)
I/Os meet the entire datasheet
and timer specifications for
but slower because VCCI is
speed, VIH / VIL , VOH / VOL , etc.
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
but I/Os are slower because
the VCC is below specification.
Activation trip point:
Va = 0.85 V ± 0.2 V
Deactivation trip point:
Vd = 0.75 V ± 0.2 V
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.15 V
Deactivation trip point:
Vd = 0.8 V ± 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
VCCI
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because dynamic and static power consumption cause the
chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
EQ 1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5 on page 2-6.
P = Power dissipation
Revision 20
2-5
IGLOO DC and Switching Characteristics
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is
θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum junction
temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for the AGL1000-FG484 package at commercial temperature and in still air.
100°C – 70°C
23.3°C/W
Max. junction temp. (°C) – Max. ambient temp. (°C)
------------------------------------
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ =
= 1.28 W
EQ 2
θja(°C/W)
Table 2-5 • Package Thermal Resistivities
θja
Package Type
Device
AGL030
AGL060
AGL125
AGL250
AGL030
Pin Count
132
132
132
132
68
θjc
13.1
11.0
9.2
Still Air
21.4
21.2
21.1
21.0
68.4
35.3
28.0
37.1
38.3
39.5
32.8
28.8
26.9
40.6
55.2
31.6
37.6
38.6
28.1
23.3
1 m/s
16.8
16.6
16.5
16.4
45.8
29.4
22.8
31.1
32.2
33.4
28.5
24.8
22.3
35.2
49.4
26.2
31.2
34.7
24.4
19.0
2.5 m/s
Unit
Quad Flat No Lead (QN)
15.3
15.0
14.9
14.8
43.1
27.1
21.5
28.9
30.0
31.1
27.2
23.5
20.9
33.7
47.2
24.2
29.0
33.0
22.7
16.7
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
8.9
13.4
10.0
6.0
Very Thin Quad Flat Pack (VQ)*
Chip Scale Package (CS)
100
281
196
196
196
81
AGL1000
AGL400
AGL250
AGL125
AGL030
AGL060
AGL250
AGL030
AGL060
AGL1000
AGL400
AGL250
AGL1000
AGL1000
7.2
7.6
8.0
12.4
11.1
10.4
16.9
18.6
6.3
81
81
Micro Chip Scale Package (UC)
Fine Pitch Ball Grid Array (FG)
81
144
144
144
256
256
484
6.8
12.0
6.6
8.0
Note: *Thermal resistances for other device-package combinations will be posted in a later revision.
Disclaimer:
The simulation for determining the junction-to-air thermal resistance is based on JEDEC standards
(JESD51) and assumptions made in building the model. Junction-to-case is based on SEMI G38-88.
JESD51 is only used for comparing one package to another package, provided the two tests uses the
same condition. They have little relevance in actual application and therefore should be used with a
degree of caution.
2-6
Revision 20
IGLOO Low Power Flash FPGAs
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ =
70°C, VCC = 1.425 V)
For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
–40°C
0.934
0.855
0.799
0°C
25°C
0.971
0.891
0.832
70°C
1.000
0.917
0.857
85°C
1.007
0.924
0.864
100°C
1.013
0.929
0.868
1.425
0.953
0.874
0.816
1.500
1.575
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ =
70°C, VCC = 1.14 V)
For IGLOO V2, 1.2 V DC Core Supply Voltage
Array
Junction Temperature (°C)
Voltage VCC
(V)
–40°C
0.967
0.864
0.794
0°C
25°C
0.991
0.885
0.814
70°C
1.000
0.894
0.821
85°C
1.006
0.899
0.827
100°C
1.010
0.902
0.830
1.14
1.20
1.26
0.978
0.874
0.803
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages
(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage.
Microsemi recommends using the PowerCalculator and SmartPower software estimation tools to
evaluate the projected static and active power based on the user design, power mode usage, operating
voltage, and temperature.
Table 2-8 • Power Supply State per Mode
Power Supply Configurations
Modes/power supplies
Flash*Freeze
VCC
On
VCCPLL
VCCI
On
VJTAG
VPUMP
On/off/floating
Off
On
Off
Off
On
On
Off
Off
On
Sleep
Off
On
Shutdown
Off
Off
Off
No Flash*Freeze
Note: Off: Power supply level = 0 V
On
On
On/off/floating
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode*
Core
Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units
Typical
(25°C)
1.2 V
1.5 V
4
4
6
8
13
18
20
34
27
51
30
72
44
µA
µA
6
10
127
Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution,
which is shown in Table 2-13 on page 2-10 through Table 2-15 on page 2-11 and Table 2-16 on page 2-11
through Table 2-18 on page 2-12 (PDC6 and PDC7).
Revision 20
2-7
IGLOO DC and Switching Characteristics
Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode*
Core
Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units
VCCI/ VJTAG = 1.2 V
(per bank) Typical
(25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI/VJTAG = 1.5 V 1.2 V /
(per bank) Typical
(25°C)
1.5 V
VCCI/VJTAG = 1.8 V 1.2 V /
(per bank) Typical
(25°C)
1.5 V
VCCI/VJTAG = 2.5 V 1.2 V /
(per bank) Typical
(25°C)
1.5 V
VCCI/VJTAG = 3.3 V 1.2 V /
(per bank) Typical
(25°C)
1.5 V
Note: IDD = NBANKS × ICCI. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-10
through Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12 (PDC6 and
PDC7).
Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode
Core Voltage
AGL015
AGL030
Units
Typical (25°C)
1.2 V / 1.5 V
0
0
µA
2-8
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1
Core
Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units
ICCA Current2
Typical (25°C)
1.2 V
1.5 V
5
6
10
20
13
28
18
44
25
66
28
82
42
µA
µA
14
16
137
ICCI or IJTAG Current3
VCCI/VJTAG = 1.2 V
(per bank) Typical
(25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI/VJTAG = 1.5 V
(per bank) Typical
(25°C)
1.2 V /
1.5 V
VCCI/VJTAG = 1.8 V
(per bank) Typical
(25°C)
1.2 V /
1.5 V
VCCI/VJTAG = 2.5 V
(per bank) Typical
(25°C)
1.2 V /
1.5 V
VCCI/VJTAG = 3.3 V
(per bank) Typical
(25°C)
1.2 V /
1.5 V
Notes:
1. IDD = N
× ICCI + ICCA. JTAG counts as one bank when powered.
BANKS
2. Includes VCC, VPUMP, and VCCPLL currents.
3. Values do not include I/O static contribution (PDC6 and PDC7).
Revision 20
2-9
IGLOO DC and Switching Characteristics
Power per I/O Pin
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
Static Power
PDC6 (mW)1
Dynamic Power
VCCI (V)
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range3
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS4
1.2 V LVCMOS Wide Range4
3.3 V PCI
3.3
3.3
2.5
1.8
1.5
1.2
1.2
3.3
3.3
–
–
–
–
–
–
–
–
–
16.27
16.27
4.65
1.61
0.96
0.58
0.58
17.67
17.67
3.3 V PCI-X
Differential
LVDS
2.5
3.3
2.26
5.72
23.39
59.05
LVPECL
Notes:
1.
2.
P
P
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCCI.
DC6
AC9
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO V2 devices only
Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
VCCI (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range3
2.5 V LVCMOS
3.3
3.3
2.5
1.8
1.5
1.2
1.2
3.3
3.3
–
–
–
–
–
–
–
–
–
16.41
16.41
4.75
1.8 V LVCMOS
1.66
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS4
1.2 V LVCMOS Wide Range4
1.00
0.61
0.61
3.3 V PCI
17.78
17.78
3.3 V PCI-X
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCCI.
3. Applicable for IGLOO V2 devices only.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
2-10
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
VCCI (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range3
2.5 V LVCMOS
3.3
3.3
2.5
1.8
1.5
1.2
1.2
–
–
–
–
–
–
–
17.24
17.24
5.64
2.63
1.97
0.57
0.57
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS4
1.2 V LVCMOS Wide Range4
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO V2 devices only.
Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
Static Power
PDC7 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS5
1.2 V LVCMOS Wide Range5
3.3 V PCI
5
5
3.3
3.3
2.5
1.8
1.5
1.2
1.2
3.3
3.3
–
–
–
–
–
–
–
–
–
136.95
136.95
76.84
49.31
33.36
16.24
16.24
194.05
194.05
5
5
5
5
5
10
10
3.3 V PCI-X
Differential
LVDS
–
–
2.5
3.3
7.74
156.22
339.35
LVPECL
19.54
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
Revision 20
2-11
IGLOO DC and Switching Characteristics
Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
Static Power
PDC7 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range4
2.5 V LVCMOS
5
5
3.3
3.3
2.5
1.8
1.5
1.2
1.2
3.3
3.3
–
–
–
–
–
–
–
–
–
122.16
122.16
68.37
34.53
23.66
14.90
14.90
181.06
181.06
5
1.8 V LVCMOS
5
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS5
1.2 V LVCMOS Wide Range5
5
5
5
3.3 V PCI
10
10
3.3 V PCI-X
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
P
is the static power (where applicable) measured on VCCI.
DC7
is the total dynamic power measured on VCCI.
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard I/O Banks
Static Power
PDC7 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range4
2.5 V LVCMOS
5
5
5
5
5
5
5
3.3
3.3
2.5
1.8
1.5
1.2
1.2
–
–
–
–
–
–
–
104.38
104.38
59.86
31.26
21.96
13.49
13.49
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS5
1.2 V LVCMOS Wide Range5
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
2-12
Revision 20
IGLOO Low Power Flash FPGAs
Power Consumption of Various Internal Resources
Table 2-19 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
Definition
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PAC1
Clock contribution of a
Global Rib
7.778
4.334
1.379
0.151
6.221
3.512
1.445
0.149
6.082
2.759
1.377
0.151
4.460
2.718
1.483
0.149
4.446
1.753
1.467
0.149
2.736
1.971
1.503
0.151
0.000
3.483
1.472
0.146
0.000
3.483
1.472
0.146
PAC2
PAC3
PAC4
Clock contribution of a
Global Spine
Clock contribution of a
VersaTile row
Clock contribution of a
VersaTile used as a
sequential module
PAC5
PAC6
PAC7
First contribution of a
VersaTile used as a
sequential module
0.057
Second contribution of a
VersaTile used as a
sequential module
0.207
Contribution of a
VersaTile used as a
combinatorial module
0.276
1.161
0.262
1.147
0.279
1.193
0.277
0.280
1.076
0.300
1.088
0.281
1.134
0.273
1.153
PAC8
PAC9
Average contribution of a
routing net
1.273
Contribution of an I/O
input pin (standard-
dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O
output pin (standard-
dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
Average contribution of a
RAM block during a read
operation
25.00
30.00
2.70
Average contribution of a
RAM block during a write
operation
Dynamic PLL
contribution
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE).
Revision 20
2-13
IGLOO DC and Switching Characteristics
Table 2-20 • Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
Definition
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PDC1
Array static power in Active
mode
See Table 2-12 on page 2-9.
PDC2
PDC3
Array static power in Static
(Idle) mode
See Table 2-11 on page 2-8.
See Table 2-9 on page 2-7.
Array static power in
Flash*Freeze mode
PDC4
PDC5
Static PLL contribution
1.84
Bank quiescent power
(VCCI-dependent)
See Table 2-12 on page 2-9.
PDC6
PDC7
I/O input pin static power
(standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
I/O output pin static power
(standard-dependent)
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE).
2-14
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-21 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
Definition
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PAC1
Clock contribution of a
Global Rib
4.978
2.773
0.883
0.096
3.982
2.248
0.924
0.095
3.892
1.765
0.881
0.096
2.854
1.740
0.949
0.095
2.845
1.122
0.939
0.095
1.751
1.261
0.962
0.096
0.000
2.229
0.942
0.094
0.000
2.229
0.942
0.094
PAC2
PAC3
PAC4
Clock contribution of a
Global Spine
Clock contribution of a
VersaTile row
Clock contribution of a
VersaTile used as a
sequential module
PAC5
PAC6
PAC7
First contribution of a
VersaTile used as a
sequential module
0.045
Second contribution of a
VersaTile used as a
sequential module
0.186
Contribution of a
VersaTile used as a
combinatorial module
0.158
0.756
0.149
0.729
0.158
0.753
0.157
0.160
0.678
0.170
0.692
0.160
0.738
0.155
0.721
PAC8
PAC9
Average contribution of a
routing net
0.817
Contribution of an I/O
input pin (standard-
dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O
output pin (standard-
dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
Average contribution of a
RAM block during a read
operation
25.00
30.00
2.10
Average contribution of a
RAM block during a write
operation
Dynamic PLL contribution
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
spreadsheet calculator or SmartPower tool in Libero IDE.
Revision 20
2-15
IGLOO DC and Switching Characteristics
Table 2-22 • Different Components Contributing to the Static Power Consumption in IGLOO Device
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Device Specific Static Power (mW)
Parameter
Definition
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PDC1
Array static power in
Active mode
See Table 2-12 on page 2-9.
PDC2
PDC3
Array static power in Static
(Idle) mode
See Table 2-11 on page 2-8.
See Table 2-9 on page 2-7.
Array static power in
Flash*Freeze mode
PDC4
PDC5
Static PLL contribution
0.90
Bank quiescent power
(VCCI-Dependent)
See Table 2-12 on page 2-9.
PDC6
PDC7
I/O input pin static power
(standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
I/O output pin static
power (standard-
dependent)
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE).
2-16
Revision 20
IGLOO Low Power Flash FPGAs
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Microsemi Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-23 on
page 2-19.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-24 on
page 2-19.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-24 on page 2-19. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7
NINPUTS is the number of I/O input buffers used in the design.
N
OUTPUTS is the number of I/O output buffers used in the design.
BANKS is the number of I/O banks powered in the design.
N
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
"Spine Architecture" section of the IGLOO FPGA Fabric User’s Guide.
NROW is the number of VersaTile rows used in the design—guidelines are provided in
"Spine Architecture" section of the IGLOO FPGA Fabric User’s Guide.
F
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
N
P
S-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on
page 2-19.
FCLK is the global clock signal frequency.
Revision 20
2-17
IGLOO DC and Switching Characteristics
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on
page 2-19.
F
CLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on
page 2-19.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-24 on page 2-19.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
F
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-24 on
page 2-19.
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.†
† If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
2-18
Revision 20
IGLOO Low Power Flash FPGAs
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-23 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 2-24 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
β1
β2
β3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
Revision 20
2-19
IGLOO DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
Y
tPD = 1.22 ns
tPD = 1.20 ns
tDP = 1.72 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
High slew rate
LVTTL
tDP = 3.05 ns (Advanced I/O Banks)
tPD = 1.80 ns
I/O Module
(Non-Registered)
Combinational Cell
I/O Module
(Registered)
Y
Output drive strength = 8 mA
High slew rate
LVTTL
t
PY = 1.20 ns
tDP = 4.12 ns (Advanced I/O Banks)
LVPECL
(Applicable
to Advanced
I/O Banks only)
tPD = 1.49 ns
I/O Module
(Non-Registered)
D
Q
Combinational Cell
Y
Output drive strength = 4 mA
LVCMOS 1.5 V
High slew rate
t
ICLKQ = 0.43 ns
t
DP = 4.42 ns (Advanced I/O Banks)
tPD = 0.86 ns
tISUD = 0.47 ns
Input LVTTL
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
t
PY = 0.87 ns (Advanced I/O Banks)
Y
D
Q
D
Q
D
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
I/O Module
(Non-Registered)
tPD = 0.92 ns
tDP = 3.05 ns
(Advanced I/O Banks)
tCLKQ = 0.90 ns
tSUD = 0.82 ns
t
t
OCLKQ = 1.02 ns
OSUD = 0.52 ns
t
CLKQ = 0.90 ns
LVDS,
BLVDS,
M-LVDS
tSUD = 0.82 ns
Input LVTTL
Clock
Input LVTTL
Clock
(Applicable for
Advanced I/O
Banks only)
tPY = 1.35 ns
tPY = 0.87 ns
tPY = 0.87 ns
(Advanced I/O Banks)
(Advanced I/O Banks)
Figure 2-3 • Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
2-20
Revision 20
IGLOO Low Power Flash FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
t
t
PY = MAX(tPY(R), tPY(F))
DIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
Revision 20
2-21
IGLOO DC and Switching Characteristics
tDOUT
tDP
D Q
CLK
PAD
DOUT
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
2-22
Revision 20
IGLOO Low Power Flash FPGAs
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% VCCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
Revision 20
2-23
IGLOO DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
Equivalent
Software
Default
VIL
VIH
VOL
VOH
IOL1 IOH1
Drive
I/O
Drive
Strength Slew
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Standard Strength Option2 Rate Min.V
mA mA
3.3 V
LVTTL /
3.3 V
12 mA
12 mA
12 mA
High –0.3
High –0.3
High –0.3
0.8
2
3.6
3.6
2.7
0.4
2.4
12
12
LVCMOS
3.3 V
100 µA
0.8
2
0.2
VCCI – 0.2 0.1 0.1
LVCMOS
Wide
Range3
2.5 V
LVCMOS
12 mA
12 mA
12 mA
2 mA
12 mA
12 mA
12 mA
2 mA
0.7
1.7
0.7
1.7
12
12
12
12
2
1.8 V
LVCMOS
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45 12
1.5 V
LVCMOS
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12
High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
1.2 V
2
LVCMOS4
1.2 V
100 µA
2 mA
High –0.3 0.3 * VCCI 0.7 * VCCI 1.575
0.1
VCCI – 0.1 0.1 0.1
LVCMOS
Wide
Range4,5
3.3 V PCI
Per PCI specifications
3.3 V
Per PCI-X specifications
PCI-X
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI ≥ VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
2-24
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
Equivalent
Software
VIL
VIH
VOL
VOH
IOL IOH
Default
Drive
I/O
Drive
Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Standard Strength Option2 Rate
V
mA mA
12 12
3.3 V
LVTTL /
3.3 V
12 mA
12 mA
High –0.3
High –0.3
High –0.3
0.8
2
3.6
3.6
2.7
0.4
2.4
LVCMOS
3.3 V
100 µA
12 mA
0.8
2
0.2
VDD-0.2
0.1 0.1
LVCMOS
Wide
Range3
2.5 V
LVCMOS
12 mA
8 mA
12 mA
8 mA
4 mA
2 mA
2 mA
0.7
1.7
0.7
1.7
12
8
12
8
1.8 V
LVCMOS
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45
1.5 V
LVCMOS
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
4
4
1.2 V
2 mA
2
2
LVCMOS4
1.2 V
100 µA
High –0.3 0.3 * VCCI 0.7 * VCCI 1.575
0.1
VCCI – 0.1 0.1 0.1
LVCMOS
Wide
Range4
3.3 V PCI
Per PCI specifications
3.3 V
Per PCI-X specifications
PCI-X
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI ≥ VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
Revision 20
2-25
IGLOO DC and Switching Characteristics
Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
1
1
Equivalent
Software
VIL
VIH
VOL
VOH
IOL IOH
Default
Drive
I/O
Drive
Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Standard Strength Option2 Rate
V
mA mA
3.3 V
LVTTL /
3.3 V
8 mA
8 mA
High –0.3
High –0.3
High –0.3
0.8
0.8
0.7
2
3.6
3.6
3.6
0.4
2.4
8
8
LVCMOS
3.3 V
100 µA
8 mA
2
0.2
VDD-0.2
0.1 0.1
LVCMOS
Wide
Range3
2.5 V
LVCMOS
8 mA
4 mA
8 mA
4 mA
2 mA
1 mA
1 mA
1.7
0.7
1.7
8
4
2
1
8
4
2
1
1.8 V
LVCMOS
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
1.5 V
LVCMOS
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
1.2 V
1 mA
LVCMOS4
1.2 V
100 µA
High –0.3 0.3 * VCCI 0.7 * VCCI 3.6
0.1
VCCI – 0.1 0.1 0.1
LVCMOS
Wide
Range4,5
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI ≥ VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
2-26
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-28 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
IIL4
Industrial2
IIH5
µA
10
10
10
10
10
10
10
10
10
IIL4
µA
15
15
15
15
15
15
15
15
15
IIH5
µA
15
15
15
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
µA
10
10
10
10
10
10
10
10
10
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS3
1.2 V LVCMOS Wide Range3
3.3 V PCI
3.3 V PCI-X
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3. Applicable to V2 Devices operating at VCCI ≥ VCC.
4. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
5. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
Revision 20
2-27
IGLOO DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-29 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
1.4 V
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V VCMOS Wide Range
2.5 V LVCMOS
1.4 V
1.2 V
1.8 V LVCMOS
0.90 V
1.5 V LVCMOS
0.75 V
1.2 V LVCMOS
0.60 V
1.2 V LVCMOS Wide Range
3.3 V PCI
0.60 V
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
Table 2-30 • I/O AC Parameter Definitions
Parameter
Parameter Definition
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
tDP
tPY
tDOUT
tEOUT
tDIN
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
tZH
tLZ
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
2-28
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
standard)
Applicable to Advanced I/O Banks
3.3 V
LVTTL /
3.3 V
12 mA
12
12
High
High
5
5
–
–
0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns
0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns
LVCMOS
3.3 V
100 µA
LVCMOS
Wide
Range2
2.5 V
LVCMOS
12 mA
12 mA
12 mA
12
12
12
–
High
High
High
5
5
5
–
–
–
0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns
0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns
0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns
1.8 V
LVCMOS
1.5 V
LVCMOS
3.3 V PCI Per PCI
spec
High 10 25 2 0.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
High 10 25 2 0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
3.3 V
PCI-X
Per
PCI-X
spec
–
LVDS
24 mA
24 mA
–
–
High
High
–
–
–
–
0.97 1.74 0.19 1.35
0.97 1.68 0.19 1.16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for
connectivity. This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-29
IGLOO DC and Switching Characteristics
Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
standard)
Applicable to Standard Plus I/O Banks
3.3 V
LVTTL /
3.3 V
12 mA
12 High
12 High
12 High
5
5
–
–
0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns
0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns
LVCMOS
3.3 V
100 µA
LVCMOS
Wide
Range2
2.5 V
LVCMOS
12 mA
8 mA
4 mA
5
5
5
–
–
–
0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns
0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns
0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns
1.8 V
LVCMOS
8
4
–
–
High
High
1.5 V
LVCMOS
3.3 V PCI Per PCI
spec
High 10 25 2 0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns
High 10 25 2 0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns
3.3 V
PCI-X
Per PCI-
X spec
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for
connectivity. This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-30
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
standard)
Applicable to Standard I/O Banks
3.3 V
LVTTL /
3.3 V
8 mA
8
8
High
High
5
5
–
–
0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26 ns
0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17 ns
LVCMOS
3.3 V
100 µA
LVCMOS
Wide
Range2
2.5 V
LVCMOS
8 mA
4 mA
2 mA
8
4
2
High
High
High
5
5
5
–
–
–
0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15 ns
0.97 2.18 0.18 0.98 0.66 2.22 1.93 1.97 2.06 ns
0.97 2.51 0.18 1.14 0.66 2.56 2.21 1.99 2.03 ns
1.8 V
LVCMOS
1.5 V
LVCMOS
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-31
IGLOO DC and Switching Characteristics
Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
standard)
Applicable to Advanced I/O Banks
3.3 V
LVTTL /
3.3 V
12 mA 12 mA High
100 µA 12 mA High
5
5
–
–
1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns
1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns
LVCMOS
3.3 V
LVCMOS
Wide
Range2
2.5 V
LVCMOS
12 mA 12 mA High
12 mA 12 mA High
12 mA 12 mA High
5
5
5
5
5
–
–
–
–
–
1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns
1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns
1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
1.8 V
LVCMOS
1.5 V
LVCMOS
1.2 V
LVCMOS
2 mA
2 mA High
1.2 V
100 µA 2 mA High
LVCMOS
Wide
Range3
3.3 V PCI Per PCI
spec
–
–
High 10 252 1.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
High 10 252 1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
3.3 V
Per
PCI-X
spec
PCI-X
LVDS
24 mA
24 mA
–
–
High
High
–
–
–
–
1.55 2.27 0.25 1.57
1.55 2.24 0.25 1.38
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for
connectivity. This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-32
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
standard)
Applicable to Standard Plus I/O Banks
3.3 V
LVTTL /
3.3 V
12 mA
12
12
High
High
5
5
–
–
1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns
1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns
LVCMOS
3.3 V
100 µA
LVCMOS
Wide
Range2
2.5 V
LVCMOS
12 mA
8 mA
12
8
High
High
High
High
High
5
5
5
5
5
–
–
–
–
–
1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns
1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns
1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns
1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns
1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns
1.8 V
LVCMOS
1.5 V
LVCMOS
4 mA
4
1.2 V
LVCMOS
2 mA
2
1.2 V
100 µA
2
LVCMOS
Wide
Range3
3.3 V PCI
Per
PCI
spec
–
–
High 10 252 1.55 2.53 0.26 0.84 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns
High 10 252 1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns
3.3 V
PCI-X
Per
PCI-X
spec
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to
the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78
for connectivity. This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-33
IGLOO DC and Switching Characteristics
Table 2-36 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
standard)
Applicable to Standard I/O Banks
3.3 V
LVTTL /
3.3 V
8 mA
8
8
High
High
5
5
–
–
1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns
1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns
LVCMOS
3.3 V
100 µA
LVCMOS
Wide
Range3
2.5 V
LVCMOS
8 mA
4 mA
8
4
2
1
1
High
High
High
High
High
5
5
5
5
5
–
–
–
–
–
1.55 2.39 0.26 1.15 1.10 2.42 2.05 2.38 2.80 ns
1.55 2.60 0.26 1.08 1.10 2.64 2.33 2.38 2.62 ns
1.55 2.92 0.26 1.22 1.10 2.96 2.60 2.40 2.56 ns
1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns
1.55 3.59 0.26 1.53 1.10 3.47 3.06 2.51 2.49 ns
1.8 V
LVCMOS
1.5 V
LVCMOS
2 mA
1.2 V
LVCMOS
1 mA
1.2 V
100 µA
LVCMOS
Wide
Range3
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to
the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-34
Revision 20
IGLOO Low Power Flash FPGAs
Detailed I/O DC Characteristics
Table 2-37 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min.
Max.
Units
pF
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
Table 2-38 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
(Ω)2
100
100
50
(Ω)3
3.3 V LVTTL / 3.3 V LVCMOS
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
24 mA
100 μA
2 mA
25
17
50
11
33
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
100
100
50
200
200
100
100
50
4 mA
6 mA
8 mA
50
12 mA
16 mA
2 mA
25
20
40
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
2 mA
33
37
1.2 V LVCMOS4
158
164
1.2 V LVCMOS Wide Range4
100 μA
Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS
25 75
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
3.
R
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC
Revision 20
2-35
IGLOO DC and Switching Characteristics
Table 2-39 • I/O Output Buffer Maximum Resistances1
Applicable to Standard Plus I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
(Ω)2
(Ω)3
3.3 V LVTTL / 3.3 V LVCMOS
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
100 μA
2 mA
25
25
75
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
100
100
50
200
200
100
100
50
4 mA
6 mA
8 mA
50
12 mA
2 mA
25
1.8 V LVCMOS
1.5 V LVCMOS
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
2 mA
200
100
158
224
112
164
4 mA
1.2 V LVCMOS4
2 mA
1.2 V LVCMOS Wide Range4
100 μA
Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS
25 75
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC
2-36
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-40 • I/O Output Buffer Maximum Resistances1
Applicable to Standard I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
(Ω)2
(Ω)3
3.3 V LVTTL / 3.3 V LVCMOS
100
100
50
300
300
150
150
4 mA
6 mA
8 mA
50
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
100 μA
2 mA
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
100
100
50
200
200
100
100
225
112
224
164
4 mA
6 mA
8 mA
50
1.8 V LVCMOS
2 mA
200
100
200
158
4 mA
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range4
Notes:
2 mA
1 mA
100 μA
Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
Table 2-41 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 K
10 K
11 K
18 K
19 K
25 K
19 K
Max.
45 K
45 K
55 K
70 K
90 K
110 K
110 K
Min.
10 K
10 K
12 K
17 K
19 K
25 K
19 K
Max.
45 K
3.3 V
3.3 V Wide Range I/Os
45 K
2.5 V
74 K
1.8 V
110 K
140 K
150 K
150 K
1.5 V
1.2 V
1.2 V Wide Range I/Os
Notes:
1.
2.
R
R
= (VCCImax – VOHspec) / I
(WEAK PULL-UP-MAX) (WEAK PULL-UP-MIN)
= (VOLspec) / I
(WEAK PULLDOWN-MAX)
(WEAK PULLDOWN-MIN)
Revision 20
2-37
IGLOO DC and Switching Characteristics
Table 2-42 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
25
25
27
27
6 mA
51
54
8 mA
51
54
12 mA
16 mA
24 mA
100 μA
2 mA
103
132
268
109
127
181
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
16
16
32
32
65
83
169
9
18
18
37
37
74
87
124
11
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
1.8 V LVCMOS
4 mA
17
35
45
91
91
13
25
32
66
66
20
20
103
22
44
51
74
74
16
33
39
55
55
26
26
109
6 mA
8 mA
12 mA
16 mA
2 mA
1.5 V LVCMOS
4 mA
6 mA
8 mA
12 mA
2 mA
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI/PCI-X
100 μA
Per PCI/PCI-X
specification
Note: *TJ = 100°C
2-38
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-43 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
100 μA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
100 μA
25
25
27
27
51
54
51
54
103
103
109
109
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
16
16
32
32
65
9
18
18
37
37
74
11
1.8 V LVCMOS
1.5 V LVCMOS
17
35
35
13
25
20
20
103
22
44
44
16
33
26
26
109
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Note: *TJ = 100°C
Revision 20
2-39
IGLOO DC and Switching Characteristics
Table 2-44 • I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
100 μA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
1 mA
100 μA
25
25
51
51
27
27
54
54
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
16
16
32
32
9
18
18
37
37
11
22
16
26
26
1.8 V LVCMOS
17
13
20
20
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Note: *TJ = 100°C
The length of time an I/O can withstand IOSH OSL
/I
events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-45 • Duration of Short Circuit Event before Failure
Temperature
–40°C
–20°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
6 months
Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Rise/Fall Time
(min.)
Input Rise/Fall Time
(max.)
Input Buffer
Reliability
LVTTL/LVCMOS
No requirement
No requirement
10 ns *
10 ns *
20 years (100°C)
10 years (100°C)
LVDS/B-LVDS/M-LVDS/
LVPECL
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Microsemi recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
2-40
Revision 20
IGLOO Low Power Flash FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V
software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
2
4
6
8
25
25
27
27
4 mA
4
6 mA
6
51
54
8 mA
8
51
54
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
103
132
268
109
127
181
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-48 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
2
25
25
27
27
4 mA
4
6 mA
6
51
54
8 mA
8
8
51
54
12 mA
16 mA
Notes:
12 12
16 16
103
103
109
109
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Revision 20
2-41
IGLOO DC and Switching Characteristics
Table 2-49 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
2
2
2
2
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2
4
6
8
2
25
25
51
51
27
27
54
54
4
6
8
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
R to GND for tHZ / tZH / tZHS
Test Point
Datapath
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
2-42
Revision 20
IGLOO Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 4.47 0.18 0.85 0.66 4.56 3.89 2.24 2.19 8.15 7.48
0.97 3.74 0.18 0.85 0.66 3.82 3.37 2.49 2.63 7.42 6.96
0.97 3.74 0.18 0.85 0.66 3.82 3.37 2.49 2.63 7.42 6.96
0.97 3.23 0.18 0.85 0.66 3.30 2.98 2.66 2.91 6.89 6.57
0.97 3.08 0.18 0.85 0.66 3.14 2.89 2.70 2.99 6.74 6.48
0.97 3.00 0.18 0.85 0.66 3.06 2.91 2.74 3.27 6.66 6.50
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH
tLZ
tHZ tZLS tZHS Units
Std.
Std.
Std.
Std.
Std.
Std.
0.97 2.73 0.18 0.85 0.66 2.79 2.22 2.25 2.32 6.38 5.82
0.97 2.32 0.18 0.85 0.66 2.37 1.85 2.50 2.76 5.96 5.45
0.97 2.32 0.18 0.85 0.66 2.37 1.85 2.50 2.76 5.96 5.45
0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27
0.97 2.05 0.18 0.85 0.66 2.10 1.64 2.70 3.12 5.69 5.24
0.97 2.07 0.18 0.85 0.66 2.12 1.60 2.75 3.41 5.71 5.20
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
0.97 3.94 0.18 0.85 0.66 4.02 3.46 1.98 2.03 7.62 7.05
0.97 3.24 0.18 0.85 0.66 3.31 2.99 2.21 2.42 6.90 6.59
0.97 3.24 0.18 0.85 0.66 3.31 2.99 2.21 2.42 6.90 6.59
0.97 2.76 0.18 0.85 0.66 2.82 2.63 2.36 2.68 6.42 6.22
0.97 2.76 0.18 0.85 0.66 2.82 2.63 2.36 2.68 6.42 6.22
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-43
IGLOO DC and Switching Characteristics
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH
tLZ
tHZ tZLS tZHS Units
Std.
Std.
Std.
Std.
Std.
0.97 2.32 0.18 0.85 0.66 2.37 1.90 1.98 2.13 5.96 5.49
0.97 1.94 0.18 0.85 0.66 1.99 1.57 2.20 2.53 5.58 5.16
0.97 1.94 0.18 0.85 0.66 1.99 1.57 2.20 2.53 5.58 5.16
0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99
0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
0.97
0.97
0.97
0.97
tDP
tDIN
tPY
tEOUT
0.66
0.66
0.66
0.66
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
3.80 0.18 0.83
3.80 0.18 0.83
3.15 0.18 0.83
3.15 0.18 0.83
3.88 3.41 1.74 1.78
3.88 3.41 1.74 1.78
3.21 2.94 1.96 2.17
3.21 2.94 1.96 2.17
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
0.97
0.97
0.97
0.97
tDP
tDIN
tPY
tEOUT
0.66
0.66
0.66
0.66
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
2.19 0.18 0.83
2.19 0.18 0.83
1.85 0.18 0.83
1.85 0.18 0.83
2.24 1.79 1.74 1.87
2.24 1.79 1.74 1.87
1.89 1.46 1.96 2.26
1.89 1.46 1.96 2.26
4 mA
ns
6 mA
ns
8 mA
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-44
Revision 20
IGLOO Low Power Flash FPGAs
Applies to 1.2 V DC Core Voltage
Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 5.12 0.26 0.98 1.10 5.20 4.46 2.81 3.02 10.99 10.25
1.55 4.38 0.26 0.98 1.10 4.45 3.93 3.07 3.48 10.23 9.72
1.55 4.38 0.26 0.98 1.10 4.45 3.93 3.07 3.48 10.23 9.72
1.55 3.85 0.26 0.98 1.10 3.91 3.53 3.24 3.77 9.69 9.32
1.55 3.69 0.26 0.98 1.10 3.75 3.44 3.28 3.84 9.54 9.23
1.55 3.61 0.26 0.98 1.10 3.67 3.46 3.33 4.13 9.45 9.24
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 3.33 0.26 0.98 1.10 3.38 2.75 2.82 3.18 9.17 8.54
1.55 2.91 0.26 0.98 1.10 2.95 2.37 3.07 3.64 8.73 8.15
1.55 2.91 0.26 0.98 1.10 2.95 2.37 3.07 3.64 8.73 8.15
1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97
1.55 2.63 0.26 0.98 1.10 2.67 2.14 3.28 4.01 8.45 7.93
1.55 2.65 0.26 0.98 1.10 2.69 2.10 3.33 4.31 8.47 7.89
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
1.55 4.56 0.26 0.97 1.10 4.63 3.98 2.54 2.83 10.42 9.76
1.55 3.84 0.26 0.97 1.10 3.90 3.50 2.77 3.24 9.69 9.29
1.55 3.84 0.26 0.97 1.10 3.90 3.50 2.77 3.24 9.69 9.29
1.55 3.35 0.26 0.97 1.10 3.40 3.13 2.93 3.51 9.19 8.91
1.55 3.35 0.26 0.97 1.10 3.40 3.13 2.93 3.51 9.19 8.91
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-45
IGLOO DC and Switching Characteristics
Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
1.55 2.89 0.26 0.97 1.10 2.93 2.38 2.53 2.96 8.72 8.17
1.55 2.50 0.26 0.97 1.10 2.54 2.04 2.77 3.37 8.33 7.82
1.55 2.50 0.26 0.97 1.10 2.54 2.04 2.77 3.37 8.33 7.82
1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65
1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
1.55
1.55
1.55
1.55
tDP
tDIN
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
4.39 0.26 0.94
4.39 0.26 0.94
3.72 0.26 0.94
3.72 0.26 0.94
4.46 3.91 2.17 2.44
4.46 3.91 2.17 2.44
3.78 3.43 2.40 2.85
3.78 3.43 2.40 2.85
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
1.55
1.55
1.55
1.55
tDP
tDIN
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
2.74 0.26 0.94
2.74 0.26 0.94
2.38 0.26 0.94
2.38 0.26 0.94
2.78 2.26 2.17 2.55
2.78 2.26 2.17 2.55
2.41 1.92 2.40 2.96
2.41 1.92 2.40 2.96
4 mA
ns
6 mA
ns
8 mA
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-46
Revision 20
IGLOO Low Power Flash FPGAs
3.3 V LVCMOS Wide Range
Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Advanced I/O Banks
3.3 V LVCMOS Wide Range
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Equivalent
Software
Default Drive
Drive
Strength
Strength
Min. Max. Min. Max. Max.
Min.
V
Max.
Max.
Option1
V
V
V
2
2
2
2
2
2
2
V
V
µA µA
mA4
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
25
27
27
10 10
10 10
10 10
10 10
10 10
10 10
10 10
25
6 mA
51
54
8 mA
51
54
12 mA
16 mA
24 mA
103
132
268
109
127
181
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Revision 20
2-47
IGLOO DC and Switching Characteristics
Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Standard Plus I/O Banks
3.3 V LVCMOS Wide Range
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Equivalent
Software
Default Drive
Drive
Strength
Strength
Min. Max. Min. Max. Max.
Min.
V
Max.
Max.
Option1
V
V
V
2
2
2
2
2
2
V
V
µA µA
mA4
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
–0.3 0.8
3.6
3.6
3.6
3.6
3.6
3.6
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
25
27
27
10 10
10 10
10 10
10 10
10 10
10 10
25
6 mA
51
54
8 mA
51
54
12 mA
16 mA
103
103
109
109
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
2-48
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-65 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Standard I/O Banks
3.3 V LVCMOS Wide Range VIL VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Equivalent
Software
DefaultDrive
Strength
Drive
Strength
Min. Max. Min. Max. Max.
Min.
V
Max.
Max.
Option1
V
V
V
2
2
2
2
V
V
µA µA
mA4
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
3.6
3.6
3.6
3.6
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
25
27
27
54
54
10 10
10 10
10 10
10 10
25
51
51
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-66 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Revision 20
2-49
IGLOO DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-67 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 6.61 0.18 1.19 0.66 6.63 5.63 3.15 2.98 10.22 9.23
ns
ns
ns
ns
ns
ns
0.97 5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66 9.10 8.44
0.97 5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66 9.10 8.44
0.97 4.69 0.18 1.19 0.66 4.71 4.25 3.80 4.10 8.31 7.85
0.97 4.46 0.18 1.19 0.66 4.48 4.11 3.86 4.21 8.07 7.71
0.97 4.34 0.18 1.19 0.66 4.36 4.14 3.93 4.64 7.95 7.74
8 mA
12 mA
16 mA
24 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-68 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 3.92 0.18 1.19 0.66 3.94 3.10 3.16 3.17 7.54 6.70
ns
ns
ns
ns
ns
ns
0.97 3.28 0.18 1.19 0.66 3.30 2.54 3.54 3.86 6.90 6.14
0.97 3.28 0.18 1.19 0.66 3.30 2.54 3.54 3.86 6.90 6.14
0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87
0.97 2.87 0.18 1.19 0.66 2.89 2.22 3.86 4.41 6.49 5.82
0.97 2.90 0.18 1.19 0.66 2.92 2.16 3.94 4.86 6.51 5.75
8 mA
12 mA
16 mA
24 mA
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Software default selection highlighted in gray.
3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2-50
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-69 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
0.97 5.84 0.18 1.20 0.66 5.86 5.04 2.74 2.71 9.46 8.64
ns
ns
ns
ns
ns
0.97 4.76 0.18 1.20 0.66 4.78 4.33 3.09 3.33 8.37 7.93
0.97 4.76 0.18 1.20 0.66 4.78 4.33 3.09 3.33 8.37 7.93
0.97 4.02 0.18 1.20 0.66 4.04 3.78 3.33 3.73 7.64 7.37
0.97 4.02 0.18 1.20 0.66 4.04 3.78 3.33 3.73 7.64 7.37
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-70 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH
tLZ
tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
0.97 3.33 0.18 1.20 0.66 3.35 2.68 2.73 2.88 6.94 6.27
ns
ns
ns
ns
ns
0.97 2.75 0.18 1.20 0.66 2.77 2.17 3.08 3.50 6.36 5.77
0.97 2.75 0.18 1.20 0.66 2.77 2.17 3.08 3.50 6.36 5.77
0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51
0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
Revision 20
2-51
IGLOO DC and Switching Characteristics
Table 2-71 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade tDOUT
Option1
tDP
tDIN
tPY
tEOUT
0.66
0.66
0.66
0.66
tZL
tZH
tLZ
tHZ
Units
ns
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
Std.
Std.
Std.
Std.
0.97
0.97
0.97
0.97
5.64 0.18
5.64 0.18
4.63 0.18
4.63 0.18
1.17
1.17
1.17
1.17
5.65
5.65
4.64
4.64
4.98
4.98
4.26
4.26
2.45
2.45
2.80
2.80
2.42
2.42
3.02
3.02
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-72 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade tDOUT
Option1
tDP
tDIN
1.17
1.17
1.17
1.17
tPY
tEOUT
3.17
3.17
2.63
2.63
tZL
tZH
tLZ
tHZ
Units
ns
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
0.97
0.97
0.97
0.97
3.16
3.16
2.62
2.62
0.18
0.18
0.18
0.18
0.66
0.66
0.66
0.66
2.53
2.53
2.02
2.02
2.45
2.45
2.79
2.79
2.56
2.56
3.17
3.17
0.97
0.97
0.97
0.97
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
2-52
Revision 20
IGLOO Low Power Flash FPGAs
Applies to 1.2 V DC Core Voltage
Table 2-73 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 7.52 0.26 1.32 1.10 7.52 6.38 3.84 4.02 13.31 12.16
1.55 6.37 0.26 1.32 1.10 6.37 5.57 4.23 4.73 12.16 11.35
1.55 6.37 0.26 1.32 1.10 6.37 5.57 4.23 4.73 12.16 11.35
1.55 5.55 0.26 1.32 1.10 5.55 4.96 4.50 5.18 11.34 10.75
1.55 5.32 0.26 1.32 1.10 5.32 4.82 4.56 5.29 11.10 10.61
1.55 5.19 0.26 1.32 1.10 5.19 4.85 4.63 5.74 10.98 10.63
ns
ns
ns
ns
ns
ns
8 mA
12 mA
16 mA
24 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-74 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Advanced Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 4.75 0.26 1.32 1.10 4.75 3.77 3.84 4.27 10.54 9.56
ns
ns
ns
ns
ns
ns
1.55 4.10 0.26 1.32 1.10 4.10 3.19 4.24 4.98 9.88 8.98
1.55 4.10 0.26 1.32 1.10 4.10 3.19 4.24 4.98 9.88 8.98
1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69
1.55 3.67 0.26 1.32 1.10 3.67 2.85 4.57 5.55 9.46 8.64
1.55 3.70 0.26 1.32 1.10 3.70 2.79 4.65 6.01 9.49 8.58
8 mA
12 mA
16 mA
24 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
Revision 20
2-53
IGLOO DC and Switching Characteristics
Table 2-75 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Plus Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
1.55 6.69 0.26 1.32 1.10 6.69 5.73 3.41 3.72 12.48 11.52
ns
ns
ns
ns
ns
1.55 5.58 0.26 1.32 1.10 5.58 5.01 3.77 4.35 11.36 10.79
1.55 5.58 0.26 1.32 1.10 5.58 5.01 3.77 4.35 11.36 10.79
1.55 4.82 0.26 1.32 1.10 4.82 4.44 4.02 4.76 10.61 10.23
1.55 4.82 0.26 1.32 1.10 4.82 4.44 4.02 4.76 10.61 10.23
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-76 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Plus Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
6 mA
Std.
Std.
Std.
Std.
Std.
1.55 4.10 0.26 1.32 1.10 4.10 3.30 3.40 3.92 9.89 9.09
ns
ns
ns
ns
ns
1.55 3.51 0.26 1.32 1.10 3.51 2.79 3.76 4.56 9.30 8.57
1.55 3.51 0.26 1.32 1.10 3.51 2.79 3.76 4.56 9.30 8.57
1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31
1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31
8 mA
12 mA
16 mA
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
2-54
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-77 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade tDOUT
Option1
tDP
tDIN
0.26
0.26
0.26
0.26
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
Std.
Std.
Std.
Std.
1.55
1.55
1.55
1.55
6.44
6.44
5.41
5.41
1.29
1.29
1.29
1.29
6.44
6.44
5.41
5.41
5.64
5.64
4.91
4.91
2.99
2.99
3.35
3.35
3.28
3.28
3.89
3.89
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-78 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Banks
Equivalent
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade tDOUT
Option1
tDP
tDIN
0.26
0.26
0.26
0.26
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
Std.
Std.
Std.
Std.
1.55
1.55
1.55
1.55
3.89
3.89
3.33
3.33
1.29
1.29
1.29
1.29
3.89
3.89
3.33
3.33
3.13
3.13
2.62
2.62
2.99
2.99
3.34
3.34
3.45
3.45
4.07
4.07
ns
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
Revision 20
2-55
IGLOO DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-79 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSH
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
16
16
18
18
4 mA
6 mA
32
37
8 mA
32
37
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
65
74
83
87
169
124
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-80 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSH
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
16
16
32
32
65
18
18
37
37
74
12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-56
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-81 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSH
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
2
4
6
8
2
16
16
32
32
18
18
37
37
4
6
8
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
R to GND for tHZ / tZH / tZHS
Test Point
Datapath
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Revision 20
2-57
IGLOO DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-83 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 4.96 0.18 1.08 0.66 5.06 4.59 2.26 2.00 8.66 8.19
0.97 4.15 0.18 1.08 0.66 4.24 3.94 2.54 2.51 7.83 7.53
0.97 4.15 0.18 1.08 0.66 4.24 3.94 2.54 2.51 7.83 7.53
0.97 3.57 0.18 1.08 0.66 3.65 3.47 2.73 2.84 7.24 7.06
0.97 3.39 0.18 1.08 0.66 3.46 3.36 2.78 2.92 7.06 6.95
0.97 3.38 0.18 1.08 0.66 3.38 3.38 2.83 3.25 6.98 6.98
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-84 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 2.77 0.18 1.08 0.66 2.83 2.60 2.26 2.08 6.42 6.19
0.97 2.34 0.18 1.08 0.66 2.39 2.08 2.54 2.60 5.99 5.68
0.97 2.34 0.18 1.08 0.66 2.39 2.08 2.54 2.60 5.99 5.68
0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43
0.97 2.05 0.18 1.08 0.66 2.09 1.78 2.78 3.02 5.69 5.38
0.97 2.06 0.18 1.08 0.66 2.10 1.72 2.83 3.35 5.70 5.32
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-85 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
0.97 4.42 0.18 1.08 0.66 4.51 4.10 1.96 1.85 8.10 7.69
0.97 3.62 0.18 1.08 0.66 3.70 3.52 2.21 2.32 7.29 7.11
0.97 3.62 0.18 1.08 0.66 3.70 3.52 2.21 2.32 7.29 7.11
0.97 3.09 0.18 1.08 0.66 3.15 3.09 2.39 2.61 6.74 6.68
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-58
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-86 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
0.97 2.36 0.18 1.08 0.66 2.41 2.21 1.96 1.92 6.01 5.81
0.97 1.97 0.18 1.08 0.66 2.01 1.75 2.21 2.40 5.61 5.34
0.97 1.97 0.18 1.08 0.66 2.01 1.75 2.21 2.40 5.61 5.34
0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-87 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
0.97
0.97
0.97
0.97
tDP
tDIN
tPY
tEOUT
0.66
0.66
0.66
0.66
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
4.27 0.18 1.04
4.27 0.18 1.04
3.54 0.18 1.04
3.54 0.18 1.04
4.36 4.06 1.71 1.62
4.36 4.06 1.71 1.62
3.61 3.48 1.95 2.08
3.61 3.48 1.95 2.08
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-88 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
0.97
0.97
0.97
0.97
tDP
tDIN
tPY
tEOUT
0.66
0.66
0.66
0.66
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
2.24 0.18 1.04
2.24 0.18 1.04
1.88 0.18 1.04
1.88 0.18 1.04
2.29 2.09 1.71 1.68
2.29 2.09 1.71 1.68
1.92 1.63 1.95 2.15
1.92 1.63 1.95 2.15
4 mA
ns
6 mA
ns
8 mA
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-59
IGLOO DC and Switching Characteristics
Applies to 1.2 V Core Voltage
Table 2-89 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 5.59 0.26 1.20 1.10 5.68 5.14 2.82 2.80 11.47 10.93
1.55 4.76 0.26 1.20 1.10 4.84 4.47 3.10 3.33 10.62 10.26
1.55 4.76 0.26 1.20 1.10 4.84 4.47 3.10 3.33 10.62 10.26
1.55 4.17 0.26 1.20 1.10 4.23 3.99 3.30 3.67 10.02 9.77
1.55 3.98 0.26 1.20 1.10 4.04 3.88 3.34 3.76 9.83 9.66
1.55 3.90 0.26 1.20 1.10 3.96 3.90 3.40 4.09 9.75 9.68
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-90 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 3.33 0.26 1.20 1.10 3.38 3.09 2.82 2.91 9.17 8.88
1.55 2.89 0.26 1.20 1.10 2.93 2.56 3.10 3.45 8.72 8.34
1.55 2.89 0.26 1.20 1.10 2.93 2.56 3.10 3.45 8.72 8.34
1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08
1.55 2.59 0.26 1.20 1.10 2.63 2.24 3.34 3.88 8.41 8.03
1.55 2.60 0.26 1.20 1.10 2.64 2.18 3.40 4.22 8.42 7.97
ns
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-91 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
1.55 5.02 0.26 1.19 1.10 5.11 4.60 2.50 2.62 10.89 10.38
1.55 4.21 0.26 1.19 1.10 4.27 4.00 2.76 3.10 10.06 9.79
1.55 4.21 0.26 1.19 1.10 4.27 4.00 2.76 3.10 10.06 9.79
1.55 3.66 0.26 1.19 1.10 3.71 3.55 2.94 3.41 9.50 9.34
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-60
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-92 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
1.55 2.91 0.26 1.19 1.10 2.95 2.66 2.50 2.72 8.74 8.45
1.55 2.51 0.26 1.19 1.10 2.54 2.18 2.75 3.21 8.33 7.97
1.55 2.51 0.26 1.19 1.10 2.54 2.18 2.75 3.21 8.33 7.97
1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-93 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
1.55
1.55
1.55
1.55
tDP
tDIN
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
4.85 0.26 1.15
4.85 0.26 1.15
4.09 0.26 1.15
4.09 0.26 1.15
4.93 4.55 2.13 2.24
4.93 4.55 2.13 2.24
4.16 3.95 2.38 2.71
4.16 3.95 2.38 2.71
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-94 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
1.55
1.55
1.55
1.55
tDP
tDIN
tPY
tEOUT
1.10
1.10
1.10
1.10
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
Std.
Std.
2.76 0.26 1.15
2.76 0.26 1.15
2.39 0.26 1.15
2.39 0.26 1.15
2.80 2.52 2.13 2.32
2.80 2.52 2.13 2.32
2.42 2.05 2.38 2.80
2.42 2.05 2.38 2.80
4 mA
ns
6 mA
ns
8 mA
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-61
IGLOO DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-95 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSH
Max.
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
V
mA mA
mA3
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
1.9
1.9
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
9
11
22
44
51
74
74
4 mA
17
35
45
91
91
6 mA
6
8 mA
8
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-96 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH
mA mA
IOSH
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
Max.
mA3
V
µA4 µA4
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
2
4
9
11
22
44
44
17
35
35
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
6
6
8
8
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-62
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-97 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSH
Max.
IOSL
IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
V
mA mA
mA3
µA4 µA4
10 10
10 10
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
2
4
9
11
22
17
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
R to GND for tHZ / tZH / tZHS
Test Point
Datapath
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-99 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 6.38 0.18 1.01 0.66 6.51 5.93 2.33 1.56 10.10 9.53
0.97 5.35 0.18 1.01 0.66 5.46 5.04 2.67 2.38 9.05 8.64
0.97 4.62 0.18 1.01 0.66 4.71 4.44 2.90 2.79 8.31 8.04
0.97 4.37 0.18 1.01 0.66 4.46 4.31 2.95 2.89 8.05 7.90
0.97 4.32 0.18 1.01 0.66 4.37 4.32 3.03 3.30 7.97 7.92
0.97 4.32 0.18 1.01 0.66 4.37 4.32 3.03 3.30 7.97 7.92
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-63
IGLOO DC and Switching Characteristics
Table 2-100 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
Std.
Std.
Std.
Std.
Std.
Std.
0.97 3.25 0.18 1.01 0.66 3.21 3.25 2.33 1.61 6.80 6.85
0.97 2.62 0.18 1.01 0.66 2.68 2.51 2.66 2.46 6.27 6.11
0.97 2.31 0.18 1.01 0.66 2.36 2.15 2.90 2.87 5.95 5.75
0.97 2.25 0.18 1.01 0.66 2.30 2.08 2.95 2.98 5.89 5.68
0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60
0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60
ns
ns
ns
ns
ns
ns
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-101 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
Std.
Std.
Std.
Std.
0.97 5.78 0.18 1.01 0.66 5.90 5.32 1.95 1.47 9.49 8.91
0.97 4.75 0.18 1.01 0.66 4.85 4.54 2.25 2.21 8.44 8.13
0.97 4.07 0.18 1.01 0.66 4.15 3.98 2.46 2.58 7.75 7.57
0.97 4.07 0.18 1.01 0.66 4.15 3.98 2.46 2.58 7.75 7.57
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-102 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
Std.
Std.
Std.
0.97 2.76 0.18 1.01 0.66 2.79 2.76 1.94 1.51 6.39 6.35
0.97 2.25 0.18 1.01 0.66 2.30 2.09 2.24 2.29 5.89 5.69
0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36
0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-103 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
0.97
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
5.63 0.18 0.98 0.66
4.69 0.18 0.98 0.66
5.74
4.79
5.30 1.68 1.24
4.52 1.97 1.98
4 mA
0.97
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-64
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-104 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
2.62
tDP
tDIN
tPY
tEOUT
2.67
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
0.18 0.98 0.66
0.18 0.98 0.66
2.59 1.67 1.29 2.62
1.93 1.97 2.06 2.18
4 mA
2.18
2.22
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-65
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-105 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 6.97 0.26 1.11 1.10 7.08 6.48 2.87 2.29 12.87 12.27
1.55 5.91 0.26 1.11 1.10 6.01 5.57 3.21 3.14 11.79 11.36
1.55 5.16 0.26 1.11 1.10 5.24 4.95 3.45 3.55 11.03 10.74
1.55 4.90 0.26 1.11 1.10 4.98 4.81 3.50 3.66 10.77 10.60
1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.58 4.08 10.68 10.61
1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.58 4.08 10.68 10.61
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-106 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
Std.
Std.
Std.
Std.
Std.
Std.
1.55 3.73 0.26 1.11 1.10 3.71 3.73 2.86 2.34 9.49 9.51
1.55 3.12 0.26 1.11 1.10 3.16 2.97 3.21 3.22 8.95 8.75
1.55 2.79 0.26 1.11 1.10 2.83 2.59 3.45 3.65 8.62 8.38
1.55 2.73 0.26 1.11 1.10 2.77 2.52 3.50 3.75 8.56 8.30
1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22
1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22
ns
ns
ns
ns
ns
ns
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-107 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
Std.
Std.
Std.
Std.
1.55 6.32 0.26 1.11 1.10 6.43 5.81 2.47 2.16 12.22 11.60
1.55 5.27 0.26 1.11 1.10 5.35 5.01 2.78 2.92 11.14 10.79
1.55 4.56 0.26 1.11 1.10 4.64 4.44 3.00 3.30 10.42 10.22
1.55 4.56 0.26 1.11 1.10 4.64 4.44 3.00 3.30 10.42 10.22
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-66
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-108 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
Std.
Std.
Std.
1.55 3.22 0.26 1.11 1.10 3.26 3.18 2.47 2.20 9.05 8.97
1.55 2.72 0.26 1.11 1.10 2.75 2.50 2.78 3.01 8.54 8.29
1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94
1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-109 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
1.55
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
6.13 0.26 1.08 1.10
5.17 0.26 1.08 1.10
6.24
5.26
5.79 2.08 1.78
4.98 2.38 2.54
4 mA
1.55
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-110 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
3.06
tDP
tDIN
tPY
tEOUT
3.10
tZL
tZH
tLZ
tHZ
Units
ns
Std.
Std.
0.26 1.08 1.10
0.26 1.08 1.10
3.01 2.08 1.83 3.06
2.33 2.38 2.62 2.60
4 mA
2.60
2.64
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-67
IGLOO DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-111 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
V
V
mA mA mA3 mA3 µA4 µA4
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
2
4
13
25
32
66
66
16
33
39
55
55
10 10
10 10
10 10
10 10
10 10
6
6
8
8
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-112 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Max. Max.
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA mA mA3
mA3 µA4 µA4
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
2
4
13
25
16
33
10 10
10 10
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-68
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-113 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA3
mA3 µA4 µA4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
2
13
16
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
R to GND for tHZ / tZH / tZHS
Test Point
Datapath
Test Point
5 pF
Enable Path
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Revision 20
2-69
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-115 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
Std.
0.97 6.62 0.18 1.17 0.66 6.75 6.06 2.79 2.31 10.35 9.66
0.97 5.75 0.18 1.17 0.66 5.86 5.34 3.06 2.78 9.46 8.93
0.97 5.43 0.18 1.17 0.66 5.54 5.19 3.12 2.90 9.13 8.78
0.97 5.35 0.18 1.17 0.66 5.46 5.20 2.63 3.36 9.06 8.79
0.97 5.35 0.18 1.17 0.66 5.46 5.20 2.63 3.36 9.06 8.79
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-116 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
Std.
0.97 2.97 0.18 1.17 0.66 3.04 2.90 2.78 2.40 6.63 6.50
0.97 2.60 0.18 1.17 0.66 2.65 2.45 3.05 2.88 6.25 6.05
0.97 2.53 0.18 1.17 0.66 2.58 2.37 3.11 3.00 6.18 5.96
0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86
0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-117 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
Std.
Std.
0.97 5.93 0.18 1.18 0.66 6.04 5.46 2.30 2.15 9.64 9.06
0.97 5.11 0.18 1.18 0.66 5.21 4.80 2.54 2.58 8.80 8.39
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-118 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus Banks
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH
tLZ
tHZ tZLS tZHS Units
Std.
Std.
0.97 2.58 0.18 1.18 0.66 2.64 2.41 2.29 2.24 6.23 6.01
0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59
ns
ns
4 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-70
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-119 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
5.88 0.18 1.14
0.66
6.00 5.45 2.00 1.94
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-120 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.97
2.51 0.18 1.14
0.66
2.56 2.21 1.99 2.03
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-71
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-121 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
Std.
Std.
Std.
Std.
1.55 7.17 0.26 1.27 1.10 7.29 6.60 3.33 3.03 13.07 12.39
1.55 6.27 0.26 1.27 1.10 6.37 5.86 3.61 3.51 12.16 11.64
1.55 5.94 0.26 1.27 1.10 6.04 5.70 3.67 3.64 11.82 11.48
1.55 5.86 0.26 1.27 1.10 5.96 5.71 2.83 4.11 11.74 11.50
1.55 5.86 0.26 1.27 1.10 5.96 5.71 2.83 4.11 11.74 11.50
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-122 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
Std.
Std.
Std.
Std.
1.55 3.44 0.26 1.27 1.10 3.49 3.35 3.32 3.12 9.28 9.14
1.55 3.06 0.26 1.27 1.10 3.10 2.89 3.60 3.61 8.89 8.67
1.55 2.98 0.26 1.27 1.10 3.02 2.80 3.66 3.74 8.81 8.58
1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48
1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-123 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
Std.
Std.
1.55 6.43 0.26 1.27 1.10 6.54 5.95 2.82 2.83 12.32 11.74
1.55 5.59 0.26 1.27 1.10 5.68 5.27 3.07 3.27 11.47 11.05
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-124 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
4 mA
Notes:
Std.
Std.
1.55 3.02 0.26 1.27 1.10 3.07 2.81 2.82 2.92 8.85 8.59
1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-72
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-125 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
6.35 0.26 1.22
1.10
6.46 5.93 2.40 2.46
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-126 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Banks
Drive Strength
2 mA
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
1.55
2.92 0.26 1.22
1.10
2.96 2.60 2.40 2.56
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-73
IGLOO DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer. Furthermore, all LVCMOS 1.2 V
software macros comply with LVCMOS 1.2 V wide range as specified in the JESD8-12A
specification.
Table 2-127 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.2 V
LVCMOS
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
V
mA mA mA3
mA3 µA4 µA4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
20
26
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-128 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.2 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA3
mA3 µA4 µA4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
20
26
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-129 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.2 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSH IOSL IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA3
mA3 µA4 µA4
1 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
1
1
20
26
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-74
Revision 20
IGLOO Low Power Flash FPGAs
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
5 pF
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-11 • AC Loading
Table 2-130 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
1.2 V DC Core Voltage
Table 2-131 • 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
ns
2 mA Std. 1.55 8.37 0.26 1.60 1.10 8.04 7.17 3.94 3.52 13.82 12.95
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-132 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ
tZLS
tZHS Units
9.14 ns
2 mA
Std.
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-133 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
ns
2 mA Std. 1.55 7.59 0.26 1.59 1.10 7.29 6.54 3.30 3.35 13.08 12.33
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-134 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA
Std.
1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-75
IGLOO DC and Switching Characteristics
Table 2-135 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
1 mA
Std.
1.55
8.57 0.26 1.53
1.10
8.23 7.38 2.51 2.39
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-136 • 1.2 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Banks
Drive Strength
1 mA
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
1.55
3.59 0.26 1.53
1.10
3.47 3.06 2.51 2.49
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
1.2 V LVCMOS Wide Range
Table 2-137 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range
Applicable to Advanced I/O Banks
1.2 V LVCMOS
Wide Range
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL2 IIH3
Equivalent
Software
Default
Drive
Drive
Strength Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
Strength Option1
V
mA mA mA4 mA4 µA5 µA5
100 µA
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20
26
10 10
Notes:
1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.
The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS
models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
2-76
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-138 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range
Applicable to Standard Plus I/O Banks
1.2 V LVCMOS
Wide Range
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL2 IIH3
Equivalent
Software
Default
Drive
Drive
Strength Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
Strength Option1
V
mA mA mA4 mA4 µA5 µA5
100 µA
2mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 100 100 20
26 10 10
Notes:
1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.
The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS
models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-139 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range
Applicable to Standard I/O Banks
1.2 V LVCMOS
Wide Range
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL2 IIH3
Equivalent
Software
Default
Drive
Drive
Strength Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
Strength Option1
V
mA mA mA4 mA4 µA5 µA5
100 µA
1 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20
26
10 10
Notes:
1. The minimum drive strength for the default LVCMOS 1.2 V software configuration when run in wide range is ± 100 µA.
The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS
models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-140 • 1.2 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-75 for worst-case timing.
Revision 20
2-77
IGLOO DC and Switching Characteristics
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
Table 2-141 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced and Standard Plus I/Os
3.3 V PCI/PCI-X
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSH
IOSL
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
Drive Strength
V
mA mA
µA2 µA2
Per PCI
Per PCI curves
10 10
specification
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-12.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-12 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
described in Table 2-142.
Table 2-142 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
10
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-143 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS tZHS
Units
Std.
0.97
2.32 0.19 0.70
0.66
2.37 1.78 2.67 3.05 5.96 5.38
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-144 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS tZHS
Units
Std.
0.97
1.97 0.19 0.70
0.66
2.01 1.50 2.36 2.79 5.61 5.10
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-78
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-145 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS tZHS
Units
Std.
1.55
2.91 0.25 0.86
1.10
2.95 2.29 3.25 3.93 8.74 8.08
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-146 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS tZHS
Units
Std.
1.55
2.53 0.25 0.85
1.10
2.57 1.98 2.93 3.64 8.35 7.76
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
N
P
N
165 Ω
165 Ω
Z0 = 50 Ω
140 Ω
Z0 = 50 Ω
INBUF_LVDS
+
–
100 Ω
Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation
Revision 20
2-79
IGLOO DC and Switching Characteristics
Table 2-147 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Min.
2.375
0.9
Typ.
2.5
Max.
2.625
1.25
1.6
Units
V
Supply Voltage
VOL
Output Low Voltage
1.075
1.425
0.91
0.91
V
VOH
Output High Voltage
1.25
0.65
0.65
0
V
IOL1
Output Lower Current
Output High Current
1.16
1.16
2.925
10
mA
mA
V
IOH1
VI
Input Voltage
IIH2
Input High Leakage Current
Input Low Leakage Current
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
µA
µA
mV
V
IIL2
10
VODIFF
VOCM
VICM
VIDIFF4
Notes:
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
V
mV
1. IOL/IOH is defined by VODIFF/(resistor network)
2. Currents are measured at 85°C junction temperature.
Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.075
1.325
Cross point
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-149 • LVDS – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.97
1.67
0.19
1.31
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7 on
page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-150 • LVDS – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
1.55
2.19
0.25
1.52
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 and Table 2-7 on
page 2-7 for derating values.
2-80
Revision 20
IGLOO Low Power Flash FPGAs
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in Figure 2-14. The input and output buffer delays are available in
the LVDS section in Table 2-149 on page 2-80 and Table 2-150 on page 2-80.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and
RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-15. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
N
OUTBUF_LVPECL
100 Ω
100 Ω
Z = 50 Ω
0
INBUF_LVPECL
+
–
187 W
Z = 50 Ω
100 Ω
0
N
Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-151 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Output Low Voltage
Min.
Max.
Min.
Max.
3.3
Min.
Max. Units
3.0
3.6
V
VOL
0.96
1.27
1.06
1.43
1.30
1.57
V
Revision 20
2-81
IGLOO DC and Switching Characteristics
Table 2-151 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VOH
Description
Output High Voltage
Min.
1.8
0
Max.
2.11
3.3
Min.
1.92
0
Max.
2.28
3.6
Min.
2.13
0
Max. Units
2.41
3.9
V
V
VIL, VIH
VODIFF
VOCM
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
0.625 0.97 0.625 0.97 0.625 0.97
1.762 1.98 1.762 1.98 1.762 1.98
V
V
VICM
1.01
300
2.57
1.01
300
2.57
1.01
300
2.57
V
VIDIFF
mV
Table 2-152 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.64
1.94
Cross point
Note: *Measuring point = Vtrip. See Table 2-28 on page 2-102 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-153 • LVPECL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.97
1.67
0.19
1.16
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-154 • LVPECL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
1.55
2.24
0.25
1.37
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-82
Revision 20
IGLOO Low Power Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
DFN1E1P1
DFN1E1P1
G
E
E
EOUT
B
A
H
I
PRE
J
D
Q
DFN1E1P1
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
CLKBUF
INBUF
INBUF
Postive-Edge Triggered
Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Revision 20
2-83
IGLOO DC and Switching Characteristics
Table 2-155 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
G, H
tOHE
G, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
J, H
tOESUE
tOEHE
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
K, H
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 2-16 on page 2-83 for more information.
2-84
Revision 20
IGLOO Low Power Flash FPGAs
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
AA
DD
CLR
LL
HH
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Revision 20
2-85
IGLOO DC and Switching Characteristics
Table 2-156 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
II, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-17 on page 2-85 for more information.
2-86
Revision 20
IGLOO Low Power Flash FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
Data
tIHD
50%
50%
1
0
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-18 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-157 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Std. Units
Clock-to-Q of the Input Data Register
0.42
0.47
0.00
0.67
0.00
0.79
0.79
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-87
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-158 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
Std. Units
0.68
0.97
0.00
1.02
0.00
1.19
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
1
CLK
tOSUD tOHD
50%
50%
0
Data_out
tOREMPRE
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOHE
50%
50%
tOSUE
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-19 • Output Register Timing Diagram
2-88
Revision 20
IGLOO Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-159 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Std. Units
Clock-to-Q of the Output Data Register
1.00
0.51
0.00
0.70
0.00
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
tOCKMPWH
tOCKMPWL
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-160 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
Std. Units
1.52
1.15
0.00
1.11
0.00
1.96
1.96
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
tOCKMPWH
tOCKMPWL
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-89
IGLOO DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD OEHD
t
50% 50%
1
0
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
50%
tOERECPRE
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
EOUT
Figure 2-20 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-161 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
Std. Units
Clock-to-Q of the Output Enable Register
0.75
0.51
0.00
0.73
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOESUE
Enable Setup Time for the Output Enable Register
tOEHE
Enable Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-90
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-162 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOECLKQ
tOESUD
Description
Clock-to-Q of the Output Enable Register
Std. Units
1.10
1.15
0.00
1.22
0.00
1.65
1.65
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOESUE
Enable Setup Time for the Output Enable Register
tOEHE
Enable Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-91
IGLOO DC and Switching Characteristics
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-21 • Input DDR Timing Model
Table 2-163 • Parameter Definitions
Parameter Name
Parameter Definition
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Measuring Nodes (from, to)
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
2-92
Revision 20
IGLOO Low Power Flash FPGAs
CLK
tDDRISUD
6
tDDRIHD
Data
CLR
1
2
3
4
5
7
8
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
7
2
4
tDDRICLKQ2
tDDRICLR2Q2
3
5
Figure 2-22 • Input DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-164 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Description
Std.
0.48
0.65
0.50
0.40
0.00
0.00
0.82
0.98
0.00
0.23
0.19
0.31
0.28
250.00
Units
Clock-to-Out Out_QR for Input DDR
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-93
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-165 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out Out_QR for Input DDR
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Std.
0.76
0.94
0.93
0.84
0.00
0.00
1.23
1.42
0.00
0.24
0.19
0.31
0.28
160.00
Units
ns
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR (negedge)
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-94
Revision 20
IGLOO Low Power Flash FPGAs
Output DDR Module
Output DDR
A
B
Data_F
(from core)
X
X
FF1
Out
0
1
CLK
E
X
CLKBUF
C
X
OUTBUF
D
Data_R
(from core)
X
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-23 • Output DDR Timing Model
Table 2-166 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Clock-to-Out
Measuring Nodes (from, to)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
Revision 20
2-95
IGLOO DC and Switching Characteristics
CLK
t
t
DDROHD2
DDROSUD2
4
9
5
Data_F
1
2
3
t
t
DDROHD1
DDROREMCLR
Data_R 6
CLR
7
8
10
11
t
DDRORECCLR
t
DDROREMCLR
t
t
DDROCLKQ
DDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-24 • Output DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-167 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
Std.
1.07
0.67
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.31
0.28
250.00
Units
ns
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-96
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-168 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Std.
1.60
1.09
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
160.00
Units
ns
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-97
IGLOO DC and Switching Characteristics
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion,
and ProASIC3 Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-25 • Sample of Combinatorial Cells
2-98
Revision 20
IGLOO Low Power Flash FPGAs
tPD
Fanout = 4
A
B
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
tPD = MAX(tPD(RR), tPD(RF),
tPD(FF), tPD(FR)) where edges are
applicable for a particular
combinatorial cell
A
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
Y
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
VCC
50%
50%
VCC
A, B, C
GND
50%
50%
OUT
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-26 • Timing Model and Waveforms
Revision 20
2-99
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-169 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y =!A
Parameter
tPD
Std.
0.80
0.84
0.90
1.19
1.10
1.37
1.33
1.79
1.48
1.21
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y =!(A · B)
tPD
ns
Y = A + B
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-170 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
1.34
1.43
1.59
2.30
2.07
2.46
2.46
3.12
2.83
2.28
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2-100
Revision 20
IGLOO Low Power Flash FPGAs
VersaTile Specifications as a Sequential Module
The IGLOO library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3
Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-27 • Sample of Sequential Cells
Revision 20
2-101
IGLOO DC and Switching Characteristics
tCKMPWH CKMPWL
t
50%
50%
50%
50%
50%
50%
50%
CLK
tHD
tSUD
50%
Data
50%
0
EN
50%
tRECPRE
50%
tWPRE
tREMPRE
50%
tHE
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-28 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-171 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-102
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-172 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
1.61
1.17
0.00
1.29
0.00
0.87
0.89
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-103
IGLOO DC and Switching Characteristics
Global Resource Characteristics
AGL250 Clock Tree Topology
Clock delays are device-specific. Figure 2-29 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-29 is driven by a CCC located on the west side of the AGL250 device. It
is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-29 • Example of Global Tree Use in an AGL250 Device for Clock Routing
2-104
Revision 20
IGLOO Low Power Flash FPGAs
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-113. Table 2-173 to Table 2-188 on page 2-112
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-173 • AGL015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.21
1.23
1.18
1.15
Units
ns
1.42
1.49
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.27
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-174 • AGL030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.21
1.23
1.18
1.15
Max.2
Units
ns
1.42
tRCKH
Input High Delay for Global Clock
1.49
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.27
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-105
IGLOO DC and Switching Characteristics
Table 2-175 • AGL060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.33
1.35
1.18
1.15
Units
ns
1.55
1.62
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.27
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-176 • AGL125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.36
1.39
1.18
1.15
Max.2
Units
ns
1.71
tRCKH
Input High Delay for Global Clock
1.82
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-106
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-177 • AGL250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.39
1.41
1.18
1.15
Max.2
Units
ns
1.73
tRCKH
Input High Delay for Global Clock
1.84
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-178 • AGL400 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min. 1
1.45
1.48
1.18
1.15
Max. 2
Units
ns
1.79
tRCKH
Input High Delay for Global Clock
1.91
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-107
IGLOO DC and Switching Characteristics
Table 2-179 • AGL600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.48
1.52
1.18
1.15
Units
ns
1.82
1.94
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-180 • AGL1000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.55
1.60
1.18
1.15
Max.2
Units
ns
1.89
tRCKH
Input High Delay for Global Clock
2.02
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.42
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-108
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-181 • AGL015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.79
1.87
1.40
1.65
Max.2
Units
ns
2.09
tRCKH
Input High Delay for Global Clock
2.26
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.39
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-182 • AGL030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
1.80
1.88
1.40
1.65
Max.2
Units
ns
2.09
tRCKH
Input High Delay for Global Clock
2.27
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.39
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-109
IGLOO DC and Switching Characteristics
Table 2-183 • AGL060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.04
2.10
1.40
1.65
Units
ns
2.33
2.51
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.40
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-184 • AGL125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.08
2.15
1.40
1.65
Max.2
Units
ns
2.54
tRCKH
Input High Delay for Global Clock
2.77
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-110
Revision 20
IGLOO Low Power Flash FPGAs
Table 2-185 • AGL250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.11
2.19
1.40
1.65
Max.2
Units
ns
2.57
tRCKH
Input High Delay for Global Clock
2.81
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-186 • AGL400 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.18
2.27
1.40
1.65
Max.2
Units
ns
2.64
tRCKH
Input High Delay for Global Clock
2.89
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-111
IGLOO DC and Switching Characteristics
Table 2-187 • AGL600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.22
2.32
1.40
1.65
Units
ns
2.67
2.93
tRCKH
Input High Delay for Global Clock
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-188 • AGL1000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1
2.31
2.42
1.40
1.65
Max.2
Units
ns
2.76
tRCKH
Input High Delay for Global Clock
3.03
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
ns
0.61
ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-112
Revision 20
IGLOO Low Power Flash FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-189 • IGLOO CCC/PLL Specification
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL4,5
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
0.75
250
3603
32
100
1
ns
ns
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter5
LockControl = 0
2.5
1.5
ns
ns
%
LockControl = 1
Output Duty Cycle
48.5
1.25
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1,2
Delay Range in Block: Programmable Delay 2 1,2
Delay Range in Block: Fixed Delay 1, 2
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
ns
ns
ns
0.469
3.5
Maximum Peak-to-Peak Jitter Data7.8
SSO ≥ 4 SSO ≥ 8 SSO ≥ 16
0.75 MHz to 50 MHz
50 MHz to 160 MHz
Notes:
0.60%
4.00%
0.80%
6.00%
1.20%
12.00%
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, V = 1.5 V
J
CC
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. The AGL030 device does not support a PLL.
5. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
7. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength, and high slew Rate. VCC/VCCPLL = 1.14 V, VQ/PQ/TQ
type of packages, 20 pF load.
8. Switching I/Os are placed outside of the PLL bank.
Revision 20
2-113
IGLOO DC and Switching Characteristics
Table 2-190 • IGLOO CCC/PLL Specification
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
160
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL4,5
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
0.75
160
5803
32
60
ns
ns
0.25
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter6
LockControl = 0
4
ns
ns
%
LockControl = 1
3
Output Duty Cycle
48.5
2.3
51.5
20.86
20.86
Delay Range in Block: Programmable Delay 11,2
Delay Range in Block: Programmable Delay 21,2
Delay Range in Block: Fixed Delay 1, 2, 5
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
ns
ns
ns
0.863
5.7
Maximum Peak-to-Peak Jitter Data7,8
SSO ≥ 4 SSO ≥ 8 SSO ≥ 16
0.75 MHz to 50 MHz
50 MHz to 160 MHz
Notes:
1.20%
5.00%
2.00%
7.00%
3.00%
15.00%
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 and Table 2-7 on page 2-7 for deratings.
2. T = 25°C, V = 1.2 V
J
CC
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
5. The AGL030 device does not support a PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V, VQ/PQ/TQ
type of packages, 20 pF load.
8. Switching I/Os are placed outside of the PLL bank.
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-30 • Peak-to-Peak Jitter Definition
2-114
Revision 20
IGLOO Low Power Flash FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-31 • RAM Models
Revision 20
2-115
IGLOO DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
tBKS
A1
A2
[R|W]ADDR
BLK
tBKH
tENS
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-32 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-33 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
2-116
Revision 20
IGLOO Low Power Flash FPGAs
t
CYC
t
t
CKL
CKH
CLK
t
t
AH
AS
A
A
A
[R|W]ADDR
BLK
0
1
2
t
t
BKS
ENS
t
BKH
t
ENH
WEN
t
t
DH
DS
DI
DI
DIN|WD
DOUT|RD
0
1
D
D
n
2
Figure 2-34 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
t
CYC
t
t
CKH
CKL
CLK
[R|W]ADDR
BLK
t
t
AH
AS
A
A
A
2
0
1
t
t
BKS
t
BKH
ENS
WEN
t
t
DH
DS
DI
DI
DI
2
DIN
0
1
DOUT
D
DI
DI
1
n
0
(pass-through)
DOUT
DI
D
DI
1
0
n
(pipelined)
Figure 2-35 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only.
Revision 20
2-117
IGLOO DC and Switching Characteristics
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
Dm
Dn
DOUT|RD
Figure 2-36 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
2-118
Revision 20
IGLOO Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-191 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Address setup time
Std. Units
0.83 ns
0.16 ns
0.81 ns
0.16 ns
1.65 ns
0.16 ns
0.71 ns
0.36 ns
3.53 ns
3.06 ns
1.81 ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address – Applicable 0.23 ns
to Closing Edge
1
tC2CRWL
Address collision clk-to-clk delay for reliable read access after write on same address – 0.35 ns
Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 0.41 ns
Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
2.06 ns
2.06 ns
0.61 ns
3.21 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-119
IGLOO DC and Switching Characteristics
Table 2-192 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std. Units
0.83 ns
0.16 ns
0.73 ns
0.08 ns
0.71 ns
0.36 ns
4.21 ns
1.71 ns
Address setup time
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address - 0.35 ns
Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address - 0.42 ns
Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on RD (flow-through)
RESET Low to data out Low on RD (pipelined)
2.06 ns
2.06 ns
0.61 ns
3.21 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
tCYC
Clock cycle time
FMAX
Notes:
Maximum frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-120
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-193 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Address setup time
Std. Units
1.53
0.29
1.50
0.29
3.05
0.29
1.33
0.66
6.61
5.72
3.38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address – 0.30
Applicable to Closing Edge
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address – 0.89
Applicable to Opening Edge
ns
ns
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 1.01
Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
ns
ns
ns
tCYC
Clock cycle time
ns
FMAX
Notes:
Maximum frequency
MHz
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-121
IGLOO DC and Switching Characteristics
Table 2-194 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std. Units
Address setup time
1.53
0.29
1.36
0.15
1.33
0.66
7.88
3.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address – 0.87
Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address – 1.04
Applicable to Opening Edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow through)
RESET Low to data out Low on RD (pipelined)
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB RESET removal
tRECRSTB RESET recovery
tMPWRSTB RESET minimum pulse width
ns
ns
ns
tCYC
Clock cycle time
ns
FMAX
Notes:
Maximum frequency
MHz
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-122
Revision 20
IGLOO Low Power Flash FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-37 • FIFO Model
Revision 20
2-123
IGLOO DC and Switching Characteristics
Timing Waveforms
RCLK/
WCLK
t
t
RSTCK
MPWRSTB
RESET
t
RSTFG
EMPTY
AEMPTY
FULL
t
RSTAF
t
RSTFG
t
RSTAF
AFULL
WA/RA
MATCH (A )
(Address Counter)
0
Figure 2-38 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
t
CKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion
2-124
Revision 20
IGLOO Low Power Flash FPGAs
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion
Revision 20
2-125
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-195 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
Std.
1.99
0.16
0.30
0.00
0.76
0.25
3.33
1.80
3.53
3.35
12.85
3.48
12.72
2.02
2.02
0.61
3.21
0.68
6.24
160
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
Input Data (WD) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
ns
ns
ns
WCLK High to Full Flag Valid
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-126
Revision 20
IGLOO Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-196 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
Std.
4.13
0.31
0.47
0.00
1.56
0.49
6.80
3.62
7.23
6.85
26.61
7.12
26.33
4.09
4.09
1.23
6.58
1.18
10.90
92
Units
ns
REN, WEN Setup Time
tENH
REN, WEN Hold Time
ns
tBKS
BLK Setup Time
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Revision 20
2-127
IGLOO DC and Switching Characteristics
Embedded FlashROM Characteristics
t
t
t
SU
SU
SU
CLK
t
t
t
HOLD
HOLD
HOLD
Address
A
A
1
0
t
t
t
CKQ2
CKQ2
CKQ2
D
D
D
Data
0
0
1
Figure 2-43 • Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-197 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
Std.
0.57
0.00
Units
ns
tHOLD
tCK2Q
Address Hold Time
ns
Clock to Out
34.14
15
ns
FMAX
Maximum Clock Frequency
MHz
1.2 V DC Core Voltage
Table 2-198 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tSU
Description
Std.
0.59
0.00
52.90
10
Units
ns
Address Setup Time
Address Hold Time
Clock to Out
tHOLD
tCK2Q
ns
ns
FMAX
Maximum Clock Frequency
MHz
2-128
Revision 20
IGLOO Low Power Flash FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-20 for more details.
Timing Characteristics
Table 2-199 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Std.
1.00
2.00
1.00
2.00
8.00
25.00
15
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
tDIHD
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
0.58
0.00
TBD
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-200 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDISU
Description
Test Data Input Setup Time
Std.
1.50
3.00
1.50
3.00
11.00
30.00
9.00
1.18
0.00
TBD
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 20
2-129
3 – Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for IGLOO V5 devices, and 1.2 V or 1.5 V for IGLOO
V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a
device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain
powered to allow JTAG signals to pass through the device.
For IGLOO V2 devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows
in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is
at 1.2 V.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on IGLOO devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI
connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V,
or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI
domain. This minimizes the noise transfer within the package and improves input signal integrity. Each
bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank
run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each
I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have
their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given
I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e.,
VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V.
•
•
1.5 V for IGLOO V5 devices
1.2 V or 1.5 V for IGLOO V2 devices
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO FPGA Fabric
User’s Guide for a complete board solution for the PLL analog power supply and ground.
•
There is one VCCPLF pin on IGLOO devices.
VCOMPLA/B/C/D/E/F PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and-
route tool automatically disables the unused PLLs to lower power consumption. The user should tie
unused VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on IGLOO devices.
Revision 20
3-1
Pin Descriptions
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
IGLOO devices support single-voltage ISP of the configuration flash and FlashROM. For programming,
VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be
tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply
voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO FPGA Fabric User’s Guide. All inputs
labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input,
GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are
direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to
the global network are multiplexed, and only one input can be used as a global input.
Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter of the IGLOO FPGA Fabric User’s
Guide for an explanation of the naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze mode is available on IGLOO devices. The FF pin is a dedicated input pin used to enter and
exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O,
and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the
FF pin is available as a regular I/O.
3-2
Revision 20
IGLOO Low Power Flash FPGAs
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO a devices. The
Flash*Freeze pin location is independent of device, allowing migration to larger or smaller IGLOO
devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology
and Low Power Modes" chapter of the IGLOO FPGA Fabric User’s Guide for more information on I/O
states during Flash*Freeze mode.
Table 3-1 • Flash*Freeze Pin Location in IGLOO Family Packages (device-independent)
IGLOO Packages
CS81/UC81
CS121
Flash*Freeze Pin
H2
J5
CS196
P3
W2
14
CS281
QN48
QN68
18
QN132
B12
27
VQ100
FG144
L3
FG256
T3
FG484
W6
Revision 20
3-3
Pin Descriptions
JTAG Pins
IGLOO devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,
even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must
be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate
I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the
JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be
tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to Table 3-2
for more information.
Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance 1,2
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
1. The TCK pin can be pulled-up or pulled-down.
2. The TRST pin is pulled-down.
3. Equivalent parallel resistance if more than one device is on the JTAG chain
Table 3-3 • TRST and TCK Pull-Down Recommendations
VJTAG
Tie-Off Resistance*
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
Note: Equivalent parallel resistance if more than one device is on the JTAG chain
TDI Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The
values in Table 3-2 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
3-4
Revision 20
IGLOO Low Power Flash FPGAs
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Related Documents
User’s Guides
IGLOO FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/IGLOO_UG.pdf
Packaging Documents
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are available on the Microsemi SoC Products Group website at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
3-5
4 – Package Pin Assignments
UC81
A1 Ball Pad Corner
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-1
Package Pin Assignments
UC81
UC81
UC81
Pin Number AGL030 Function
Pin Number AGL030 Function
Pin Number AGL030 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
IO00RSB0
IO02RSB0
IO06RSB0
IO11RSB0
IO16RSB0
IO19RSB0
IO22RSB0
IO24RSB0
IO26RSB0
IO81RSB1
IO04RSB0
IO10RSB0
IO13RSB0
IO15RSB0
IO20RSB0
IO21RSB0
IO28RSB0
IO25RSB0
IO79RSB1
IO80RSB1
IO08RSB0
IO12RSB0
IO17RSB0
IO14RSB0
IO18RSB0
IO29RSB0
IO27RSB0
IO74RSB1
IO76RSB1
IO77RSB1
VCC
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GEB0/IO71RSB1
GEA0/IO72RSB1
GEC0/IO73RSB1
VCCIB1
J1
J2
J3
J4
J5
J6
J7
J8
J9
IO63RSB1
IO61RSB1
IO59RSB1
IO56RSB1
IO52RSB1
IO44RSB1
TCK
VCC
VCCIB0
GDC0/IO32RSB0
GDA0/IO33RSB0
GDB0/IO34RSB0
IO68RSB1
IO67RSB1
IO64RSB1
GND
TMS
VPUMP
VCCIB1
IO47RSB1
IO36RSB0
IO38RSB0
IO40RSB0
IO65RSB1
IO66RSB1
IO57RSB1
IO53RSB1
IO49RSB1
IO45RSB1
IO46RSB1
VJTAG
TRST
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO54RSB1
IO48RSB1
IO43RSB1
IO42RSB1
TDI
VCCIB0
GND
IO23RSB0
IO31RSB0
IO30RSB0
TDO
4-2
Revision 20
IGLOO Low Power Flash FPGAs
CS81
A1 Ball Pad Corner
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-3
Package Pin Assignments
CS81
CS81
CS81
Pin Number AGL030 Function
Pin Number AGL030 Function
Pin Number AGL030 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
IO00RSB0
IO02RSB0
IO06RSB0
IO11RSB0
IO16RSB0
IO19RSB0
IO22RSB0
IO24RSB0
IO26RSB0
IO81RSB1
IO04RSB0
IO10RSB0
IO13RSB0
IO15RSB0
IO20RSB0
IO21RSB0
IO28RSB0
IO25RSB0
IO79RSB1
IO80RSB1
IO08RSB0
IO12RSB0
IO17RSB0
IO14RSB0
IO18RSB0
IO29RSB0
IO27RSB0
IO74RSB1
IO76RSB1
IO77RSB1
VCC
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GEB0/IO71RSB1
GEA0/IO72RSB1
GEC0/IO73RSB1
VCCIB1
J1
J2
J3
J4
J5
J6
J7
J8
J9
IO63RSB1
IO61RSB1
IO59RSB1
IO56RSB1
IO52RSB1
IO45RSB1
TCK
VCC
VCCIB0
GDC0/IO32RSB0
GDA0/IO33RSB0
GDB0/IO34RSB0
IO68RSB1
IO67RSB1
IO64RSB1
GND
TMS
VPUMP
VCCIB1
IO47RSB1
IO36RSB0
IO38RSB0
IO40RSB0
IO65RSB1
IO66RSB1
IO57RSB1
IO53RSB1
IO49RSB1
IO44RSB1
IO46RSB1
VJTAG
TRST
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO54RSB1
IO48RSB1
IO43RSB1
IO42RSB1
TDI
VCCIB0
GND
IO23RSB0
IO31RSB0
IO30RSB0
TDO
4-4
Revision 20
IGLOO Low Power Flash FPGAs
CS81
CS81
CS81
Pin Number AGL250 Function
Pin Number AGL250 Function
Pin Number AGL250 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
GAA0/IO00RSB0
GAA1/IO01RSB0
GAC0/IO04RSB0
IO13RSB0
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
GFB0/IO109NDB3
GFB1/IO109PDB3
GFA1/IO108PSB3
VCCIB3
J1
J2
J3
J4
J5
J6
J7
J8
J9
GEA2/IO97RSB2
GEC2/IO95RSB2
IO92RSB2
IO88RSB2
IO84RSB2
IO74RSB2
TCK
IO21RSB0
VCC
IO27RSB0
VCCIB1
GBB0/IO37RSB0
GBA1/IO40RSB0
GBA2/IO41PPB1
GAA2/IO118UPB3
GAB0/IO02RSB0
GAC1/IO05RSB0
IO11RSB0
GCA0/IO50NDB1
GCA1/IO50PDB1
GCB2/IO52PPB1
VCCPLF
TMS
VPUMP
VCOMPLF
GND
GND
IO23RSB0
VCCIB2
GBC0/IO35RSB0
GBB1/IO38RSB0
IO41NPB1
GND
GDA1/IO60USB1
GDC1/IO58UDB1
GDC0/IO58VDB1
GEA0/IO98NDB3
GEC1/IO100PDB3
GEC0/IO100NDB3
IO91RSB2
GBB2/IO42PSB1
GAB2/IO117UPB3
IO118VPB3
GND
IO15RSB0
IO25RSB0
IO86RSB2
GND
IO71RSB2
GBA0/IO39RSB0
GBC2/IO43PDB1
IO43NDB1
GDB2/IO62RSB2
VJTAG
TRST
GAC2/IO116USB3
IO117VPB3
GEA1/IO98PDB3
FF/GEB2/IO96RSB2
IO93RSB2
GFA2/IO107PSB3
VCC
IO90RSB2
VCCIB0
IO85RSB2
GND
IO77RSB2
IO52NPB1
GDA2/IO61RSB2
TDI
GCC1/IO48PDB1
GCC0/IO48NDB1
TDO
Revision 20
4-5
Package Pin Assignments
CS121
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-6
Revision 20
IGLOO Low Power Flash FPGAs
CS121
CS121
CS121
Pin Number AGL060 Function
Pin Number AGL060 Function
Pin Number AGL060 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
GNDQ
D4
D5
D6
D7
D8
D9
D10
D11
E1
IO10RSB0
IO11RSB0
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
VCC
GDC0/IO46RSB0
GDA1/IO49RSB0
GDB0/IO48RSB0
GCA0/IO40RSB0
IO75RSB1
IO01RSB0
GAA1/IO03RSB0
GAC1/IO07RSB0
IO15RSB0
IO18RSB0
IO32RSB0
IO31RSB0
IO13RSB0
GCA2/IO41RSB0
IO30RSB0
IO17RSB0
IO76RSB1
GBB1/IO22RSB0
GBA1/IO24RSB0
GNDQ
IO33RSB0
GFC2/IO78RSB1
GFA2/IO80RSB1
IO77RSB1
IO87RSB1
E2
GFC0/IO85RSB1
IO92RSB1
VMV0
E3
GEC2/IO66RSB1
IO54RSB1
GAA2/IO95RSB1
IO00RSB0
E4
IO94RSB1
E5
VCC
GDC2/IO53RSB1
VJTAG
GAA0/IO02RSB0
GAC0/IO06RSB0
IO08RSB0
E6
VCCIB0
E7
GND
TRST
E8
GCC0/IO36RSB0
IO34RSB0
IO44RSB0
IO12RSB0
E9
GEC1/IO74RSB1
GEC0/IO73RSB1
GEB1/IO72RSB1
GEA0/IO69RSB1
FF/GEB2/IO67RSB1
IO62RSB1
IO16RSB0
E10
E11
F1*
F2
GCB1/IO37RSB0
GCC1/IO35RSB0
VCOMPLF
J2
GBC1/IO20RSB0
GBB0/IO21RSB0
GBB2/IO27RSB0
GBA2/IO25RSB0
IO89RSB1
J3
J4
GFB0/IO83RSB1
GFA0/IO82RSB1
GFC1/IO86RSB1
VCCIB1
J5
F3
J6
F4
J7
GDA2/IO51RSB1
GDB2/IO52RSB1
TDI
GAC2/IO91RSB1
GAB1/IO05RSB0
GAB0/IO04RSB0
IO09RSB0
F5
J8
F6
VCC
J9
F7
VCCIB0
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
TDO
F8
GCB2/IO42RSB0
GCC2/IO43RSB0
GCB0/IO38RSB0
GCA1/IO39RSB0
VCCPLF
GDC1/IO45RSB0
GEB0/IO71RSB1
GEA1/IO70RSB1
GEA2/IO68RSB1
IO64RSB1
IO14RSB0
F9
GBA0/IO23RSB0
GBC0/IO19RSB0
IO26RSB0
F10
F11
G1*
G2
G3
G4
G5
G6
IO28RSB0
GFB2/IO79RSB1
GFA1/IO81RSB1
GFB1/IO84RSB1
GND
IO60RSB1
GBC2/IO29RSB0
IO88RSB1
IO59RSB1
IO56RSB1
IO90RSB1
TCK
GAB2/IO93RSB1
VCCIB1
TMS
Note: *Pin numbers F1 and G1 must be connected to ground because a PLL is not supported for AGL060-CS/G121.
Revision 20
4-7
Package Pin Assignments
CS121
Pin Number AGL060 Function
K10
K11
L1
VPUMP
GDB1/IO47RSB0
VMV1
L2
GNDQ
L3
IO65RSB1
IO63RSB1
IO61RSB1
IO58RSB1
IO57RSB1
IO55RSB1
GNDQ
L4
L5
L6
L7
L8
L9
L10
L11
GDA0/IO50RSB0
VMV1
4-8
Revision 20
IGLOO Low Power Flash FPGAs
CS121
CS121
CS121
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
GNDQ
D4
D5
D6
D7
D8
D9
D10
D11
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
F1
IO15RSB0
IO18RSB0
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
VCC
GDC0/IO62RSB0
GDA1/IO65RSB0
GDB0/IO64RSB0
GCA0/IO56RSB0
IO112RSB1
IO09RSB0
GAA1/IO01RSB0
GAC1/IO05RSB0
IO26RSB0
IO33RSB0
IO48RSB0
IO47RSB0
IO22RSB0
GCA2/IO57RSB0
IO46RSB0
IO31RSB0
IO113RSB1
GBB1/IO38RSB0
GBA1/IO40RSB0
GNDQ
IO49RSB0
GFC2/IO115RSB1
GFA2/IO117RSB1
IO114RSB1
IO124RSB1
GFC0/IO122RSB1
IO129RSB1
IO131RSB1
VCC
VMV0
GEC2/IO101RSB1
IO71RSB1
GAA2/IO132RSB1
IO07RSB0
GDC2/IO69RSB1
VJTAG
GAA0/IO00RSB0
GAC0/IO04RSB0
IO11RSB0
VCCIB0
GND
TRST
GCC0/IO52RSB0
IO50RSB0
IO60RSB0
IO20RSB0
GEC1/IO109RSB1
GEC0/IO108RSB1
GEB1/IO107RSB1
GEA0/IO104RSB1
FF/GEB2/IO102RSB1
IO91RSB1
IO28RSB0
GCB1/IO53RSB0
GCC1/IO51RSB0
VCOMPLF
J2
GBC1/IO36RSB0
GBB0/IO37RSB0
GBB2/IO43RSB0
GBA2/IO41RSB0
IO126RSB1
J3
J4
F2
GFB0/IO120RSB1
GFA0/IO119RSB1
GFC1/IO123RSB1
VCCIB1
J5
F3
J6
F4
J7
GDA2/IO67RSB1
GDB2/IO68RSB1
TDI
GAC2/IO128RSB1
GAB1/IO03RSB0
GAB0/IO02RSB0
IO13RSB0
F5
J8
F6
VCC
J9
F7
VCCIB0
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
TDO
F8
GCB2/IO58RSB0
GCC2/IO59RSB0
GCB0/IO54RSB0
GCA1/IO55RSB0
VCCPLF
GDC1/IO61RSB0
GEB0/IO106RSB1
GEA1/IO105RSB1
GEA2/IO103RSB1
IO95RSB1
IO24RSB0
F9
GBA0/IO39RSB0
GBC0/IO35RSB0
IO42RSB0
F10
F11
G1
G2
G3
G4
G5
G6
IO44RSB0
GFB2/IO116RSB1
GFA1/IO118RSB1
GFB1/IO121RSB1
GND
IO85RSB1
GBC2/IO45RSB0
IO125RSB1
IO83RSB1
IO77RSB1
IO127RSB1
TCK
GAB2/IO130RSB1
VCCIB1
TMS
Revision 20
4-9
Package Pin Assignments
CS121
Pin Number AGL125 Function
K10
K11
L1
VPUMP
GDB1/IO63RSB0
VMV1
L1
VMV1
L2
GNDQ
L3
IO99RSB1
IO93RSB1
IO87RSB1
IO81RSB1
IO79RSB1
IO73RSB1
GNDQ
L4
L5
L6
L7
L8
L9
L10
L11
GDA0/IO66RSB0
VMV1
4-10
Revision 20
IGLOO Low Power Flash FPGAs
CS196
A1 Ball Pad Corner
14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-11
Package Pin Assignments
CS196
CS196
CS196
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
A1
A2
GND
GAA0/IO00RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO09RSB0
C9
C10
C11
C12
C13
C14
D1
IO23RSB0
IO29RSB0
VCCIB0
F3
F4
IO113RSB1
IO112RSB1
IO111RSB1
NC
A3
F5
A4
IO42RSB0
GNDQ
F6
A5
F7
VCC
A6
IO15RSB0
IO44RSB0
IO127RSB1
IO129RSB1
GAA2/IO132RSB1
IO126RSB1
IO06RSB0
IO13RSB0
IO19RSB0
IO21RSB0
IO26RSB0
IO31RSB0
IO30RSB0
VMV0
F8
VCC
A7
IO18RSB0
F9
NC
A8
IO22RSB0
D2
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
H1
IO07RSB0
IO25RSB0
IO10RSB0
IO33RSB0
IO47RSB0
GFB1/IO121RSB1
GFA0/IO119RSB1
GFA2/IO117RSB1
VCOMPLF
GFC0/IO122RSB1
VCC
A9
IO27RSB0
D3
A10
A11
A12
A13
A14
B1
GBC0/IO35RSB0
GBB0/IO37RSB0
GBB1/IO38RSB0
GBA1/IO40RSB0
GND
D4
D5
D6
D7
D8
VCCIB1
D9
B2
VMV0
D10
D11
D12
D13
D14
E1
B3
GAA1/IO01RSB0
GAB1/IO03RSB0
GND
B4
B5
IO46RSB0
GBC2/IO45RSB0
IO125RSB1
GND
GND
B6
IO16RSB0
GND
B7
IO20RSB0
VCC
B8
IO24RSB0
E2
GCC0/IO52RSB0
GCB1/IO53RSB0
GCA0/IO56RSB0
IO48RSB0
GCC2/IO59RSB0
GFB0/IO120RSB1
GFA1/IO118RSB1
VCCPLF
B9
IO28RSB0
E3
IO131RSB1
VCCIB1
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
GND
E4
GBC1/IO36RSB0
GBA0/IO39RSB0
GBA2/IO41RSB0
GBB2/IO43RSB0
GAC2/IO128RSB1
GAB2/IO130RSB1
GNDQ
E5
NC
E6
IO08RSB0
IO17RSB0
IO12RSB0
IO11RSB0
NC
E7
E8
H2
E9
H3
E10
E11
E12
E13
E14
F1
H4
GFB2/IO116RSB1
GFC1/IO123RSB1
VCC
VCCIB0
H5
VCCIB0
IO32RSB0
GND
H6
GAB0/IO02RSB0
IO14RSB0
H7
GND
IO34RSB0
IO124RSB1
IO114RSB1
H8
GND
VCCIB0
H9
VCC
NC
F2
H10
GCC1/IO51RSB0
4-12
Revision 20
IGLOO Low Power Flash FPGAs
CS196
CS196
CS196
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
H11
H12
H13
H14
J1
GCB0/IO54RSB0
GCA1/IO55RSB0
IO49RSB0
GCA2/IO57RSB0
GFC2/IO115RSB1
IO110RSB1
IO94RSB1
IO93RSB1
IO89RSB1
NC
L5
L6
IO91RSB1
IO90RSB1
IO83RSB1
IO81RSB1
IO71RSB1
IO70RSB1
VPUMP
N13
N14
P1
GNDQ
TDO
L7
GND
L8
P2
GEA2/IO103RSB1
FF/GEB2/IO102RSB1
IO98RSB1
IO97RSB1
IO85RSB1
IO84RSB1
IO79RSB1
IO77RSB1
IO75RSB1
GDC2/IO69RSB1
GDA2/IO67RSB1
TMS
L9
P3
J2
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
P4
J3
P5
J4
VJTAG
P6
J5
GDA0/IO66RSB0
GDB0/IO64RSB0
GEB0/IO106RSB1
GEA1/IO105RSB1
GNDQ
P7
J6
P8
J7
VCC
P9
J8
VCC
P10
P11
P12
P13
P14
J9
NC
J10
J11
J12
J13
J14
K1
IO60RSB0
GCB2/IO58RSB0
IO50RSB0
GDC1/IO61RSB0
GDC0/IO62RSB0
IO99RSB1
GND
VCCIB1
IO92RSB1
IO88RSB1
NC
GND
VCCIB1
IO76RSB1
GDB2/IO68RSB1
VCCIB1
K2
K3
IO95RSB1
VCCIB1
K4
VMV1
K5
NC
TRST
K6
IO86RSB1
IO80RSB1
IO74RSB1
IO72RSB1
NC
VCCIB0
K7
GEA0/IO104RSB1
VMV1
K8
N2
K9
N3
GEC2/IO101RSB1
IO100RSB1
GND
K10
K11
K12
K13
K14
L1
N4
VCCIB0
N5
GDA1/IO65RSB0
GND
N6
IO87RSB1
IO82RSB1
IO78RSB1
IO73RSB1
GND
N7
GDB1/IO63RSB0
GEB1/IO107RSB1
GEC1/IO109RSB1
GEC0/IO108RSB1
IO96RSB1
N8
N9
L2
N10
N11
N12
L3
TCK
L4
TDI
Revision 20
4-13
Package Pin Assignments
CS196
CS196
CS196
Pin Number AGL250 Function
Pin Number AGL250 Function
Pin Number AGL250 Function
A1
A2
GND
GAA0/IO00RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO10RSB0
C9
C10
C11
C12
C13
C14
D1
IO30RSB0
IO33RSB0
VCCIB0
F3
F4
IO111PDB3
IO111NDB3
IO113NPB3
IO06RSB0
A3
F5
A4
IO41NPB1
GNDQ
F6
A5
F7
VCC
A6
IO13RSB0
IO42NDB1
IO116VDB3
IO117VDB3
GAA2/IO118UDB3
IO113PPB3
IO08RSB0
IO14RSB0
IO15RSB0
IO18RSB0
IO25RSB0
IO32RSB0
IO44PPB1
VMV1
F8
VCC
A7
IO17RSB0
F9
IO28RSB0
A8
IO19RSB0
D2
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
H1
IO54PDB1
A9
IO23RSB0
D3
IO54NDB1
IO47NDB1
IO47PDB1
A10
A11
A12
A13
A14
B1
GBC0/IO35RSB0
GBB0/IO37RSB0
GBB1/IO38RSB0
GBA1/IO40RSB0
GND
D4
D5
D6
IO45NDB1
GFB1/IO109PDB3
GFA0/IO108NDB3
GFA2/IO107PPB3
VCOMPLF
GFC0/IO110NDB3
VCC
D7
D8
VCCIB3
D9
B2
VMV0
D10
D11
D12
D13
D14
E1
B3
GAA1/IO01RSB0
GAB1/IO03RSB0
GND
B4
B5
IO43NDB1
GBC2/IO43PDB1
IO112PDB3
GND
GND
B6
IO12RSB0
GND
B7
IO16RSB0
VCC
B8
IO22RSB0
E2
GCC0/IO48NDB1
GCB1/IO49PDB1
GCA0/IO50NDB1
IO53NDB1
GCC2/IO53PDB1
GFB0/IO109NDB3
GFA1/IO108PDB3
VCCPLF
B9
IO24RSB0
E3
IO118VDB3
VCCIB3
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
GND
E4
GBC1/IO36RSB0
GBA0/IO39RSB0
GBA2/IO41PPB1
GBB2/IO42PDB1
GAC2/IO116UDB3
GAB2/IO117UDB3
GNDQ
E5
IO114USB3
IO07RSB0
IO09RSB0
IO21RSB0
IO31RSB0
IO34RSB0
VCCIB1
E6
E7
E8
H2
E9
H3
E10
E11
E12
E13
E14
F1
H4
GFB2/IO106PPB3
GFC1/IO110PDB3
VCC
H5
VCCIB0
IO44NPB1
GND
H6
GAB0/IO02RSB0
IO11RSB0
H7
GND
IO45PDB1
IO112NDB3
IO107NPB3
H8
GND
VCCIB0
H9
VCC
IO20RSB0
F2
H10
GCC1/IO48PDB1
4-14
Revision 20
IGLOO Low Power Flash FPGAs
CS196
CS196
CS196
Pin Number AGL250 Function
Pin Number AGL250 Function
Pin Number AGL250 Function
H11
H12
H13
H14
J1
GCB0/IO49NDB1
GCA1/IO50PDB1
IO51NDB1
L5
L6
IO89RSB2
IO92RSB2
IO75RSB2
IO66RSB2
IO65RSB2
IO71RSB2
VPUMP
N13
N14
P1
GNDQ
TDO
L7
GND
GCA2/IO51PDB1
GFC2/IO105PDB3
IO104PPB3
IO106NPB3
IO103PDB3
IO103NDB3
IO80RSB2
L8
P2
GEA2/IO97RSB2
FF/GEB2/IO96RSB2
IO90RSB2
IO85RSB2
IO83RSB2
IO79RSB2
IO76RSB2
IO72RSB2
IO68RSB2
GDC2/IO63RSB2
GDA2/IO61RSB2
TMS
L9
P3
J2
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
P4
J3
P5
J4
VJTAG
P6
J5
GDA0/IO60VPB1
GDB0/IO59VDB1
GEB0/IO99NDB3
GEA1/IO98PPB3
GNDQ
P7
J6
P8
J7
VCC
P9
J8
VCC
P10
P11
P12
P13
P14
J9
IO64RSB2
J10
J11
J12
J13
J14
K1
IO56PDB1
VCCIB2
GCB2/IO52PDB1
IO52NDB1
IO88RSB2
IO87RSB2
IO82RSB2
VCCIB2
GND
GDC1/IO58UDB1
GDC0/IO58VDB1
IO105NDB3
GND
IO67RSB2
GDB2/IO62RSB2
VCCIB2
K2
K3
IO104NPB3
VCCIB3
K4
VMV2
K5
IO101PPB3
IO91RSB2
TRST
K6
VCCIB1
K7
IO81RSB2
GEA0/IO98NPB3
VMV3
K8
IO73RSB2
N2
K9
IO77RSB2
N3
GEC2/IO95RSB2
IO94RSB2
GND
K10
K11
K12
K13
K14
L1
IO56NDB1
N4
VCCIB1
N5
GDA1/IO60UPB1
GND
N6
IO86RSB2
IO78RSB2
IO74RSB2
IO69RSB2
GND
N7
GDB1/IO59UDB1
GEB1/IO99PDB3
GEC1/IO100PDB3
GEC0/IO100NDB3
IO101NPB3
N8
N9
L2
N10
N11
N12
L3
TCK
L4
TDI
Revision 20
4-15
Package Pin Assignments
CS196
CS196
CS196
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
A1
A2
GND
GAA0/IO00RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO14RSB0
C8
C9
IO31RSB0
IO44RSB0
IO49RSB0
VCCIB0
F2
F3
IO144NPB3
IO148PDB3
IO148NDB3
IO150NPB3
IO07RSB0
VCC
A3
C10
C11
C12
C13
C14
D1
F4
A4
F5
A5
IO60NPB1
GNDQ
F6
A6
IO18RSB0
F7
A7
IO26RSB0
IO61NDB1
IO153VDB3
IO154VDB3
GAA2/IO155UDB3
IO150PPB3
IO11RSB0
IO20RSB0
IO23RSB0
IO28RSB0
IO41RSB0
IO47RSB0
IO63PPB1
VMV1
F8
VCC
A8
IO29RSB0
F9
IO43RSB0
IO73PDB1
IO73NDB1
IO66NDB1
IO66PDB1
IO64NDB1
GFB1/IO146PDB3
GFA0/IO145NDB3
GFA2/IO144PPB3
VCOMPLF
GFC0/IO147NDB3
VCC
A9
IO36RSB0
D2
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
H1
A10
A11
A12
A13
A14
B1
GBC0/IO54RSB0
GBB0/IO56RSB0
GBB1/IO57RSB0
GBA1/IO59RSB0
GND
D3
D4
D5
D6
D7
VCCIB3
D8
B2
VMV0
D9
B2
VMV0
D10
D11
D12
D13
D14
E1
B3
GAA1/IO01RSB0
GAB1/IO03RSB0
GND
B4
B5
IO62NDB1
GBC2/IO62PDB1
IO149PDB3
GND
GND
B6
IO17RSB0
GND
B7
IO25RSB0
VCC
B8
IO34RSB0
E2
GCC0/IO67NDB1
GCB1/IO68PDB1
GCA0/IO69NDB1
IO72NDB1
GCC2/IO72PDB1
GFB0/IO146NDB3
GFA1/IO145PDB3
VCCPLF
B9
IO39RSB0
E3
IO155VDB3
VCCIB3
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
GND
E4
GBC1/IO55RSB0
GBA0/IO58RSB0
GBA2/IO60PPB1
GBB2/IO61PDB1
GAC2/IO153UDB3
GAB2/IO154UDB3
GNDQ
E5
IO151USB3
IO09RSB0
IO12RSB0
IO32RSB0
IO46RSB0
IO51RSB0
VCCIB1
E6
E7
E8
H2
E9
H3
E10
E11
E12
E13
E14
F1
H4
GFB2/IO143PPB3
GFC1/IO147PDB3
VCC
H5
VCCIB0
IO63NPB1
GND
H6
GAB0/IO02RSB0
IO15RSB0
H7
GND
IO64PDB1
IO149NDB3
H8
GND
VCCIB0
H9
VCC
4-16
Revision 20
IGLOO Low Power Flash FPGAs
CS196
CS196
CS196
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
H10
H11
H12
H13
H14
J1
GCC1/IO67PDB1
GCB0/IO68NDB1
GCA1/IO69PDB1
IO70NDB1
L4
L5
IO138NPB3
IO122RSB2
IO128RSB2
IO101RSB2
IO88RSB2
IO86RSB2
IO94RSB2
VPUMP
N11
N12
N13
N14
P1
TCK
TDI
L6
GNDQ
L7
TDO
GCA2/IO70PDB1
GFC2/IO142PDB3
IO141PPB3
IO143NPB3
IO140PDB3
IO140NDB3
IO109RSB2
VCC
L8
GND
L9
P2
GEA2/IO134RSB2
J2
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M12
M13
M14
N1
P3
FF/GEB2/IO133RSB
2
J3
P4
P5
IO123RSB2
IO116RSB2
IO114RSB2
IO107RSB2
IO103RSB2
IO95RSB2
IO91RSB2
GDC2/IO82RSB2
GDA2/IO80RSB2
TMS
J4
VJTAG
J5
GDA0/IO79VPB1
GDB0/IO78VDB1
GEB0/IO136NDB3
GEA1/IO135PPB3
GNDQ
P6
J6
P7
J7
P8
J8
VCC
P9
J9
IO84RSB2
P10
P11
P12
P13
P14
J10
J11
J12
J13
J14
K1
IO75PDB1
VCCIB2
GCB2/IO71PDB1
IO71NDB1
IO120RSB2
IO119RSB2
IO112RSB2
VCCIB2
GDC1/IO77UDB1
GDC0/IO77VDB1
IO142NDB3
GND
GND
IO89RSB2
GDB2/IO81RSB2
VCCIB2
K2
K3
IO141NPB3
VCCIB3
K4
VMV2
K5
IO138PPB3
IO125RSB2
IO110RSB2
IO98RSB2
VMV2
K6
TRST
K7
VCCIB1
K8
GEA0/IO135NPB3
VMV3
K9
IO104RSB2
IO75NDB1
N2
K10
K11
K12
K13
K14
L1
N3
GEC2/IO132RSB2
IO130RSB2
GND
VCCIB1
N4
GDA1/IO79UPB1
GND
N5
N6
IO117RSB2
IO106RSB2
IO100RSB2
IO92RSB2
GND
GDB1/IO78UDB1
GEB1/IO136PDB3
GEC1/IO137PDB3
GEC0/IO137NDB3
N7
N8
L2
N9
L3
N10
Revision 20
4-17
Package Pin Assignments
CS281
19 18 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-18
Revision 20
IGLOO Low Power Flash FPGAs
CS281
CS281
CS281
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
A1
A2
GND
GAB0/IO02RSB0
GAC1/IO05RSB0
IO07RSB0
B18
B19
C1
VCCIB1
IO61NDB1
E13
E14
E15
E16
E18
E19
F1
IO46RSB0
GBB1/IO57RSB0
IO62NPB1
A3
GAB2/IO173PPB3
IO174NPB3
IO12RSB0
A4
C2
IO63PPB1
A5
IO10RSB0
C6
IO64PPB1
A6
IO14RSB0
C14
C18
C19
D1
IO50RSB0
IO65NPB1
A7
IO18RSB0
IO60NPB1
IO168NPB3
GND
A8
IO21RSB0
GBB2/IO61PDB1
IO170PPB3
IO172NPB3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO09RSB0
F2
A9
IO22RSB0
F3
IO169PPB3
IO170NPB3
IO173NPB3
IO63NPB1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
VCCIB0
D2
F4
IO33RSB0
D4
F5
IO40RSB0
D5
F15
F16
F17
F18
F19
G1
IO37RSB0
D6
IO65PPB1
IO48RSB0
D7
IO16RSB0
IO64NPB1
IO51RSB0
D8
IO19RSB0
GND
IO53RSB0
D9
IO26RSB0
IO68PPB1
GBC1/IO55RSB0
GBA0/IO58RSB0
GND
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
IO167NPB3
IO165NDB3
IO168PPB3
IO167PPB3
GAC2/IO172PPB3
VCCIB0
IO34RSB0
G2
IO45RSB0
G4
GAA2/IO174PPB3
VCCIB0
IO49RSB0
G5
B2
IO47RSB0
G7
B3
GAB1/IO03RSB0
GAC0/IO04RSB0
IO06RSB0
GBB0/IO56RSB0
GBA2/IO60PPB1
GBC2/IO62PPB1
IO66NPB1
G8
B4
G9
IO28RSB0
B5
G10
G11
G12
G13
G15
G16
G18
G19
H1
IO32RSB0
B6
GND
IO43RSB0
B7
IO15RSB0
IO169NPB3
IO171PPB3
IO171NPB3
IO08RSB0
VCCIB0
B8
IO20RSB0
E2
IO66PPB1
B9
IO23RSB0
E4
IO67NDB1
B10
B11
B12
B13
B14
B15
B16
B17
IO24RSB0
E5
IO67PDB1
IO36RSB0
E6
IO11RSB0
GCC0/IO69NPB1
GCB1/IO70PPB1
GFB0/IO163NPB3
IO165PDB3
GFC1/IO164PPB3
GFB1/IO163PPB3
VCCIB3
IO35RSB0
E7
IO13RSB0
IO44RSB0
E8
IO17RSB0
GND
E9
IO25RSB0
H2
IO52RSB0
E10
E11
E12
IO30RSB0
H4
GBC0/IO54RSB0
GBA1/IO59RSB0
IO41RSB0
H5
IO42RSB0
H7
Revision 20
4-19
Package Pin Assignments
CS281
CS281
CS281
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
H8
H9
VCC
VCCIB0
K15
K16
K18
K19
L1
IO73NPB1
GND
N4
N5
IO150PPB3
IO148NPB3
GEA2/IO143RSB2
VCCIB2
H10
H11
H12
H13
H15
H16
H18
H19
J1
VCC
IO74NPB1
VCCIB1
N7
VCCIB0
N8
VCC
GFB2/IO160PDB3
IO160NDB3
GFC2/IO159PPB3
IO153PPB3
IO153NPB3
VCCIB3
N9
IO117RSB2
IO115RSB2
IO114RSB2
VCCIB2
VCCIB1
L2
N10
N11
N12
N13
N15
N16
N18
N19
P1
IO68NPB1
GCB0/IO70NPB1
GCA1/IO71PPB1
GCA2/IO72PPB1
VCOMPLF
GFA0/IO162NDB3
VCCPLF
L4
L5
L7
VPUMP
L8
IO82PPB1
L9
GND
IO85PPB1
J2
L10
L11
L12
L13
L15
L16
L18
L19
M1
GND
IO82NPB1
J4
GND
IO81PPB1
J5
GFC0/IO164NPB3
GFA2/IO161PDB3
VCCIB3
VCCIB1
IO151PDB3
GND
J7
IO76PPB1
IO76NPB1
IO77PPB1
IO78NPB1
IO77NPB1
IO158PDB3
IO158NDB3
IO154NPB3
IO152PPB3
VCCIB3
P2
J8
P3
IO151NDB3
IO149PPB3
GEA0/IO144NPB3
IO83NDB1
IO83PDB1
J9
GND
P4
J10
J11
J12
J13
J15
J16
J18
J19
K1
GND
P5
GND
P15
P16
P17
P18
P19
R1
VCCIB1
GCC1/IO69PPB1
GCA0/IO71NPB1
GCB2/IO73PPB1
IO72NPB1
IO75PSB1
VCCIB3
M2
GDC1/IO86PPB1
GND
M4
M5
IO85NPB1
M7
IO150NPB3
IO149NPB3
GEC1/IO146PPB3
GEB1/IO145PPB3
IO138RSB2
IO127RSB2
IO123RSB2
IO118RSB2
IO111RSB2
IO106RSB2
IO103RSB2
IO97RSB2
M8
VCC
R2
M9
VCCIB2
R4
K2
GFA1/IO162PDB3
GND
M10
M11
M12
M13
M15
M16
M18
M19
N1
VCC
R5
K4
VCCIB2
R6
K5
IO159NPB3
IO161NDB3
VCC
VCC
R7
K7
VCCIB1
R8
K8
IO79NPB1
IO81NPB1
IO79PPB1
IO78PPB1
IO154PPB3
IO152NPB3
R9
K9
GND
R10
R11
R12
R13
R14
K10
K11
K12
K13
GND
GND
VCC
GCC2/IO74PPB1
N2
IO95RSB2
4-20
Revision 20
IGLOO Low Power Flash FPGAs
CS281
CS281
Pin Number AGL600 Function
Pin Number AGL600 Function
R15
R16
R18
R19
T1
IO94RSB2
GDA1/IO88PPB1
GDB0/IO87NPB1
GDC0/IO86NPB1
IO148PPB3
GEC0/IO146NPB3
GEB0/IO145NPB3
IO132RSB2
IO136RSB2
IO130RSB2
IO126RSB2
IO120RSB2
GND
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
IO112RSB2
IO110RSB2
IO108RSB2
IO102RSB2
GND
T2
IO93RSB2
GDA2/IO89RSB2
TDI
T4
T5
T6
VCCIB2
T7
TDO
T8
GND
T9
W2
FF/GEB2/IO142RSB2
IO139RSB2
IO137RSB2
IO134RSB2
IO133RSB2
IO128RSB2
IO124RSB2
IO119RSB2
VCCIB2
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
W3
IO113RSB2
IO104RSB2
IO101RSB2
IO98RSB2
W4
W5
W6
W7
GDC2/IO91RSB2
TMS
W8
W9
VJTAG
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
GDB1/IO87PPB1
IO147PDB3
GEA1/IO144PPB3
IO131RSB2
IO99RSB2
IO109RSB2
IO107RSB2
IO105RSB2
IO100RSB2
IO96RSB2
IO92RSB2
GDB2/IO90RSB2
TCK
U2
U6
U14
U18
U19
V1
TRST
GDA0/IO88NPB1
IO147NDB3
VCCIB3
V2
GND
V3
GEC2/IO141RSB2
IO140RSB2
IO135RSB2
GND
V4
V5
V6
V7
IO125RSB2
IO122RSB2
IO116RSB2
V8
V9
Revision 20
4-21
Package Pin Assignments
CS281
CS281
CS281
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
A1
A2
GND
GAB0/IO02RSB0
GAC1/IO05RSB0
IO13RSB0
B18
B19
C1
VCCIB1
IO79NDB1
E13
E14
E15
E16
E18
E19
F1
IO53RSB0
GBB1/IO75RSB0
IO80NPB1
A3
GAB2/IO224PPB3
IO225NPB3
IO18RSB0
A4
C2
IO85PPB1
A5
IO11RSB0
C6
IO83PPB1
A6
IO16RSB0
C14
C18
C19
D1
IO63RSB0
IO84NPB1
A7
IO20RSB0
IO78NPB1
IO214NPB3
GND
A8
IO24RSB0
GBB2/IO79PDB1
IO219PPB3
IO223NPB3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO15RSB0
F2
A9
IO29RSB0
F3
IO217PPB3
IO219NPB3
IO224NPB3
IO85NPB1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
VCCIB0
D2
F4
IO39RSB0
D4
F5
IO45RSB0
D5
F15
F16
F17
F18
F19
G1
IO48RSB0
D6
IO84PPB1
IO58RSB0
D7
IO19RSB0
IO83NPB1
IO61RSB0
D8
IO27RSB0
GND
IO62RSB0
D9
IO32RSB0
IO90PPB1
GBC1/IO73RSB0
GBA0/IO76RSB0
GND
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
IO212NPB3
IO211NDB3
IO214PPB3
IO212PPB3
GAC2/IO223PPB3
VCCIB0
IO38RSB0
G2
IO44RSB0
G4
GAA2/IO225PPB3
VCCIB0
IO47RSB0
G5
B2
IO60RSB0
G7
B3
GAB1/IO03RSB0
GAC0/IO04RSB0
IO12RSB0
GBB0/IO74RSB0
GBA2/IO78PPB1
GBC2/IO80PPB1
IO88NPB1
G8
B4
G9
IO30RSB0
B5
G10
G11
G12
G13
G15
G16
G18
G19
H1
IO37RSB0
B6
GND
IO43RSB0
B7
IO21RSB0
IO217NPB3
IO221PPB3
IO221NPB3
IO10RSB0
VCCIB0
B8
IO26RSB0
E2
IO88PPB1
B9
IO34RSB0
E4
IO89NDB1
B10
B11
B12
B13
B14
B15
B16
B17
IO35RSB0
E5
IO89PDB1
IO36RSB0
E6
IO14RSB0
GCC0/IO91NPB1
GCB1/IO92PPB1
GFB0/IO208NPB3
IO211PDB3
GFC1/IO209PPB3
GFB1/IO208PPB3
VCCIB3
IO46RSB0
E7
IO25RSB0
IO52RSB0
E8
IO28RSB0
GND
E9
IO31RSB0
H2
IO59RSB0
E10
E11
E12
IO33RSB0
H4
GBC0/IO72RSB0
GBA1/IO77RSB0
IO42RSB0
H5
IO49RSB0
H7
4-22
Revision 20
IGLOO Low Power Flash FPGAs
CS281
CS281
CS281
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
H8
H9
VCC
VCCIB0
K15
K16
K18
K19
L1
IO95NPB1
GND
N4
N5
IO196PPB3
IO197NPB3
GEA2/IO187RSB2
VCCIB2
H10
H11
H12
H13
H15
H16
H18
H19
J1
VCC
IO96NPB1
VCCIB1
N7
VCCIB0
N8
VCC
GFB2/IO205PDB3
IO205NDB3
GFC2/IO204PPB3
IO203PPB3
IO203NPB3
VCCIB3
N9
IO155RSB2
IO154RSB2
IO150RSB2
VCCIB2
VCCIB1
L2
N10
N11
N12
N13
N15
N16
N18
N19
P1
IO90NPB1
GCB0/IO92NPB1
GCA1/IO93PPB1
GCA2/IO94PPB1
VCOMPLF
GFA0/IO207NDB3
VCCPLF
L4
L5
L7
VPUMP
L8
IO107PPB1
IO105PPB1
IO107NPB1
IO100PPB1
IO195PDB3
GND
L9
GND
J2
L10
L11
L12
L13
L15
L16
L18
L19
M1
GND
J4
GND
J5
GFC0/IO209NPB3
GFA2/IO206PDB3
VCCIB3
VCCIB1
J7
IO103PPB1
IO103NPB1
IO97PPB1
IO98NPB1
IO97NPB1
IO202PDB3
IO202NDB3
IO201NPB3
IO198PPB3
VCCIB3
P2
J8
P3
IO195NDB3
IO194PPB3
GEA0/IO188NPB3
IO108NDB1
IO108PDB1
GDC1/IO111PPB1
GND
J9
GND
P4
J10
J11
J12
J13
J15
J16
J18
J19
K1
GND
P5
GND
P15
P16
P17
P18
P19
R1
VCCIB1
GCC1/IO91PPB1
GCA0/IO93NPB1
GCB2/IO95PPB1
IO94NPB1
IO102PSB1
VCCIB3
M2
M4
M5
IO105NPB1
IO196NPB3
IO194NPB3
GEC1/IO190PPB3
GEB1/IO189PPB3
IO184RSB2
IO173RSB2
IO168RSB2
IO160RSB2
IO151RSB2
IO141RSB2
IO136RSB2
IO127RSB2
IO124RSB2
M7
M8
VCC
R2
M9
VCCIB2
R4
K2
GFA1/IO207PDB3
GND
M10
M11
M12
M13
M15
M16
M18
M19
N1
VCC
R5
K4
VCCIB2
R6
K5
IO204NPB3
IO206NDB3
VCC
VCC
R7
K7
VCCIB1
R8
K8
IO104NPB1
IO100NPB1
IO104PPB1
IO98PPB1
IO201PPB3
IO198NPB3
R9
K9
GND
R10
R11
R12
R13
R14
K10
K11
K12
K13
GND
GND
VCC
GCC2/IO96PPB1
N2
Revision 20
4-23
Package Pin Assignments
CS281
CS281
Pin Number AGL1000 Function
Pin Number AGL1000 Function
R15
R16
R18
R19
T1
IO122RSB2
GDA1/IO113PPB1
GDB0/IO112NPB1
GDC0/IO111NPB1
IO197PPB3
GEC0/IO190NPB3
GEB0/IO189NPB3
IO181RSB2
IO172RSB2
IO171RSB2
IO156RSB2
IO159RSB2
GND
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
IO145RSB2
IO144RSB2
IO134RSB2
IO133RSB2
GND
T2
IO119RSB2
GDA2/IO114RSB2
TDI
T4
T5
T6
VCCIB2
T7
TDO
T8
GND
T9
W2
FF/GEB2/IO186RSB2
IO183RSB2
IO176RSB2
IO170RSB2
IO162RSB2
IO157RSB2
IO152RSB2
IO149RSB2
VCCIB2
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
W3
IO139RSB2
IO138RSB2
IO129RSB2
IO123RSB2
GDC2/IO116RSB2
TMS
W4
W5
W6
W7
W8
W9
VJTAG
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
GDB1/IO112PPB1
IO193PDB3
GEA1/IO188PPB3
IO167RSB2
IO128RSB2
TRST
IO140RSB2
IO135RSB2
IO130RSB2
IO125RSB2
IO120RSB2
IO118RSB2
GDB2/IO115RSB2
TCK
U2
U6
U14
U18
U19
V1
GDA0/IO113NPB1
IO193NDB3
VCCIB3
V2
GND
V3
GEC2/IO185RSB2
IO182RSB2
IO175RSB2
GND
V4
V5
V6
V7
IO161RSB2
IO143RSB2
IO146RSB2
V8
V9
4-24
Revision 20
IGLOO Low Power Flash FPGAs
QN48
Pin 1
48
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-25
Package Pin Assignments
QN48
QN48
Pin Number AGL030 Function
Pin Number AGL030 Function
1
IO82RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
GND
37
38
39
40
41
42
43
44
45
46
47
48
IO24RSB0
IO22RSB0
IO20RSB0
IO18RSB0
IO16RSB0
IO14RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
2
3
4
5
6
VCCIB1
7
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO62RSB1
IO61RSB1
FF/IO60RSB1
IO57RSB1
IO55RSB1
IO53RSB1
VCC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
IO46RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
TRST
VJTAG
IO38RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
GND
VCC
IO25RSB0
4-26
Revision 20
IGLOO Low Power Flash FPGAs
QN68
Pin A1 Mark
68
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-27
Package Pin Assignments
QN68
QN68
Pin Number AGL015 Function
Pin Number AGL015 Function
1
IO82RSB1
IO80RSB1
IO78RSB1
IO76RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
VCC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TRST
VJTAG
2
3
IO40RSB0
IO37RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
4
5
6
7
8
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
VCC
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO56RSB1
IO54RSB1
IO52RSB1
IO51RSB1
VCC
IO31RSB0
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO24RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO15RSB0
IO14RSB0
VCCIB0
GND
GND
VCC
VCCIB1
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
IO50RSB1
IO48RSB1
IO46RSB1
IO44RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
4-28
Revision 20
IGLOO Low Power Flash FPGAs
QN68
QN68
Pin Number AGL030 Function
Pin Number AGL030 Function
1
IO82RSB1
IO80RSB1
IO78RSB1
IO76RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
VCC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TRST
VJTAG
2
3
IO40RSB0
IO37RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
4
5
6
7
8
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
VCC
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
FF/IO60RSB1
IO58RSB1
IO56RSB1
IO54RSB1
IO52RSB1
IO51RSB1
VCC
IO31RSB0
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO24RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO15RSB0
IO14RSB0
VCCIB0
GND
GND
VCC
VCCIB1
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
IO50RSB1
IO48RSB1
IO46RSB1
IO44RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
Revision 20
4-29
Package Pin Assignments
QN132
A37
B34
C31
A48
B44
C40
Pin A1Mark
D1
D4
A36
B33
C30
A1
B1
C1
C21
B23
A25
C10
B11
A12
D3
D2
Optional
Corner Pad (4x)
C20
B22
A24
C11
B12
A13
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-30
Revision 20
IGLOO Low Power Flash FPGAs
QN132
QN132
QN132
Pin Number AGL030 Function
Pin Number AGL030 Function
Pin Number AGL030 Function
A1
A2
IO80RSB1
IO77RSB1
NC
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
IO22RSB0
IO19RSB0
NC
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
NC
A3
IO37RSB0
GND
A4
IO76RSB1
GEC0/IO73RSB1
NC
IO18RSB0
IO16RSB0
IO14RSB0
VCC
A5
GDA0/IO33RSB0
NC
A6
A7
GEB0/IO71RSB1
IO69RSB1
NC
GND
A8
IO11RSB0
IO08RSB0
IO06RSB0
IO05RSB0
IO02RSB0
IO81RSB1
IO78RSB1
GND
IO29RSB0
IO26RSB0
IO23RSB0
IO20RSB0
GND
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
VCC
IO67RSB1
IO64RSB1
IO59RSB1
IO56RSB1
NC
IO17RSB0
IO15RSB0
GND
B2
B3
IO55RSB1
IO53RSB1
VCC
B4
IO75RSB1
NC
IO12RSB0
IO09RSB0
GND
B5
B6
GND
IO50RSB1
IO48RSB1
IO45RSB1
IO44RSB1
IO43RSB1
TDI
B7
IO70RSB1
NC
IO04RSB0
IO01RSB0
IO82RSB1
IO79RSB1
NC
B8
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
IO66RSB1
IO63RSB1
FF/IO60RSB1
IO57RSB1
GND
C2
C3
C4
IO74RSB1
GEA0/IO72RSB1
NC
TRST
C5
IO40RSB0
NC
C6
IO54RSB1
IO52RSB1
GND
C7
NC
IO39RSB0
IO38RSB0
IO36RSB0
IO35RSB0
GDC0/IO32RSB0
NC
C8
VCCIB1
IO65RSB1
IO62RSB1
IO61RSB1
IO58RSB1
NC
C9
IO49RSB1
IO46RSB1
GND
C10
C11
C12
C13
C14
C15
C16
IO42RSB1
TMS
VCC
NC
IO30RSB0
IO27RSB0
TDO
IO51RSB1
VCCIB1
IO41RSB0
Revision 20
4-31
Package Pin Assignments
QN132
Pin Number AGL030 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO47RSB1
NC
TCK
NC
VPUMP
VJTAG
NC
NC
NC
GDB0/IO34RSB0
NC
VCCIB0
IO28RSB0
IO25RSB0
IO24RSB0
IO21RSB0
NC
NC
VCCIB0
IO13RSB0
IO10RSB0
IO07RSB0
IO03RSB0
IO00RSB0
GND
D2
GND
D3
GND
D4
GND
4-32
Revision 20
IGLOO Low Power Flash FPGAs
QN132
QN132
QN132
Pin Number AGL060 Function
Pin Number AGL060 Function
Pin Number AGL060 Function
A1
A2
GAB2/IO00RSB1
IO93RSB1
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
GBB1/IO25RSB0
GBC0/IO22RSB0
VCCIB0
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GDC0/IO49RSB0
GND
A3
VCCIB1
NC
A4
GFC1/IO89RSB1
GFB0/IO86RSB1
VCCPLF
IO21RSB0
IO18RSB0
IO15RSB0
IO14RSB0
IO11RSB0
GCB2/IO45RSB0
GND
A5
A6
GCB0/IO41RSB0
GCC1/IO38RSB0
GND
A7
GFA1/IO84RSB1
GFC2/IO81RSB1
IO78RSB1
A8
A9
GAB1/IO08RSB0
NC
GBB2/IO30RSB0
VMV0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
VCC
GEB1/IO75RSB1
GEA0/IO72RSB1
GEC2/IO69RSB1
IO65RSB1
GAB0/IO07RSB0
IO04RSB0
IO01RSB1
GAC2/IO94RSB1
GND
GBA0/IO26RSB0
GBC1/IO23RSB0
GND
B2
IO20RSB0
IO17RSB0
GND
VCC
B3
IO64RSB1
B4
GFC0/IO88RSB1
VCOMPLF
GND
IO63RSB1
B5
IO12RSB0
GAC0/IO09RSB0
GND
IO62RSB1
B6
IO61RSB1
B7
GFB2/IO82RSB1
IO79RSB1
GND
IO58RSB1
B8
GAA1/IO06RSB0
GNDQ
GDB2/IO55RSB1
NC
B9
B10
B11
B12
GEB0/IO74RSB1
VMV1
GAA2/IO02RSB1
IO95RSB1
VCC
GDA2/IO54RSB1
TDI
C2
FF/GEB2/IO70RSB
1
C3
TRST
C4
GFB1/IO87RSB1
GFA0/IO85RSB1
GFA2/IO83RSB1
IO80RSB1
VCCIB1
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
IO67RSB1
GND
GDC1/IO48RSB0
VCC
C5
C6
NC
IO47RSB0
C7
NC
GCC2/IO46RSB0
GCA2/IO44RSB0
GCA0/IO43RSB0
GCB1/IO40RSB0
IO36RSB0
C8
GND
C9
GEA1/IO73RSB1
GNDQ
IO59RSB1
GDC2/IO56RSB1
GND
C10
C11
C12
C13
C14
C15
GEA2/IO71RSB1
IO68RSB1
VCCIB1
GNDQ
TMS
VCC
IO31RSB0
NC
TDO
GBA2/IO28RSB0
NC
Revision 20
4-33
Package Pin Assignments
QN132
Pin Number AGL060 Function
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO60RSB1
IO57RSB1
NC
TCK
VMV1
VPUMP
VJTAG
VCCIB0
NC
NC
GCA1/IO42RSB0
GCC0/IO39RSB0
VCCIB0
IO29RSB0
GNDQ
GBA1/IO27RSB0
GBB0/IO24RSB0
VCC
IO19RSB0
IO16RSB0
IO13RSB0
GAC1/IO10RSB0
NC
GAA0/IO05RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-34
Revision 20
IGLOO Low Power Flash FPGAs
QN132
QN132
QN132
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
A1
A2
GAB2/IO69RSB1
IO130RSB1
VCCIB1
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
NC
A3
GCB2/IO58RSB0
GND
A4
GFC1/IO126RSB1
GFB0/IO123RSB1
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO54RSB0
GCC1/IO51RSB0
GND
A6
A7
GFA1/IO121RSB1
GFC2/IO118RSB1
IO115RSB1
VCC
A8
GBB2/IO43RSB0
VMV0
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEB1/IO110RSB1
GEA0/IO107RSB1
GEC2/IO104RSB1
IO100RSB1
VCC
GAC1/IO05RSB0
GAB0/IO02RSB0
IO68RSB1
GAC2/IO131RSB1
GND
IO26RSB0
IO21RSB0
GND
B2
B3
IO99RSB1
B4
GFC0/IO125RSB1
VCOMPLF
GND
IO13RSB0
IO08RSB0
GND
IO96RSB1
B5
IO94RSB1
B6
IO91RSB1
B7
GFB2/IO119RSB1
IO116RSB1
GND
GAC0/IO04RSB0
GNDQ
IO85RSB1
B8
IO79RSB1
B9
GAA2/IO67RSB1
IO132RSB1
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO109RSB1
VMV1
C2
GDB2/IO71RSB1
TDI
C3
FF/GEB2/IO105RSB1
IO101RSB1
GND
C4
GFB1/IO124RSB1
GFA0/IO122RSB1
GFA2/IO120RSB1
IO117RSB1
VCCIB1
TRST
C5
GDC1/IO61RSB0
VCC
C6
IO98RSB1
IO95RSB1
GND
C7
IO60RSB0
C8
GCC2/IO59RSB0
GCA2/IO57RSB0
GCA0/IO56RSB0
GCB1/IO53RSB0
IO49RSB0
C9
GEA1/IO108RSB1
GNDQ
IO87RSB1
IO81RSB1
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO106RSB1
IO103RSB1
VCCIB1
GNDQ
VCC
TMS
IO97RSB1
IO93RSB1
IO89RSB1
IO44RSB0
TDO
GBA2/IO41RSB0
GDC0/IO62RSB0
Revision 20
4-35
Package Pin Assignments
QN132
Pin Number AGL125 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO83RSB1
VCCIB1
TCK
VMV1
VPUMP
VJTAG
VCCIB0
NC
NC
GCA1/IO55RSB0
GCC0/IO52RSB0
VCCIB0
IO42RSB0
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-36
Revision 20
IGLOO Low Power Flash FPGAs
QN132
QN132
QN132
Pin Number
A1
AGL250 Function
GAB2/IO117UPB3
IO117VPB3
VCCIB3
Pin Number
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
AGL250 Function
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
Pin Number
AGL250 Function
GND
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
A2
IO54PDB1
A3
GCB2/IO52PDB1
GND
A4
GFC1/IO110PDB3
GFB0/IO109NPB3
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO49NDB1
GCC1/IO48PDB1
GND
A6
A7
GFA1/IO108PPB3
GFC2/IO105PPB3
IO103NDB3
VCC
A8
GBB2/IO42PDB1
VMV1
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEA1/IO98PPB3
GEA0/IO98NPB3
GEC2/IO95RSB2
IO91RSB2
GAC1/IO05RSB0
GAB0/IO02RSB0
IO118VDB3
GAC2/IO116UDB3
GND
IO26RSB0
B2
IO21RSB0
VCC
B3
GND
IO90RSB2
B4
GFC0/IO110NDB3
VCOMPLF
GND
IO13RSB0
IO87RSB2
B5
IO08RSB0
IO85RSB2
B6
GND
IO82RSB2
B7
GFB2/IO106PSB3
IO103PDB3
GND
GAC0/IO04RSB0
GNDQ
IO76RSB2
B8
IO70RSB2
B9
GAA2/IO118UDB3
IO116VDB3
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO99NDB3
VMV3
C2
GDB2/IO62RSB2
TDI
C3
FF/GEB2/IO96RSB2
IO92RSB2
GND
C4
GFB1/IO109PPB3
GFA0/IO108NPB3
GFA2/IO107PSB3
IO105NPB3
VCCIB3
TRST
C5
GDC1/IO58UDB1
VCC
C6
IO89RSB2
IO86RSB2
GND
C7
IO54NDB1
C8
IO52NDB1
C9
GEB1/IO99PDB3
GNDQ
GCA2/IO51PPB1
GCA0/IO50NPB1
GCB1/IO49PDB1
IO47NSB1
IO78RSB2
IO72RSB2
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO97RSB2
IO94RSB2
GNDQ
VCCIB2
VCC
TMS
IO88RSB2
IO41NPB1
TDO
IO84RSB2
GBA2/IO41PPB1
GDC0/IO58VDB1
IO80RSB2
Revision 20
4-37
Package Pin Assignments
QN132
Pin Number
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
AGL250 Function
IO74RSB2
VCCIB2
TCK
VMV2
VPUMP
VJTAG
VCCIB1
IO53NSB1
IO51NPB1
GCA1/IO50PPB1
GCC0/IO48NDB1
VCCIB1
IO42NDB1
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-38
Revision 20
IGLOO Low Power Flash FPGAs
VQ100
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-39
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number AGL030 Function
Pin Number AGL030 Function
Pin Number AGL030 Function
1
GND
IO82RSB1
IO81RSB1
IO80RSB1
IO79RSB1
IO78RSB1
IO77RSB1
IO76RSB1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
VCCIB0
2
3
VCCIB1
4
IO49RSB1
IO47RSB1
IO46RSB1
IO45RSB1
IO44RSB1
IO43RSB1
IO42RSB1
TCK
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO75RSB1
IO74RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
IO70RSB1
IO69RSB1
VCC
TDI
TMS
NC
GND
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO12RSB0
IO10RSB0
IO08RSB0
IO07RSB0
IO06RSB0
IO05RSB0
IO04RSB0
IO03RSB0
IO02RSB0
IO01RSB0
IO00RSB0
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO61RSB1
FF/IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
IO56RSB1
IO55RSB1
IO54RSB1
IO53RSB1
IO52RSB1
IO51RSB1
TRST
VJTAG
IO41RSB0
IO40RSB0
IO39RSB0
IO38RSB0
IO37RSB0
IO36RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
GND
VCC
IO31RSB0
IO30RSB0
IO29RSB0
IO28RSB0
4-40
Revision 20
IGLOO Low Power Flash FPGAs
VQ100
VQ100
VQ100
Pin Number AGL060 Function
Pin Number AGL060 Function
Pin Number AGL060 Function
1
GND
GAA2/IO51RSB1
IO52RSB1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO25RSB0
VMV0
2
3
VCCIB1
GNDQ
4
GAB2/IO53RSB1
IO95RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
5
6
GAC2/IO94RSB1
IO93RSB1
7
8
IO92RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
IO17RSB0
TDI
IO15RSB0
GFA0/IO85RSB1
VCCPLF
TMS
IO13RSB0
VMV1
IO11RSB0
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO10RSB0
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
TRST
IO09RSB0
VJTAG
IO08RSB0
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GNDQ
GEA2/IO71RSB1
FF/GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO00RSB0
IO67RSB1
IO66RSB1
GND
IO65RSB1
VCC
IO64RSB1
IO31RSB0
GBC2/IO29RSB0
GBB2/IO27RSB0
IO26RSB0
IO63RSB1
IO62RSB1
IO61RSB1
Revision 20
4-41
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
1
GND
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
IO93RSB1
VCC
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IO42RSB0
GBA2/IO41RSB0
VMV0
2
GAA2/IO67RSB1
IO68RSB1
3
GND
4
GAB2/IO69RSB1
IO132RSB1
VCCIB1
GNDQ
5
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
6
GAC2/IO131RSB1
IO130RSB1
7
8
IO129RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
IO28RSB0
GFA0/IO122RSB1
VCCPLF
TDI
IO25RSB0
TMS
IO22RSB0
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
VMV1
IO19RSB0
GND
VCCIB0
VPUMP
GND
VCCIB1
NC
VCC
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
TDO
IO15RSB0
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO09RSB0
IO07RSB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO106RSB1
FF/GEB2/IO105RSB
1
28
29
30
31
32
33
34
35
GEC2/IO104RSB1
IO102RSB1
IO100RSB1
IO99RSB1
GND
IO97RSB1
VCC
IO96RSB1
IO47RSB0
GBC2/IO45RSB0
GBB2/IO43RSB0
IO95RSB1
IO94RSB1
4-42
Revision 20
IGLOO Low Power Flash FPGAs
VQ100
VQ100
VQ100
Pin Number AGL250 Function
Pin Number AGL250 Function
Pin Number AGL250 Function
1
GND
GAA2/IO118UDB3
IO118VDB3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41PDB1
VMV1
2
3
VCCIB2
GNDQ
4
GAB2/IO117UDB3
IO117VDB3
IO77RSB2
IO74RSB2
IO71RSB2
GDC2/IO63RSB2
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO29RSB0
5
6
GAC2/IO116UDB3
IO116VDB3
7
8
IO112PSB3
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
TCK
IO27RSB0
TDI
IO25RSB0
GFA0/IO108NPB3
VCCPLF
TMS
IO23RSB0
VMV2
IO21RSB0
GFA1/IO108PPB3
GFA2/IO107PSB3
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB3
TDO
IO15RSB0
GFC2/IO105PSB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO60USB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO52NDB1
GCB2/IO52PDB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
VCCIB1
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GNDQ
GEA2/IO97RSB2
FF/GEB2/IO96RSB2
GEC2/IO95RSB2
IO93RSB2
VMV0
IO92RSB2
IO91RSB2
GND
IO90RSB2
VCC
IO88RSB2
IO43NDB1
GBC2/IO43PDB1
GBB2/IO42PSB1
IO41NDB1
IO86RSB2
IO85RSB2
IO84RSB2
Revision 20
4-43
Package Pin Assignments
FG144
A1 Ball Pad Corner
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-44
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL060 Function
Pin Number AGL060 Function
Pin Number AGL060 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO91RSB1
IO92RSB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO84RSB1
GND
A3
GAB0/IO04RSB0
GAB1/IO05RSB0
IO08RSB0
IO93RSB1
VCCPLF
A4
GAA2/IO51RSB1
GAC0/IO06RSB0
GAC1/IO07RSB0
GBC0/IO19RSB0
GBC1/IO20RSB0
GBB2/IO27RSB0
IO18RSB0
GFA0/IO85RSB1
GND
A5
A6
GND
GND
A7
IO11RSB0
GND
A8
VCC
GDC1/IO45RSB0
IO32RSB0
GCC2/IO43RSB0
IO31RSB0
GCB2/IO42RSB0
VCC
A9
IO16RSB0
A10
A11
A12
B1
GBA0/IO23RSB0
GBA1/IO24RSB0
GNDQ
IO28RSB0
GCB1/IO37RSB0
VCC
GAB2/IO53RSB1
GND
B2
E2
GFC0/IO88RSB1
GFC1/IO89RSB1
VCCIB1
GFB2/IO82RSB1
GFC2/IO81RSB1
GEC1/IO77RSB1
VCC
B3
GAA0/IO02RSB0
GAA1/IO03RSB0
IO00RSB0
E3
B4
E4
B5
E5
IO52RSB1
B6
IO10RSB0
E6
VCCIB0
IO34RSB0
IO44RSB0
GDB2/IO55RSB1
GDC0/IO46RSB0
VCCIB0
B7
IO12RSB0
E7
VCCIB0
B8
IO14RSB0
E8
GCC1/IO35RSB0
VCCIB0
B9
GBB0/IO21RSB0
GBB1/IO22RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO40RSB0
IO30RSB0
IO33RSB0
VCC
VMV0
IO95RSB1
GFB0/IO86RSB1
VCOMPLF
GEB1/IO75RSB1
IO78RSB1
VCCIB1
GFA2/IO83RSB1
GAC2/IO94RSB1
VCC
F2
J2
F3
GFB1/IO87RSB1
IO90RSB1
J3
F4
J4
GEC0/IO76RSB1
IO79RSB1
IO80RSB1
VCC
IO01RSB0
F5
GND
J5
IO09RSB0
F6
GND
J6
IO13RSB0
F7
GND
J7
IO15RSB0
F8
GCC0/IO36RSB0
GCB0/IO38RSB0
GND
J8
TCK
IO17RSB0
F9
J9
GDA2/IO54RSB1
TDO
GBA2/IO25RSB0
IO26RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO39RSB0
GCA2/IO41RSB0
GDA1/IO49RSB0
GDB1/IO47RSB0
GBC2/IO29RSB0
Revision 20
4-45
Package Pin Assignments
FG144
Pin Number AGL060 Function
K1
K2
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
GEA2/IO71RSB1
IO65RSB1
IO64RSB1
GND
K3
K4
K5
K6
K7
K8
IO57RSB1
GDC2/IO56RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO50RSB0
GDB0/IO48RSB0
GND
L2
VMV1
L3
FF/GEB2/IO70RSB1
IO67RSB1
VCCIB1
L4
L5
L6
IO62RSB1
IO59RSB1
IO58RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO69RSB1
IO68RSB1
IO66RSB1
IO63RSB1
IO61RSB1
IO60RSB1
NC
TDI
VCCIB1
VPUMP
GNDQ
4-46
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL125 Function
Pin Number AGL125 Function
Pin Number AGL125 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO128RSB1
IO129RSB1
IO130RSB1
GAA2/IO67RSB1
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO43RSB0
IO28RSB0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO121RSB1
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO11RSB0
VCCPLF
A4
GFA0/IO122RSB1
GND
A5
A6
GND
GND
A7
IO18RSB0
GND
A8
VCC
GDC1/IO61RSB0
IO48RSB0
A9
IO25RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
GCC2/IO59RSB0
IO47RSB0
IO44RSB0
GCB1/IO53RSB0
VCC
GCB2/IO58RSB0
VCC
GAB2/IO69RSB1
GND
B2
E2
GFC0/IO125RSB1
GFC1/IO126RSB1
VCCIB1
GFB2/IO119RSB1
GFC2/IO118RSB1
GEC1/IO112RSB1
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO08RSB0
E3
B4
E4
B5
E5
IO68RSB1
B6
IO14RSB0
E6
VCCIB0
IO50RSB0
B7
IO19RSB0
E7
VCCIB0
IO60RSB0
B8
IO22RSB0
E8
GCC1/IO51RSB0
VCCIB0
GDB2/IO71RSB1
GDC0/IO62RSB0
VCCIB0
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO56RSB0
IO46RSB0
IO49RSB0
VMV0
VCC
IO132RSB1
GFA2/IO120RSB1
GAC2/IO131RSB1
VCC
GFB0/IO123RSB1
VCOMPLF
GEB1/IO110RSB1
IO115RSB1
VCCIB1
F2
J2
F3
GFB1/IO124RSB1
IO127RSB1
GND
J3
F4
J4
GEC0/IO111RSB1
IO116RSB1
IO117RSB1
VCC
IO10RSB0
F5
J5
IO12RSB0
F6
GND
J6
IO21RSB0
F7
GND
J7
IO24RSB0
F8
GCC0/IO52RSB0
GCB0/IO54RSB0
GND
J8
TCK
IO27RSB0
F9
J9
GDA2/IO70RSB1
TDO
GBA2/IO41RSB0
IO42RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO55RSB0
GCA2/IO57RSB0
GDA1/IO65RSB0
GDB1/IO63RSB0
GBC2/IO45RSB0
Revision 20
4-47
Package Pin Assignments
FG144
Pin Number AGL125 Function
K1
K2
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
GEA2/IO106RSB1
IO100RSB1
IO98RSB1
GND
K3
K4
K5
K6
K7
K8
IO73RSB1
GDC2/IO72RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO66RSB0
GDB0/IO64RSB0
GND
L2
VMV1
L3
FF/GEB2/IO105RSB1
IO102RSB1
VCCIB1
L4
L5
L6
IO95RSB1
IO85RSB1
IO74RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO104RSB1
IO103RSB1
IO101RSB1
IO97RSB1
IO94RSB1
IO86RSB1
IO75RSB1
TDI
VCCIB1
VPUMP
GNDQ
4-48
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL250 Function
Pin Number AGL250 Function
Pin Number AGL250 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO112NDB3
IO112PDB3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO108PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
IO116VDB3
VCCPLF
A4
GAA2/IO118UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO42PDB1
IO42NDB1
GFA0/IO108NPB3
GND
A5
A6
GND
GND
A7
IO29RSB0
GND
A8
VCC
GDC1/IO58UPB1
IO53NDB1
GCC2/IO53PDB1
IO52NDB1
GCB2/IO52PDB1
VCC
A9
IO33RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
IO43NPB1
GCB1/IO49PPB1
VCC
GAB2/IO117UDB3
GND
B2
E2
GFC0/IO110NDB3
GFC1/IO110PDB3
VCCIB3
GFB2/IO106PDB3
GFC2/IO105PSB3
GEC1/IO100PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO118VPB3
B6
IO19RSB0
E6
VCCIB0
IO79RSB2
B7
IO22RSB0
E7
VCCIB0
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
VCCIB1
GDB2/IO62RSB2
GDC0/IO58VPB1
VCCIB1
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO50NDB1
IO51NDB1
IO54PSB1
VMV1
VCC
IO117VDB3
GFA2/IO107PPB3
GAC2/IO116UDB3
VCC
GFB0/IO109NPB3
VCOMPLF
GEB1/IO99PDB3
IO106NDB3
VCCIB3
F2
J2
F3
GFB1/IO109PPB3
IO107NPB3
GND
J3
F4
J4
GEC0/IO100NDB3
IO88RSB2
IO12RSB0
F5
J5
IO17RSB0
F6
GND
J6
IO81RSB2
IO24RSB0
F7
GND
J7
VCC
IO31RSB0
F8
GCC0/IO48NDB1
GCB0/IO49NPB1
GND
J8
TCK
IO34RSB0
F9
J9
GDA2/IO61RSB2
TDO
GBA2/IO41PDB1
IO41NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO50PDB1
GCA2/IO51PDB1
GDA1/IO60UDB1
GDB1/IO59UDB1
GBC2/IO43PPB1
Revision 20
4-49
Package Pin Assignments
FG144
Pin Number AGL250 Function
K1
K2
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
GEA2/IO97RSB2
IO90RSB2
IO84RSB2
GND
K3
K4
K5
K6
K7
K8
IO66RSB2
GDC2/IO63RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO60VDB1
GDB0/IO59VDB1
GND
L2
VMV3
L3
FF/GEB2/IO96RSB2
IO91RSB2
VCCIB2
L4
L5
L6
IO82RSB2
IO80RSB2
IO72RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO95RSB2
IO92RSB2
IO89RSB2
IO87RSB2
IO85RSB2
IO78RSB2
IO76RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-50
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO149NDB3
IO149PDB3
IO153VDB3
GAA2/IO155UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO54RSB0
GBC1/IO55RSB0
GBB2/IO61PDB1
IO61NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO145PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
VCCPLF
A4
GFA0/IO145NPB3
GND
A5
A6
GND
GND
A7
IO30RSB0
GND
A8
VCC
GDC1/IO77UPB1
IO72NDB1
A9
IO34RSB0
A10
A11
A12
B1
GBA0/IO58RSB0
GBA1/IO59RSB0
GNDQ
GCC2/IO72PDB1
IO71NDB1
IO62NPB1
GCB1/IO68PPB1
VCC
GCB2/IO71PDB1
VCC
GAB2/IO154UDB3
GND
B2
E2
GFC0/IO147NDB3
GFC1/IO147PDB3
VCCIB3
GFB2/IO143PDB3
GFC2/IO142PSB3
GEC1/IO137PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO155VPB3
B6
IO19RSB0
E6
VCCIB0
IO75PDB1
B7
IO23RSB0
E7
VCCIB0
IO75NDB1
B8
IO31RSB0
E8
GCC1/IO67PDB1
VCCIB1
GDB2/IO81RSB2
GDC0/IO77VPB1
VCCIB1
B9
GBB0/IO56RSB0
GBB1/IO57RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO69NDB1
IO70NDB1
IO73PSB1
VMV1
VCC
IO154VDB3
GFA2/IO144PPB3
GAC2/IO153UDB3
VCC
GFB0/IO146NPB3
VCOMPLF
GEB1/IO136PDB3
IO143NDB3
VCCIB3
F2
J2
F3
GFB1/IO146PPB3
IO144NPB3
GND
J3
F4
J4
GEC0/IO137NDB3
IO125RSB2
IO116RSB2
VCC
IO12RSB0
F5
J5
IO17RSB0
F6
GND
J6
IO25RSB0
F7
GND
J7
IO32RSB0
F8
GCC0/IO67NDB1
GCB0/IO68NPB1
GND
J8
TCK
IO53RSB0
F9
J9
GDA2/IO80RSB2
TDO
GBA2/IO60PDB1
IO60NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO69PDB1
GCA2/IO70PDB1
GDA1/IO79UDB1
GDB1/IO78UDB1
GBC2/IO62PPB1
Revision 20
4-51
Package Pin Assignments
FG144
Pin Number AGL400 Function
K1
K2
GEB0/IO136NDB3
GEA1/IO135PDB3
GEA0/IO135NDB3
GEA2/IO134RSB2
IO127RSB2
IO121RSB2
GND
K3
K4
K5
K6
K7
K8
IO104RSB2
GDC2/IO82RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO79VDB1
GDB0/IO78VDB1
GND
L2
VMV3
L3
FF/GEB2/IO133RSB2
IO128RSB2
VCCIB2
L4
L5
L6
IO119RSB2
IO114RSB2
IO110RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO132RSB2
IO129RSB2
IO126RSB2
IO124RSB2
IO122RSB2
IO117RSB2
IO115RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-52
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO169PDB3
IO169NDB3
IO172NDB3
GAA2/IO174PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO54RSB0
GBC1/IO55RSB0
GBB2/IO61PDB1
IO61NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO162PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO162NPB3
GND
A5
A6
GND
GND
A7
IO34RSB0
GND
A8
VCC
GDC1/IO86PPB1
IO74NDB1
A9
IO50RSB0
A10
A11
A12
B1
GBA0/IO58RSB0
GBA1/IO59RSB0
GNDQ
GCC2/IO74PDB1
IO73NDB1
IO62NPB1
GCB1/IO70PPB1
VCC
GCB2/IO73PDB1
VCC
GAB2/IO173PDB3
GND
B2
E2
GFC0/IO164NDB3
GFC1/IO164PDB3
VCCIB3
GFB2/IO160PDB3
GFC2/IO159PSB3
GEC1/IO146PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO174NPB3
VCCIB0
B6
IO19RSB0
E6
IO80PDB1
B7
IO31RSB0
E7
VCCIB0
IO80NDB1
B8
IO39RSB0
E8
GCC1/IO69PDB1
VCCIB1
GDB2/IO90RSB2
GDC0/IO86NPB1
VCCIB1
B9
GBB0/IO56RSB0
GBB1/IO57RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO71NDB1
IO72NDB1
IO84PSB1
VMV1
VCC
IO173NDB3
GFA2/IO161PPB3
GAC2/IO172PDB3
VCC
GFB0/IO163NPB3
VCOMPLF
GEB1/IO145PDB3
IO160NDB3
VCCIB3
F2
J2
F3
GFB1/IO163PPB3
IO161NPB3
GND
J3
F4
J4
GEC0/IO146NDB3
IO129RSB2
IO131RSB2
VCC
IO16RSB0
F5
J5
IO25RSB0
F6
GND
J6
IO28RSB0
F7
GND
J7
IO42RSB0
F8
GCC0/IO69NDB1
GCB0/IO70NPB1
GND
J8
TCK
IO45RSB0
F9
J9
GDA2/IO89RSB2
TDO
GBA2/IO60PDB1
IO60NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO71PDB1
GCA2/IO72PDB1
GDA1/IO88PDB1
GDB1/IO87PDB1
GBC2/IO62PPB1
Revision 20
4-53
Package Pin Assignments
FG144
Pin Number AGL600 Function
K1
K2
GEB0/IO145NDB3
GEA1/IO144PDB3
GEA0/IO144NDB3
GEA2/IO143RSB2
IO119RSB2
IO111RSB2
GND
K3
K4
K5
K6
K7
K8
IO94RSB2
GDC2/IO91RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO88NDB1
GDB0/IO87NDB1
GND
L2
VMV3
L3
FF/GEB2/IO142RSB2
IO136RSB2
VCCIB2
L4
L5
L6
IO115RSB2
IO103RSB2
IO97RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO141RSB2
IO138RSB2
IO123RSB2
IO126RSB2
IO134RSB2
IO108RSB2
IO99RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-54
Revision 20
IGLOO Low Power Flash FPGAs
FG144
FG144
FG144
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO213PDB3
IO213NDB3
IO223NDB3
GAA2/IO225PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO72RSB0
GBC1/IO73RSB0
GBB2/IO79PDB1
IO79NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO207PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO207NPB3
GND
A5
A6
GND
GND
A7
IO44RSB0
GND
A8
VCC
GDC1/IO111PPB1
IO96NDB1
A9
IO69RSB0
A10
A11
A12
B1
GBA0/IO76RSB0
GBA1/IO77RSB0
GNDQ
GCC2/IO96PDB1
IO95NDB1
IO80NPB1
GCB1/IO92PPB1
VCC
GCB2/IO95PDB1
VCC
GAB2/IO224PDB3
GND
B2
E2
GFC0/IO209NDB3
GFC1/IO209PDB3
VCCIB3
GFB2/IO205PDB3
GFC2/IO204PSB3
GEC1/IO190PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO225NPB3
VCCIB0
B6
IO26RSB0
E6
IO105PDB1
IO105NDB1
GDB2/IO115RSB2
GDC0/IO111NPB1
VCCIB1
B7
IO35RSB0
E7
VCCIB0
B8
IO60RSB0
E8
GCC1/IO91PDB1
VCCIB1
B9
GBB0/IO74RSB0
GBB1/IO75RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO93NDB1
IO94NDB1
IO101PSB1
VCC
VMV1
IO224NDB3
GFA2/IO206PPB3
GAC2/IO223PDB3
VCC
GFB0/IO208NPB3
VCOMPLF
GEB1/IO189PDB3
IO205NDB3
VCCIB3
F2
J2
F3
GFB1/IO208PPB3
IO206NPB3
GND
J3
F4
J4
GEC0/IO190NDB3
IO160RSB2
IO157RSB2
VCC
IO16RSB0
F5
J5
IO29RSB0
F6
GND
J6
IO32RSB0
F7
GND
J7
IO63RSB0
F8
GCC0/IO91NDB1
GCB0/IO92NPB1
GND
J8
TCK
IO66RSB0
F9
J9
GDA2/IO114RSB2
TDO
GBA2/IO78PDB1
IO78NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO93PDB1
GCA2/IO94PDB1
GDA1/IO113PDB1
GDB1/IO112PDB1
GBC2/IO80PPB1
Revision 20
4-55
Package Pin Assignments
FG144
Pin Number AGL1000 Function
K1
K2
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
GEA2/IO187RSB2
IO169RSB2
IO152RSB2
GND
K3
K4
K5
K6
K7
K8
IO117RSB2
GDC2/IO116RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO113NDB1
GDB0/IO112NDB1
GND
L2
VMV3
L3
FF/GEB2/IO186RSB2
IO172RSB2
VCCIB2
L4
L5
L6
IO153RSB2
IO144RSB2
IO140RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO185RSB2
IO173RSB2
IO168RSB2
IO161RSB2
IO156RSB2
IO145RSB2
IO141RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-56
Revision 20
IGLOO Low Power Flash FPGAs
FG256
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-57
Package Pin Assignments
FG256
FG256
FG256
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
A1
A2
GND
C7
C8
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO45RSB0
GBC0/IO54RSB0
IO48RSB0
VMV0
E13
E14
E15
E16
F1
GBC2/IO62PDB1
IO65RSB1
IO52RSB0
IO66PDB1
IO150NDB3
IO149NPB3
IO09RSB0
IO152UDB3
VCCIB3
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
A3
C9
A4
C10
C11
C12
C13
C14
C15
C16
D1
A5
A6
IO17RSB0
F2
A7
IO22RSB0
F3
A8
IO28RSB0
F4
A9
IO34RSB0
IO61NPB1
IO63PDB1
IO151VDB3
IO151UDB3
GAC2/IO153UDB3
IO06RSB0
GNDQ
F5
A10
A11
A12
A13
A14
A15
A16
B1
IO37RSB0
F6
GND
IO41RSB0
F7
VCC
IO43RSB0
D2
F8
VCC
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
D3
F9
VCC
D4
F10
F11
F12
F13
F14
F15
F16
G1
VCC
D5
GND
D6
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO46RSB0
GNDQ
VCCIB1
GAB2/IO154UDB3
GAA2/IO155UDB3
IO12RSB0
D7
IO62NDB1
IO49RSB0
IO64PPB1
IO66NDB1
IO148NDB3
IO148PDB3
IO149PPB3
GFC1/IO147PPB3
VCCIB3
B2
D8
B3
D9
B4
GAB1/IO03RSB0
IO13RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B5
B6
IO14RSB0
G2
B7
IO21RSB0
IO47RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
IO150PDB3
IO08RSB0
IO153VDB3
IO152VDB3
VMV0
G3
B8
IO27RSB0
G4
B9
IO32RSB0
G5
B10
B11
B12
B13
B14
B15
B16
C1
IO38RSB0
G6
VCC
IO42RSB0
G7
GND
GBC1/IO55RSB0
GBB0/IO56RSB0
IO44RSB0
E2
G8
GND
E3
G9
GND
E4
G10
G11
G12
G13
G14
G15
G16
H1
GND
GBA2/IO60PDB1
IO60NDB1
E5
VCC
E6
VCCIB0
VCCIB1
IO154VDB3
E7
VCCIB0
GCC1/IO67PPB1
IO64NPB1
IO73PDB1
IO73NDB1
GFB0/IO146NPB3
GFA0/IO145NDB3
C2
IO155VDB3
E8
IO25RSB0
IO31RSB0
VCCIB0
C3
IO11RSB0
E9
C4
IO07RSB0
E10
E11
E12
C5
GAC0/IO04RSB0
GAC1/IO05RSB0
VCCIB0
C6
VMV1
H2
4-58
Revision 20
IGLOO Low Power Flash FPGAs
FG256
FG256
FG256
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
GFB1/IO146PPB3
VCOMPLF
GFC0/IO147NPB3
VCC
K9
K10
K11
K12
K13
K14
K15
K16
L1
GND
GND
M15
M16
N1
GDC1/IO77UDB1
IO75NDB1
VCC
IO140NDB3
IO138PPB3
GEC1/IO137PPB3
IO131RSB2
GNDQ
VCCIB1
N2
GND
IO71NPB1
IO74RSB1
IO72NPB1
IO70NDB1
IO142NDB3
IO141NPB3
IO125RSB2
IO139RSB3
VCCIB3
N3
GND
N4
GND
N5
GND
N6
GEA2/IO134RSB2
IO117RSB2
IO111RSB2
IO99RSB2
VCC
N7
GCC0/IO67NPB1
GCB1/IO68PPB1
GCA0/IO69NPB1
NC
L2
N8
L3
N9
L4
N10
N11
N12
N13
N14
N15
N16
P1
IO94RSB2
L5
IO87RSB2
GCB0/IO68NPB1
GFA2/IO144PPB3
GFA1/IO145PDB3
VCCPLF
L6
GND
GNDQ
L7
VCC
IO93RSB2
J2
L8
VCC
VJTAG
J3
L9
VCC
GDC0/IO77VDB1
GDA1/IO79UDB1
GEB1/IO136PDB3
GEB0/IO136NDB3
VMV2
J4
IO143NDB3
GFB2/IO143PDB3
VCC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
VCC
J5
GND
J6
VCCIB1
P2
J7
GND
GDB0/IO78VPB1
IO76VDB1
IO76UDB1
IO75PDB1
IO140PDB3
IO130RSB2
IO138NPB3
GEC0/IO137NPB3
VMV3
P3
J8
GND
P4
IO129RSB2
IO128RSB2
IO122RSB2
IO115RSB2
IO110RSB2
IO98RSB2
J9
GND
P5
J10
J11
J12
J13
J14
J15
J16
K1
GND
P6
VCC
P7
GCB2/IO71PPB1
GCA1/IO69PPB1
GCC2/IO72PPB1
NC
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO95RSB2
IO88RSB2
GCA2/IO70PDB1
GFC2/IO142PDB3
IO144NPB3
IO141PPB3
IO120RSB2
VCCIB3
VCCIB2
IO84RSB2
VCCIB2
TCK
K2
IO108RSB2
IO101RSB2
VCCIB2
VPUMP
K3
TRST
K4
GDA0/IO79VDB1
GEA1/IO135PDB3
GEA0/IO135NDB3
IO127RSB2
GEC2/IO132RSB2
K5
VCCIB2
K6
VCC
VMV2
R2
K7
GND
IO83RSB2
GDB1/IO78UPB1
R3
K8
GND
R4
Revision 20
4-59
Package Pin Assignments
FG256
Pin Number AGL400 Function
R5
R6
IO123RSB2
IO118RSB2
IO112RSB2
IO106RSB2
IO100RSB2
IO96RSB2
IO89RSB2
IO85RSB2
GDB2/IO81RSB2
TDI
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
NC
TDO
GND
T2
IO126RSB2
FF/GEB2/IO133RSB2
IO124RSB2
IO116RSB2
IO113RSB2
IO107RSB2
IO105RSB2
IO102RSB2
IO97RSB2
IO92RSB2
GDC2/IO82RSB2
IO86RSB2
GDA2/IO80RSB2
TMS
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
GND
4-60
Revision 20
IGLOO Low Power Flash FPGAs
FG256
FG256
FG256
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO11RSB0
C7
C8
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
E13
E14
E15
E16
F1
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
IO66PDB1
IO166NDB3
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
A3
C9
A4
C10
C11
C12
C13
C14
C15
C16
D1
A5
A6
IO16RSB0
F2
A7
IO18RSB0
F3
A8
IO28RSB0
F4
A9
IO34RSB0
IO61NPB1
IO63PDB1
IO171NDB3
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
F5
A10
A11
A12
A13
A14
A15
A16
B1
IO37RSB0
F6
GND
IO41RSB0
F7
VCC
IO43RSB0
D2
F8
VCC
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
D3
F9
VCC
D4
F10
F11
F12
F13
F14
F15
F16
G1
VCC
D5
GND
D6
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO45RSB0
GNDQ
VCCIB1
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
D7
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
B2
D8
B3
D9
B4
GAB1/IO03RSB0
IO13RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B5
B6
IO14RSB0
G2
B7
IO21RSB0
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
G3
B8
IO27RSB0
G4
B9
IO32RSB0
G5
B10
B11
B12
B13
B14
B15
B16
C1
IO38RSB0
G6
VCC
IO42RSB0
G7
GND
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
E2
G8
GND
E3
G9
GND
E4
G10
G11
G12
G13
G14
G15
G16
H1
GND
GBA2/IO60PDB1
IO60NDB1
E5
VCC
E6
VCCIB0
VCCIB1
IO173NDB3
IO174NDB3
VMV3
E7
VCCIB0
GCC1/IO69PPB1
IO65NPB1
IO75PDB1
IO75NDB1
GFB0/IO163NPB3
GFA0/IO162NDB3
C2
E8
IO25RSB0
IO31RSB0
VCCIB0
C3
E9
C4
IO07RSB0
E10
E11
E12
C5
GAC0/IO04RSB0
GAC1/IO05RSB0
VCCIB0
C6
VMV1
H2
Revision 20
4-61
Package Pin Assignments
FG256
FG256
FG256
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
GFB1/IO163PPB3
VCOMPLF
GFC0/IO164NPB3
VCC
K9
K10
K11
K12
K13
K14
K15
K16
L1
GND
GND
M15
M16
N1
GDC1/IO86PDB1
IO84NDB1
VCC
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
VCCIB1
N2
GND
IO73NPB1
IO80NPB1
IO74NPB1
IO72NDB1
IO159NDB3
IO156NPB3
IO151PPB3
IO158PSB3
VCCIB3
N3
GND
N4
GND
N5
GND
N6
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
VCC
N7
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
GCB0/IO70NPB1
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
L2
N8
L3
N9
L4
N10
N11
N12
N13
N14
N15
N16
P1
L5
L6
GND
GNDQ
L7
VCC
IO92RSB2
J2
L8
VCC
VJTAG
J3
L9
VCC
GDC0/IO86NDB1
GDA1/IO88PDB1
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
J4
IO160NDB3
GFB2/IO160PDB3
VCC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
VCC
J5
GND
J6
VCCIB1
P2
J7
GND
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
VMV3
P3
J8
GND
P4
IO138RSB2
IO136RSB2
IO131RSB2
IO124RSB2
IO119RSB2
IO107RSB2
IO104RSB2
IO97RSB2
J9
GND
P5
J10
J11
J12
J13
J14
J15
J16
K1
GND
P6
VCC
P7
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
GCA2/IO72PDB1
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
VCCIB2
VMV1
VCCIB2
TCK
K2
IO117RSB2
IO110RSB2
VCCIB2
VPUMP
K3
TRST
K4
GDA0/IO88NDB1
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
K5
VCCIB2
K6
VCC
VMV2
R2
K7
GND
IO94RSB2
GDB1/IO87PPB1
R3
K8
GND
R4
4-62
Revision 20
IGLOO Low Power Flash FPGAs
FG256
Pin Number AGL600 Function
R5
R6
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO96RSB2
GDB2/IO90RSB2
TDI
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO137RSB2
FF/GEB2/IO142RSB2
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
GDC2/IO91RSB2
IO93RSB2
GDA2/IO89RSB2
TMS
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
GND
Revision 20
4-63
Package Pin Assignments
FG256
FG256
FG256
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
C7
C8
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
E13
E14
E15
E16
F1
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
A3
C9
A4
C10
C11
C12
C13
C14
C15
C16
D1
A5
A6
IO22RSB0
F2
A7
IO28RSB0
F3
A8
IO35RSB0
F4
A9
IO45RSB0
IO78NDB1
IO81NDB1
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
F5
A10
A11
A12
A13
A14
A15
A16
B1
IO50RSB0
F6
GND
IO55RSB0
F7
VCC
IO61RSB0
D2
F8
VCC
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
D3
F9
VCC
D4
F10
F11
F12
F13
F14
F15
F16
G1
VCC
D5
GND
D6
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
VCCIB1
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
D7
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
IO210PSB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
B2
D8
B3
D9
B4
GAB1/IO03RSB0
IO17RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B5
B6
IO21RSB0
G2
B7
IO27RSB0
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NSB1
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
G3
B8
IO34RSB0
G4
B9
IO44RSB0
G5
B10
B11
B12
B13
B14
B15
B16
C1
IO51RSB0
G6
VCC
IO57RSB0
G7
GND
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
E2
G8
GND
E3
G9
GND
E4
G10
G11
G12
G13
G14
G15
G16
H1
GND
GBA2/IO78PDB1
IO81PDB1
E5
VCC
E6
VCCIB0
VCCIB1
IO224NDB3
IO225NDB3
VMV3
E7
VCCIB0
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
IO88NDB1
GFB0/IO208NPB3
GFA0/IO207NDB3
C2
E8
IO38RSB0
IO47RSB0
VCCIB0
C3
E9
C4
IO11RSB0
E10
E11
E12
C5
GAC0/IO04RSB0
GAC1/IO05RSB0
VCCIB0
C6
VMV1
H2
4-64
Revision 20
IGLOO Low Power Flash FPGAs
FG256
FG256
FG256
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
K9
K10
K11
K12
K13
K14
K15
K16
L1
GND
GND
M15
M16
N1
GDC1/IO111PDB1
IO107NDB1
IO194PSB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
VCC
VCCIB1
N2
GND
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
N3
GND
N4
GND
N5
GND
N6
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
VCC
N7
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
GFA2/IO206PSB3
GFA1/IO207PDB3
VCCPLF
L2
N8
L3
N9
L4
N10
N11
N12
N13
N14
N15
N16
P1
L5
L6
GND
L7
VCC
IO110PDB1
VJTAG
J2
L8
VCC
J3
L9
VCC
GDC0/IO111NDB1
GDA1/IO113PDB1
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
J4
IO205NDB3
GFB2/IO205PDB3
VCC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
VCC
J5
GND
J6
VCCIB1
P2
J7
GND
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
IO197NSB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
P3
J8
GND
P4
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
J9
GND
P5
J10
J11
J12
J13
J14
J15
J16
K1
GND
P6
VCC
P7
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PSB1
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
VCCIB2
VCCIB2
TCK
K2
IO147RSB2
IO136RSB2
VCCIB2
VPUMP
K3
TRST
K4
GDA0/IO113NDB1
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
K5
VCCIB2
K6
VCC
VMV2
R2
K7
GND
IO110NDB1
GDB1/IO112PPB1
R3
K8
GND
R4
Revision 20
4-65
Package Pin Assignments
FG256
Pin Number AGL1000 Function
R5
R6
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO183RSB2
FF/GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
GND
4-66
Revision 20
IGLOO Low Power Flash FPGAs
FG484
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 20
4-67
Package Pin Assignments
FG484
FG484
FG484
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
A1
A2
GND
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
NC
B7
B8
NC
NC
A3
VCCIB0
NC
NC
B9
NC
A4
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
NC
A5
NC
NC
NC
A6
IO15RSB0
IO18RSB0
NC
NC
NC
A7
VCCIB1
GND
NC
A8
NC
A9
NC
GND
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
IO23RSB0
IO29RSB0
IO35RSB0
IO36RSB0
NC
AB2
GND
NC
AB3
VCCIB2
NC
NC
AB4
NC
AB5
NC
NC
AB6
IO121RSB2
IO119RSB2
IO114RSB2
IO109RSB2
NC
NC
NC
AB7
VCCIB1
GND
VCCIB3
NC
IO50RSB0
IO51RSB0
NC
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
NC
C3
NC
VCCIB0
GND
IO104RSB2
IO103RSB2
NC
C4
NC
C5
GND
NC
GND
C6
GND
NC
C7
NC
VCCIB3
NC
IO91RSB2
IO90RSB2
NC
C8
VCC
VCC
NC
C9
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
NC
NC
NC
NC
VCCIB2
GND
NC
NC
NC
NC
GND
VCC
VCC
NC
NC
GND
NC
B2
VCCIB3
NC
NC
B3
NC
NC
B4
NC
GND
NC
NC
B5
NC
NC
B6
NC
NC
4-68
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
C21
C22
D1
NC
VCCIB1
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO38RSB0
IO42RSB0
GBC1/IO55RSB0
GBB0/IO56RSB0
IO44RSB0
GBA2/IO60PDB1
IO60NDB1
GND
G5
G6
IO151UDB3
GAC2/IO153UDB3
IO06RSB0
GNDQ
NC
G7
D2
NC
G8
D3
NC
G9
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO46RSB0
GNDQ
D4
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
IO17RSB0
IO22RSB0
IO28RSB0
IO34RSB0
IO37RSB0
IO41RSB0
IO43RSB0
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
D6
D7
NC
D8
NC
D9
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
NC
IO47RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
NC
F3
NC
F4
IO154VDB3
IO155VDB3
IO11RSB0
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO45RSB0
GBC0/IO54RSB0
IO48RSB0
VMV0
F5
F6
F7
NC
F8
NC
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO150PDB3
IO08RSB0
IO153VDB3
IO152VDB3
VMV0
NC
H5
NC
H6
NC
H7
E2
NC
H8
E3
GND
H9
VCCIB0
E4
GAB2/IO154UDB3
GAA2/IO155UDB3
IO12RSB0
GAB1/IO03RSB0
IO13RSB0
IO14RSB0
IO21RSB0
IO27RSB0
IO32RSB0
IO61NPB1
IO63PDB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO25RSB0
IO31RSB0
VCCIB0
E6
E7
NC
E8
NC
VCCIB0
E9
NC
VMV1
E10
E11
E12
G2
NC
GBC2/IO62PDB1
IO65RSB1
IO52RSB0
G3
NC
G4
IO151VDB3
Revision 20
4-69
Package Pin Assignments
FG484
FG484
FG484
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
H19
H20
H21
H22
J1
IO66PDB1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
M3
M4
NC
GFA2/IO144PPB3
GFA1/IO145PDB3
VCCPLF
IO143NDB3
GFB2/IO143PDB3
VCC
GND
NC
GND
M5
NC
VCC
M6
NC
VCCIB1
M7
J2
NC
GCC1/IO67PPB1
M8
J3
NC
IO64NPB1
M9
J4
IO150NDB3
IO149NPB3
IO09RSB0
IO152UDB3
VCCIB3
GND
IO73PDB1
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
IO73NDB1
GND
J6
NC
GND
J7
NC
GND
J8
NC
VCC
J9
NC
GCB2/IO71PPB1
GCA1/IO69PPB1
GCC2/IO72PPB1
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
NC
VCC
L3
NC
VCC
L4
GFB0/IO146NPB3
VCC
L5
GFA0/IO145NDB3
GCA2/IO70PDB1
NC
GND
L6
GFB1/IO146PPB3
VCCIB1
IO62NDB1
IO49RSB0
IO64PPB1
IO66NDB1
NC
L7
VCOMPLF
NC
L8
GFC0/IO147NPB3
NC
L9
VCC
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
NC
GND
N3
NC
GND
N4
GFC2/IO142PDB3
IO144NPB3
IO141PPB3
IO120RSB2
VCCIB3
VCC
NC
GND
N5
NC
VCC
N6
NC
GCC0/IO67NPB1
N7
K2
NC
GCB1/IO68PPB1
N8
K3
NC
GCA0/IO69NPB1
N9
K4
IO148NDB3
IO148PDB3
IO149PPB3
GFC1/IO147PPB3
VCCIB3
VCC
NC
N10
N11
N12
N13
N14
N15
N16
GND
K5
GCB0/IO68NPB1
GND
K6
NC
NC
NC
NC
NC
GND
K7
GND
K8
VCC
K9
VCCIB1
IO71NPB1
K10
GND
M2
4-70
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL400 Function
Pin Number AGL400 Function
Pin Number AGL400 Function
N17
N18
N19
N20
N21
N22
P1
IO74RSB1
IO72NPB1
IO70NDB1
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB2
VCCIB2
U1
U2
NC
NC
IO108RSB2
IO101RSB2
VCCIB2
U3
NC
U4
GEB1/IO136PDB3
GEB0/IO136NDB3
VMV2
NC
U5
NC
VCCIB2
U6
NC
VMV2
U7
IO129RSB2
IO128RSB2
IO122RSB2
IO115RSB2
IO110RSB2
IO98RSB2
IO95RSB2
IO88RSB2
IO84RSB2
TCK
P2
NC
IO83RSB2
GDB1/IO78UPB1
GDC1/IO77UDB1
IO75NDB1
VCC
U8
P3
NC
U9
P4
IO142NDB3
IO141NPB3
IO125RSB2
IO139RSB3
VCCIB3
GND
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
NC
P8
NC
P9
NC
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
NC
VCC
T3
NC
VPUMP
VCC
T4
IO140NDB3
IO138PPB3
GEC1/IO137PPB3
IO131RSB2
GNDQ
TRST
VCC
T5
GDA0/IO79VDB1
NC
GND
T6
VCCIB1
GDB0/IO78VPB1
IO76VDB1
IO76UDB1
IO75PDB1
NC
T7
NC
T8
NC
T9
GEA2/IO134RSB2
IO117RSB2
IO111RSB2
IO99RSB2
IO94RSB2
IO87RSB2
GNDQ
NC
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO135PDB3
GEA0/IO135NDB3
IO127RSB2
GEC2/IO132RSB2
IO123RSB2
IO118RSB2
IO112RSB2
IO106RSB2
IO100RSB2
IO96RSB2
IO89RSB2
NC
V5
NC
V6
NC
V7
R2
NC
IO93RSB2
VJTAG
V8
R3
VCC
V9
R4
IO140PDB3
IO130RSB2
IO138NPB3
GEC0/IO137NPB3
VMV3
GDC0/IO77VDB1
GDA1/IO79UDB1
NC
V10
V11
V12
V13
V14
R5
R6
R7
NC
R8
NC
Revision 20
4-71
Package Pin Assignments
FG484
FG484
Pin Number AGL400 Function
Pin Number AGL400 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO85RSB2
Y7
NC
VCC
VCC
NC
GDB2/IO81RSB2
Y8
TDI
Y9
NC
TDO
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
NC
GND
NC
NC
NC
NC
VCC
VCC
NC
NC
W2
NC
W3
NC
NC
W4
GND
GND
NC
W5
IO126RSB2
FF/GEB2/IO133RSB2
IO124RSB2
IO116RSB2
IO113RSB2
IO107RSB2
IO105RSB2
IO102RSB2
IO97RSB2
IO92RSB2
GDC2/IO82RSB2
IO86RSB2
GDA2/IO80RSB2
TMS
W6
NC
W7
NC
W8
VCCIB1
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB3
NC
Y2
Y3
NC
Y4
NC
Y5
GND
Y6
NC
4-72
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
A1
A2
GND
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
IO101RSB2
NC
B7
B8
IO12RSB0
NC
A3
VCCIB0
NC
B9
NC
A4
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO17RSB0
NC
A5
NC
NC
A6
IO09RSB0
IO15RSB0
NC
NC
NC
A7
VCCIB1
GND
IO36RSB0
NC
A8
A9
NC
GND
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
IO22RSB0
IO23RSB0
IO29RSB0
IO35RSB0
NC
AB2
GND
IO47RSB0
IO49RSB0
NC
AB3
VCCIB2
NC
AB4
AB5
NC
NC
AB6
IO130RSB2
IO128RSB2
IO122RSB2
IO116RSB2
NC
NC
NC
AB7
VCCIB1
GND
VCCIB3
NC
IO46RSB0
IO48RSB0
NC
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
NC
C3
NC
VCCIB0
GND
IO113RSB2
IO112RSB2
NC
C4
NC
C5
GND
NC
GND
C6
GND
NC
C7
NC
VCCIB3
NC
IO100RSB2
IO95RSB2
NC
C8
VCC
VCC
NC
C9
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
NC
NC
NC
IO135RSB2
IO133RSB2
NC
VCCIB2
GND
NC
NC
GND
VCC
VCC
NC
NC
GND
NC
B2
VCCIB3
NC
NC
B3
NC
NC
B4
NC
GND
NC
NC
B5
NC
NC
B6
IO08RSB0
NC
Revision 20
4-73
Package Pin Assignments
FG484
FG484
FG484
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
C21
C22
D1
NC
VCCIB1
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO38RSB0
IO42RSB0
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
GBA2/IO60PDB1
IO60NDB1
GND
G5
G6
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
NC
G7
D2
NC
G8
D3
NC
G9
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO45RSB0
GNDQ
D4
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO11RSB0
IO16RSB0
IO18RSB0
IO28RSB0
IO34RSB0
IO37RSB0
IO41RSB0
IO43RSB0
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
D6
D7
NC
D8
NC
D9
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
NC
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
NC
F3
NC
F4
IO173NDB3
IO174NDB3
VMV3
F5
F6
F7
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
NC
F8
NC
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
NC
H5
NC
H6
NC
H7
E2
NC
H8
E3
GND
H9
VCCIB0
E4
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
IO61NPB1
IO63PDB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO25RSB0
IO31RSB0
VCCIB0
E6
E7
GAB1/IO03RSB0
IO13RSB0
IO14RSB0
IO21RSB0
IO27RSB0
IO32RSB0
NC
E8
NC
VCCIB0
E9
IO170NDB3
IO170PDB3
NC
VMV1
E10
E11
E12
G2
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
G3
G4
IO171NDB3
4-74
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
H19
H20
H21
H22
J1
IO66PDB1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO158NPB3
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
NC
GND
M5
NC
VCC
M6
NC
VCCIB1
M7
IO160NDB3
GFB2/IO160PDB3
VCC
J2
NC
GCC1/IO69PPB1
IO65NPB1
IO75PDB1
IO75NDB1
NC
M8
J3
NC
M9
J4
IO166NDB3
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
IO76NDB1
IO76PDB1
NC
GND
J8
VCC
J9
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
GCA2/IO72PDB1
IO79PPB1
IO78PPB1
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO155PDB3
NC
VCC
L3
VCC
L4
GFB0/IO163NPB3
GFA0/IO162NDB3
GFB1/IO163PPB3
VCOMPLF
GFC0/IO164NPB3
VCC
VCC
L5
GND
L6
VCCIB1
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
NC
L7
L8
L9
IO154NDB3
IO154PDB3
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
IO68PDB1
IO68NDB1
IO157PDB3
IO157NDB3
NC
GND
N5
VCC
N6
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
GCB0/IO70NPB1
IO77PDB1
IO77NDB1
IO78NPB1
NC
N7
K2
N8
K3
N9
VCC
K4
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
VCC
N10
N11
N12
N13
N14
N15
N16
GND
K5
GND
K6
GND
K7
GND
K8
VCC
K9
VCCIB1
K10
GND
M2
IO155NDB3
IO73NPB1
Revision 20
4-75
Package Pin Assignments
FG484
FG484
FG484
Pin Number AGL600 Function
Pin Number AGL600 Function
Pin Number AGL600 Function
N17
N18
N19
N20
N21
N22
P1
IO80NPB1
IO74NPB1
IO72NDB1
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB2
VCCIB2
U1
U2
IO149PDB3
IO149NDB3
NC
IO117RSB2
IO110RSB2
VCCIB2
U3
U4
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
IO79NPB1
NC
U5
VCCIB2
U6
NC
VMV2
U7
IO138RSB2
IO136RSB2
IO131RSB2
IO124RSB2
IO119RSB2
IO107RSB2
IO104RSB2
IO97RSB2
VMV1
P2
IO153PDB3
IO153NDB3
IO159NDB3
IO156NPB3
IO151PPB3
IO158PPB3
VCCIB3
GND
IO94RSB2
GDB1/IO87PPB1
GDC1/IO86PDB1
IO84NDB1
VCC
U8
P3
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO81NDB1
IO82PDB1
IO152PDB3
IO152NDB3
NC
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
TRST
VCC
T5
GDA0/IO88NDB1
NC
GND
T6
VCCIB1
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
NC
T7
IO83NDB1
NC
T8
T9
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
GNDQ
NC
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO81PDB1
NC
V5
V6
NC
V7
R2
NC
IO92RSB2
VJTAG
V8
R3
VCC
V9
R4
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
VMV3
GDC0/IO86NDB1
GDA1/IO88PDB1
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO83PDB1
IO82NDB1
R8
4-76
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
Pin Number AGL600 Function
Pin Number AGL600 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO96RSB2
GDB2/IO90RSB2
TDI
Y7
NC
VCC
VCC
NC
Y8
Y9
GNDQ
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
TDO
NC
GND
NC
NC
NC
NC
VCC
VCC
NC
NC
W2
IO148PDB3
NC
W3
NC
W4
GND
GND
NC
W5
IO137RSB2
FF/GEB2/IO142RSB2
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
GDC2/IO91RSB2
IO93RSB2
GDA2/IO89RSB2
TMS
W6
NC
W7
NC
W8
VCCIB1
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB3
IO148NDB3
NC
Y2
Y3
Y4
NC
Y5
GND
Y6
NC
Revision 20
4-77
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
B7
B8
IO15RSB0
IO19RSB0
IO24RSB0
IO31RSB0
IO39RSB0
IO48RSB0
IO54RSB0
IO58RSB0
IO63RSB0
IO66RSB0
IO68RSB0
IO70RSB0
NC
GND
IO122RSB2
IO119RSB2
IO117RSB2
NC
A3
VCCIB0
B9
A4
IO07RSB0
IO09RSB0
IO13RSB0
IO18RSB0
IO20RSB0
IO26RSB0
IO32RSB0
IO40RSB0
IO41RSB0
IO53RSB0
IO59RSB0
IO64RSB0
IO65RSB0
IO67RSB0
IO69RSB0
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
A6
NC
A7
VCCIB1
A8
GND
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
AB3
VCCIB2
AB4
IO180RSB2
IO176RSB2
IO173RSB2
IO167RSB2
IO162RSB2
IO156RSB2
IO150RSB2
IO145RSB2
IO144RSB2
IO132RSB2
IO127RSB2
IO126RSB2
IO123RSB2
IO121RSB2
IO118RSB2
NC
AB5
AB6
NC
AB7
VCCIB1
GND
AB8
AB9
VCCIB3
IO220PDB3
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
C3
VCCIB0
C4
NC
GND
C5
GND
GND
C6
IO10RSB0
IO14RSB0
VCC
GND
C7
VCCIB3
C8
NC
C9
VCC
IO181RSB2
IO178RSB2
IO175RSB2
IO169RSB2
IO166RSB2
IO160RSB2
IO152RSB2
IO146RSB2
IO139RSB2
IO133RSB2
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO30RSB0
IO37RSB0
IO43RSB0
NC
VCCIB2
GND
GND
VCC
GND
VCC
B2
VCCIB3
NC
B3
NC
NC
B4
IO06RSB0
IO08RSB0
IO12RSB0
GND
B5
NC
B6
NC
Revision 20
4-78
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
C21
C22
D1
NC
VCCIB1
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO51RSB0
IO57RSB0
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
GBA2/IO78PDB1
IO81PDB1
GND
G5
G6
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
IO219PDB3
IO220NDB3
NC
G7
D2
G8
D3
G9
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
D4
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
IO22RSB0
IO28RSB0
IO35RSB0
IO45RSB0
IO50RSB0
IO55RSB0
IO61RSB0
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
D6
D7
NC
D8
IO84PDB1
NC
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
IO215PDB3
IO215NDB3
IO224NDB3
IO225NDB3
VMV3
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NPB1
IO85PDB1
IO85NDB1
NC
F3
F4
F5
F6
F7
IO11RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
F8
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
NC
H5
NC
H6
IO219NDB3
NC
H7
E2
H8
E3
GND
H9
VCCIB0
E4
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
IO78NDB1
IO81NDB1
IO82PPB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO38RSB0
IO47RSB0
VCCIB0
E6
E7
GAB1/IO03RSB0
IO17RSB0
IO21RSB0
IO27RSB0
IO34RSB0
IO44RSB0
E8
IO84NDB1
IO214NDB3
IO214PDB3
NC
VCCIB0
E9
VMV1
E10
E11
E12
G2
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
G3
G4
IO222NDB3
Revision 20
4-79
Package Pin Assignments
FG484
FG484
FG484
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
H19
H20
H21
H22
J1
IO87PDB1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO206NDB3
GFA2/IO206PDB3
GFA1/IO207PDB3
VCCPLF
NC
GND
M5
NC
VCC
M6
IO212NDB3
IO212PDB3
NC
VCCIB1
M7
IO205NDB3
GFB2/IO205PDB3
VCC
J2
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
IO88NDB1
IO94NPB1
IO98NDB1
IO98PDB1
NC
M8
J3
M9
J4
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PPB1
IO101PPB1
IO99PPB1
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO200PDB3
IO210NPB3
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
VCC
L3
VCC
L4
VCC
L5
GND
L6
VCCIB1
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
NC
L7
L8
L9
IO201NDB3
IO201PDB3
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
IO89PDB1
IO89NDB1
IO211PDB3
IO211NDB3
NC
GND
N5
VCC
N6
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
IO97PDB1
IO97NDB1
IO99NPB1
NC
N7
K2
N8
K3
N9
VCC
K4
IO210PPB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
VCC
N10
N11
N12
N13
N14
N15
N16
GND
K5
GND
K6
GND
K7
GND
K8
VCC
K9
VCCIB1
K10
GND
M2
IO200NDB3
IO95NPB1
4-80
Revision 20
IGLOO Low Power Flash FPGAs
FG484
FG484
FG484
Pin Number AGL1000 Function
Pin Number AGL1000 Function
Pin Number AGL1000 Function
N17
N18
N19
N20
N21
N22
P1
IO100NPB1
IO102NDB1
IO102PDB1
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB2
VCCIB2
U1
U2
IO195PDB3
IO195NDB3
IO194NPB3
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
IO147RSB2
IO136RSB2
VCCIB2
U3
U4
IO101NPB1
IO103PDB1
NC
U5
VCCIB2
U6
VMV2
U7
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
P2
IO199PDB3
IO199NDB3
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
IO110NDB1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
VCC
U8
P3
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO104NDB1
IO105PDB1
IO198PDB3
IO198NDB3
NC
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
IO194PPB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
TRST
VCC
T5
GDA0/IO113NDB1
NC
GND
T6
VCCIB1
T7
IO108NDB1
IO109PDB1
NC
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
NC
T8
T9
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO104PDB1
IO103NDB1
NC
V5
V6
V7
R2
IO197PPB3
VCC
IO110PDB1
VJTAG
V8
R3
V9
R4
IO197NPB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
GDC0/IO111NDB1
GDA1/IO113PDB1
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO108PDB1
IO105NDB1
R8
Revision 20
4-81
Package Pin Assignments
FG484
FG484
Pin Number AGL1000 Function
Pin Number AGL1000 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO125RSB2
GDB2/IO115RSB2
TDI
Y7
IO174RSB2
VCC
Y8
Y9
VCC
GNDQ
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO154RSB2
IO148RSB2
IO140RSB2
NC
TDO
GND
NC
IO109NDB1
NC
VCC
VCC
W2
IO191PDB3
NC
NC
W3
NC
W4
GND
GND
W5
IO183RSB2
FF/GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
NC
W6
NC
W7
NC
W8
VCCIB1
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB3
Y2
IO191NDB3
NC
Y3
Y4
IO182RSB2
GND
Y5
Y6
IO177RSB2
4-82
Revision 20
5 – Datasheet Information
List of Changes
The following tables list critical changes that were made in each revision of the IGLOO datasheet.
Revision
Changes
Page
Revision 20
(March 2012)
Notes indicating that AGL015 is not recommended for new designs have been added. I to IV
The "Devices Not Recommended For New Designs" section is new (SAR 35015).
Notes indicating that device/package support is TBD for AGL250-QN132 and I to IV
AGL060-FG144 have been reinserted (SAR 33689).
Values for the power data for PAC1, PAC2, PAC3, PAC4, PAC7, and PAC8 were 2-13,
revised in Table 2-19 · Different Components Contributing to Dynamic Power
Consumption in IGLOO Devices and Table 2-21 · Different Components Contributing to
Dynamic Power Consumption in IGLOO Devices to match the SmartPower tool in
Libero software version 9.0 SP1 and Power Calculator spreadsheet v7a released on
08/10/2010 (SAR 33768).
2-15
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture" section
of the Global Resources chapter in the IGLOO FPGA Fabric User’s Guide (SAR
34730).
2-17
2-21
Figure 2-4 • Input Buffer Timing Model and Delays (example) has been modified for the
DIN waveform; the Rise and Fall time label has been changed to tDIN (37104).
Added missing characteristics for 3.3 V LVCMOS, 3.3 V LVCMOS Wide range, 1.2 V 2-35
to
to
LVCMOS, and 1.2 V LVCMOS Wide range to the following tables:
2-40,
2-47
2-49,
2-74,
•
Table 2-38, Table 2-39, Table 2-40, Table 2-42, Table 2-43, and Table 2-44 (SARs
33854 and 36891)
•
•
Table 2-63, Table 2-64, and Table 2-65 (SAR 33854)
2-76, and
2-77
Table 2-127, Table 2-128, Table 2-129, Table 2-137, Table 2-138, and Table 2-139
(SAR 36891).
AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to
match Table 2-50 · AC Waveforms, Measuring Points, and Capacitive Loads (SAR
34878).
2-42
Added values for minimum pulse width and removed the FRMAX row from Table 2-173 2-105
through Table 2-188 in the "Global Tree Timing Characteristics" section. Use the through
software to determine the FRMAX for the device you are using (SAR 29271).
2-112
Revision 19
CS121 was added to the product tables in the "IGLOO Low Power Flash FPGAs"
I
(September 2011) section for AGL125 (SAR 22737). CS81 was added for AGL250 (SAR 22737).
Notes indicating that device/package support is TBD for AGL250-QN132 and I to IV
AGL060-FG144 have been removed (SAR 33689).
M1AGL400 was removed from the "I/Os Per Package1" table. This device was
discontinued in April 2009 (SAR 32450).
II
Dimensions for the QN48 package were added to Table 1 • IGLOO FPGAs Package
Sizes Dimensions (SAR 30537).
II
Revision 20
5-1
Datasheet Information
Revision
Changes
Page
Revision 19
(continued)
The Y security option and Licensed DPA Logo were added to the "IGLOO Ordering
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
32151).
III
The "In-System Programming (ISP) and Security" section and "Security" section were I, 1-2
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry
(SAR 32865).
The following sentence was removed from the "Advanced Architecture" section:
1-3
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR
28756).
The "Specifying I/O States During Programming" section is new (SAR 21281).
1-8
2-2
Values for VCCPLL at 1.2 V –1.5 V DC core supply voltage were revised in Table 2-2 •
Recommended Operating Conditions 1 (SAR 22356).
The value for VPUMP operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR
25220).
The value for VCCPLL 1.5 V DC core supply voltage was changed from" 1.4 to 1.6 V" to
"1.425 to 1.575 V" (SAR 26551).
The notes in the table were renumbered in order of their appearance in the table (SAR
21869).
The temperature used in EQ 2 was revised from 110°C to 100°C for consistency with
the limits given in Table 2-2 • Recommended Operating Conditions 1. The resulting
maximum power allowed is thus 1.28 W. Formerly it was 1.71 W (SAR 26259).
2-6
Values for CS196, CS281, and QN132 packages were added to Table 2-5 • Package
Thermal Resistivities (SARs 26228, 32301).
2-6
2-7
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to
TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors
for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were updated to remove
the column for –20°C and shift the data over to correct columns (SAR 23041).
The tables in the "Quiescent Supply Current" section were updated with revised notes
on IDD (SAR 24112). Table 2-8 • Power Supply State per Mode is new.
2-7
The formulas in the table notes for Table 2-41 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 21348).
2-37
2-40
The row for 110°C was removed from Table 2-45 • Duration of Short Circuit Event
before Failure. The example in the associated paragraph was changed from 110°C to
100°C. Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was
revised to change 110° to 100°C. (SAR 26259).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics – 2-28,
Default I/O Software Settings" section, "3.3 V LVCMOS Wide Range" section and "1.2 2-47,
V LVCMOS Wide Range" section tables were revised for clarification. They now state
that the minimum drive strength for the default software configuration when run in wide
range is ±100 µA. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 25700).
2-76
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): "It
uses a 5 V–tolerant input buffer and push-pull output buffer."
2-56
The values for FDDRIMAX and FDDOMAX were updated in the tables in the "Input DDR 2-92,
Module" section and "Output DDR Module" section (SAR 23919).
2-95
5-2
Revision 20
IGLOO Low Power Flash FPGAs
Revision
Changes
Page
Revision 19
(continued)
The following notes were removed from Table 2-147 • Minimum and Maximum DC Input
and Output Levels (SAR 29428):
2-80
±5%
Differential input voltage = ±350 mV
Table 2-189 • IGLOO CCC/PLL Specification and Table 2-190 • IGLOO CCC/PLL 2-113
Specification were updated. A note was added to both tables indicating that when the
CCC/PLL core is generated by Mircosemi core generator software, not all delay values
of the specified delay increments are available (SAR 25705).
The following figures were deleted (SAR 29991). Reference was made to a new
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs, which covers these cases in detail (SAR 21770).
N/A
Figure 2-36 • Write Access after Write onto Same Address
Figure 2-37 • Read Access after Write onto Same Address
Figure 2-38 • Write Access after Read onto Same Address
2-116 to
2-126
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-38 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SARs 29991, 30510).
The "Pin Descriptions" chapter has been added (SAR 21642).
3-1
4-1
Package names used in the "Package Pin Assignments" section were revised to match
standards given in Package Mechanical Drawings (SAR 27395).
The "CS81" pin table for AGL250 is new (SAR 22737).
4-5
4-9
The "CS121" pin table for AGL125 is new (SAR 22737).
The P3 function was revised in the "CS196" pin table for AGL250 (SAR 24800).
4-14
The "QN132" pin table for AGL250 was added.
4-37,
4-45
The "FG144" pin table for AGL060 was added (SAR 33689)
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOO
Device Status" table indicates the status for each device in the device family.
N/A
Revision 20
5-3
Datasheet Information
Revision / Version
Changes
Page
Revision 18 (Nov 2009) The version changed to v2.0 for IGLOO datasheet chapters, indicating the
datasheet contains information based on final characterization. Please review the
datasheet carefully as most tables were updated with new data.
N/A
Revision 17 (Sep 2009) The "Reprogrammable Flash Technology" section was modified to add "250 MHz
I
(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."
Product Brief v1.6
"IGLOO Ordering Information" was revised to note that halogen-free packages
are available with RoHS-compliant packaging.
III
Table 1-1 • I/O Standards Supported is new.
1-7
1-7
The definitions of hot-swap and cold-sparing were added to the "I/Os with
Advanced I/O Standards" section.
Revision 16 (Apr 2009) M1AGL400 is no longer offered and was removed from the "IGLOO Devices" I, III, IV
product table, "IGLOO Ordering Information", and "Temperature Grade
Offerings".
Product Brief v1.5
The –F speed grade is no longer offered for IGLOO devices. The speed grade III, IV
column and note regarding –F speed grade were removed from "IGLOO Ordering
Information". The "Speed Grade and Temperature Grade Matrix" section was
removed.
This datasheet now has fully characterized data and has moved from being
Advance to a Production version. The version number changed from Advance
v0.5 to v2.0.
N/A
Please review the datasheet carefully as most tables were updated with new
data.
DC and Switching
Characteristics
Advance v0.6
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
N/A
–F was removed from the datasheet. The speed grade is no longer supported.
The notes in Table 2-2 • Recommended Operating Conditions 1 were updated.
Table 2-4 • Overshoot and Undershoot Limits 1 was updated.
N/A
2-2
2-3
2-6
2-7
Table 2-5 • Package Thermal Resistivities was updated.
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and
Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.14 V) were updated.
In Table 2-191 • RAM4K9 and Table 2-193 • RAM4K9, the following specifications 2-119
were removed:
and
2-121
tWRO
tCCKH
In Table 2-192 • RAM512X18 and Table 2-194 • RAM512X18, the following 2-120
specifications were removed:
and
2-122
tWRO
tCCKH
Revision 15 (Feb 2009) The "QN132" pin table for the AGL060 device is new.
4-33
Packaging v1.9
5-4
Revision 20
IGLOO Low Power Flash FPGAs
Revision / Version
Changes
Page
Revision 14 (Feb 2009) The "Advanced I/O" section was revised to include two bullets regarding wide
I
range power supply voltage support.
Product Brief v1.4
3.0 V wide range was added to the list of supported voltages in the "I/Os with
Advanced I/O Standards" section. The "Wide Range I/O Support" section is new.
1-8
4-7
Revision 13 (Jan 2009) The "CS121" pin table was revised to add a note regarding pins F1 and G1.
Packaging v1.8
Revision 12 (Dec 2008) QN48 and QN68 were added to the AGL030 for the following tables:
N/A
Product Brief v1.3
"IGLOO Devices" Product Family Table
"IGLOO Ordering Information"
"Temperature Grade Offerings"
QN132 is fully supported by AGL125 so footnote 3 was removed.
The "QN48" pin diagram and pin table are new.
The "QN68" pin table for AGL030 is new.
Packaging v1.7
4-26
4-28
4-73
N/A
Revision 12 (Dec 2008) The AGL600 Function for pin K15 in the "FG484" table was changed to VCCIB1.
Revision 11 (Oct 2008) This document was updated to include AGL400 device information. The following
sections were updated:
Product Brief v1.2
"IGLOO Devices" Product Family Table
"IGLOO Ordering Information"
"Temperature Grade Offerings"
Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250,
AGL600, AGL400, and AGL1000)
DC and Switching
Characteristics
Advance v0.5
The tables in the "Quiescent Supply Current" section were updated with values
for AGL400. In addition, the title was updated to include:
(VCC = VJTAG = VPP = 0 V).
2-7
The tables in the "Power Consumption of Various Internal Resources" section
were updated with values for AGL400.
2-13
Table 2-178 • AGL400 Global Resource is new.
The "CS196" table for the AGL400 device is new.
The "FG144" table for the AGL400 device is new.
The "FG256" table for the AGL400 device is new.
The "FG484" table for the AGL400 device is new.
2-107
4-16
4-51
4-58
4-68
2-2
Packaging v1.6
Revision 10 (Aug 2008) 3.0 V LVCMOS wide range support data was added to Table 2-2 • Recommended
Operating Conditions 1.
DC and Switching
Characteristics
Advance v0.4
3.3 V LVCMOS wide range support data was added to Table 2-25 • Summary of 2-24 to
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings to Table 2-27 • Summary of
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings.
2-26
3.3 V LVCMOS wide range support data was added to Table 2-28 • Summary of
Maximum and Minimum DC Input Levels.
2-27
2-39
3.3 V LVCMOS wide range support text was added to Table 2-49 · Minimum and
Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range.
Revision 20
5-5
Datasheet Information
Revision / Version
Changes
Page
DC & Switching, cont’d. Table 2-49 · Minimum and Maximum DC Input and Output Levels for LVCMOS
3.3 V Wide Range is new.
2-39
Revision 9 (Jul 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
Revision 8 (Jun 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
N/A
N/A
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
DC and Switching
Characteristics
Advance v0.2
Tables have been updated to reflect default values in the software. The default I/O
capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O
set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
The power data table has been updated to match SmartPower data rather then
simulation values.
AGL015 global clock delays have been added.
Table 2-1 • Absolute Maximum Ratings was updated to combine the VCCI and
VMV parameters in one row. The word "output" from the parameter description for
VCCI and VMV, and table note 3 was added.
2-1
2-2
2-2
2-3
Table 2-2 • Recommended Operating Conditions 1 was updated to add references
to tables notes 4, 6, 7, and 8. VMV was added to the VCCI parameter row, and
table note 9 was added.
In Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating
Temperature1, the maximum operating junction temperature was changed from
110° to 100°.
VMV was removed from Table 2-4 • Overshoot and Undershoot Limits 1. The
table title was modified to remove "as measured on quiet I/Os." Table note 2 was
revised to remove "estimated SSO density over cycles." Table note 3 was revised
to remove "refers only to overshoot/undershoot limits for simultaneous switching
I/Os."
The "PLL Behavior at Brownout Condition" section is new.
2-4
2-5
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage
Levels is new.
EQ 2 was updated. The temperature was changed to 100°C, and therefore the
end result changed.
2-6
2-7
The table notes for Table 2-9 • Quiescent Supply Current (IDD) Characteristics,
IGLOO Flash*Freeze Mode*, Table 2-10 • Quiescent Supply Current (IDD)
Characteristics, IGLOO Sleep Mode*, and Table 2-11 • Quiescent Supply Current
(IDD) Characteristics, IGLOO Shutdown Mode were updated to remove VMV and
include PDC6 and PDC7. VCCI and VJTAG were removed from the statement
about IDD in the table note for Table 2-11 • Quiescent Supply Current (IDD)
Characteristics, IGLOO Shutdown Mode.
Note 2 of Table 2-12 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze
Mode1 was updated to include VCCPLL. Note 4 was updated to include PDC6
and PDC7.
2-9
5-6
Revision 20
IGLOO Low Power Flash FPGAs
Revision / Version
Revision 8 (cont’d)
Changes
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Page
2-10
Settings, Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O through
Software Settings, Table 2-15 • Summary of I/O Input Buffer Power (per pin) –
Default I/O Software Settings, and Table 2-16 • Summary of I/O Output Buffer
Power (per pin) – Default I/O Software Settings1 were updated to change PDC2
to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power
was measured on VCCI.
2-11
In Table 2-19
• Different Components Contributing to Dynamic Power
2-13
Consumption in IGLOO Devices, the description for PAC13 was changed from
Static to Dynamic.
Table 2-20 • Different Components Contributing to the Static Power Consumption 2-14,
in IGLOO Devices and Table 2-22 • Different Components Contributing to the
Static Power Consumption in IGLOO Device were updated to add PDC6 and
PDC7, and to change the definition for PDC5 to bank quiescent power. Subtitles
were added to indicate type of devices and core supply voltage.
2-16
The "Total Static Power Consumption—PSTAT" section was updated to revise the
calculation of PSTAT, including PDC6 and PDC7.
2-17
2-18
Footnote † was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to
PPLL = PDC4 + PAC13 * FCLKOUT
.
Revision 7 (Jun 2008) The "QN132" package diagram was updated to include D1 to D4. In addition, note
4-30
N/A
1 was changed from top view to bottom view, and note 2 is new.
Packaging v1.5
Revision 6 (Jun 2008) This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
Packaging v1.4
Pin numbers were added to the "QN68" package diagram. Note 2 was added
below the diagram.
4-27
4-14
Revision 5 (Mar 2008) The "CS196" package and pin table was added for AGL250.
Packaging v1.3
Revision 4 (Mar 2008) The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"
I
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed
from "Low Power Active FPGA Operation."
Product Brief v1.0
1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and
"I/Os with Advanced I/O Standards" section sections.
I, 1-7
I
The "Embedded Memory" section was updated to remove the footnote reference
from the section heading and place it instead after "4,608-Bit" and "True Dual-Port
SRAM (except ×18)."
Revision 20
5-7
Datasheet Information
Revision / Version
Changes
Page
Revision 3 (Feb 2008) This document was updated to include AGL015 device information. QN68 is a
N/A
new package offered in the AGL015. The following sections were updated:
Product Brief rev. 2
"Features and Benefits"
"IGLOO Ordering Information"
"Temperature Grade Offerings"
"IGLOO Devices" Product Family Table
Table 1 • IGLOO FPGAs Package Sizes Dimensions
"AGL015 and AGL030" note
The "Temperature Grade Offerings" table was updated to include M1AGL600.
IV
III
In the "IGLOO Ordering Information" table, the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
In the "General Description" section, the number of I/Os was updated from 288 to
300.
1-1
Packaging v1.2
The "QN68" section is new.
4-27
4-12
Revision 2 (Jan 2008) The "CS196" package and pin table was added for AGL125.
Packaging v1.1
Revision 1 (Jan 2008) The "Low Power" section was updated to change the description of low power I, 1-1
active FPGA operation to "from 12 µW" from "from 25 µW." The same update was
made in the "General Description" section and the "Flash*Freeze Technology"
section.
Product Brief rev. 1
Revision 0 (Jan 2008) This document was previously in datasheet Advance v0.7. As a result of moving
N/A
to the handbook format, Actel has restarted the numbering.
Advance v0.7
Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the i, ii, iv
(December 2007)
Temperature Grade Offerings table were updated to reflect the following: CS196
is now supported for AGL250; device/package support for QN132 is to be
determined for AGL250; the CS281 package was added for AGL600 and
AGL1000.
Table 2 • IGLOO FPGAs Package Sizes Dimensions is new, and package sizes
were removed from the "I/Os Per Package1" table.
ii
The "I/Os Per Package1"table was updated to reflect 77 instead of 79 single-
ended I/Os for the VG100 package for AGL030.
ii
The "Timing Model" was updated to be consistent with the revised timing
numbers.
2-20
2-26
In Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings,
TJ was changed to TA in notes 1 and 2.
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-74
N/A
This document was previously in datasheet Advance v0.7. As a result of moving
to the handbook format, Actel has restarted the version numbers. The new
version number is Advance v0.1.
Table 2-4 • IGLOO CCC/PLL Specification and Table 2-5 • IGLOO CCC/PLL 2-19,
Specification were updated. 2-20
5-8
Revision 20
IGLOO Low Power Flash FPGAs
Revision / Version
Changes
Page
Advance v0.7
(continued)
The former Table 2-16 • Maximum I/O Frequency for Single-Ended and
Differential I/Os in All Banks in IGLOO Devices (maximum drive strength and high
slew selected) was removed.
N/A
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core.
2-57
2-61
Table 2-31 • Flash*Freeze Pin Location in IGLOO Family Packages (device-
independent) was updated to add UC81 and CS281. Flash*Freeze pins were
assigned for CS81, CS121, and CS196.
Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
2-55
3-6
3-6
3-6
3-7
Information regarding calculation of the quiescent supply current was added to
the "Quiescent Supply Current" section.
Table 3-8 • Quiescent Supply Current (IDD
)
Characteristics, IGLOO
Flash*Freeze Mode† was updated.
Table 3-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode
(VCC = 0 V)† was updated.
Table 3-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1
was updated.
Table 3-115 • Minimum and Maximum DC Input and Output Levels was updated.
Table 3-156 • JTAG 1532 was updated and Table 3-155 • JTAG 1532 is new.
The "121-Pin CSP" and "281-Pin CSP" packages are new.
3-58
3-104
4-5, 4-7
4-4
The "81-Pin CSP" table for the AGL030 device was updated to change the G6 pin
function to IO44RSB1 and the JG pin function to IO45RSB1.
The "121-Pin CSP" table for the AGL060 device is new.
The "256-Pin FBGA" table for the AGL1000 device is new.
The "281-Pin CSP" table for the AGL 600 device is new.
The "100-Pin VQFP" table for the AGL060 device is new.
The "144-Pin FBGA" table for the AGL250 device is new.
The "144-Pin FBGA" table for the AGL1000 device is new.
The "484-Pin FBGA" table for the AGL600 device is new.
The "484-Pin FBGA" table for the AGL1000 device is new.
4-6
4-34
4-8
4-18
4-24
4-28
4-38
4-43
Advance v0.6
(November 2007)
Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the "IGLOO i, ii, iii, iv
Ordering Information", and the Temperature Grade Offerings table were updated
to add the UC81 package.
The "81-Pin µCSP" table for the AGL030 device is new.
The "81-Pin CSP" table for the AGL030 device is new.
4-3
4-1
i
Advance v0.5
(September 2007)
Table 1 • IGLOO Product Family was updated for AGL030 in the Package Pins
section to change CS181 to CS81.
Revision 20
5-9
Datasheet Information
Revision / Version
Changes
Page
Advance v0.4
(September 2007)
Cortex-M1 device information was added to Table 1 • IGLOO Product Family, the i, ii, iii, iv
"I/Os Per Package1" table, "IGLOO Ordering Information", and Temperature
Grade Offerings.
The number of single-ended I/Os for the CS81 package for AGL030 was updated
to 66 in the "I/Os Per Package1" table.
ii
2-51
i
The "Power Conservation Techniques" section was updated to recommend that
unused I/O signals be left floating.
Advance v0.3
(August 2007)
In Table 1 • IGLOO Product Family, the CS81 package was added for AGL030.
The CS196 was replaced by the CS121 for AGL060. Table note 3 was moved to
the specific packages to which it applies for AGL060: QN132 and FG144.
The CS81 and CS121 packages were added to the "I/Os Per Package1" table.
The number of single-ended I/Os was removed for the CS196 package in
AGL060. Table note 6 was moved to the specific packages to which it applies for
AGL060: QN132 and FG144.
ii
The CS81 and CS121 packages were added to the Temperature Grade Offerings
table. The temperature grade offerings were removed for the CS196 package in
AGL060. Table note 3 was moved to the specific packages to which it applies for
AGL060: QN132 and FG144.
iv
The CS81 and CS121 packages were added to Table 2-31 • Flash*Freeze Pin
Location in IGLOO Family Packages (device-independent).
2-61
iii, iv
Advance v0.2
The words "ambient temperature" were added to the temperature range in the
"IGLOO Ordering Information", Temperature Grade Offerings, and "Speed Grade
and Temperature Grade Matrix" sections.
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
5-10
Revision 20
IGLOO Low Power Flash FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "IGLOO Device Status" table, is designated as either "Product Brief," "Advance,"
"Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The Microsemi products described in this advance status document may not have completed
Microsemi’s qualification process. Microsemi may amend or enhance products during the product
introduction and qualification process, resulting in changes in device functionality or performance. It is
the responsibility of each customer to ensure the fitness of any Microsemi product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and other
high-reliability applications. Consult Microsemi’s Terms and Conditions for specific liability exclusions
relating to life-support applications. A reliability report covering all of the Microsemi SoC Products
Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi
also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Microsemi sales office for additional reliability information.
Revision 20
5-11
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
51700095-20/3.12
相关型号:
M1AGL250V2-FGG144
Field Programmable Gate Array, 6144 CLBs, 250000 Gates, 108MHz, CMOS, PBGA144, 13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-144
MICROSEMI
M1AGL250V2-FGG144I
Field Programmable Gate Array, 6144 CLBs, 250000 Gates, 108MHz, 6144-Cell, CMOS, PBGA144, 13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-144
ACTEL
M1AGL250V2-FQN132
Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132
MICROSEMI
M1AGL250V2-FQNG132
Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132
MICROSEMI
©2020 ICPDF网 联系我们和版权申明