M2S025TS-1VFG144YES [MICROSEMI]

SmartFusion2 System-on-Chip FPGAs;


型号：	M2S025TS-1VFG144YES
厂家：	Microsemi
描述：	SmartFusion2 System-on-Chip FPGAs
文件：	总156页 (文件大小：7404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Revision 0

SmartFusion2 System-on-Chip FPGAs

Microsemi’s SmartFusion^®2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM^®Cortex™-M3 processor,

and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most

reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate

count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded

memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an

embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including

controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include

peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +

native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide

high speed memory interfaces.

SmartFusion2 Family

–

Enhanced Anti-Tamper Features

Zeroization

Reliability

•

Single Event Upset (SEU) Immune

•

Data Security Features (available on premium devices)

–

Zero FIT FPGA Configuration Cells

–

Non-Deterministic Random Bit Generator (NRBG)

•

Single Error Correct Double Error Detect (SECDED)

Protection on the Following:

User Cryptographic Services (AES-256, SHA-256,

Elliptical Curve Cryptographic (ECC) Engine)

–

Ethernet Buffers

–

User Physically Unclonable Function (PUF) Key

Enrollment and Regeneration

CAN Message Buffers

Cortex-M3 Embedded Scratch Pad Memory

(eSRAMs)

–

CRI Pass-Through DPA Patent Portfolio License

Hardware Firewalls Protecting Microcontroller

Subsystem (MSS) Memories

–

USB Buffers

PCIe Buffer

Low Power

DDR Memory Controllers with Optional SECDED

Modes

•

Low Static and Dynamic Power

Flash*Freeze Mode for Fabric

For the M2S050 Device:

•

Buffers Implemented with SEU Resistant Latches on the

Following:

–

•

–

DDR Bridges (MSS, MDDR, FDDR)

Instruction Cache

–

< 1 mW in Flash*Freeze Mode

10 mW in Standby Mode

MMUART FIFOs

•

Based on 65 nm Nonvolatile Flash Process

SPI FIFOs

High-Performance FPGA

•

NVM Integrity Check at Power-Up and On-Demand

•

Efficient 4-Input LUTs with Carry Chains for High

Performance and Low Power

No External Configuration Memory Required—Instant-

On, Retains Configuration When Powered Off

•

Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large

SRAM) with 400 MHz Synchronous Performance (x18,

x9, x4, x2, x1)

Security

•

Design Security Features (available on all devices)

•

Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2

Read Ports and 1 Write Port (micro SRAM)

–

Intellectual Property (IP) Protection via Unique

Security Features and Use Models New to the PLD

Industry

High Performance DSP Signal Processing

–

Encrypted User Key and Bitstream Loading,

Enabling Programming in Less-Trusted Locations

–

Up to 240 Fast Math Blocks with 18 x 18 Signed

Multiplication, 17 x 17 Unsigned Multiplication and

44-Bit Accumulator

Supply-Chain Assurance Device Certificate

October 2012

SmartFusion2 System-on-Chip FPGAs

Microcontroller Subsystem (MSS)

High Speed Serial Interfaces

•

Hard 166 MHz 32-Bit ARM Cortex-M3 Processor

•

Up to 16 SERDES Lanes, Each Supporting:

–

1.25 DMIPS/MHz

–

XGXS/XAUI Extension (to implement a 10 Gbps

(XGMII) Ethernet PHY interface)

8 Kbyte Instruction Cache

–

Native SERDES Interface Facilitates Implementation

of Serial RapidIO in Fabric or an SGMII Interface to

the Ethernet MAC in MSS

Embedded Trace Macrocell (ETM)

Memory Protection Unit (MPU)

Single Cycle Multiplication, Hardware Divide

–

PCI Express (PCIe) Endpoint Controller

JTAG Debug (4 wires), Serial Wire Debug (SWD, 2

wires), and Serial Wire Viewer (SWV) Interfaces

x1, x2, x4 Lane PCI Express Core with 16-bit

PIPE Interface (Gen1/Gen2)

•

64 KB Embedded SRAM (eSRAM)

256 Bytes Maximum Payload Size

Up to 512 KB Embedded Nonvolatile Memory (eNVM)

Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC

64-/32-Bit AXI/AHB Master and Slave Interfaces

to the Application Layer

USB 2.0 High Speed On-The-Go (OTG) Controller with

ULPI Interface

High Speed Memory Interfaces

•

Up to 2 High Speed DDRx Memory Controllers

•

CAN Controller, 2.0B Compliant, Conforms to

ISO11898-1, 32 Transmit and 32 Receive Buffers

Two Each: SPI, I²C, Multi-Mode UARTs (MMUART)

–

MSS DDR (MDDR) and Fabric DDR (FDDR)

Controllers

–

Supports LPDDR/DDR2/DDR3

Maximum 333 MHz Clock Rate

SECDED Enable/Disable Feature

Peripherals

•

Hardware Based Watchdog Timer

1 General Purpose 64-Bit (or two 32-bit) Timer(s)

Real-Time Calendar/Counter (RTC)

Supports Various DRAM Bus Width Modes, x16,

x18, x32, x36

DDR Bridge (4 Port Data R/W Buffering Bridge to DDR

Memory) with 64-Bit AXI Interface

–

Supports Command Reordering to Optimize Memory

Efficiency

•

Non-Blocking, Multi-Layer AHB Bus Matrix Allowing

Multi-Master Scheme Supporting 10 Masters and 7

Slaves

Supports Data Reordering, Returning Critical Word

First for Each Command

•

SDRAM Support

•

Two AHB/APB Interfaces to FPGA Fabric (master/slave

capable)

Operating Voltage and I/Os

Two DMA Controllers to Offload Data Transactions from

the Cortex-M3 Processor

•

1.2 V Core Voltage

•

Multi-Standard User I/Os (MSIO/MSIOD)

–

8-Channel Peripheral DMA (PDMA) for Data

Transfer Between MSS Peripherals and Memory

–

LVTTL/LVCMOS 3.3 V

LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V

DDR (SSTL2_1, SSTL2_2)

DDR2 (SSTL18_1, SSTL18_2)

–

High Performance DMA (HPDMA) for Data Transfer

Between eSRAM and DDR Memories

Clocking Resources

LVDS, MLVDS, Mini-LVDS, RSDS Differential

Standards

•

Clock Sources

–

Up to Two High Precision 32 KHz to 20 MHz Main

Crystal Oscillator

–

PCI

LVPECL (receiver only)

–

1 MHz Embedded RC Oscillator

50 MHz Embedded RC Oscillator

•

DDR I/Os (DDRIO)

–

DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18,

HSTL

•

Up to 8 Clock Conditioning Circuits (CCCs) with Up to 8

Integrated Analog PLLs

–

LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V

–

Output Clock with 8 Output Phases and 45° Phase

Difference (Multiply/Divide, and Delay Capabilities)

–

Frequency: Input 1 to 200 MHz, Output 20 to 400

MHz

Revision 0

SmartFusion2 System-on-Chip FPGAs

SmartFusion2 SoC FPGA Block Diagram

JTAG I/O

SPI I/O

Multi-Standard User I/O (MISO)

DDR User I/O

ARM Cortex^™-M3

SPI x 2

Instruction

Cache

MMUART x 2

Microcontroller

Subsystem (MSS)

C x 2

MPU

ETM

System Controller

Timer x 2

AES256 SHA256 SRAM-PUF

CAN

DDR

Bridge

HS USB

OTG ULPI

APB

PDMA

SYSREG

eNVM

ECC

NRBG

WDT

RTC

FIIC

In-Application

Programming

Flash*Freeze

MSS

DDR Controller

+ PHY

AHB Bus Matrix (ABM)

eSRAM

COMM_BLK

FIC_0

FIC_1

TSE MAC

HPDMA

SMC_FIC Conﬁg

AXI/AHB

Interupts

AHB AHB

AHB

FPGA Fabric

Micro SRAM

(64x18)

Large SRAM

(1024x18)

Math Block

MACC (18x18)

Micro SRAM

(64x18)

Large SRAM

(1024x18)

Math Block

MACC (18x18)

Conﬁg

AXI/AHB/XGXS

Conﬁg

AXI/AHB/XGXS

Conﬁg

AXI/AHB

Standard Cell /

SEU Immune

Serial Controller 0

(PCIe, XAUI/XGXS)

+ Native SERDES

Serial Controller 1

(PCIe, XAUI/XGXS)

+ Native SERDES

Fabric DDR

Controller + PHY

Flash Based /

SEU Immune

OSCs

PLLs

Serial 0 I/O

Serial 1 I/O

DDR User I/O

Acronyms

AES

AHB

APB

AXI

Advanced Encryption Standard

Advanced High-Performance Bus

Advanced Peripheral Bus

MDDR

DDR2/3 Controller in MSS

MMUART Multi-Mode UART

MPU

MSS

Memory Protection Unit

Advanced eXtensible Interface

Microcontroller Subsystem

COMM_BLK Communication Block

SECDED Single Error Correct Double Error Detect

DDR

DPA

ECC

EDAC

ETM

FDDR

FIC

Double Data Rate

SEU

SHA

Single Event Upset

Differential Power Analysis

Elliptical Curve Cryptography

Error Detection And Correction

Embedded Trace Macrocell

DDR2/3 controller in FPGA fabric

Fabric Interface Controller

Fabric Interface Interrupt Controller

Secure Hashing Algorithm

SMC_FIC Soft Memory Controller

TSE

Triple Speed Ethernet (10/100/1000 Mbps)

ULPI

UTMI

WDT

XAUI

XGMII

XGXS

UTMI + Low Pin Interface

USB 2.0 Transceiver Macrocell Interface

Watchdog Timer

FIIC

10 Gbps Attachment Unit Interface

10 Gigabit Media Independent Interface

XGMII Extended Sublayer

HS USB OTG High Speed USB 2.0 On-The-Go

IAP

In-Application Programming

Multiply-Accumulate

MACC

Revision 0

III

SmartFusion2 System-on-Chip FPGAs

Table 1 • SmartFusion2 SoC FPGA Product Family

Features

M2S005

4,956

M2S010

9,744

M2S025

23,988

M2S050

48,672

M2S080

82,232

160

3,040K

160

M2S120

120,348

236

240

4,500K

240

Logic Modules (4-Input LUT)

LSRAM 18K Blocks

uSRAM 1K Blocks

Total RAM (Bits)

191K

400K

592K

1,314K

Math Blocks

PLLs and CCCs

Yes

128K

64K

80K

Yes

256K

64K

80K

Yes

256K

64K

80K

Yes

256K

64K

80K

Yes

512K

64K

80K

Yes

512K

64K

80K

Cortex-M3 Processor + Instruction Cache

eNVM (Bytes)

eSRAM (Bytes)

eSRAM (Bytes non-SECDED)

CAN 2.0 A and B

Triple speed Ethernet 10/100/1000

USB 2.0 High Speed On-The-Go

Multi-Mode UART

SPI

I2C

Timer

DDR Controllers

1x18

2x36

SERDES Channels

PCIe Endpoint × 4

3.3 V Multi-Standard User I/Os (MSIOs)

MSIOD I/Os

123

159

139

292

106

176

574

292

106

176

574

DDRIO I/Os

176

377

Total User I/Os

217

233

289

SERDES I/Os

Total User I/Os + SERDES I/Os

217

249

305

409

638

I/Os Per Package

Table 2 • I/Os per Package and Package Options

Package Options

Pin Count

VF400

400

FG484

FG896

FC1152

484

1.0

896

1.0

1,152

1.0

Ball Pitch (mm)

0.8

Length × Width (mm\mm)

17 × 17

23 × 23

31 × 31

35 × 35

I/Os

XCVRs

I/Os

XCVRs

I/Os

–

XCVRs

I/Os

XCVRs

M2S005

M2S010

M2S025

M2S050

M2S080

M2S120

160

–

217

233

267

–

377

–

574

–

Note: User I/Os do not include the SERDES and JTAG pins.

Revision 0

SmartFusion2 System-on-Chip FPGAs

SmartFusion2 Ordering Information

144

M2S050

Application (Temperature Range)

Blank = Commercial (0°C to +85°C Ambient Temperature)

I = Industrial (–40°C to +100°C Ambient Temperature)

ES= Engineering Sample (Room Temperature Only)

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant

Package Type

Fine Pitch Ball Grid Array (1.0 mm pitch)

Very Fine Pitch Ball Grid Array (0.8 mm pitch)

Speed Grade

Blank = TBD

1 = TBD

Security

Design Security

Data and Design Security

Blank

Transceiver

T = With Transceiver

Blank = No Transceiver

Part Number (Digits Indicate Thousands of LUTs)

M2S005

M2S010

M2S025

M2S050

M2S080

M2S120

Revision 0

SmartFusion2 System-on-Chip FPGAs

SmartFusion2 Valid Part Numbers

Table 3 • SmartFusion2 Valid Part Numbers for Devices with Design Security

Commercial

Industrial

–1 Speed Grade, Data Security

Std. Speed Grade

M2S005-VF400

M2S010-VF400

M2S025-VF400

M2S050-VF400

M2S005-FG484

M2S010-FG484

M2S025-FG484

M2S050-FG484

M2S050-FG896

M2S080-FC1152

M2S120-FC1152

Transceivers

–1 Speed Grade

M2S005-1VF400

M2S010-1VF400

M2S025-1VF400

M2S050-1VF400

M2S005-1FG484

M2S010-1FG484

M2S025-1FG484

M2S050-1FG484

M2S050-1FG896

M2S080-1FC1152

M2S120-1FC1152

Transceivers

–1 Speed Grade

M2S005-1VF400I

M2S010-1VF400I

M2S025-1VF400I

M2S050-1VF400I

M2S005-1FG484I

M2S010-1FG484I

M2S025-1FG484I

M2S050-1FG484I

M2S050-1FG896I

M2S080-1FC1152I

M2S120-1FC1152I

Transceivers

M2S005S-1VF400I

M2S010S-1VF400I

M2S025S-1VF400I

M2S050S-1VF400I

M2S005S-1FG484I

M2S010S-1FG484I

M2S025S-1FG484I

M2S050S-1FG484I

M2S050S-1FG896I

M2S080S-1FC1152I

M2S120S-1FC1152I

Transceivers

M2S010T-VF400

M2S025T-VF400

M2S050T-VF400

M2S010T-FG484

M2S025T-FG484

M2S050T-FG484

M2S050T-FG896

M2S080T-FC1152

M2S120T-FC1152

M2S010T-1VF400

M2S025T-1VF400

M2S050T-1VF400

M2S010T-1FG484

M2S025T-1FG484

M2S050T-1FG484

M2S050T-1FG896

M2S080T-1FC1152

M2S120T-1FC1152

M2S010T-1VF400I

M2S025T-1VF400I

M2S050T-1VF400I

M2S010T-1FG484I

M2S025T-1FG484I

M2S050T-1FG484I

M2S050T-1FG896I

M2S080T-1FC1152I

M2S120T-1FC1152I

M2S010TS-1VF400I

M2S025TS-1VF400I

M2S050TS-1VF400I

M2S010TS-1FG484I

M2S025TS-1FG484I

M2S050TS-1FG484I

M2S050TS-1FG896I

M2S080TS-1FC1152I

M2S120TS-1FC1152I

SmartFusion2 Device Status

Family Devices

Status

Advance

M2S050T

Contact your local Microsemi SoC Products Group representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Revision 0

SmartFusion2 System-on-Chip FPGAs

Table of Contents

SmartFusion2 Device Family Overview

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Highest Security Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

High Performance FPGA Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Clock Sources: On-Chip Oscillators, PLLs, and CCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

High Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

High Speed Memory Interfaces: DDRx Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

SmartFusion2 DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Average Fabric Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Logic Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

FPGA Fabric SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80

Clock Conditioning Circuits (CCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83

Inter-Integrated Circuit (I²C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

SmartFusion2 Development Tools

Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SoftConsole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

SoftConsole User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Firmware Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Firmware Catalog User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

SoC FPGA Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

SmartFusion2 Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Dedicated Global I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

User I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Multi-Standard I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Multi-Function I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Datasheet Information

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Revision 0

VII

1 – SmartFusion2 Device Family Overview

Microsemi’s SmartFusion2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM

Cortex-M3 processor and high performance communications interfaces on a single chip. The

SmartFusion2 family is the industry’s lowest power, highest reliability and most secure programmable

logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate count implemented

with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple

embedded memory options and math blocks for DSP. The 166 MHz ARM Cortex-M3 processor is

enhanced with ETM and 8 Kbyte instruction cache, and additional peripherals including CAN, Gigabit

Ethernet, and high speed USB. High speed serial interfaces enable PCIe, XAUI / XGXS + Native

SERDES communication while DDR2/DDR3 memory controllers provide high speed memory interfaces.

SmartFusion2 Chip Layout

4 PLLs

SERDES

MSS DDR

uSRAM

(1 Kb)

East IOs

West IOs

FPGA

Fabric

eNVM

Math

Blocks

HVBias

LSRAM

(18 Kb)

Oscillators

MSS

Column

Access

Fabric DDR

Crystal

SERDES

3 PLLs

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1-1

SmartFusion2 Device Family Overview

Reliability

SmartFusion2 flash-based fabric has zero FIT configuration rate due to its single event upset (SEU)

immunity, which is critical in reliability applications. The flash fabric also has the advantage that no

external configuration memory is required, making the device instant-on; it retains configuration when

powered off. To complement this unique FPGA capability, SmartFusion2 adds reliability to many other

aspects of the device. Single Error Correct Double Error Detect (SECDED) protection is implemented on

the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the

DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of

more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA

fabric to allow the user to monitor the status of these protected internal memories. Other areas of the

architecture are implemented with latches, which are not subject to SEUs. Therefore, no correction is

needed in these locations: DDR Bridges (MSS, MDDR, FDDR), Instruction Cache and MMUART, SPI,

and PCIe FIFOs.

Highest Security Devices

Building further on the intrinsic security benefits of flash nonvolatile memory technology, the

SmartFusion2 family incorporates essentially all the legacy security features that made the original

SmartFusion, Fusion^®, IGLOO^®, and ProASIC^®3 third-generation flash FPGAs and cSoCs the gold

standard for secure devices in the PLD industry. In addition, the fourth-generation flash-based

SmartFusion2 SoC FPGAs add many unique design and data security features and use models new to

the PLD industry.

Design Security vs. Data Security

When classifying security attributes of programmable logic devices (PLDs), a useful distinction is made

between design security and data security.

Design Security

Design security is protecting the intent of the owner of the design, such as keeping the design and

associated bitstream keys confidential, preventing design changes (insertion of Trojan Horses, for

example), and controlling the number of copies made throughout the device life cycle. Design security

may also be known as intellectual property (IP) protection. It is one aspect of anti-tamper (AT) protection.

Design security applies to the device from initial production, includes any updates such as in-the-field

upgrades, and can include decommissioning of the device at the end of its life, if desired. Good design

security is a prerequisite for good data security.

The following are the main design security features supported:

•

User key and bitstream loading in less-trusted locations

Encrypted key loading using device-unique built-in factory key

–

•

Methods to verify devices are programmed correctly, even if done in less-trusted locations

Supply-chain assurances to eliminate counterfeiting

Differential power analysis (DPA) and enhanced anti-tamper features to address non-invasive,

semi-invasive, and invasive attacks

•

Ability to zeroize (destroy) all sensitive stored data in the event of tampering

The M2S080 and M2S120 also have the following features:

–

Elliptic Curve Cryptography (ECC) for securely loading user keys

An SRAM-type Physically Unclonable Function (SRAM-PUF) for device authentication

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SmartFusion2 System-on-Chip FPGAs

Data Security

Data security is protecting the information the FPGA is storing, processing, or communicating in its role in

the end application. If, for example, the configured design is implementing the key management and

encryption portion of a secure military radio, data security could entail encrypting and authenticating the

radio traffic, and protecting the associated application-level cryptographic keys. Data security is closely

related to the terms information assurance (IA) and information security.

All SmartFusion2 devices incorporate enhanced design security, making them the most secure

programmable logic devices ever made. Select SmartFusion2 models also include an advanced set of

on-chip data security features that make designing secure information assurance applications easier and

better than ever before.

The following are the main data security features supported:

•

Non-deterministic random bit generator (NRBG) service

User Cryptographic services (e.g., AES-128/-256, SHA-256, and HMAC)

Hardware firewalls protecting MSS memories

Cryptography Research Inc. (CRI) pass-through Differential Power Analysis (DPA) Patent

Portfolio license

•

The M2S080 and M2S120 also have the following features:

–

Elliptic Curve Cryptography (ECC) cryptographic computation services

User PUF key enrollment and regeneration for advanced design and data security

applications

Low Power

Microsemi’s flash-based FPGA fabric results in extremely low power design implementation with static

power on the M2S050 device as low as 10 mW. Flash*Freeze (F*F) technology provides an ultra-low

power static mode (Flash*Freeze mode) for SmartFusion2 devices, with power less than 1 mW. F*F

mode entry retains all the SRAM and register information and the exit from F*F mode achieves rapid

recovery to active mode.

High Performance FPGA Fabric

Built on 65 nm process technology, the SmartFusion2 FPGA fabric is composed of 4 building blocks: the

logic module, the large SRAM, the micro SRAM and the Math block. The logic module is the basic logic

element and has advanced features:

•

A fully permutable 4-input LUT (look-up table) optimized for lowest power

A dedicated carry chain based on carry look-ahead technique

A separate flip-flop which can be used independently from the LUT

The 4-input look-up table can be configured either to implement any 4-input combinatorial function or to

implement an arithmetic function where the LUT output is XORed with carry input to generate the sum

output.

Dual-Port Large SRAM (LSRAM)

Large SRAM (RAM1Kx18) is targeted for storing large memory for use with various operations. Each

LSRAM block can store up to 18,432 bits. Each RAM1Kx18 block contains two independent data ports:

Port A and Port B. The LSRAM is synchronous for both Read and Write operations. Operations are

triggered on the rising edge of the clock. The data output ports of the LSRAM have pipeline registers

which have control signals that are independent of the SRAM’s control signals.

Three-Port Micro SRAM (uSRAM)

Micro SRAM (RAM64x18) is the second type of SRAM which is embedded in the fabric of SmartFusion2

devices. RAM64x18 uSRAM is a 3-port SRAM; it has two read ports (Port A and Port B) and one write

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1-3

SmartFusion2 Device Family Overview

port (Port C). The two read ports are independent of each other and can perform Read operations in both

synchronous and asynchronous modes. The write port is always synchronous. The uSRAM block is

approximately 1 Kb (1,152 bits) in size. These uSRAM blocks are primarily targeted for building

embedded FIFOs to be used by any embedded fabric masters.

Math Blocks for DSP Applications

The fundamental building block in any digital signal processing algorithm is the multiply-accumulate

function. SmartFusion2 implements a custom 18x18 Multiply-Accumulate (18x18 MACC) block for

efficient implementation of complex DSP algorithms such as finite impulse response (FIR) filters, infinite

impulse response (IIR) filters, and fast Fourier transform (FFT) for filtering and image processing

applications.

Each Math block has the following capabilities:

•

Supports 18x18 signed multiplications natively (a[17:0] x b[17:0])

Supports dot product; the multiplier computes:

(A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 2⁹

•

Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently

In addition to the basic MACC function, DSP algorithms typically need small amounts of RAM for

coefficients and larger RAMs for data storage. SmartFusion2 micro RAMs are ideally suited to serve the

needs of coefficient storage while the large RAMs are used for data storage.

Microcontroller Subsystem (MSS)

The microcontroller subsystem (MSS) contains a high-performance integrated Cortex-M3 processor,

running at up to 166 MHz. The MSS contains an 8 Kbyte instruction cache to provide low latency access

to internal eNVM and external DDR memory. The MSS provides multiple interfacing options to the FPGA

fabric in order to facilitate tight integration between the MSS and user logic in the fabric.

ARM Cortex-M3 Processor

The MSS uses the latest revision (r2p1) of the ARM Cortex-M3 processor. Microsemi’s implementation

includes the optional embedded trace macrocell (ETM) features for easier development and debug and

the memory protection unit (MPU) for real-time operating system support.

Cache Controller

In order to minimize latency for instruction fetches when executing firmware out of off-chip DDR or

on-chip eNVM, an 8 kbyte, 4-way set associative instruction cache is implemented. This provides zero

wait state access for cache hits and is shared by both I and D Code buses of the Cortex-M3 processor. In

the event of cache misses, cache lines are filled, replacing existing cache entries based on a least

recently used (LRU) algorithm.

There is a configurable option available to operate the cache in a locked mode, whereby a fixed segment

of code from either the DDR or eNVM is copied into the cache and locked there, so that it is not replaced

when cache misses occur. This would be used for performance-critical code.

It is also possible to disable the cache altogether, which is desirable in systems requiring very

deterministic execution times.

The cache is implemented with SEU tolerant latches.

DDR Bridge

The DDR bridge is a data bridge between four AHB bus masters and a single AXI bus slave. The DDR

bridge accumulates AHB writes into write combining buffers prior to bursting out to external DDR

memory. The DDR bridge also includes read combining buffers, allowing AHB masters to efficiently read

data from the external DDR memory from a local buffer. The DDR bridge optimizes reads and writes from

multiple masters to a single external DDR memory. Data coherency rules between the four masters and

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SmartFusion2 System-on-Chip FPGAs

the external DDR memory are implemented in hardware. The DDR Bridge contains three write

combining / read buffers and one read buffer. All buffers within the DDR bridge are implemented with

SEU tolerant latches and are not subject to the single event upsets (SEUs) that SRAM exhibits.

SmartFusion2 devices implement three DDR bridges in the MSS, FDDR, and MDDR subsystems.

AHB Bus Matrix (ABM)

The AHB bus matrix (ABM) is a non-blocking, AHB-Lite multi-layer switch, supporting 10 master

interfaces and 7 slave interfaces. The switch decodes access attempts by masters to various slaves,

according to the memory map and security configurations. When multiple masters are attempting to

access a particular slave simultaneously, an arbiter associated with that slave decides which master

gains access, according to a configurable set of arbitration rules. These rules can be configured by the

user to provide different usage patterns to each slave. For example, a number of consecutive access

opportunities to the slave can be allocated to one particular master, to increase the likelihood of same

type accesses (all reads or all writes), which makes more efficient usage of the bandwidth to the slave.

System Registers

The MSS System registers are implemented as an AHB slave on the AHB bus matrix. This means the

Cortex-M3 processor or a soft master in the FPGA fabric may access the registers and therefore control

the MSS. The System registers can be initialized by user-defined flash configuration bits on power-up.

Each register also has a flash bit to enable write protecting the contents of the registers. This allows the

MSS system configuration to be reliably fixed for a given application.

Fabric Interface Controller (FIC)

The FIC block provides two separate interfaces between the MSS and the FPGA fabric: the MSS Master

(MM) and Fabric Master (FM). Each of these interfaces can be configured to operate as AHB-Lite or

APB3. Depending on device density, there are up to two FIC blocks present in the MSS (FIC_0 and

FIC_1).

Embedded SRAM (eSRAM)

The MSS contains two blocks of 32 KB eSRAM, giving a total of 64 KB. Having the eSRAM arranged as

two separate blocks allows the user to take advantage of the Harvard architecture of the Cortex-M3

processor. For example, code could be located in one eSRAM, while data, such as the stack, could be

located in the other.

The eSRAM is designed for Single Error Correct Double Error Detect (SECDED) protection. When

SECDED is disabled, the SRAM usually used to store SECDED data may be reused as an extra 16 KB

of eSRAM.

Embedded NVM (eNVM)

The MSS contains up to 512 KB of eNVM (64 bits wide). Accesses to the eNVM from the Cortex-M3

processor are cacheable.

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1-5

SmartFusion2 Device Family Overview

DMA Engines

Two DMA engines are present in the MSS: high performance DMA and peripheral DMA.

High Performance DMA (HPDMA)

The high-performance DMA (HPDMA) engine provides efficient memory to memory data transfers

between an external DDR memory and internal eSRAM. This engine has two separate AHB-Lite

interfaces—one to the MDDR bridge and the other to the AHB bus matrix. All transfers by the HPDMA

are full word transfers.

Peripheral DMA (PDMA)

The peripheral DMA engine (PDMA) is tuned for offloading byte-intensive operations, involving MSS

peripherals, to and from the internal eSRAMs. Data transfers can also be targeted to user logic/RAM in

the FPGA fabric.

APB Configuration Bus

On every SmartFusion2 device memory, an APB configuration bus is present to allow the user to initialize

the SERDES ASIC blocks, the fabric DDR memory controller, and user instantiated peripherals in the

FPGA fabric.

Peripherals

A large number of communications and general purpose peripherals are implemented in the MSS.

USB Controller

The MSS contains a high speed USB 2.0 On-The-Go (OTG) controller with the following features:

•

Operates either as the function controller of a high-speed / full-speed USB peripheral or as the

host/peripheral in point-to-point or multi-point communications with other USB functions.

Complies with the USB 2.0 standard for high-speed functions and with the On-The-Go

supplement to the USB 2.0 specification.

Supports OTG communications with one or more high-speed, full-speed, or low-speed devices.

TSE Ethernet MAC

The Triple Speed Ethernet (TSE) MAC supports IEEE 802.3 10/100/1000Mbps Ethernet operation. The

following PHY interfaces are directly supported by the MAC:

•

RMII

GMII

MII

TBI

The Ethernet MAC hardware implements the following functions:

•

4 KB internal transmit FIFO and 8 KB internal receive FIFO

IEEE 802.3X full-duplex flow control

DMA of Ethernet frames between internal FIFOs and system memory (such as eSRAM or DDR)

Cut-through operation

SECDED protection on internal FIFOs

SGMII PHY Interface

SGMII mode is implemented by means of configuring the MAC for 10-bit interface (TBI) operation,

allocating one of the high-speed serial channels to SGMII and by implementing custom logic in the fabric.

10 Gbps Ethernet

Support for 10 Gbps Ethernet is achieved by programming the SERDES interface to XAUI mode. In this

mode, a soft 10G EMAC with XGMII interface can be directly connected to the SERDES. interface.

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SmartFusion2 System-on-Chip FPGAs

Communication Block (COMM_BLK)

The COMM block provides a UART-like communications channel between the MSS and the System

Controller. System services are initiated through the COMM block. System services such as Enter

Flash*Freeze Mode are initiated though this block.

SPI

The serial peripheral interface controller is compliant with the Motorola SPI, Texas Instruments

synchronous serial, and National Semiconductor MICROWIRE™ formats. In addition, the SPI supports

interfacing to large SPI flash and EEPROM devices by way of the slave protocol engine. The SPI

controller supports both Master and Slave modes of operation.

The SPI controller embeds two 4×32 (depth × width) FIFOs for receive and transmit. These FIFOs are

accessible through RX data and TX data registers. Writing to the TX data register causes the data to be

written to the transmit FIFO. This is emptied by transmit logic. Similarly, reading from the RX data register

causes data to be read from the receive FIFO.

Multi-Mode UART (MMUART)

SmartFusion2 devices contain two identical multi-mode universal asynchronous/synchronous

receiver/transmitter (MMUART) peripherals that provide software compatibility with the popular 16550

device. They perform serial-to-parallel conversion on data originating from modems or other serial

devices, and perform parallel-to-serial conversion on data from the Cortex-M3 processor to these

devices.

The following are the main features supported:

•

Fractional baud rate capability

Asynchronous and synchronous operation

Full programmable serial interface characteristics

–

Data width is programmable to 5, 6, 7, or 8 bits

Even, odd, or no-parity bit generation/detection

1,1½, and 2 stop bit generation

•

9-bit address flag capability used for multidrop addressing topologies

I C

SmartFusion2 devices contain two identical master/slave I²C peripherals that perform serial to-parallel

conversion on data originating from serial devices, and perform parallel-to-serial conversion on data from

the ARM Cortex-M3 processor, or any other bus master, to these devices. The following are the main

features supported:

•

I²C v2.1

–

100 Kbps

400 Kbps

•

Dual-slave addressing

SMBus v2.0

PMBus v1.1

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1-7

SmartFusion2 Device Family Overview

Clock Sources: On-Chip Oscillators, PLLs, and CCCs

SmartFusion2 devices have two on-chip RC oscillators—a 1 MHz RC oscillator and a 50 MHz RC

oscillator—and up to two main crystal oscillators (32 KHz–20 MHz). These are available to the user for

generating clocks to the on-chip resources and the logic built on the FPGA fabric array. The second

crystal oscillator available on the SmartFusion2 devices is dedicated for RTC clocking. These oscillators

(except the RTC crystal oscillator) can be used in conjunction with the integrated user phase-locked

loops (PLLs) and FAB_CCCs to generate clocks of varying frequency and phase. In addition to being

available to the user, these oscillators are also used by the system controller, power-on reset circuitry,

MSS during Flash*Freeze mode, and the RTC.

SmartFusion2 devices have up to eight fabric CCC (FAB_CCC) blocks and a dedicated PLL associated

with each CCC to provide flexible clocking to the FPGA fabric portion of the device. The user has the

freedom to use any of the eight PLLs and CCCs to generate the fabric clocks and the internal MSS clock

from the base fabric clock (CLK_BASE). There is also a dedicated CCC block for the MSS (MSS_CCC)

and an associated PLL (MPLL) for MSS clocking and de-skewing the CLK_BASE clock. The fabric

alignment clock controller (FACC), part of the MSS CCC, is responsible for generating various aligned

clocks required by the MSS for correct operation of the MSS blocks and synchornous communication

with the user logic in the FPGA fabric.

High Speed Serial Interfaces

SERDES Interface

SmartFusion2 has up to four 5 Gbps SERDES transceivers, each supporting the following:

•

4 SERDES/PCS lanes

The native SERDES interface facilitates implementation of Serial RapidIO (SRIO) in fabric or an

SGMII interface for the Ethernet MAC in MSS

PCI Express (PCIe)

PCIe is a high speed, packet-based, point-to-point, low pin count, serial interconnect bus. The

SmartFusion2 family has two hard high-speed serial interface blocks. Each SERDES block contains a

PCIe (PCI Express) system block. The PCIe system is connected to the SERDES block and following

are the main features supported:

•

Supports x1, x2 and x4 lane configuration

Endpoint configuration only

PCI Express Base Specification Revision 2.0

2.5 and 5.0 Gbps compliant

Embedded Receive (2 KB), Transmit (1 KB) and Retry (1 KB) buffer dual-port RAM

implementation

•

256 bytes maximum payload size

64-bit AXI or 32-bit/64-bit AHBL Master and Slave interface to the application layer

32-bit APB interface to access configuration and status registers of PCIe system

Up to 3 x 64 bit base address registers

1 virtual channel (VC)

Intel’s PIPE interface (8-bit/16-bit) to interface between the PHY MAC and PHY (SERDES)

Fully compliant PHY PCS sub-layer (125/250 MHz)

XAUI/XGXS Extension

The XAUI/XGXS extension allows the user to implement a 10 Gbps (XGMII) Ethernet PHY interface by

connecting the Ethernet MAC fabric interface through an appropriate soft IP block in the fabric.

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SmartFusion2 System-on-Chip FPGAs

High Speed Memory Interfaces: DDRx Memory Controllers

There are up to two DDR subsystems, MDDR (MSS DDR) and FDDR (Fabric DDR) present in

SmartFusion2 devices. Each subsystem consists of a DDR controller, PHY and a wrapper. The MDDR

has an interface from the MSS and fabric and FDDR provides an interface from the fabric.

The following are the main features supported by FDDR and MDDR:

•

Support for LPDDR, DDR2, and DDR3 memories

Support for SDRAM memories

Simplified DDR command interface to standard AMBA AXI/AHB interface

Up to 667 Mbps (333 MHz double data rate) performance

Supports 1, 2, or 4 ranks of memory

Supports different DRAM Bus width modes: x16, x18, x32, and x36

Supports DRAM burst length of 2, 4, or 8 in full bus-width mode; supports DRAM burst length of 2,

4, 8, or 16 in half bus-width mode

•

Supports memory densities up to 4 GB

Supports a maximum of 8 memory banks

SECDED enable/disable feature

Embedded physical interface (PHY)

Read and Write buffers in fully associative CAMs, configurable in powers of 2, up to 64 Reads

plus 64 Writes

•

Support for dynamically changing clock frequency while in self-refresh.

Supports command reordering to optimize memory efficiency

Supports data reordering, returning critical word first for each command

MDDR Subsystem

The MDDR subsystem has two interfaces to the DDR. One is an AXI 64-bit bus from the DDR bridge

within the MSS. The other is a multiplexed interface from the FPGA fabric, which can be configured as

either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus,

which is used to initialize the majority of the internal registers within the MDDR subsystem after reset.

This APB configuration bus can be mastered by the MSS directly or by a master in the FPGA fabric.

FDDR Subsystem

The FDDR subsystem has one interface to the DDR. This is a multiplexed interface from the FPGA

fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is

also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within

the FDDR subsystem after reset. This APB configuration bus can be mastered by the MSS directly or by

a master in the FPGA fabric.

Revision 0

1-9

ADVANCE INFORMATION (Subject to Change)

2 – SmartFusion2 DC and Switching Characteristics

General Specifications

Operating Conditions

Table 2-1 • Recommended Operating Conditions

Conditions

Symbol

Parameter

Junction temperature

DC core supply voltage

Min.

Typ. Max. Units Notes

T_J

Commercial

Industrial

°C

–40

100

VDD

VPP

1.14

2.375

3.15

1.2

2.5

3.3

1.26

2.625

3.45

Power supply for charge pumps (for 2.5 V range

normal opeartion and

programming)

3.3 V range

PLLx_VDDA

Analog power supply for PLL0 to

PLL5

2.5 V range

3.3 V range

2.5 V range

3.3 V range

2.375

3.15

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

1.2

2.5

1.2

1.5

1.8

2.5

3.3

2.5

3.3

0.5

2.625

3.45

PLL_PCIE_x_VDDA Auxiliary power supply voltage by

core to macro

2.375

3.15

2.625

3.45

PLL_MDDR_VDDA Analog power supply for PLL 2.5 V range

2.375

3.15

2.625

3.45

MDDR

3.3 V range

PLL_FDDR_VDDA Analog power supply for PLL FDDR 2.5 V range

3.3 V range

2.375

3.15

2.625

3.45

PCIExVDD

PCIe/PCS power supply

1.14

1.26

PCIExVDDIO[L/R]

Tx/Rx analog I/O voltage supply

1.14

1.26

PCIExVDDPLL[L/R] Anlog power supply for SERDES PLL of PCIe

2.375

1.14

2.625

1.26

VDDIx

1.2 V DC supply voltage

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS differential I/O

1.425

1.71

1.575

1.89

2.375

3.15

2.625

3.45

2.375

3.45

B-LVDS, M-LVDS, Mini-LVDS, RSDS differential I/O 2.375

2.625

3.45

LVPECL differential I/O

3.15

VREFx

Reference voltage supply for FDDR (bank 0) and

MDDR (bank 5)

0.49

0.51

* VDDI0 * VDDI0 * VDDI0

VCCENVM

Embedded nonvolatile memory 2.5 V range

2.375

3.15

2.5

3.3

2.625

3.45

supply

3.3 V range

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2-1

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-2 • FPGA and Embedded Flash Programming, Storage and Operating Limits

Storage

Temperature

Programming

Temperature

Grade Programming

Cycles

Product Grade

Element

Retention

Commercial

Min. T_J= 0°C

FPGA

500

20 years

Max. T_J= 85°C

Min. T_J= 0°C

Embedded Flash

< 1,000

< 10,000

500

20 years

10 years

20 years

Max. T_J= 85°C

Industrial

Min. T_J= –40°C

Max. T_J= 100°C

Min. T_J= 0°C

FPGA

Max. T_J= 85°C

Min. T_J= –40°C

Max. T_J= 100°C

Embedded Flash

< 1,000

20 years

10 years

< 10,000

Power Supply Sequencing and Power-On Reset (Commercial and

Industrial)

Sophisticated power-up management circuitry is designed into every SmartFusion2 SoC FPGA. These

circuits ensure easy transition from powered-off state to powered-up state of the device. The

SmartFusion2 system controller is responsible for systematic power-on reset whenever the device is

powered on or reset. All the I/Os are held in a high-impedance state by the system controller until all

power supplies are at their required levels and the system controller has completed the reset sequence.

The power-on reset circuitry in SmartFusion2 devices requires the VDD supply to ramp at a predefined

rate. Four ramp rate options are available during design generation: 50 µs, 100 µs, 1 ms, and 100 ms.

2-2

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ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Thermal Characteristics

Introduction

The temperature variable in the SoC Products Group Designer software refers to the junction

temperature, not the ambient, case, or board temperatures. This is an important distinction because

dynamic and static power consumption will cause the chip's junction temperature to be higher than the

ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal

resistance, temperature gradient, and power.

T_J– θ_A

------------------

θ_JA

θ_JB

θ_JC

EQ 1

T_J– T_B

------------------

EQ 2

EQ 3

T_J– T_C

------------------

where

θ_JA= Junction-to-air thermal resistance

θ_JB= Junction-to-board thermal resistance

θ_JC= Junction-to-case thermal resistance

T_J= Junction temperature

T_A= Ambient temperature

T_B= Board temperature (measured 1.0 mm away from the

package edge)

T_C= Case temperature

= Total power dissipated by the device

Table 2-3 • Package Thermal Resistance

θ_JA

1.0 m/s

12.5

Product

Still Air

2.5 m/s

θ_JC

θ_JB

Units

°C/W

M2S050T-FG896

14.7

10.9

7.2

4.9

Revision 0

2-3

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Theta-JA

Junction-to-ambient thermal resistance (θ_JA) is determined under standard conditions specified by

JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with

caution but is useful for comparing the thermal performance of one package to another.

The maximum power dissipation allowed is calculated using EQ 4.

_J(MAX)– T_A(MAX)

---------------------------------------------

Maximum Power Allowed =

θ_JA

EQ 4

The absolute maximum junction temperature is 100°C. EQ 5 shows a sample calculation of the absolute

maximum power dissipation allowed for the M2S050T-FG896 package at commercial temperature and in

still air, where

θ_JA= 14.7°C/W (taken from Table 2-3 on page 2-3).

T_A

= 85°C

100°C – 85°C

14.7°C/W

------------------------------------

Maximum Power Allowed =

= 1.088 W

EQ 5

The power consumption of a device can be calculated using the Microsemi SoC Products Group power

calculator. The device's power consumption must be lower than the calculated maximum power

dissipation by the package. If the power consumption is higher than the device's maximum allowable

power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must

be increased.

Theta-JB

Junction-to-board thermal resistance (θ_JB) measures the ability of the package to dissipate heat from the

surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance

from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a

means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a

JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.

Theta-JC

Junction-to-case thermal resistance (θ_JC) measures the ability of a device to dissipate heat from the

surface of the chip to the top or bottom surface of the package. It is applicable for packages used with

external heat sinks. Constant temperature is applied to the surface in consideration and acts as a

boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through

the surface in consideration.

2-4

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Calculating Power Dissipation

Quiescent Supply Current

Table 2-4 • Quiescent Supply Current Characteristics

M2S050T

Parameter

IDC1

Modes

VDD = 1.2 V

7.5

Units

Active mode

IDC2

Standby mode

7.5

IDC3

Flash*Freeze mode

0.387

I/O Power

Table 2-5 • Summary of I/O Input Buffer Power (per pin)

Using Default Software Setting with Technology Selected

MSIO I/O Bank

MSIOD I/O Bank

DDR I/O Bank

Static Dynamic

Static

Dynamic

Static

Dynamic

Power

PDC8

(mW)

PAC9

(µW/MHz)

PDC8

(mW)

PAC9

(µW/MHz)

PDC8

(mW)

PAC9

(µW/MHz) Notes

Single Ended I/O Standards

1.2 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11)

1.8 V LVCMOS

0.00

11.72

8.32

10.69

4.14

5.47

1.82

0.00

–

11.72

8.32

10.69

4.14

–

0.00

–

11.72

8.32

10.69

4.14

–

2.5 V LVCMOS

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V PCI/PCIX

–

Memory Interface and Voltage Reference Standard

HSTL 1.5 V

2.21

1.25

10.02

4.39

3.88

1.97

–

5.57

47.38

42.68

12.35

3.81

56.80

–

2.21

1.25

10.02

4.39

3.88

1.97

–

5.57

47.38

42.68

12.35

3.81

56.80

–

2.21

1.25

10.02

4.39

3.88

1.97

2.20

1.23

3.88

1.97

5.57

47.38

42.68

12.35

3.81

HSTL 1.5 V – True differential

SSTL2/DDR

SSTL2/DDR – True differential

SSTL18/DDR2

SSTL18/DDR2 – True differential

SSTL15/DDR3

56.80

18.00

46.81

4.46

SSTL15/DDR3 – True differential

LPDDR

–

LPDDR – True differential

Differential Standards

LVDS

–

5.08

5.74

5.65

5.74

TBD

17.65

8.76

0.93

TBD

5.74

5.65

5.74

TBD

–

17.65

8.76

0.93

TBD

–

B-LVDS

M-LVDS

RSDS

Mini-LVDS

LVPECL

Revision 0

2-5

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-6 • Summary of I/O Output Buffer Power (per pin)

Default Software Setting with Technology selected

MSIO I/O Bank

MSIOD I/O Bank

DDR I/O Bank

Static Dynamic Static Dynamic Static Dynamic

Power

Power Power Power

PDC9

PAC9

PDC9

PAC9 PDC9 PAC9

(mW) (µW/MHz) (mW) (µW/MHz) (mW) (µW/MHz) Notes

Single Ended I/O Standards

1.2 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11)

1.8 V LVCMOS

0.00

16.74

26.31

38.23

75.35

137.04

TBD

0.00

–

16.74

26.31

38.23

75.35

–

0.00

–

16.74

26.31

38.23

75.35

–

2.5 V LVCMOS

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V PCI/PCIX

–

Memory Interface and Voltage Reference Standard

HSTL 1.5 V Class I

6.45

60.17

80.30

–

6.45

12.90

–

60.17

80.30

–

6.45

12.90

12.56

25.08

18.12

36.16

60.17

80.30

104.21

87.09

76.44

218.81

HSTL 1.5 V Class I – True differential

HSTL 1.5 V Class II

12.90

–

HSTL 1.5 V Class II – True differential

SSTL2 Class I / DDR Reduced Drive

–

18.12

36.16

76.44

218.81

18.12

36.16

76.44

218.81

SSTL2 Class I / DDR Reduced Drive

– True differential

SSTL2 Class II / DDR Full Drive

37.20

74.41

317.68

110.90

37.20

74.41

317.68

110.90

37.20

74.41

317.68

110.90

SSTL2 Class II / DDR Full Drive

– True differential

SSTL18 Class I / DDR2 Reduced Drive

9.06

15.09

56.33

9.06

15.09

56.33

9.06

15.09

56.33

SSTL18 Class I / DDR2 Reduced Drive

– True differential

18.09

SSTL18 Class II / DDR2 Full Drive

18.63

37.28

170.66

9.12

18.63

37.28

170.66

9.12

18.63

37.28

170.66

9.12

SSTL18 Class II / DDR2 Full Drive

– True differential

SSTL15 Class I / DDR3 Reduced Drive

–

11.28

22.52

62.13

SSTL15 Class I / DDR3 Reduced Drive

– True differential

131.80

SSTL15 Class II / DDR3 Full Drive

–

12.15

24.29

47.65

SSTL15 Class II / DDR3 Full Drive

– True differential

142.98

LPDDR Reduced Drive

–

18.62

37.28

9.06

331.33

9.12

LPDDR Reduced Drive – True differential

LPDDR Full Drive

46.40

56.33

LPDDR Full Drive – True differential

18.09

Differential Standards

LVDS

13.48

18.37

8.50

63.84

30.73

82.76

TBD

13.48

–

63.84

–

B-LVDS

M-LVDS

–

RSDS

8.50

TBD

82.76

TBD

Mini-LVDS

TBD

2-6

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Power Consumption of Various Internal Resources

Table 2-7 • Different Components Contributing to Dynamic Power Consumption

in SmartFusion2 Devices

Power Supply

Device

Param.

Definition

Name

Domain

1.2 V

M2S050T

3.50

Units Notes

µW/MHz

PAC1 Global Clock contribution of a GB

VDD

PAC2 Global Clock contribution of a RGB

0.87

µW/MHz

PAC3 Global Clock contribution of a sequential module.

PAC4 Clock contribution of a sequential module.

PAC5 Data contribution of a sequential module.

PAC6 Average contribution of a combinatorial module.

0.02

µW/MHz

0.01

µW/MHz

0.06965 µW/MHz

0.709 µW/MHz

0.821657 µW/MHz

PAC7 Average contribution of a combinatorial module with VDD

carry chain.

PAC8 Average contribution of a routing net.

VDD

1.2 V

0.87

µW/MHz

–

PAC9 Contribution of an I/O input pin (standard dependent)

VDDI

Table 2-5

on page 2-5 on page 2-5

PAC10 Contribution of an I/O output pin (standard dependent) VDDI

Table 2-6 Table 2-6

–

on page 2-6 on page 2-6

PAC11 Average contribution of a uSRAM block during a read VDD

operation.

1.2 V

2.39

µW/MHz

PAC12 Average contribution of a uSRAM block during a write VDD

operation.

7.01

PAC13 Average contribution of a LSRAM block during a read VDD

operation.

19.85

24.85

PAC14 Average contribution of a LSRAM block during a write VDD

operation.

PAC15 CCC contribution

VDD

1.2 V

8.00

55.51

37.2

µW/MHz

PAC16 Main Crystal Oscillator contribution

PAC17 1 MHz RC Oscillator contribution

PAC18 50 MHz RC Oscillator contribution

PAC19 Math Block contribution

7.30

TBD

PAC20 MSS Dynamic Power Contribution with

MDDR/USB/Ethernet OFF,

91.986

Clock Frequency = 100 MHz

PAC21 MSS Dynamic Power Contribution with USB/Ethernet VDD

OFF, Clock Frequency = 100 MHz,

1.2 V

137.43

MDDR mode–MSS Bridge

Notes:

1. For a different use of MSS peripherals and resources, refer to SmartPower.

2. Dynamic power contribution of FDDR does not include the DDRIO power. Use I/O power for calculation of I/O power. For

a different use of the FDDR, refer to SmartPower.

3. For a different use of the SERDES block, refer to SmartPower.

Revision 0

2-7

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-7 • Different Components Contributing to Dynamic Power Consumption

in SmartFusion2 Devices (continued)

Power Supply

Device

M2S050T

108.81

Param.

Definition

Name

Domain

Units Notes

PAC22 FDDR Dynamic Power Contribution

VDD

1.2 V

with frequency = 100 MHz, DDR Clock Multiplier = 2

PAC23 SERDES Dynamic Power Contribution configured as VDD

PCIe_GEN1 with 1 Lane at 125 MHz

1.2 V

91.70

Notes:

1. For a different use of MSS peripherals and resources, refer to SmartPower.

2. Dynamic power contribution of FDDR does not include the DDRIO power. Use I/O power for calculation of I/O power. For

a different use of the FDDR, refer to SmartPower.

3. For a different use of the SERDES block, refer to SmartPower.

Table 2-8 • Different Components Contributing to the Static Power Consumption in SmartFusion Devices

Power Supply

Name Domain Mode

Device

M2S050T

9.000

Param.

Definition

Units

PDC1

Core static power contribution in Active Operating VDD

mode

1.2 V

Active

PDC2

PDC3

PDC4

PDC5

PDC6

PDC7

PDC8

PDC9

Core static power contribution in Standby VDD

Operating mode

1.2 V

Standby

9.000

0.465

1.250

10.140

0.500

4.970

Core static power contribution in Flash*Freeze VDD

Operating mode

1.2 V Flash*Freeze

LSRAM static power contribution in Flash*Freeze VDD

configured in "Sleep" State

LSRAM static power contribution in Flash*Freeze VDD

configured in "Suspended" State

USRAM static power contribution in Flash*Freeze VDD

configured in "Sleep" State

USRAM static power contribution in Flash*Freeze VDD

configured in "Suspend" State

I/O Input static power contribution in Active VDDI

Operating mode

VDDI

Active

SeeTable 2-5

on page 2-5

I/O Output static power contribution in Active VDDI

Operating mode

SeeTable 2-6

on page 2-6

2-8

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Power Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power

calculation methodology described below uses the following variables:

•

The number of PLLs/CCCs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as the logic module—guidelines are provided in Table 2-9 on

page 2-13.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-10 on

page 2-13.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-10 on page 2-13.

The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—P

TOTAL

Active, Standby and Flash*Freeze Mode

P_TOTAL= P_STAT+ PDYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

Active Mode

STAT

P_STAT= PDC1 + (N_I_NPUTS* PDC7) + (N_OUTPUTS* PDC8) + (N_PLLS* PDC9)

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

N_PLLSis the number of PLLs available in the device.

Standby Mode

P_STAT= PDC2

Flash*Freeze Mode

P_STAT= PDC3 + PDC4 + PDC 6 when both LSRAM and uSRAM are configured in Sleep state

P_STAT= PDC3 + PDC5 + PDC 7 when both LSRAM and uSRAM are configured in Suspend state

Total Dynamic Power Consumption—P

Active Mode

DYN

P_DYN= P_CLOCK+ P_LOGIC+ P_IOS+ P_MEMORY+ P_CCC+ P_MATH+ P_MSS+ P_FDDR+ P_SERDES

Flash*Freeze Mode

P_DYN= PDC3 + P_MEMORY

Standby Mode

P_DYN= PDC2

Revision 0

2-9

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Global Clock Dynamic Power Contribution—P

CLOCK

Active Mode

P_CLOCK= (PAC1 + N_ROWS* PAC2 + N_S-CELL* PAC3) * F_CLK

Where:

N_ROWSis the number of global rows used in the design—guidelines are provided in the "Fabric

Global Routing Resources" chapter of the SmartFusion2 FPGA Fabric Architecture User's Guide.

F_CLKis the global clock signal frequency.

N_{S-CELL i}s the number of Registers used in the design.

Standby and Flash*Freeze Mode

P_CLOCK= 0 W

Logic Module Dynamic Power Contribution—P

LOGIC

Active Mode

P_LOGIC= P_SEQ+ P_LUT+ P_NET

Standby and Flash*Freeze Mode

P_LOGIC= 0 W

Registers Dynamic Power Contribution—P

SEQ

P_SEQ= N_S-CELL* PAC4 * F_CLK+ N_S-CELL* PAC5 * F_CLK* α1/2

Where:

N_S-CELLis the number of registers used in the design.

α1 is the toggle rate of the LUT outputs—guidelines are provided in Table 2-9 on page 2-13.

F_CLKis the global clock signal frequency.

LUTs Dynamic Power Contribution—P

LUT

P_LUT= (N_LUT* PAC6 + N_CC* PAC7) * F_CLK* α1/2

Where:

N_LUTis the number of LUT-4 used as combinatorial modules in the design.

_CCis the number of LUT-4 used with the carry chain in the design.

α1 is the toggle rate of the LUT outputs—guidelines are provided in Table 2-9 on page 2-13.

_CLKis the global clock signal frequency.

Routing Net Dynamic Power Contribution—P

NET

P_NET= (N_S-CELL+ N_LUT+ N_CC)* (α1 / 2) * PAC8 * F_CLK

Where:

_S-CELLis the number of registers used in the design.

N_LUTis the number of LUT-4 used as combinatorial modules in the design.

_CCis the number of LUT-4 used with the carry chain in the design.

α1 is the toggle rate of the LUT outputs—guidelines are provided in Table 2-9 on page 2-13.

_CLKis the global clock signal frequency.

I/O Dynamic Contribution—P

IOS

Active Mode

P_IOS= PI_NPUTS+ P_OUTPUTS

Standby and Flash*Freeze Mode

P_IOS= 0 W

2-10

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

I/O Input Buffer Dynamic Contribution—P

INPUTS

PINPUTS = NINPUTS * (α2 / 2) * β1 * PAC9 * FCLK

Where:

N_INPUTSis the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-9 on page 2-13.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-10 on page 2-13.

F_CLKis the global clock signal frequency.

I/O Output Buffer Dynamic Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* (α2 / 2) * β1 * PAC10 * F_CLK

Where:

N_OUTPUTSis the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-9 on page 2-13.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-10 on page 2-13.

F_CLKis the global clock signal frequency.

FPGA Fabric SRAM Dynamic Contribution—P

MEMORY

Active Mode

P_MEMORY= P_USRAM+ P_LSRAM

Flash*Freeze Mode

P_MEMORY= PDC4 + PDC6 for RAM in "Sleep" State

P_MEMORY= PDC5 + PDC7 for RAM in "Suspend" State

Standby Mode

P_MEMORY= 0 W

FPGA Fabric uSRAM Dynamic Contribution—P_USRAM

P_uSRAM= (N_{uSRAM_BLK}* PAC13 *β2 * F_uSRAM-RDCLK) + (N_{uSRAM_BLK}* PAC14 * β3

* F_uSRAM-WRTCLK

)

Where:

Nu_{SRAM_BLK}is the number of uRAM blocks used in the design.

_uSRAM-RDCLKis the uSRAM memory read clock frequency.

F_uSRAM-WRTCLKis the uSRAM memory write clock frequency.

β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-10 on

page 2-13.

β3 the RAM enable rate for write operations—guidelines are provided in Table 2-10 on page 2-13.

FPGA Fabric Large SRAM Dynamic Contribution—P

LSRAM

P_LSRAM= (N_{LSRAM_BLK}* PAC13 * β2 * F_LSRAM-RDCLK) + (N_{LSRAM_BLK}* PAC14 * β3

* F_LSRAM-WRTCLK

)

Where:

N_{LSRAM_BLK}is the number of Large SRAM blocks used in the design.

_LSRAM-RDCLKis the Large SRAM memory read clock frequency.

_LSRAM-WRTCLKis the Large SRAM memory write clock frequency.

β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-10 on

page 2-13.

β3 the RAM enable rate for write operations—guidelines are provided in Table 2-10 on page 2-13.

Revision 0

2-11

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

PLL/CCC Dynamic Contribution—P

PLL

Active Mode

P_PLL= PAC15

Flash*Freeze/Standby Mode

P_PLL= 0 W

External Main Crystal Oscillator Dynamic Contribution—P

XTL-OSC

Active Mode

P_XTL-OSC= PAC16 * F_CLK

Where:

F_CLKis the output frequency of the oscillator.

Flash*Freeze/Standby Mode

P_XTL-OSC= 0 W

On-Chip 25/50MHz RC Oscillator Dynamic Contribution—P_50RC-OSC

Active Mode/Standby Mode

P_50RC-OSC= 0 W

Flash*Freeze

When used by MSS:

P_50RC-OSC= PAC18

When not used by MSS:

P50RC-OSC = 0 W

Math Block Dynamic Power Contribution—P

MATH

Active Mode

P_MATH= PAC19 * N_{MATH_BLK}* F_MATHCLK

N_{MATH_BLK}is the number of math blocks used in the design.

_MATHCLKis the math block clock frequency.

Flash*Freeze/Standby Mode

P_MATH= 0 W

Microcontroller Subsystem Dynamic Power Contribution—P

MSS

Active Mode

With MDDR OFF:

P_MSS= PAC20

With MDDR ON:

P_MSS= PAC21

Flash*Freeze/Standby Mode

P_MSS= 0 W

2-12

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

FDDR Dynamic Power Contribution—P

FDDR

Active Mode

PFDDR = PAC22

FDDR Dynamic power contributions do not include the power contributions of the DDR I/O. This should

be accounted for in the I/O power calculations.

Flash*Freeze/Standby Mode

P_FDDR= 0 W

SERDES Contribution—P

SERDES

Active Mode

P_SERDES= PAC23

Flash*Freeze/Standby Mode

P_SERDES= 0 W

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1 = 50%

Bit 2 = 25%

…

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 2-9 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of Logic Module outputs

I/O buffer toggle rate

Guideline

10%

α1

α2

10%

Table 2-10 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

β1

β2

β3

β4

Toggle rate of the logic driving the output buffer

FPGA fabric SRAM enable rate for read operations

FPGA fabric SRAM enable rate for write operations

eNVM enable rate for read operations

12.50%

< 5%

Revision 0

2-13

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Average Fabric Temperature and Voltage Derating Factors

Table 2-11 • Average Temperature and Voltage Derating Factors for Fabric Timing Delays

(normalized to T_J= 100°C, worst-case VDD = 1.14 V)

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

TBD

0°C

TBD

25°C

TBD

70°C

TBD

85°C

TBD

100°C

TBD

1.14

1.2

1.26

2-14

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

LVDS

I/O Module

(Non-Registered)

Combinational Cell

Buffer

LVCMOS 2.5 V

Output Drive Strength = 7X

MSIO I/O Bank

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Buffer

LVCMOS 2.5 V

Output Drive Strength = 4X

MSIO I/O Bank

DDR3

I/O Module

(Non-Registered)

Combinational Cell

LVCMOS 1.5 V

Output Drive Strength = 12X

DDRIO I/O Bank

Input

Clock

I/O Module

(Registered)

Combinational Cell

Buffer

LVCMOS 2.5 V

SSTL2

Class I

I/O Module

(Non-Registered)

LVDS

Input

Clock

Input

Clock

LVCMOS 2.5 V

Figure 2-1 • Timing Model

Revision 0

2-15

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-12 • Timing Model Parameters

Index Parameter Description

Propagation Delay of DDR3 Receiver

Value

TBD

0.22

0.172

TBD

0.24

Units

Notes

tPY

Table 2-51 on page 2-51

Table 2-73 on page 2-65

Table 2-79 on page 2-76

Table 2-57 on page 2-55

Table 2-77 on page 2-73

Table 2-58 on page 2-55

Table 2-77 on page 2-73

Table 2-25 on page 2-25

tICLKQ Clock-to-Q of the Input Data Register

tISUD Setup Time of the Input Data Register

tRCKH Input High Delay for Global Clock

tRCKL Input Low Delay for Global Clock

tPY

tDP

Input Propagation Delay of LVDS Receiver

Propagation Delay of a three input AND Gate

Propagation Delay of a OR Gate

Propagation Delay of a LVDS Transmitter

Propagation Delay of a three input XOR Gate

Propagation Delay of LVCMOS 2.5 V Transmitter, 2.481

Drive strength of 8X on the MSIO Bank

tDP

Propagation Delay of a two input MUX gate

0.172

Table 2-77 on page 2-73

Table 2-25 on page 2-25

Propagation Delay of LVCMOS 2.5 V Transmitter, 2.382

Drive strength of 4X on the MSIO Bank

tCLKQ Clock-to-Q of the Data Register

0.114

0.267

0.172

TBD

Table 2-78 on page 2-75

Table 2-77 on page 2-73

Table 2-73 on page 2-65

Table 2-46 on page 2-44

tSUD

tDP

Setup Time of the Data Register

Propagation Delay of a two input AND gate

tOCLKQ Clock-to-Q of the Output Data Register

tOSUD Setup Time of the Output Data Register

TBD

tDP

Propagation Delay of SSTL2, Class I Transmitter on TBD

the MSIO Bank

tDP

Propagation Delay of LVCMOS 1.5 V Transmitter, TBD

Drive strength of 15X on the DDRIO Bank

Table 2-33 on page 2-31

2-16

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

User I/O Characteristics

There are three types of I/Os supported in the SmartFusion2 FPGA Family: MSIO, MSIOD, and DDRIO

I/O banks. The I/O standards supported by the different I/O banks is described in the "I/Os" section of the

SmartFusion2 FPGA Fabric Architecture User’s Guide.

Input Buffer and AC Loading

t_PY

t_PYS

PAD

t_PY= MAX(t_PY(R), t_PY(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

Vtrip

VDD

VIL

PAD

50%

GND

t_PYS

(R)

t_PY

t_PYS

(F)

t_PY

(F)

(R)

Revision 0

2-17

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Output Buffer and AC Loading

Single-Ended I/O Test Setup

t_DP

HSTL/PCI Test Setup

t_DP

VTT/VDDI

PAD

Rtt

Cload

t_DP= MAX(t_DP(R), t_DP(F))

Voltage-Referenced, Singled-Ended I/O Test Setup

t_DP

PAD

Rtt

Cload

_DP= MAX(t_DP(R), t_DP(F))

Differential I/O Test Setup

t_DP

t_PY

PAD_P

Z₀= 50 Ohms

PAD_P

PAD_N

Z₀= 50 Ohms

t_PY= MAX(t_PY(R), t_PY(F))

t_DP= MAX(t_DP(R), t_DP(F))

t_PYS= MAX(t_PYS(R), t_PYS(F))

VDD

50%

VOH

0 V

Vtrip

VOL

OUT

t_DP

(R)

t_DP

(F)

2-18

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Tristate Buffer and AC Loading

The tristate path for enable path loadings is described in the respective specifications. The methodology

of characterization is illustrated by the enable path test point below.

_ZL, t_ZH, t_HZ, t_LZ

PAD

OUT

R_entto GND for t_ZH, t_HZ

Data

(D)

50%

t_HZ

50%

t_ZL

Enable

(E)

50%

t_LZ

t_ZH

PAD

90% VDDI

10% VDDI

Revision 0

2-19

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Detailed I/O Characteristics

Table 2-13 • Input Capacitance

Symbol

Definition

Conditions

Minimum

Maximum

Units

C_IN

Input capacitance

VIN = 0, f = 1.0 MHz

–

Table 2-14 • I/O Weak Pull-Up/Pull-Down Resistances for DDRIO I/O Bank

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values at VOH/VOL

Level

DDRIO I/O Bank

R(WEAK PULL-UP) at VOH (Ω) R(WEAK PULL-DOWN) at VOL (Ω)

VDDI

Domain

Min.

N/A

Max.

N/A

Min.

N/A

Max.

N/A

Notes

–

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

Notes:

10.6 K

1.11 K

10 K

17.3 K

19.3 K

13.4 K

14.5 K

10.5 K

11.2 K

9.99 K

10.3 K

18.1 K

20.9 K

13.4 K

14.7 K

1, 2

10.3 K

1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)

2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)

Table 2-15 • I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values at VOH/VOL

Level

MSIO IO Bank

R(WEAK PULL-UP) at VOH (Ω) R(WEAK PULL-DOWN) at VOL (Ω)

VDDI

Domain

Min.

Max.

Min.

Max.

Notes

–

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

Notes:

9.9 K

14.7 K

15.1 K

16.2 K

17.3 K

19.7 K

10.1 K

10.4 K

10.8 K

11.5 K

15.3 K

15.7 K

17.3 K

18.9 K

22.7 K

10.1 K

10.4 K

10.7 K

11.3 K

1, 2

1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)

2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)

2-20

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-16 • I/O Weak Pull-Up/Pull-Down Resistances for MSIOD I/O Bank

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values at VOH/VOL

Level

R(WEAK PULL-UP) at VOH (Ω) R(WEAK PULL-DOWN) at VOL (Ω)

VDDI

Domain

Min.

N/A

Max.

N/A

Min.

N/A

Max.

N/A

Notes

–

3.3 V

2.5 V

9.6 K

9.7 K

9.9 K

10.3 K

14.1 K

14.7 K

15.3 K

16.7 K

9.5 K

9.7 K

9.8 K

10 K

13.9 K

14.5 K

15 K

1, 2

1.8 V

1.5 V

1.2 V

16.2 K

Notes:

1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)

2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)

Table 2-17 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value for Schmitt Trigger Mode Input Buffers

Input Buffer Configuration

3.3 V LVTTL / LVCMOS / PCI / PCI-X

2.5 V LVCMOS

Hysteresis Value (typical, unless otherwise noted)

0.05 × VDDI (worst-case)

0.1 × VDDI (worst-case)

60 mV

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

20 mV

Revision 0

2-21

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Single-Ended I/O Standards

Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined

by JEDEC (JESD 8-5). The LVCMOS standards supported in SmartFusion2 SoC FPGAs are

LVCMOS12, LVCMOS15, LVCMOS18, and LVCMOS25 and LVCMOS33.

3.3 V LVCMOS/LVTTL

LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V

applications.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-18 • LVTTL/LVCMOS 3.3 V DC Voltage Specification

Symbol

Recommended DC Operating Conditions

VDDI Supply voltage

Parameters

Conditions

Min.

Typ. Max. Units Notes

3.15

3.3

3.45

LVTTL/LVCMOS 3.3 V DC Input Voltage Specification

VIH (DC) DC input logic High

2.0

–0.3

–

3.45

0.8

VIL (DC) DC input logic Low

IIH (DC) Input current High

IIL (DC) Input current Low

–

LVCMOS 3.3 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

VDDI – 0.4

–

0.4

LVTTL 3.3 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

0.4

–

2.4

LVTTL/LVCMOS 3.3 V AC Specifications

Fmax

Maximum data rate

(for MSIO I/O bank)

AC loading: 10 pF / 500 Ohm Load,

maximum drive/slew

–

600

Mbps

LVTTL/LVCMOS 3.3 V AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path

–

1.4

–

Ohms

Rent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for data path (tDP)

Cent

Cload

Notes:

1. The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements.

2-22

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-19 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications

Output Drive Selection

MSIO I/O Bank

VOH (V)

VOL (V)

0.4

IOH (at VOH) mA

IOL (at VOL) mA

Notes

VDDI – 0.4

0.4

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 3.0 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-20 • LVCMOS 3.3 V Receiver Characteristics

TDIN

TSCH_DIN

On Die Termination

(ODT)

–1

Std.

–1

Std.

Units

LVCMOS 3.3 V (For MSIO I/O bank)

None

2.46

2.893

2.408

2.833

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-21 • LVCMOS 3.3 V Transmitter Characteristics

Output

Drive

Selection Control

TDOUT

TENZL

–1 Std.

TENZH

TENHZ

–1 Std.

TENLZ

Slew

–1

Std.

–1

Std.

–1

Std. Units

LVCMOS 3.3 V (for MSIO I/O bank)

–

3.274 3.853 3.459 4.069

2.418 2.845 2.914 3.427

2.221 2.614 4.195 4.935

2.128 2.505 5.135 6.041

2.147 2.526 5.776 6.795

2.228 2.622 5.958 7.009

3.269

4.35

3.845 3.608 4.244

5.116 3.064 3.604

3.419 4.022

4.5

5.293

5.7

4.695

5.105

5.451

5.691

5.523 4.345

5.112

4.845

6.005 5.285 6.218

6.412 5.926 6.972

6.695 6.108 7.186

5.255 6.182

5.601 6.589

5.841 6.872

Revision 0

2-23

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

LVCMOS 2.5 V

LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in SmartFusion2 FPGAs in

compliance to the JEDEC specification JESD8-5A.

Minimum and Maximum DC Input and Output Levels Specification

Table 2-22 • LVCMOS 2.5 V DC Voltage Specification

Symbol

Recommended DC Operating Conditions

VDDI Supply Voltage

LVCMOS 2.5 V DC Input Voltage Specification

Parameters

Conditions

Min.

Typ.

Max. Units Notes

2.375

2.5

2.625

VIH (DC) DC input logic High for (MSIOD and DDRIO I/O bank)

VIH (DC) DC input logic High (for MSIO I/O bank)

1.7

–0.3

–

2.625

3.45

0.7

–

VIL (DC)

IIH (DC)

IIL (DC)

DC input logic Low

Input current High

Input current Low

–

LVCMOS 2.5 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

VDDI – 0.4

–

0.4

LVCMOS 2.5 V AC Specifications

Fmax

Maximum data rate (for AC loading: 5 pF load,

DDRIO I/O bank) maximum drive/slew

–

250

410

420

Mbps

Ohms

Maximum data rate (for AC loading: 10 pF / 500 Ohm

MSIO I/O bank) load, maximum drive/slew

Maximum data rate (for AC loading: 10 pF / 500 Ohm

MSIOD I/O bank)

load, maximum drive/slew

Supported output driver

calibrated impedance (for

DDRIO I/O bank)

75, 60,

50, 33,

25, 20

LVCMOS 2.5 V AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path

1.2

Ohms

Rent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for data path (tDP)

Cent

Cload

Notes:

1. The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.

2-24

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-23 • LVCMOS 2.5 V Transmitter Drive Strength Specifications

Output Drive Selection

VOH (V)

Min.

VOL (V)

Max.

0.4

IOH (at VOH) IOL (at VOL)

MSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank

Notes

VDDI – 0.4

0.4

N/A

0.4

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 3.0 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-24 • LVCMOS 2.5 V Receiver Characteristics

TDIN

TSCH_DIN

On Die Termination

(ODT)

N/A

–1

Std.

TBD

3.052

TBD

–1

Std.

TBD

3.013

TBD

Units

LVCMOS 2.5 V (for DDRIO I/O bank)

LVCMOS 2.5 V (for MSIO I/O bank)

LVCMOS 2.5 V (for MSIOD I/O bank)

TBD

2.594

TBD

2.561

TBD

N/A

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-25 • LVCMOS 2.5 V Transmitter Characteristics

Slew

TDOUT

TENZL

TENZH

TENHZ

TENZH

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std. Units

LVCMOS 2.5 V (for DDRIO I/O bank with FIED CODES)

TBD

Revision 0

2-25

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-25 • LVCMOS 2.5 V Transmitter Characteristics (continued)

Slew

TDOUT

TENZL

TENZH

TENHZ

TENZH

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std. Units

TBD

LVCMOS 2.5 V (for MSIO I/O bank)

None

3.534 4.158 3.816 4.489

2.651 3.118 3.898 4.586

2.463 2.898 4.794 5.639

2.382 2.802 5.724 6.734

2.405 2.829 5.883 6.921

2.481 2.918 6.281 7.389

3.742

4.625

4.994

5.417

5.593

5.871

4.402 3.888 4.574 3.814 4.487

5.441 3.971 4.672 4.698 5.527

5.875 4.867 5.725 5.067 5.961

6.373 5.797

6.58 5.956 7.007 5.666 6.666

6.907 6.354 7.475 5.944 6.993

6.82

5.49

6.459

LVCMOS 2.5 V (for MSIOD I/O bank)

None

2.367 2.786 5.054 5.946

1.978 2.328 5.533 6.509

1.843 2.169 5.927 6.973

4.749

5.159

5.495

5.795

5.998

5.587 5.158 6.069 4.853

5.71

6.069 5.637 6.632 5.263 6.192

6.465 6.031 7.096 5.599 6.588

1.757 2.067 6.33

7.447

6.818 6.434

7.57

5.899 6.941

1.77 2.083 6.607 7.773

7.056 6.711 7.896 6.102 7.179

2-26

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

1.8 V LVCMOS

LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in SmartFusion2 FPGAs in

compliance to the JEDEC specification JESD8-7A.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-26 • LVCMOS 1.8 V DC Voltage Specification

Symbols

Recommended DC Operating Conditions

VDDI Supply Voltage

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

1.710

1.8

1.89

LVCMOS 1.8 V DC Input Voltage Specification

VIH (DC) DC input logic High for (MSIOD and DDRIO I/O bank)

VIH (DC) DC input logic High (for MSIO I/O bank)

VIL (DC) DC input logic Low

0.65 * VDDI

–

1.89

3.45

0.65 * VDDI

–0.3

–

0.35 * VDDI

IIH (DC) Input current High

IIL (DC) Input current Low

–

LVCMOS 1.8 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

VDDI – 0.45

–

0.45

LVCMOS 1.8 V AC Specifications

Fmax

Maximum data rate (for AC loading: 5 pF load,

DDRIO I/O bank) maximum drive/slew

–

200

295

320

Mbps

Ohms

Maximum data rate (for AC loading: 10 pF / 500 Ohm

MSIO I/O bank) load, maximum drive/slew

Maximum data rate (for AC loading: 10 pF / 500 Ohm

MSIOD I/O bank)

load, maximum drive/slew

Supported output driver

calibrated impedance (for

DDRIO I/O bank)

75, 60,

50, 33,

25, 20

LVCMOS 1.8 V AC Test Parameters Specifications

Vtrip

Rent

Cent

Cload

Measuring/trip point for data path

–

0.9

–

Ohms

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for data path (tDP)

Table 2-27 • LVCMOS 1.8 V Transmitter Drive Strength Specifications

Output Drive Selection

VOH (V)

Min.

VOL (V)

Max.

0.45

IOH (at VOH) IOL (at VOL)

MSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank

Notes

VDDI – 0.4

0.45

N/A

0.45

N/A

0.45

Revision 0

2-27

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 1.71 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-28 • LVCMOS 1.8 V Receiver Characteristics

TDIN

TSCH_DIN

–1

Units

On Die Termination (ODT)

–1

Std.

TBD

3.813

3.973

3.92

3.865

TBD

Std.

TBD

3.82

3.977

3.932

3.879

TBD

LVCMOS 1.8 V

(for DDRIO I/O bank)

150

TBD

3.241

3.377

3.332

3.285

TBD

3.248

3.381

3.342

3.297

TBD

LVCMOS 1.8 V

(for MSIO I/O bank)

150

LVCMOS 1.8 V

(for MSIOD I/O bank)

150

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-29 • LVCMOS 1.8 V Transmitter Characteristics

Slew

TDOUT

TENZL

TENZH

TENHZ

TENLZ

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std. Units

LVCMOS 1.8 V (for DDRIO I/O bank)

TBD

2-28

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-29 • LVCMOS 1.8 V Transmitter Characteristics (continued)

Slew

TDOUT

TENZL

TENZH

TENHZ

TENLZ

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std. Units

TBD

LVCMOS 1.8 V (for MSIO I/O bank)

None

3.486 4.101 4.621 5.436

3.244 3.816 5.351 6.295

5.107

5.518

5.963

6.131

6.344

6.44

6.008 4.607 5.419

6.492 5.337 6.278

7.015 6.306 7.419

7.213 6.563 7.721

7.464 6.942 8.167

7.577 7.062 8.307

5.093 5.991

5.504 6.475

5.949 6.998

6.117 7.196

3.148 3.703 6.32

7.436

3.189 3.752 8.577 7.738

3.241 3.812 6.956 8.184

3.319 3.904 7.076 8.324

6.33

7.447

7.56

6.426

LVCMOS 1.8 V (For MSIOD I/O bank)

None

2.789 3.282 5.321

6.26

4.98

5.42

5.86

5.383 6.333

5.042 5.933

5.482 6.45

6.007 7.067

2.332 2.744 5.846 6.878

6.377 5.908 6.951

6.994 6.559 7.717

2.1

2.472 6.497 7.644

2.47 6.755 7.947

5.945

6.142

6.355

2.099

7.227 6.817

8.02

6.204

6.417

7.3

2.136 2.513 7.046

8.29

7.477 7.108 8.363

7.55

Revision 0

2-29

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

1.5 V LVCMOS

LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in SmartFusion2 FPGAs in

compliance to the JEDEC specification JESD8-11A.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-30 • LVCMOS 1.5 V DC Voltage Specification

Symbols

Recommended DC Operating Conditions

VDDI Supply Voltage

LVCMOS 1.5 V DC Input Voltage Specification

VIH (DC) DC input logic High for (MSIOD and DDRIO I/O banks) 0.65 * VDDI

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

1.425

1.5

1.575

–

1.575

3.45

VIH (DC) DC input logic High (for MSIO I/O bank)

VIL (DC) DC input logic Low

0.65 * VDDI

–0.3

–

0.35 * VDDI

IIH (DC) Input current High

IIL (DC

Input current Low

–

LVCMOS 1.5 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

VDDI * 0.75

–

VDDI * 0.25

LVCMOS 1.5 V AC Specifications

Fmax

Maximum data rate (for AC loading: 5 pF load,

DDRIO I/O bank) maximum drive/slew

–

130

Mbps

Ohms

Maximum data rate (for AC loading: 10 pF / 500 Ohm

MSIO I/O bank) load, maximum drive/slew

Maximum data rate (for AC loading: 10 pF / 500 Ohm

170

MSIOD I/O bank)

load, maximum drive/slew

Supported output driver

75, 60,

50, 40

calibrated

impedance

(for DDRIO I/O bank)

LVCMOS 1.5 V AC Test Parameters Specifications

Vtrip

Rent

Cent

Cload

Measuring/trip point

–

0.75

–

Ohms

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for data path (tDP)

Table 2-31 • LVCMOS 1.5 V Transmitter Drive Strength Specifications

Output Drive Selection

VOH (V)

VOL (V)

MSIO I/O

Bank

MSIOD I/O

DDRIO I/O

Bank

IOH (at VOH) IOL (at VOL)

Bank

Min.

Max.

Notes

VDDI * 0.75 VDDI * 0.25

N/A

2-30

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 1.425 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-32 • LVCMOS 1.5 V Receiver Characteristics

TDIN

TSCH_DIN

On Die Termination

(ODT)

–1

Std.

TBD

4.49

4.858

4.717

4.607

TBD

–1

Std.

TBD

4.522

4.898

4.757

4.64

TBD

Units

LVCMOS 1.5 V

(for DDRIO I/O bank)

150

TBD

3.817

4.13

4.01

3.916

TBD

3.844

4.164

4.044

3.944

TBD

LVCMOS 1.5 V

(for MSIO I/O bank)

150

LVCMOS 1.5 V

(for MSIOD I/O bank)

150

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-33 • LVCMOS 1.5 V Transmitter Characteristics

Slew

TDOUT

TENZL

TENZH

TENHZ

TENLZ

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std. Units

LVCMOS 1.5 V (for DDRIO I/O bank)

TBD

Revision 0

2-31

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-33 • LVCMOS 1.5 V Transmitter Characteristics (continued)

Slew

TDOUT

TENZL

TENZH

TENHZ

TENLZ

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std.

TBD

–1

Std. Units

TBD

LVCMOS 1.5 V (for MSIO I/O bank)

None

4.437 5.219 5.342 6.285

3.989 4.692 7.006 8.242

5.57

6.488

6.664

6.99

6.552 5.295

6.23

5.523 6.497

7.633 6.959 8.187 6.441 7.578

7.839 7.241 8.519 6.617 7.784

8.224 7.822 9.202 6.943 8.169

4.046

4.76 7.288 8.574

4.226 4.971 7.869 9.257

LVCMOS 1.5 V (For MSIOD I/O bank)

None

2.788 3.279 6.125 7.206

2.489 2.927 6.831 8.037

5.662

6.24

6.661 6.179

7.27

5.716 6.725

7.341 6.885 8.101 6.294 7.405

7.679 7.266 8.548 6.581 7.743

2.508

2.95 7.212 8.484

6.527

2-32

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

1.2 V LVCMOS

LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in SmartFusion2 FPGAs in

compliance to the JEDEC specification JESD8-12A.

LVCMOS 1.2 V Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-34 • LVCMOS 1.2 V DC Voltage Specification

Symbols

Recommended DC Operating Conditions

VDDI Supply Voltage

LVCMOS 1.2 V DC Input Voltage Specification

VIH (DC) DC input logic High for (MSIOD and DDRIO I/O bank) 0.65 * VDDI

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

1.14

1.2

1.26

–

1.26

3.45

VIH (DC) DC input logic High (for MSIO I/O bank)

VIL (DC) DC input logic Low

0.65 * VDDI

–0.3

–

0.35 * VDDI

IIH (DC) Input current High

IIL (DC) Input current Low

–

LVCMOS 1.2 V DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

VDDI * 0.75

–

VDDI * 0.25

LVCMOS 1.2 V AC Specifications

Fmax

Rref

Maximum data rate (for AC loading: 2 pF load,

DDRIO I/O bank) maximum drive/slew

–

Mbps

Ohms

Maximum data rate (for AC loading: 2.5 pF load,

MSIO I/O bank) maximum drive/slew

Maximum data rate (for AC loading: 2.5 pF load,

100

MSIOD I/O bank)

maximum drive/slew

Supported output driver

calibrated impedance (for

DDRIO I/O bank)

75, 60,

50, 40

LVCMOS 1.2 V AC Test Parameters Specifications

Vtrip

Rent

Cent

Cload

Measuring/trip point

–

0.6

–

Ohms

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for data path (tDP)

Table 2-35 • LVCMOS 1.2 V Transmitter Drive Strength Specifications

Output Drive Selection

VOH (V)

VOL (V)

MSIO I/O

Bank

MSIOD I/O

DDRIO I/O

Bank

IOH (at VOH) IOL (at VOL)

Bank

Min.

Max.

Notes

VDDI * 0.75 VDDI * 0.25

N/A

Revision 0

2-33

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 1.14 V

AC Switching Characteristics for Receiver (Input Buffers))

Table 2-36 • LVCMOS 1.2 V Receiver Characteristics

TDIN

TSCH_DIN

–1

On Die Termination (ODT)

–1

Std.

TBD

Std.

TBD

6.276

8.042

7.32

Units

LVCMOS 1.2 V

(for DDRIO I/O bank)

150

TBD

5.3

TBD

5.335

6.836

6.23

TBD

LVCMOS 1.2 V

6.235

7.971

7.269

6.686

TBD

(for MSIO I/O bank)

150

6.776

6.179

5.683

TBD

4.639

5.599

5.037

5.73

6.741

TBD

5.502

6.66

LVCMOS 1.2 V

(for MSIOD I/O bank)

TBD

4.676

5.66

150

5.458

6.588

5.926

5.081

5.978

2-34

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-37 • LVCMOS 1.2 V Transmitter Characteristics

Slew

TDOUT

TENZL

TENZH

TENHZ

TENLZ

Output

Drive

Control

(0 lowest,

Selection 3 highest)

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std. Units

LVCMOS 1.2 V (for DDRIO I/O bank)

TBD

LVCMOS 1.2 V (for MSIO I/O bank)

None

5.87

6.905 8.659 10.186 7.563 8.897

8.53 10.035 7.434 8.746

9.51 11.188 7.985 9.395

6.215 7.312 9.639 11.339 8.114 9.546

LVCMOS 1.2 V (For MSIOD I/O bank)

None

3.509 4.128 7.29

8.577 6.693 7.874 7.356 8.654 6.759 7.951

3.419 4.022 8.135 9.571 7.347 8.644 8.201 9.648 7.413 8.721

Revision 0

2-35

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

3.3 V PCI/PCIX

Peripheral Component Interface (PCI) for 3.3 V standards specifies support for 33 MHz and 66 MHz PCI

bus applications.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-38 • PCI/PCIX DC Voltage Specification – Applicable to MSIO Bank ONLY

Symbols

PCI/PCIX Recommended DC Operating Conditions

VDDI Supply Voltage

PCI/PCIX DC Input Voltage Specification

Parameters

Conditions

Min.

Typ.

Max. Units Notes

3.15

3.3

3.45

DC input voltage

Input current High

Input current Low

–

3.45

IIH(DC)

IIL(DC)

µA

PCI/PCIX DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

Per PCI Specification

PCI/PCIX AC Specifications

Fmax Maximum data rate (MSIO

AC Loading: per JEDEC

specifications

–

630

Mbps

I/O bank)

PCI/PCIX AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path (falling edge)

–

0.615 * VDDI

–

Vtrip

Measuring/trip point for data path (rising edge)

Resistance for data test path

0.285 * VDDI

Rtt_test

Rent

Ohms

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Cent

2-36

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 3.0 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-39 • AC Switching Characteristics for Receiver (Input Buffers)

TDIN

TSCH_DIN

Speed Grade

On Die Termination

(ODT)

–

Std.

2.667

–1

2.25

Std.

Units

PCI/PCIX (for MSIO I/O bank)

None

2.266

2.648

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-40 • AC Switching Characteristics for Transmitter (Output and Tristate Buffers

TDOUT

–1 Std.

PCI/PCIX (for MSIO I/O bank)

TBD TBD TBD

TENZL

TENZH

TENHZ

TENLZ

–1 Std.

–1

Std.

–1

Std.

–1

Std.

Units

TBD

Revision 0

2-37

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Memory Interface and Voltage Referenced I/O Standards

High-Speed Transceiver Logic (HSTL)

The High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard

sponsored by IBM (EIA/JESD8-6). SmartFusion2 devices support two classes of the 1.5 V HSTL. These

differential versions of the standard require a differential amplifier input buffer and a push-pull output

buffer.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-41 • HSTL DC Voltage Specification

Symbols Parameters

Recommended DC Operating Conditions

Conditions

Min.

Typ.

Max.

Units Notes

VDDI

VTT

Supply Voltage

1.425

0.698

1.5

1.575

0.803

Termination Voltage

Input Reference Voltage

0.750

VREF

HSTL DC Input Voltage Specification

VIH (DC)

VIL (DC)

IIH (DC)

IIL (DC)

DC input logic High

DC input logic Low

Input current High

Input current Low

VREF + 0.1

–

1.575

VREF – 0.1

–0.3

–

HSTL DC Output Voltage Specification

HSTL Class I

VOH

VOL

DC output logic High

DC output logic Low

VDDI – 0.4

–

0.4

–

IOH at VOH Output minimum source DC current (MSIOD I/O bank)

IOL at VOL Output minimum sink current (MSIOD I/O bank)

–7.8

7.8

–

IOH at VOH Output minimum source DC current (MSIO and

DDRIO I/O banks)

–8.0

–

IOL at VOL Output minimum sink current (MSIO and DDRIO I/O

banks)

8.0

–

HSTL Class II (Applicable to MSIO and DDRIO IO Bank only)

VOH

VOL

DC output logic High

DC output logic Low

VDDI – 0.4

–

0.4

–

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

–16.0

16.0

–

HSTL AC/DC Differential Voltage Specifications

VID (DC)

VDIFF (AC) AC input differential voltage

Vx (AC) AC differential cross point voltage

HSTL AC Specifications

DC input differential voltage

0.2

0.4

–

0.68

0.9

Fmax

Notes:

Maximum data rate (DDRIO

I/O bank)

AC loading: per

JEDEC specifications

–

800

140

Mbps

Maximum data rate (for MSIO AC loading:

I/O bank) 3 pF / 50 Ohm load

1. MSIOD I/O bank HSTL Class I does not meet standard JEDEC test point. Use provided lower current values as

specified.

2-38

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-41 • HSTL DC Voltage Specification (continued)

Symbols

Parameters

Conditions

AC loading:

3 pF / 50 Ohm load

Min.

Typ.

Max.

Units Notes

Fmax

Maximum data rate (for

MSIOD I/O bank)

–

180

Mbps

Rref

RTT

Supported output driver

calibrated impedance (for

DDRIO I/O bank)

Reference resistance

= 191 Ohms

–

25.5,

47.8

–

Ohms

Effective impedance value

(with respect to reference

resistor of 191 Ohms) (ODT for

DDRIO I/O bank only)

Reference resistance

= 191 Ohms

47.8

RTT

Effective impedance value

(ODT for MSIO and MSIOD I/O = 191 Ohms

banks only)

Reference resistance

–

50, 75,

150

–

Ohms

HSTL AC Test Parameters Specification

Vtrip

Measuring/trip point for data path

–

Rent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

Ohms

Cent

Rtt_test

Reference resistance for data test path for SSTL15

Class I (tDP)

Ohms

Rtt_test

Reference resistance for data test path for SSTL15

Class II (tDP)

–

Ohms

Cload

Capacitive Loading for Data Path (tDP)

Notes:

1. MSIOD I/O bank HSTL Class I does not meet standard JEDEC test point. Use provided lower current values as

specified.

Revision 0

2-39

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

AC Switching Characteristics

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-42 • HSTL Receiver Characteristics

On Die

TDIN

TSCH_DIN

Termination

(ODT)

–1

Std.

–1

Std.

Units

HSTL (for DDRIO I/O bank)

Pseudo-Differential

None

47.8

TBD

N/A

True-Differential

None

47.8

HSTL (for MSIO I/O bank)

Pseudo-Differential

None

13.8

13.65

13.637

13.597

TBD

16.236

16.059

16.044

15.996

TBD

18.906

19.056

19.02

18.964

TBD

22.242

22.419

22.377

22.31

TBD

150

None

True-Differential

TBD

150

TBD

HSTL (for MSIOD I/O bank)

Pseudo-Differential

None

TBD

150

None

True-Differential

150

2-40

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-43 • HSTL Transmitter Characteristics

TDOUT TENZL TENLZ

TENZH

TENHZ

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

Units

HSTL Class I

For DDRIO I/O Bank

Single-ended

Differential

TBD

For MSIO I/O Bank

Single-ended

Differential

TBD

For MSIOD I/O Bank

Single-ended

TBD

Differential

HSTL Class II

For DDRIO I/O Bank

Single-ended

Differential

TBD

Revision 0

2-41

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Stub-Series Terminated Logic

Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is

supported in SmartFusion2 devices. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is

defined by JEDEC standard JESD8-15. SmartFusion2 SSTL I/O configurations are designed to meet

double data rate standards DDR/2/3 for general purpose memory buses. Double data rate standards are

designed to meet their JEDEC specifications as defined by JEDEC standard JESD79F for DDR, JEDEC

standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3 and JEDEC standard JESD209A

for LPDDR.

Stub-Series Terminated Logic 2.5 V (SSTL2)

SSTL2 Class I and Class II are supported in SmartFusion2 devices, and also comply with reduced and

full drive of double data rate (DDR) standards. SmartFusion2 FPGA I/O supports both standards for

single-ended signaling and differential signaling for SSTL2. This standard requires a differential amplifier

input buffer and a push-pull output buffer.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-44 • DDR1/SSTL2 DC Voltage Specification

Symbols

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

Recommended DC Operating Conditions

VDDI

VTT

Supply Voltage

2.375

1.164

2.5

2.625

1.339

Termination Voltage

Input Reference Voltage

1.250

VREF

DDR/SSTL2 DC Input Voltage Specification

VIH (DC)

VIL (DC)

IIH (DC)

IIL (DC)

DC input logic High

DC input logic Low

Input current High

Input current Lo

VREF + 0.125

–

2.625

–0.3

–

VREF – 0.15

µA

–

DDR/SSTL2 DC Output Voltage Specification

SSTL2 Class I (DDR Reduced Drive)

VOH

VOL

DC output logic High

DC output logic Low

VTT + 0.608

–

VTT – 0.608

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

8.1

–

–8.1

SSTL2 Class II (DDR Full Drive) – Applicable to MSIO and DDRIO I/O Banks ONLY

VOH

VOL

DC output logic High

DC output logic Low

VTT + 0.81

–

VTT – 0.81

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

16.2

–

–16.2

SSTL2 AC/DC Differential Voltage Specification

VID (DC)

DC input differential voltage

0.3

0.7

–

VDIFF (AC) AC input differential voltage

Vx (AC)

AC differential cross point voltage

0.5 * VDDI

– 0.2

0.5 * VDDI

+ 0.2

2-42

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-44 • DDR1/SSTL2 DC Voltage Specification (continued)

Symbols Parameters Conditions

SSTL2 AC Specifications

Min.

Typ.

Max.

Units Notes

Fmax

Rref

Maximum data rate (for AC loading: per JEDEC

DDRIO I/O bank) specifications

–

400

575

700

–

Mbps

Ohms

Maximum data rate (for AC loading:

–

MSIO I/O bank)

10 pF / 50 Ohm load

Maximum data rate (for AC loading:

MSIOD I/O bank)

30 pF / 50 Ohm load

Supported output driver Reference resistor

calibrated impedance = 150 Ohms

(for DDRIO I/O bank)

20, 42

AC Test Parameters Specifications

Vtrip

Rent

Cent

Measuring/trip point for data path

–

1.25

–

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ,

tLZ)

Series resistance for data test path (tDP)

–

Ohms

Rtt_test

Reference resistance for data test path for SSTL2

Class I (tDP)

Rtt_test

Cload

Reference resistance for data test path for SSTL2

Class II (tDP)

–

Ohms

Capacitive loading for data path (tDP)

Revision 0

2-43

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-45 • DDR1/SSTL2 Receiver Characteristics

TDIN

TSCH_DIN

On Die

Termination (ODT)

–1

Std.

–1

Std.

Units

SSTL2 (for DDRIO I/O bank)

Pseudo-Differential

None

TBD

–

True-Differential

SSTL2 (for MSIO I/O bank)

Pseudo-Differential

None

2.805

TBD

3.3

2.987

TBD

3.515

TBD

True-Differential

TBD

SSTL2 (for MSIOD I/O bank)

Pseudo-Differential

None

TBD

True-Differential

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-46 • DDR1/SSTL2 Transmitter Characteristics

TDOUT TENZL

–1 STD

TENZH

TENHZ

TENLZ

–1

STD

–1

STD

–1

STD

–1

STD Units

SSTL2 Class I

For DDRIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIOD I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

SSTL2 Class II

For DDRIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIOD I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

2-44

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Stub-Series Terminated Logic 1.8 V (SSTL18)

SSTL18 Class I and Class II are supported in SmartFusion2 devices, and also comply with the reduced

and full drive double date rate (DDR2) standard. SmartFusion2 FPGA I/O supports both standards for

single-ended signaling and differential signaling for SSTL18. This standard requires a differential

amplifier input buffer and a push-pull output buffer.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-47 • SSTL18 DC Voltage Specification

Symbols Parameters Conditions

Recommended DC Operating Conditions

Min.

Typ.

Max.

Units Notes

VDDI

VTT

Supply Voltage

1.71

0.838

1.8

1.89

0.964

Termination Voltage

Input Reference Voltage

0.900

VREF

SSTL18 DC Input Voltage Specification

VIH (DC)

VIL (DC)

IIH (DC)

IIL (DC)

DC input logic High

DC input logic Low

Input current High

Input current Low

VREF + 0.125

–

1.89

–0.3

–

VREF – 0.125

µA

–

SSTL18 DC Output Voltage Specification

SSTL18 Class I (DDR2 Reduced Drive)

VOH

VOL

DC output logic High

DC output logic Low

VTT + 0.603

–

VTT– 0.603

–

IOH at VOH Output minimum source DC current (MSIO I/O

bank only

4.7

IOL at VOL Output minimum sink current (MSIO I/O bank

only)

–4.7

6.3

–

IOH at VOH Output minimum source DC current (MSIOD I/O

bank only

IOL at VOL Output minimum sink current (MSIOD I/O bank

only)

–6.3

6.5

IOH at VOH Output minimum source DC current (DDRIO I/O

bank only

IOL at VOL Output minimum sink current (DDRIO I/O bank

only)

–6.5

Notes:

1. MSIO I/O bank SSTL18/DDR2 Reduced Drive does not have a standard test point. This is defined to fit within the DDR2

Reduced Drive IV Curve minimums.

2. MSIO I/O bank SSTL18/DDR2 Class II does not meet the standard JEDEC test points. Use provided lower current values

as specified.

Revision 0

2-45

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-47 • SSTL18 DC Voltage Specification (continued)

Symbols Parameters Conditions

STL18 Class II (DDR2 Full Drive) – Applicable to MSIO and DDRIO I/O Banks ONLY

Min.

Typ.

Max.

Units Notes

VOH

VOL

DC output logic High

DC output logic Low

VTT + 0.603

–

VTT– 0.603

–

IOH at VOH Output minimum source DC current (MSIO I/O

bank only)

9.3

IOL at VOL Output minimum sink current (MSIO I/O bank

only)

–9.3

13.4

–

IOH at VOH Output minimum source DC current (DDRIO I/O

bank only)

IOL at VOL Output minimum sink current (DDRIO I/O bank

only)

–13.4

SSTL18 AC/DC Differential Voltage Specification

VID (DC

VDIFF (AC) AC input differential voltage

Vx (AC) AC differential cross point voltage

DC input differential voltage

0.3

0.7

–

0.5 * VDDI

– 0.175

0.5 * VDDI

+ 0.175

SSTL18 AC Specification

Fmax

Rref

Maximum data rate (for

DDRIO I/O bank)

AC loading: per

JEDEC specification

–

800

432

430

Mbps

Ohms

Maximum data rate (for

MSIO I/O bank)

AC loading:

3 pF / 25 Ohm load

–

Maximum data rate (for

MSIOD I/O bank)

AC loading:

3 pF / 25 Ohm load

Supported output driver

Reference resistor

20, 42

calibrated impedance (for = 150 Ohms

DDRIO I/O bank)

RTT

Effective impedance value Reference resistor

(with respect to reference = 150 Ohms

resistor 150 Ohms) (ODT

–

50, 75,

150

Ohms

for DDRIO I/O bank only)

Notes:

1. MSIO I/O bank SSTL18/DDR2 Reduced Drive does not have a standard test point. This is defined to fit within the DDR2

Reduced Drive IV Curve minimums.

2. MSIO I/O bank SSTL18/DDR2 Class II does not meet the standard JEDEC test points. Use provided lower current values

as specified.

2-46

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-47 • SSTL18 DC Voltage Specification (continued)

Symbols

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

AC Test Parameters Specifications

Vtrip

Rent

Cent

Measuring/trip point for data path

–

0.9

–

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Ohms

Capacitive loading for enable path (tZH, tZL,

tHZ, tLZ)

Series resistance for data test path (tDP)

–

Ohms

Rtt_test

Reference resistance for data test path for

SSTL18 Class I (tDP)

Rtt_test

Reference resistance for data test path for

SSTL18 Class II (tDP)

–

Ohms

Cload

Capacitive loading for data path (tDP)

Notes:

1. MSIO I/O bank SSTL18/DDR2 Reduced Drive does not have a standard test point. This is defined to fit within the DDR2

Reduced Drive IV Curve minimums.

2. MSIO I/O bank SSTL18/DDR2 Class II does not meet the standard JEDEC test points. Use provided lower current values

as specified.

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 1.71 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-48 • DDR2/SSTL18 Receiver Characteristics

TDIN

TSCH_DIN

STD

ODT (On Die

Termination)

–1

STD

–1

Units

SSTL18 (for DDRIO I/O bank)

Pseudo-Differential

None

TBD

N/A

150

None

True-Differential

150

SSTL18 (for MSIO I/O bank)

Pseudo-Differential

None

TBD

150

Revision 0

2-47

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-48 • DDR2/SSTL18 Receiver Characteristics

TDIN

TSCH_DIN

ODT (On Die

Termination)

–1

STD

TBD

–1

STD

TBD

Units

True-Differential

None

TBD

150

SSTL18 (for MSIOD I/O bank)

Pseudo-Differential

None

TBD

150

None

True-Differential

150

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-49 • DDR2/SSTL18 Transmitter Characteristics

TDOUT TENZL

–1 STD

TENZH

TENHZ

TENLZ

–1

STD

–1

STD

–1

STD

–1

STD Units

SSTL2 Class I

For DDRIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIOD I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

SSTL2 Class II

For DDRIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIO I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

For MSIOD I/O Bank

Single-ended

TBD

TBD TBD

TBD

Differential

2-48

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Stub-Series Terminated Logic 1.5 V (SSTL15)

SSTL15 Class I and Class II are supported in SmartFusion2 devices, and also comply with the reduced

and full drive double data rate (DDR3) standard. SmartFusion2 FPGA I/O supports both standards for

single-ended signaling and differential signaling for SSTL18. This standard requires a differential

amplifier input buffer and a push-pull output buffer.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-50 • SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only)

Symbols

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

Recommended DC Operating Conditions

VDDI

VTT

Supply Voltage

1.425

0.698

1.5

1.575

0.803

Termination Voltage

Input Reference Voltage

0.750

VREF

SSTL15 DC Input Voltage Specification

VIH(DC)

VIL(DC)

IIH (DC)

IIL (DC)

DC input logic High

DC input logic Low

Input current High

Input current Low

VREF + 0.1

–

1.575

VREF – 0.1

–0.3

–

µA

–

SSTL15 DC Output Voltage Specification

DDR3/SSTL15 Class I (DDR3 Reduced Drive)

VOH

VOL

DC output logic High

DC output logic Low

0.8 * VDDI

–

0.2 * VDDI

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

SSTL15 Class II (DDR3 Full Drive)

6.5

–

–6.5

VOH

VOL

DC output logic High

DC output logic Low

0.8 * VDDI

–

0.2 * VDDI

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

SSTL15 Differential Voltage Specification

7.6

–

–7.6

VID (DC)

VDIFF (AC) AC input differential voltage

Vx (AC) AC differential cross point voltage

DC input differential voltage

0.2

0.7

–

0.5 * VDDI

– 0.150

0.5 * VDDI

+ 0.150

Revision 0

2-49

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-50 • SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) (continued)

Symbols

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

SSTL15 AC Specification

Fmax

Rref

Maximum Data Rate

(for DDRIO I/O bank)

AC loading: per

JEDEC specifications

800

Mbps

Ohms

Supported output driver Reference resistor =

34, 40

calibrated impedance

240 Ohms

RTT

Effective impedance

value (with respect to

Reference Resistor 240

ohms) (ODT for DDRIO

I/O bank only)

Reference resistor =

240 Ohms

20, 30,

40, 60,

120

Ohms

AC Test Parameters Specifications

Vtrip

Rent

Cent

Measuring/trip point for data path

–

0.75

–

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Ohms

Capacitive loading for enable path (tZH, tZL,

tHZ, tLZ)

Series resistance for data test path (tDP)

–

Ohms

Rtt_test

Reference resistance for data test path for

SSTL15 Class I (tDP)

Rtt_test

Cload

Reference resistance for data test path for

SSTL15 Class II (tDP)

–

Ohms

Capacitive loading for data path (tDP)

2-50

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 1.425 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-51 • SSTL15 Receiver Characteristics

TDIN

On Die Termination

(ODT)

–1

Std.

Units

DDR3/SSTL15 (For DDRIO I/O bank)

Pseudo-Differential

None

TBD

120

None

True-Differential

120

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-52 • DDR3/SSTL15 Transmitter Characteristics

TDOUT TENZL

–1 STD –1 STD

TENZH

TENHZ

TENLZ

–1 STD

–1

STD

–1

STD

Units

DDR3 Reduced Drive/SSTL15 Class I

For DDRIO I/O Bank

Single Ended

Differential

TBD

DDR3 Full DriveSSTL15 Class II

For DDRIO IO Bank

Single Ended

Differential

TBD

Revision 0

2-51

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Low Power Double Data Rate (LPDDR)

LPDDR reduced and full drive low power double data rate standards are supported in SmartFusion2

FPGA I/Os. This standard requires a differential amplifier input buffer and a push-pull output buffer.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-53 • LPDDR DC Voltage Specification

Symbols Parameters Conditions

Recommended DC Operating Conditions

Min.

Typ.

Max.

Units Notes

VDDI

VTT

Supply Voltage

1.71

0.838

1.8

1.89

0.964

Termination Voltage

Input Reference Voltage

0.900

VREF

LPDDR DC Input Voltage Specification

VIH (DC)

VIL (DC)

IIH (DC)

IIL (DC)

DC input Logic High

DC input Logic Low

Input current High

Input current Low

0.3 * VDDI

–

1.89

0.7 * VDDI

–0.3

–

µA

–

LPDDR DC Output Voltage Specification

VOH

VOL

DC output Logic High

DC output Logic Low

0.9 * VDDI

–

0.1 * VDDI

IOH at VOH Output minimum source DC current

IOL at VOL Output minimum sink current

LPDDR Differential Voltage Specification

0.1

–

–0.1

VID (DC)

VDIFF (AC) AC input differential voltage

Vx (AC) AC differential cross point voltage

LPDDR AC Specifications

DC input differential voltage

0.4 * VDDI

0.6 * VDDI

0.4 * VDDI

–

0.6 * VDDI

Fmax

Maximum Data Rate

AC loading: per JEDEC

specifications

Mbps

Ohms

Rref

Supported output

driver calibrated

impedance

Reference resistor =

150 Ohms

20, 42

Rtt

Effective impedance

value – ODT

Reference resistor =

150 Ohms

50, 70,

150

Ohms

AC Test Parameters Specifications

Vtrip

Rent

Cent

Measuring/trip point for data path

–

0.9

–

Ohms

Resistance for enable path (tZH, tZL, tHZ, tLZ)

Capacitive loading for enable path (tZH, tZL, tHZ,

tLZ)

Series resistance for data test path (tDP)

–

Ohms

Rtt_test

Reference resistance for data test path for

LPDDR (tDP)

Cload

Capacitive loading for data path (tDP)

–

Ohms

2-52

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Table 2-54 • LPDDR Receiver Characteristics

TDIN

On Die Termination (ODT)

–1

Std.

Units

LPDDR (for DDRIO I/O Bank)

Pseudo-Differential

None

TBD

True-Differential

150

Table 2-55 • LPDDR Transmitter Characteristics

TDOUT TENZL

TENZH

TENHZ

TENLZ

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

Units

LPDDR Reduced Drive

For DDRIO I/O Bank

Single-ended

Differential

TBD

LPDDR Full Drive

For DDRIO I/O Bank

Single-ended

Differential

TBD

Revision 0

2-53

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Differential I/O Standards

Configuration of the I/O modules as a differential pair is handled by SoC Products Group Libero software

when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in

conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register

(EnReg), and Double Data Rate registers (DDR).

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard.

Minimum and Maximum Input and Output Levels

Table 2-56 • LVDS DC Voltage Specification

Symbols Parameters

Recommended DC Operating Conditions

VDDI Supply Voltage

LVDS DC Input Voltage Specification

Conditions

Min.

Typ. Max. Units Notes

2.375

2.5

3.45

DC Input voltage

Input current High

Input current Low

–

2.925

IIH (DC)

IIL (DC)

µA

LVDS DC Output Voltage Specification

VOH

VOL

DC output logic High

DC output logic Low

1.25 1.425 1.6

0.9

1.075 1.25

LVDS Differential Voltage Specification

VOD

VOCM

VICM

VID

Differential output voltage swing

Output common mode voltage

Input common mode voltage

Input differential voltage

250

350

450

1.125 1.25 1.375

0.05

100

1.25 1.375

350

600

LVDS AC Specifications

Fmax

Maximum data rate (for MSIO I/O AC loading: 2 pF / 100 Ohm

bank) differential load

–

535 Mbps

750 Mbps

Maximum data rate (for MSIOD I/O AC loading: 2 pF / 100 Ohm

bank) – NO PRE-EMPHASIS differential load

700

970

730

Maximum data rate (for MSIOD I/O AC loading: 2 pF / 100 Ohm

bank) – MIN. PRE-EMPHASIS differential load

1200 1270 Mbps

Maximum Data Rate (for MSIOD IO AC loading: 2 pF / 100 Ohm

1000 1500 1700 Mbps

Bank) – MAX. PRE-EMPHASIS

differential load

Termination resistance

–

100

–

Ohms

AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path

Cross

point

Rent

Cent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

2-54

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-57 • LVDS Receiver Characteristics

TDIN

TSCH_DIN

On Die Termination

(ODT)

–1

Std.

TBD

–1

Std.

TBD

Units

LVDS (for MSIO I/O bank)

LVDS (for MSIOD I/O bank)

None

100

TBD

None

100

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-58 • LVDS Transmitter Characteristics

TDOUT

–1 Std.

TENZL

–1 Std.

TENZH

–1 Std.

TENHZ

–1 Std.

TENLZ

–1

Std. Units

LVDS (For MSIO I/O bank)

LVDS (For MSIOD I/O bank)

No pre-emphasis

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Min. pre-emphasis

Max. pre-emphasis

Revision 0

2-55

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

B-LVDS

Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint

bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers,

receivers, and transceivers.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-59 • B-LVDS DC Voltage Specification

Symbols Parameters

Recommended DC Operating Conditions

VDDI Supply Voltage

Bus LVDS DC Input Voltage Specification

Conditions

Min.

Typ.

Max.

Units Notes

2.375

2.5

2.625

DC input voltage

Input current High

Input current Low

–

2.925

IIH (DC)

IIL (DC)

µA

Bus LVDS DC Output Voltage Specification (For MSIO I/O Bank ONLY)

VOH

VOL

DC output logic High

DC output logic Low

1.25

0.9

1.425

1.075

1.6

1.25

Bus LVDS Differential Voltage Specification

VOD

Differential output voltage swing (for MSIO I/O bank

240

–

460

ONLY)

VOCM

VICM

VID

Output common mode voltage (for MSIO I/O bank ONLY)

Input common mode voltage

Input differential voltage

1.1

0.05

100

–

1.5

2.4 – VID/2

2 * VDDI

Bus LVDS AC Specifications

Fmax

Maximum data rate (for AC loading: 2 pF / 100 Ohm

MSIO I/O bank) differential load

–

500

Mbps

Fmax

Maximum data rate (for MSIOD I/O bank, receiver ONLY)

Termination resistance

–

Mbps

Ohms

Bus LVDS AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path

–

Cross

point

–

Rent

Cent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

2-56

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-60 • AC Switching Characteristics for Receiver (Input Buffers)

TDIN

TSCH_DIN

Speed Grade

On Die Termination

(ODT)

–1

Std.

–1

Std.

Units

None

100

TBD

Bus LVDS (For MSIO I/O Bank)

Bus LVDS (For MSIOD I/O Bank)

None

100

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-61 • AC Switching Characteristics for Transmitter (Output and Tristate Buffers

TDOUT

TENZL

TENZH

TENHZ

TENLZ

–1 Std.

TBD TBD

–1

TBD

Std.

–1

TBD

Std.

–1

Std.

–1

TBD

Std.

Units

Bus-LVDS

TBD

(For MSIO I/O Bank)

Revision 0

2-57

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

M-LVDS

MLVDS specifications extend the existing LVDS standard to high-performance multipoint bus

applications. Multidrop and multipoint bus configurations may contain any combination of drivers,

receivers, and transceivers.

Minimum and Maximum Input and Output Levels

Table 2-62 • M-LVDS DC Voltage Specification

Symbols Parameters

M-LVDS Recommended DC Operating Conditions

VDDI Supply Voltage

M-LVDS DC Input Voltage Specification

VI DC input voltage

IIH (DC) Input current High

IIL (DC) Input current Low

M-LVDS DC Output Voltage Specification (For MSIO IO Bank ONLY)

Conditions

Min.

Typ.

Max.

Units Notes

2.375

2.5

2.625

–

2.925

µA

VOH

VOL

DC output logic High

DC output logic Low

1.25

0.9

1.425

1.075

1.6

1.25

M-LVDS Differential Voltage Specification

VOD

VOCM

VICM

VID

Differential output voltage Swing (for MSIO I/O bank ONLY)

480

0.3

–

650

2.1

Output common mode voltage (for MSIO I/O bank ONLY)

Input common mode voltage

1.2

Input differential voltage

2400

M-LVDS AC Specifications

Fmax

Maximum data rate (for AC loading: 2 pF / 100 Ohm

–

500

–

Mbps

Ohms

MSIO I/O bank)

differential load

Termination resistance

M-LVDS AC Test Parameters Specifications

VTrip

Measuring/trip point for data path

–

Cross

point

–

Rent

Cent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

2-58

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-63 • AC Switching Characteristics for Receiver (Input Buffers)

TDIN

TSCH_DIN

Speed Grade

On Die Termination

(ODT)

–1

Std.

–1

Std.

Units

MLVDS (For MSIO I/O Bank)

MLVDS (For MSIOD I/O Bank)

None

100

TBD

None

100

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-64 • AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

TDOUT

–1 Std.

TENZL

–1 Std.

TENZH

–1 Std.

TENHZ

–1 Std.

TENLZ

–1

Std. Units

M-LVDS (For MSIO I/O Bank) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Revision 0

2-59

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Mini-LVDS

Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed

to the Texas Instruments Standard SLDA007A.

Mini-LVDS Minimum and Maximum Input and Output Levels

Table 2-65 • Mini-LVDS DC Voltage Specification

Symbols Parameters

Recommended DC Operating Conditions

VDDI Supply Voltage

Mini-LVDS DC Input Voltage Specification

VI DC Input voltage

Mini-LVDS DC Output Voltage Specification

Conditions

Min.

2.375

Typ. Max. Units Notes

2.5

–

2.625

2.925

1.6

VOH

VOL

DC output logic High

DC output logic Low

1.25 1.425

0.9

1.075 1.25

Mini-LVDS Differential Voltage Specification

VOD

VOCM

VICM

VID

Differential output voltage swing

Output common mode voltage

Input common mode voltage

Input differential voltage

300

–

600

1.4

0.3

200

1.2

600

Mini-LVDS AC Specifications

Fmax

Maximum data rate (for MSIO I/O AC loading: 2 pF / 100 Ohm

–

520

740

750

Mbps

bank)

differential load

Maximum data rate (for MSIOD

I/O bank, No Pre-Emphasis)

AC loading: 2 pF / 100 Ohm

differential load

700

970

725

735

Maximum data rate (for MSIOD

I/O bank) – Min. Pre-Emphasis

AC loading: 2 pF / 100 Ohm

differential load

Maximum data rate (for MSIOD

I/O bank) – Med. Pre-Emphasis

AC loading: 2 pF / 100 Ohm

differential load

1,200 1,280 Mbps

Maximum Data Rate (for MSIOD AC loading: 2 pF / 100 Ohm 1,000 1,500 1,700 Mbps

I/O bank) – Max. Pre-Emphasis

differential load

Termination resistance

–

150 Ohms

Mini-LVDS AC Test Parameters Specifications

VTrip

Measuring/trip point for data path

Cross

point

–

Rent

Cent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

2-60

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-66 • AC Switching Characteristics for Receiver (Input Buffers)

TDIN

TSCH_DIN

Speed Grade

On Die Termination

(ODT)

–1

Std.

TBD

–1

Std.

TBD

Units

Mini-LVDS (For MSIO I/O Bank)

Mini-LVDS (For MSIOD I/O Bank)

None

100

TBD

None

100

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-67 • AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

TDOUT

–1 Std.

TENZL

–1 Std.

TENZH

–1 Std.

TENHZ

–1 Std.

TENLZ

–1

Std. Units

Mini-LVDS

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

(for MSIO I/O bank)

Mini-LVDS (for MSIOD I/O bank)

No Pre-Emphasis

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Min. Pre-Emphasis

Max. Pre-Emphasis

Revision 0

2-61

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

RSDS

Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using

differential signaling. RSDS has a similar implementation to LVDS devices and is only intended for point-

to-point applications.

Minimum and Maximum Input and Output Levels

Table 2-68 • RSDS DC Voltage Specification

Symbols Parameters

Recommended DC Operating Conditions

VDDI Supply Voltage

RSDS DC Input Voltage Specification

VI DC input voltage

RSDS DC Output Voltage Specification

Conditions

Min.

2.375

Typ.

2.5

–

Max.

2.625

2.925

Units Notes

VOH

VOL

DC output Logic High

DC output Logic Low

1.25

0.9

1.425

1.075

1.6

1.25

RSDS Differential Voltage Specification

VOD

VOCM

VICM

VID

Differential output voltage swing

Output common mode voltage

Input common mode voltage

Input differential voltage

100

0.5

0.3

100

–

600

1.5

2 * VDDI

RSDS AC Specifications

Fmax

Maximum data rate (for AC loading: 2 pF / 100 Ohm

MSIO I/O bank) differential load

–

520

740

Mbps

Fmax

Maximum data Rate (for AC loading: 2 pF / 100 Ohm

MSIOD I/O banks, No differential load

Pre-Emphasis)

700

725

Fmax

Maximum Data Rate (for AC loading: 2 pF / 100 Ohm

MSIOD I/O Banks) – Min. differential load

Pre-Emphasis

700

970

735

1200

1,500

100

750

Mbps

Maximum data rate (for AC loading: 2 pF / 100 Ohm

MSIOD I/O banks) – Med. differential load

Pre-Emphasis

1,280

1,700

Maximum data rate (for AC loading: 2 pF / 100 Ohm

MSIOD I/O banks) – Max. differential load

Pre-Emphasis)

1,000

Termination Resistance

Ohms

AC Test Parameters Specifications

VTrip

Measuring/trip point for data path

–

Cross

point

–

Rent

Cent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

Ohms

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

2-62

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-69 • AC Switching Characteristics for Receiver (Input Buffers)

TDIN

TSCH_DIN

Speed Grade

On Die Termination

(ODT)

–1

Std.

TBD

–1

Std.

TBD

Units

RSDS (for MSIO I/O bank)

RSDS (for MSIOD I/O bank)

None

100

TBD

None

100

AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Table 2-70 • AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

TDOUT

–1 Std.

TENZL

–1 Std.

TENZH

–1 Std.

TENHZ

–1 Std.

TENLZ

–1

Std. Units

RSDS (for MSIO I/O bank)

RSDS (for MSIOD I/O bank)

No Pre-Emphasis

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Min. Pre-Emphasis

Max. Pre-Emphasis

Revision 0

2-63

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Similar to LVDS, two pins are needed. It also

requires external resistor termination. SmartFusion2 devices support only LVPECL receivers and do not

support LVPECL transmitters.

Minimum and Maximum Input and Output Levels

Table 2-71 • LVPECL DC Voltage Specification – Applicable to MSIO I/O Banks Only

Symbols

Recommended DC Operating Conditions

VDDI Supply Voltage

LVPECL DC Input Voltage Specification

Parameters

Conditions

Min.

Typ.

Max.

Units Notes

3.15

3.3

3.45

VIH (DC)

VIL (DC)

DC input logic High

DC input logic Low

–

2.3

–

1.6

LVPECL Differential Voltage Specification

VICM

Input common mode voltage

Input differential voltage

0.3

2.8

VIDIFF

100

300

–

1,000

Other Specifications

Fmax Maximum data rate (for MSIO I/O bank)

–

900

Mbps

AC Switching Characteristics

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V, VDDI = 2.375 V

AC Switching Characteristics for Receiver (Input Buffers)

Table 2-72 • LVPECL Receiver Characteristics

TDIN

TSCH_DIN

On Die Termination

(ODT)

None

100

–1

Std.

TBD

–1

Std.

Units

LVPECL (for MSIO I/O bank)

TBD

2-64

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

I/O Register Specifications

Input Register

Table 2-73 • Input Data Enable Register Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V

Measuring

Nodes

Parameter

tICLKQ

tISUD

tIHD

Description

Clock-to-Q of the Input Data Register

(from, to)*

–1

Std. Units

TBD

Data Setup Time for the Input Data Register

Data Hold Time for the Input Data Register

Enable Setup Time for the Input Data Register

Enable Hold Time for the Input Data Register

tISUE

tIHE

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register

tIWCLR

Asynchronous Clear Minimum Pulse Width for the Input Data

tIWPRE

Asynchronous Preset Minimum Pulse Width for the Input Data

TBD

tICKMPWH Clock Minimum Pulse Width High for the Input Data Register

tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register

TBD

*For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-11 on page 2-14

for derating values.

Revision 0

2-65

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Output/Enable Register

Table 2-74 • Output Data/Enable Register Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, VDD = 1.14 V

Measuring

Nodes

Parameter

tOCLKQ

tOSUD

tOHD

Description

(from, to)*

–1

Std.

TBD

Units

Clock-to-Q of the Output/Enable Register

TBD

Data Setup Time for the Output/Enable Register

Data Hold Time for the Output/Enable Register

Enable Setup Time for the Output/Enable Register

Enable Hold Time for the Output/Enable Register

tOSUE

tOHE

tOSUSL

Synchronous Load Setup Time for the Output/Enable

tOHSL

Synchronous Load Hold Time for the Output/Enable Register

TBD

tOALn2Q

Asynchronous Clear-to-Q of the Output/Enable Register

(ADn = 1)

Asynchronous Preset-to-Q of the Output/Enable Register

(ADn = 0)

TBD

tOREMALn Asynchronous Load Removal Time for the Output/Enable

tORECALn Asynchronous Load Recovery Time for the Output/Enable

tOWALn

Asynchronous Load Minimum Pulse Width for the

Output/Enable Register

tOCKMPWH Clock Minimum Pulse Width High for the Output/Enable

tOCKMPWL Clock Minimum Pulse Width Low for the Output/Enable

Note: *For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-11 on

page 2-14 for derating values.

2-66

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

DDR Module Specification

Input DDR Module

ALn

ADn

SLn

ALn

ADn

SLE

SLn

LAT

CLK

LAT

CLK

ALn

ADn

Latch

ALn

ADn

SLn

SLE

CLK

LAT

CLK

DDR_IN

Figure 2-2 • Input DDR Module

Revision 0

2-67

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Input DDR Timing Diagram

t_DDRICKMPWL

t_DDRICKMPWH

CLK

t_DDRISUD

t_DDRIHD

ADn

t_DDRISUSLn

t_DDRIHSLn

SLn

ALn

t_DDRIWAL

t_DDRIRECAL

t_DDRIREMAL

t_DDRISUE

t_DDRIHE

t_DDRIAL2Q1

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRIAL2Q2

Figure 2-3 • Input DDR Timing Diagram

2-68

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Timing Characteristics

Table 2-75 • Input DDR Propagation Delays

Measuring

Nodes

Parameter

tDDRICLKQ1

tDDRICLKQ2

tDDRISUD

Description

(from, to)

B, C

B, D

A, B

E, B

G, B

F, C

–1

Std. Units

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR

0.178 0.209

0.175 0.205

0.464 0.546

tDDRIHD

Data Hold for Input DDR

TBD

tDDRISUE

Enable Setup for Input DDR

tDDRIHE

Enable Hold for Input DDR

tDDRISUSLn

tDDRIHSLn

tDDRIAL2Q1

tDDRIAL2Q2

tDDRIREMAL

tDDRIRECAL

tDDRIWAL

Synchronous Load Setup for Input DDR

Synchronous Load Hold for Input DDR

Asynchronous Load-to-Out QR for Input DDR

Asynchronous Load-to-Out QF for Input DDR

Asynchronous Load Removal time for Input DDR

Asynchronous Load Recovery time for Input DDR

Asynchronous Load Minimum Pulse Width for Input DDR

0.577 0.679

0.618 0.727

F, D

0.569

0.67

F, B

0.041 0.048

F, F

0.32

0.08

0.376

0.094

0.08

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR

B, B

0.068

Revision 0

2-69

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Output DDR Module

ALn

ADn

SLn

ADn

SLE

SLn

LAT

CLK

LAT

CLK

ALn

ADn

SLn

SLE

LAT

CLK

DDR_OUT

Figure 2-4 • Output DDR Module

2-70

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

t_DDROCKMPWLt_DDROCKMPWH

t_DDROSUE

Clk

t_DDROHDE

t_DDROSUDR

t_DDROHDR

t_DDROHDF

t_DDROSUDF

ADn

t_DDROSUSLn

t_DDROHDSLn

SLn

t_DDRORECAL

t_DDROREMAL

ALn

t_DDROCLKQ

t_DDROAL2Q

Out

Figure 2-5 • Output DDR Timing Diagram

Revision 0

2-71

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Timing Characteristics

Table 2-76 • Output DDR Propagation Delays

Measuring

Nodes

Parameter

Description

(from, to)

–1

Std. Units

tDDROCLKQ

tDDROSUDF

tDDROSUDR

tDDROHDF

tDDROHDR

tDDROSUE

tDDROHE

Clock-to-Out of DDR for Output DDR

Data_F Data Setup for Output DDR

E, G

F, E

0.288 0.339

0.154 0.181

Data_R Data Setup for Output DDR

A, E

F, E

TBD

Data_F Data Hold for Output DDR

Data_R Data Hold for Output DDR

A, E

B, E

D, E

C, G

C, E

C, C

E, E

Enable Setup for Input DDR

0.148 0.174

Enable Hold for Input DDR

0.79

0.93

tDDROSUSLn

tDDROHSLn

tDDROAL2Q

tDDROREMAL

tDDRORECAL

tDDROWAL

Synchronous Load Setup for Input DDR

Synchronous Load Hold for Input DDR

Asynchronous Load-to-Out for Output DDR

Asynchronous Load Removal time for Output DDR

Asynchronous Load Recovery time for Output DDR

Asynchronous Load Minimum Pulse Width for Output DDR

0.575 0.677

0.775 0.911

0.191 0.224

0.101 0.119

0.156 0.184

tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR

tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR

2-72

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Logic Module Specifications

4-input LUT (LUT-4)

The SmartFusion2 offers a fully permutable 4-input LUT. In this section, timing characteristics are

presented for a sample of the library.

t_PD

PAD

ADN4 OR

Any

Combinational

Logic

PAD

D/S (where

applicable)

PAD

VDD

t_PD= Max(t_PD(RR), t_PD(RF), t_PD(FF), t_PD(FR))

where edges are applicable for the particular

combinatorial cell

A, B, C, D, S

50%

GND

50%

VDD

50%

OUT

t_PD

GND

VDD

t_PD

(RR)

(FF)

t_PD

(FR)

50%

t_PD

(RF)

GND

Figure 2-6 • LUT-4

Timing Characteristics

Table 2-77 • Combinatorial Cell Propagation Delays

Combinatorial Cell

INV

Equation

Parameter

–1

Std.

Units

Notes

Y = !A

tPD

0.108

0.172

0.16

0.127

0.203

0.188

0.203

0.188

0.203

0.283

0.259

0.58

AND2

Y = A · B

Y = !(A · B)

Y = A + B

Y = !(A + B)

^{Y = A}⊕ B

NAND2

OR2

0.172

0.16

NOR2

XOR2

0.172

0.24

XOR3

Y = A ⊕ B ⊕ C

Y = A · B · C

AND3

0.22

AND4

Y = A · B · C · D

0.493

Revision 0

2-73

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Sequential Module

SmartFusion2 offers a separate flip flop which can be used independently from the LUT. The flip-flop can

be configured as a register or a latch and has a data input and optional enable, synchronous load (clear

or preset), and asynchronous load (clear or preset).

ALn

ADn

SLE

SLn

LAT

CLK

Figure 2-7 • Sequential Module

Figure 2-8 shows a configuration with SD = 1 (synchronous preset) and ADn = 1 (asynchronous clear)

for a flip-flop (LAT = 0).

t_CKMPWH

t_CKMPWL

50%

CLK

t_SUD

50%

t_HD

50%

ADn

SD = 1

ADn = 1

50%

t_SUSL

50%

t_HSL

t_HE

t_SUE

50%

t_WALn

t_RECALn

t_REMALn

50%

ALn

t_ALnQ2

50%

t_CLKQ

Figure 2-8 • Timing Diagram

2-74

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Timing Characteristics

Table 2-78 • Register Delays

Parameter

tCLKQ

tSUD

Description

Clock-to-Q of the Core Register

–1

0.114

0.267

Std.

0.134

0.314

Units Notes

Data Setup Time for the Core Register

tHD

Data Hold Time for the Core Register

tSUE

Enable Setup Time for the Core Register

0.353

0.415

tHE

Enable Hold Time for the Core Register

tSUSL

tHSL

Synchronous Load Setup Time for the Core Register

Synchronous Load Hold Time for the Core Register

Asynchronous Clear-to-Q of the Core Register (ADn = 1)

Asynchronous Preset-to-Q of the Core Register (ADn = 0)

Asynchronous Load Removal Time for the Core Register

Asynchronous Load Recovery Time for the Core Register

0.353

0.415

tALn2Q

0.498

0.475

0.586

0.559

tREMALn

tRECALn

tWALn

0.371

0.32

0.437

0.376

Asynchronous Load Minimum Pulse Width for the Core

tCKMPWH

tCKMPWL

Clock Minimum Pulse Width High for the Core Register

Clock Minimum Pulse Width Low for the Core Register

0.079

0.168

0.093

0.197

Revision 0

2-75

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Global Resource Characteristics

SmartFusion2 devices offer a powerful, low skew global routing network which provides an effective

clock distribution throughout the FPGA fabric. Refer to the SmartFusion2 FPGA Fabric Architecture

User’s Guide for the positions of various global routing resources.

Table 2-79 • M2S050T Global Resource

Speed Grade

–1

Std.

Parameter

tRCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.

TBD

Max.

TBD

Min.

TBD

Max.

TBD

Units Notes

tRCKH

tRCKMPWH Minimum Pulse Width High for Global Clock

tRCKMPWL

tRCKSW

Minimum Pulse Width Low for Global Clock

Maximum Skew for Global Clock

2-76

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

FPGA Fabric SRAM

Refer to the SmartFusion2 FPGA Fabric Architecture User’s Guide for more information.

FPGA Fabric Large SRAM (LSRAM)

Table 2-80 • RAM1K18

–1

Std.

Parameter

tcy

Description

Min.

Max. Min. Max. Units

Clock Period

1.656

0.828

0.327

1.652

0.826

0.324

–

1.948

0.974

0.384

1.944

0.972

0.381

–

tclkmpwh

tclkmpwl

tplcy

Clock Minimum Pulse Width High

Clock Minimum pulse Width Low

Pipelined Clock Period

–

tplclkmpwh Pipelined Clock Minimum Pulse Width High

tplclkmpwl Pipelined Clock Minimum pulse Width Low

–

tclk2q

Read Access Time with Pipeline Register

Read Access Time without Pipeline Register

Access Time with Feed-Through Write Timing

Address Setup Time

0.337

TBD

–

0.396 ns

–

TBD

–

TBD

taddrsu

taddrhd

tdsu

0.207

0.041

0.33

0.074

0.188

0.079

–

0.244

0.048

0.389

0.087

0.221

0.093

–

Address Hold Time

–

Data Setup Time

–

tdhd

Data Hold Time

–

tblksu

tblkhd

tblk2q

Block Select Setup Time (With Pipe-Line Register Enabled)

Block Select Hold Time (With Pipe-Lined Register Enabled)

–

Block Select to Out Disable Time (when Pipe-Lined

Registered is Disabled)

TBD

Block Select to Out Enable Time (when Pipe-Lined Registered

is Disabled)

–

TBD

–

TBD

tblkmpw

trdesu

Block Select Minimum Pulse Width

TBD

0.465

0.053

–

TBD

0.547

0.063

0.827

–

Read Enable Setup Time (A_WEN, B_WEN =0)

Read Enable Hold Time (A_WEN, B_WEN =0)

trdehd

trdplesu

Pipelined Read Enable Setup Time (A_DOUT_EN, 0.703

B_DOUT_EN)

–0.053

–

–0.062

–

trdplehd

Pipelined Read Enable Hold Time (A_DOUT_EN,

B_DOUT_EN)

0.792

–

0.931 ns

tr2q

Asynchronous Reset to Output Propagation Delay

Asynchronous Reset Removal Time

TBD

0.005

0.323

TBD

0.344

–

TBD

0.006

0.38

–

trstrem

trstrec

trstmpw

Asynchronous Reset Recovery Time

Asynchronous Reset Minimum Pulse Width

TBD

0.405

0.361

0.271

tplrstrem Pipelined Register Asynchronous Reset Removal Time

tplrstrec

tplrstmpw

tsrstsu

Pipelined Register Asynchronous Reset Recovery Time

Pipelined Register Asynchronous Reset Minimum Pulse Width 0.307

Synchronous Reset Setup Time 0.231

Revision 0

2-77

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Table 2-80 • RAM1K18

–1

Std.

Parameter

Description

Min.

Max. Min. Max. Units

tsrsthd

twesu

twehd

Synchronous Reset Hold Time

TBD

–

TBD

0.474

0.072

–

Write Enable Setup Time (A_WEN, B_WEN = 1)

Write Enable Hold Time (A_WEN, B_WEN = 1)

0.403

0.061

FPGA Fabric Micro SRAM (uSRAM)

Table 2-81 • uSRAM (RAM64x18) in 64x18 Mode

–1

Std.

Parameter

Description

Min.

0.65

Max. Min. Max. Units

tcy

Read Clock Period

–

0.766

0.348

0.383

0.732

0.331

0.366

TBD

–

tclkmpwh Read Clock Minimum Pulse Width High

0.296

0.325

0.622

0.281

0.311

TBD

tclkmpwl

tplcy

Read Clock Minimum pulse Width Low

Read Pipe-line clock period

tplclkmpwh Read Pipe-line clock Minimum Pulse Width High

tplclkmpwl Read Pipe-line clock Minimum Pulse Width Low

tclpl1

Minimum pipe-line clock low phase in order to prevent glitches

with Pipeline Register in Latch Mode

tclk2q

Read Access Time with Pipeline Register

Read Access Time with Pipeline Register in Latch Mode

Read Access Time without Pipeline Register

Read Address Setup Time in Synchronous Mode

Read Address Setup Time in Asynchronous Mode

Read Address Hold Time in Synchronous Mode

Read Address Hold Time in Asynchronous Mode

Read Enable Setup Time

–

0.368

–

0.433

–

TBD

–

TBD

–

1.777

–

2.09

–

taddrsu

taddrhd

0.172

1.059

0.028

0.008

0.245

0.074

–

0.202

1.246

0.033

0.01

0.289

0.087

0.355

–

trdensu

trdenhd

tblksu

–

Read Enable Hold Time

–

Read Block Select Setup Time (With Pipe-Line Register 0.301

Enabled)

–

tblkhd

tblk2q

Read Block Select Hold Time (With Pipe-Lined Register

Enabled)

TBD

–

TBD

–

Read Block Select to Out Disable Time (when Pipe-Lined

Registered is Disabled)

–

2.093

1.503

–

2.462

1.768

Read Block Select to Out Enable Time (when Pipe-Lined

Registered is Disabled)

tblkmpw

trstrem

Read Block Select Minimum Pulse Width

TBD

–0.002

0.03

–

TBD

–0.002

0.036

–

Read Asynchronous Reset Removal Time (Pipelined Clock)

Read Asynchronous Reset Removal Time (Non-Pipelined

Clock)

2-78

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-81 • uSRAM (RAM64x18) in 64x18 Mode (continued)

–1

Std.

Parameter

Description

Min.

0.546

Max. Min. Max. Units

trstrec

Read Asynchronous Reset Recovery Time (Pipelined Clock)

–

0.642

0.099

–

Read Asynchronous Reset Recovery Time (Non-Pipelined 0.085

Clock)

tr2q

Read Asynchronous Reset to Output Propagation Delay (With

Pipe-Line Register Enabled)

–

0.938

1.588

1.103

1.868

–

Read Asynchronous Reset to Output Propagation Delay

(With Pipe-Line Register Disabled)

tsrstsu

tsrsthd

tccy

Read Synchronous Reset Setup Time

0.189

0.074

1.012

0.506

0.297

0.332

TBD

–

0.222

0.087

1.192

0.596

0.349

0.39

–

Read Synchronous Reset Hold Time

Write Clock Period

tcclkmpwh Write Clock Minimum Pulse Width High

tcclkmpwl Write Clock Minimum Pulse Width Low

tblkcsu

tblkchd

tdincsu

tdinchd

taddrcsu

taddrchd

twecsu

twechd

Write Block Setup Time

Write Block Hold Time

TBD

Write Input Data setup Time

Write Input Data hold Time

Write Address Setup Time

Write Address Hold Time

Write Enable Setup Time

Write Enable Hold Time

TBD

0.002

TBD

0.003

TBD

0.32

0.377

TBD

Revision 0

2-79

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

On-Chip Oscillators

Table 2-82 through Table 2-84 on page 2-81 describe the electrical characteristics of the available

on-chip oscillators in SmartFusion2 devices.

Table 2-82 • Electrical Characteristics of the Crystal Oscillator

Parameter

FXTAL

Description

Operating frequency

Accuracy

Condition

Min. Typ.

Max.

–

Units Notes

–

kHz

ACCXTAL

CYCXTAL

JITXTAL

Temperature: 0°C to 85°C

TBD

Output duty cycle

Output jitter

Period jitter

ps RMS

Cycle-to-Cyle jitter

IDYNXTAL Operating current

ISTBXTAL Standby current of crystal

oscillator

µA

PSRRXTAL Power supply noise

tolerance

TBD

Vp-p

ENXTAL

VIHXTAL

VILXTAL

SUXTAL

Enable Time

TBD

µs

Input logic level High

Input logic level Low

Startup time

Test load used:

µs

Table 2-83 • Electrical Characteristics of the 25/50 MHz RC Oscillator

Parameter

Description

Operating frequency

Accuracy

Condition

Min.

–

Typ.

25/50

TBD

Max.

–

Units

MHz

Notes

F25_50RC

ACC25_50RC

CYC25_50RC

JIT25_50RC

Temperature: 0°C to 85°C

TBD

Output duty cycle

Output jitter

Period Jitter

ps RMS

Cycle-to-Cyle Jitter

IDYN25_50RC Operating current

ISTB25_50RC Standby current

µA

crystal oscillator

PSRR25_50RC Power supply noise

tolerance

TBD

Vp-p

VIH25_50RC

VIL25_50RC

SU25_50RC

Input logic level High

Input logic level Low

Startup time

TBD

Test load used:

µs

2-80

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Table 2-84 • Electrical Characteristics of the 1 MHz RC Oscillator

Parameter

F1RC

Description

Operating frequency

Accuracy

Condition

Min. Typ.

Max.

–

Units Notes

–

MHz

ACC1RC

CYC1RC

JIT1RC

Temperature: 0°C to 85°C

TBD

Output duty cycle

Output jitter

Period Jitter

ps RMS

Cycle-to-Cyle Jitter

IDYN1RC

ISTB1RC

Operating current

Standby current of crystal

oscillator

µA

PSRR1RC

Power supply noise

tolerance

TBD

Vp-p

EN1RC

VIH1RC

VIL1RC

SU1RC

Enable Time

TBD

µs

Input logic level High

Input logic level Low

Startup time

Test load used:

µs

Revision 0

2-81

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

Clock Conditioning Circuits (CCC)

Table 2-85 • SmartFusion2 CCC/PLL Specification

Parameter

Minimum Typical Maximum

Units

MHz

Notes

Clock Conditioning Circuitry Input Frequency f_{IN_CCC}

Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}

Delay Increments in Programmable Delay Blocks

200

400

100

Number of Programmable Values in Each Programmable

Delay Block

Acquisition Time

Tracking Jitter

500

µs

TBD

Output Duty Cycle

Feedback Delay

CCC Output Peak-to-Peak Period

Jitter FCCC_OUT

Maximum peak-to-peak period Jitter

SSO = 0 0 < SSO ≤ 2 SSO ≤ 4 SSO ≤ 8 SSO ≤ 16

FG896

TBD

FG896

TBD

FG896

TBD

FG896

TBD

20 MHz to 100 MHz

100 MHz to 200 MHz

% f_{OUT_CCC}

TBD

200 MHz to 400 MHz

TBD

Spread Spectrum Characteristics

Modulation Frequency Range

Modulation Depth Range

Modulation Depth Control

kHz

1.5

0.5

2-82

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Serial Peripheral Interface (SPI) Characteristics

This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output

characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to

SPI_x_CLK. For timing parameter definitions, refer to Figure 2-9 on page 2-84.

Table 2-86 • SPI Characteristics

Commercial Case Conditions: T_J= 85ºC, VDD = 1.425 V, –1 Speed Grade

Symbol

Description and Condition

SPI_x_CLK minimum period

M2S050T

Unit

sp1

SPI_x_CLK = PCLK/2

–

µs

SPI_x_CLK = PCLK/4

TBD

SPI_x_CLK = PCLK/8

SPI_x_CLK = PCLK/16

SPI_x_CLK = PCLK/32

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

SPI_x_CLK = PCLK/256

sp2

SPI_x_CLK minimum pulse width high

SPI_x_CLK = PCLK/2

–

µs

SPI_x_CLK = PCLK/4

TBD

SPI_x_CLK = PCLK/8

SPI_x_CLK = PCLK/16

SPI_x_CLK = PCLK/32

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

SPI_x_CLK = PCLK/256

sp3

SPI_x_CLK minimum pulse width low

SPI_x_CLK = PCLK/2

–

SPI_x_CLK = PCLK/4

TBD

SPI_x_CLK = PCLK/8

SPI_x_CLK = PCLK/16

µs

SPI_x_CLK = PCLK/32

µs

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

µs

SPI_x_CLK = PCLK/256

µs

sp4

sp5

sp6

sp7

sp8

sp9

SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%)

SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%)

Data from master (SPI_x_DO) setup time

Data from master (SPI_x_DO) hold time

SPI_x_DI setup time

pclk cycles

SPI_x_DI hold time

Revision 0

2-83

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

SP1

SP4

SP5

SP3

SP2

50% 50%

90%

10%

50%

SPI_x_CLK

SPO = 0

10%

SPI_x_CLK

SPO = 1

90%

SPI_x_SS

10%

SP4

10%

SP5

SP6

SP7

90%

MSB

50%

SPI_x_DO

SPI_x_DI

10%

SP8

SP9

SP5

SP4

50%

MSB

Figure 2-9 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)

2-84

Revision 0

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 System-on-Chip FPGAs

Inter-Integrated Circuit (I C) Characteristics

This section describes the DC and switching of the I²C interface. Unless otherwise noted, all output

characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 2-

10 on page 2-86.

Table 2-87 • I²C Characteristics

Commercial Case Conditions: T_J= 85ºC, VDD = 1.14 V, –1 Speed Grade

Parameter

Definition

Condition

Value

Unit

VIL

Minimum input low voltage

–

See Table 2-18 on

page 2-22

–

Maximum input low voltage

Minimum input high voltage

Maximum input high voltage

Maximum output voltage low

Input current high

–

See Table 2-18

–

VIH

–

VOL

IIL

IOL = TBD

–

IIH

Input current low

Vhyst

Hysteresis of Schmitt trigger

inputs

See Table 2-17 on

page 2-21

T_FALL

Fall time

VIHmin to VILMax, Cload = 400 pF

VIHmin to VILMax, Cload = 100 pF

VILMax to VIHmin, Cload = 400 pF

VILMax to VIHmin, Cload = 100 pF

VIN = 0, f = 1.0 MHz

TBD

T_RISE

Rise time

Cin

Pin capacitance

R_pull-up

Output buffer maximum pull-

down Resistance

–

R_pull-downOutput buffer maximum pull-up

Resistance

–

TBD

D_max

Maximum data rate

Low period of I2C_x_SCL

High period of I2C_x_SCL

START hold time

Fast mode

TBD

Kbps

t_LOW

–

pclk cycles

t_HIGH

t_HD;STA

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_FILT

START setup time

DATA hold time

DATA setup time

STOP setup time

Maximum spike width filtered

Revision 0

2-85

ADVANCE INFORMATION (Subject to Change)

SmartFusion2 DC and Switching Characteristics

SDA

SCL

T_RISE

t_LOW

T_FALL

t_HIGH

t_SU;STO

t_SU;DAT

t_SU;STA

t_HD;DAT

t_HD;STA

Figure 2-10 • I2C Timing Parameter Definition

2-86

Revision 0

3 – SmartFusion2 Development Tools

System designers can leverage the newly released, easy-to-use Libero^®system-on-chip (SoC) software

toolset for designing SmartFusion2 devices. Libero SoC highlights include the following:

•

System Builder for creation of system level architecture

Synthesis, debug and DSP support from Synopsys

Simulation from Mentor Graphics

Push-button design flow with power analysis and timing analysis

SmartDebug for access to non-invasive probes within SmartFusion2 devices

Integrated firmware flows for GNU, IAR, and Keil

Operating system support includes uClinux from Emcraft Systems, FreeRTOS,™ SAFERTOS,^®

and uc/OS-III™ from Micrium.

Figure 3-1 • Tool Flow

Libero SoC

Libero SoC and Libero Integrated Design Environment (IDE) are comprehensive software toolsets for

designing with Microsemi FPGAs. Different versions of Libero support different families.

•

Libero SoC v11.0 Beta software release supports only the recently announced SmartFusion2 SoC

FPGAs. This version includes a new System Builder design approach, specifically targeted for

SmartFusion2 devices. A production version of this software will be available in April 2013, when

it will integrate support for the other production flash families currently supported by Libero v10.1.

Libero SoC v10.1 software release for designing with Microsemi's SmartFusion, IGLOO,^®

ProASIC^®3, and Fusion^®families, managing the entire design flow from design entry, synthesis

and simulation, through place-and-route, timing and power analysis, with enhanced integration of

the embedded design flow.

Libero IDE software release for designing with Microsemi antifuse and legacy flash FPGAs and

managing the entire design flow from design entry, synthesis and simulation, through place-and-

route, timing and power analysis (refer to PCN 1108).

Libero SoC introduces a new SoC design flow, specifically targeted to simplify the design of our newest

flash FPGAs. Standalone tools such as Silicon Sculptor, FlashPro, Identify ME, and Synphony Model

Compiler ME are not changing and will continue to include support for all silicon devices.

Current licenses are valid for both SoC and IDE releases; a new license is not required for Libero SoC.

Revision 0

3-1

SmartFusion2 Development Tools

From design, synthesis and simulation, through floorplanning, place-and-route, timing constraints and

analysis, power analysis, and program file generation, Libero manages the entire design flow quickly and

efficiently. SmartDesign provides an efficient methodology for creating complete simple and complex

embedded processor-based system-on-chip (SoC) designs with ease.

The SoC design flow provides the designer the choice of using the powerful microprocessor subsystem

(MSS) standalone or creating a more complex system by utilizing available programmable gates in the

FPGA fabric. Libero enables the designer to configure the hardwired Cortex-M3 processor, analog

(SmartFusion only), and peripherals within MSS, plus extend additional logic functionality into the FPGA

fabric, thus taking full advantage of the specific SoC FPGA device resources.

Libero provides full power optimization and analysis tools for Microsemi's low-power flash FPGA families.

Libero Software Features

Libero software offers the latest and best-in-class FPGA development tools from leading EDA vendors

such as Mentor Graphics and Synopsys. These tools, combined with tools developed by Microsemi,

allow you to quickly and easily manage your Microsemi FPGA designs. An intuitive user interface and

powerful design manager guide you through the process while organizing design files and seamlessly

managing exchanges between the various tools.

•

Powerful project and design flow management

Full suite of integrated design entry tools and methodologies:

–

SmartDesign graphical SoC design creation with automatic abstraction to HDL

Core Catalog and configuration

Fabric utilization for SmartFusion2 designs

HDL and HDL templates

User-defined block creation flow for design re-use

Microsemi cell libraries

•

Synplify Pro^®ME synthesis fully optimizes Microsemi FPGA device performance and area

utilization

Synphony Model Compiler ME performs high-level synthesis optimizations within a Simulink^®

environment

•

ModelSim^®ME VHDL or Verilog behavioral, post-synthesis and post-layout simulation capability

Designer physical design implementation, floorplanning, physical constraints, and layout

Timing-driven and power-driven place-and-route

SmartTime environment for timing constraint management and analysis

SmartPower provides comprehensive power analysis for actual and "what if" power scenarios

Interface to FlashPro programmers

Post-route probe insertion and Identify^®AE debugging software for Microsemi flash designs

Supported on Microsoft^®Windows^®and RedHat Linux operating systems

System Builder

System builder (Figure 3-2 on page 3-3) is a new graphical design wizard designed specifically for

SmartFusion2 based designs. System builder walks the user through the following steps:

•

Asks the user basic questions on system architecture

Adds any additional peripherals in the fabric

Walks through configuration options for each selected feature

Builds complete base system and API – correct by design

3-2

Revision 0

SmartFusion2 System-on-Chip FPGAs

Figure 3-2 • System Builder

SmartDebug

SmartDebug is a new debug tool added in Libero SoC v11.0 software that supports probe capabilities in

the SmartFusion2 architecture and also supports device debug features for memory. SmartFusion2

devices have built-in probe points that greatly enhance the ability to debug logic elements within the

device. The enhanced debug features implemented in SmartFusion2 devices give access to any logic

element and enable designers to check the state of inputs and outputs in real time. Live Probe and Active

Probe are only available on the SmartFusion2 family of products.

•

With Live Probe, two dedicated probes can be configured to observe a Probe Point which is any

input or output of a logic element. The probe data can then be sent to an oscilloscope or even

redirected back to the FPGA fabric to drive a software logic analyzer.

Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This

enables a user to quickly observe the output of the logic internally or to quickly experiment on how

the logic will be affected by writing to a probe point.

Memory debug gives the ability to perform dynamic asynchronous reads and writes to a micro

SRAM or large SRAM block so the user can quickly verify if the content of the memory is

changing as expected.

SmartDebug features can be accessed from within the Libero design flow or FlashPro software.

Revision 0

3-3

SmartFusion2 Development Tools

SoftConsole

Microsemi's Embedded Software Development Environment

SoftConsole is Microsemi's free software development environment that enables the rapid production of

C and C++ executables for Microsemi FPGAs using Cortex-M3, Cortex-M1, and Core8051s. Libero SoC

automatically generates SoftConsole projects and firmware for SoC FPGA designs. SoftConsole

includes a fully integrated debugger that offers easy access to memory contents, registers, and single-

instruction execution.

Product Features

SoftConsole (Figure 3-3 on page 3-5) provides a flexible and easy-to-use graphical user interface for

managing your embedded software development projects. You can quickly develop and debug software

programs and implement them in Microsemi FPGAs. SoftConsole enables you to configure project

settings, edit and debug software programs, and organize your files. With this tool you have

simultaneous access to multiple tool windows and the ability to quickly switch editing and debug views.

•

Available for free download

Eclipse-based IDE

GNU C/C++ compiler (Cortex-M3 and Cortex-M1)

SDCC compiler (Core8051s)

GDB debugger

FlashPro4/3/3X compatible debug sprite

Seamless access to and debug of flash memory (SmartFusion2 eNVM, Fusion NVM, external

flash)

•

Simultaneous access to multiple tool windows

Fast switch between C/C++ and debug

One or more perspectives in a workbench window

Perspectives can be customized by the user

Provides a direct interface to:

–

SmartFusion2 microcontroller subsystem (MSS) for SmartFusion2 designs

Firmware Catalog, which includes CMSIS-PAL for Cortex-M3, HALs for Cortex-M1 and 8051s,

driver firmware packages, sample programs, and linker scripts

•

Compatible with Libero SoC and IDE design flows

3-4

Revision 0

SmartFusion2 System-on-Chip FPGAs

SoftConsole User Interface

Figure 3-3 • SoftConsole User Interface

Revision 0

3-5

SmartFusion2 Development Tools

Firmware Catalog

The Firmware Catalog is a standalone executable program that supports Microsemi SoftConsole, Keil™,

and IAR Systems^®embedded processor development toolchains targeting the ARM Cortex-M3,

Cortex-M1, and Core8051s processors. The Firmware Catalog streamlines locating and generating

firmware that is compatible with Intellectual Property (IP) cores used in Microsemi FPGA designs.

Firmware can also be delivered through SmartDesign within the Libero environment.

Software Drivers

Microsemi has a broad offering of proven and pre-implemented synthesizable IP building blocks that can

be easily configured and used within Microsemi FPGA system-level designs. Software drivers for many

Microsemi IP cores are available within the Firmware Catalog. The drivers are free of charge and

delivered as C source, so they can be easily compiled and linked into a user's program or executable.

These drivers hide the implementation details of peripheral operations behind a driver application

program interface (API), so the developer need only be concerned with the peripheral's function.

Hardware Abstraction Layers

A hardware abstraction layer (HAL) that supports ARM Cortex-M3, Cortex-M1 and Core8051s

processors is also available. HALs enable the software driver to be used without modification, isolating

the driver's implementation from the hardware platform variations. A driver implementation interacts with

the hardware peripheral it is controlling. This enables programmers to seamlessly reuse code, even

when the hardware platform changes.

Web Repositories

(Microsemi, Other)

Access Repositories

Download

Browse for Firmware

Firmware Catalog

SoftConsole

Generate Core

Vault

(Local or Remote)

Load Program

Figure 3-4 • Hardware Abstraction Layer

The Firmware Catalog notifies the user if new firmware cores or firmware updates are available from

Microsemi's web repository. The updates can be downloaded into a local vault on a PC. A vault is a local

directory (either local to a machine or on the local network) that contains cores downloaded from one or

more repositories. The repository is a location on the web that contains firmware cores ready to be used

directly in any toolchain software.

3-6

Revision 0

SmartFusion2 System-on-Chip FPGAs

After selecting IPs to use in the Microsemi FPGA design, the associated firmware can be selected in the

Firmware Catalog and the IP cores can be generated. The IP cores are then loaded into the code via

SoftConsole, Keil, or IAR Systems software development environments.

For the SoC design flow, the designer does not need to determine which firmware must be selected and

generated. Although the designer can browse the complete listing of firmware in the Firmware Catalog,

the SmartDesign flow for SmartFusion2 and SmartFusion searches the design for instantiated IP and

automatically presents the appropriate firmware.

Firmware Catalog User Interface

Figure 3-5 • Firmware Catalog User Interface

The Firmware Catalog is configured within SoftConsole so that it is integrated in the toolchain, which

allows seamless location, configuration, and addition of firmware to the user's SoftConsole project.

Revision 0

3-7

SmartFusion2 Development Tools

SoC FPGA Ecosystem

Microsemi has a long history of supplying comprehensive FPGA development tools and recognizes the

benefit of partnering with industry leaders to deliver the optimum usability and productivity to customers.

Taking the same approach with processor development, Microsemi has partnered with key industry

leaders in the microcontroller space to provide the robust SoC FPGA ecosystem.

Microsemi is partnering with Keil and IAR to provide Software IDE support to system designers. The

result is a robust solution that can be easily adopted by developers who are already doing embedded

design. The learning path is straightforward for FPGA designers.

Figure 3-6 shows a software stack with examples of drivers, RTOS and middleware from Microsemi and

partners. By leveraging the software stack, designers can decide at which level to add their own

customization to their design, thus speeding time to market and reducing overhead in the design.

Application

Customer Secret Sauce

Layer

Middleware

OS/RTOS

TCP/IP, HTTP, SMTP, DHCP, LCD

μC/OS-III, RTX, uClinux, FreeRTOS

...

Drivers

Hardware

Abstraction

Layer

Microsemi CMSIS-based HAL

Microsemi SmartFusion2

Hardware

Platform

Figure 3-6 • Software Stack

3-8

Revision 0

SmartFusion2 System-on-Chip FPGAs

ARM

Because an ARM processor was chosen for SmartFusion2 and SmartFusion devices, Microsemi's

customers can benefit from the extensive ARM ecosystem. By building on Microsemi supplied hardware

abstraction layer (HAL) and drivers, third party vendors can easily port RTOS and middleware for the

SmartFusion devices.

•

ARM Cortex-M Series Processors

ARM Cortex-M3 Processor Resources

ARM Cortex-M3 Technical Reference Manual

ARM Cortex-M3 Processor Software Development for ARM7TDMI Processor Programmers

White Paper

Compile and Debug

Software IDE

SoftConsole

Keil MDK

www.keil.com

32 K code limited

IAR Embedded Workbench^®

www.iar.com

Website

www.microsemi.com/soc

Free with Libero SoC

Free versions from SoC

Products Group

32 K code limited

Available from Vendor

Compiler

N/A

Full version

RealView C/C++

Vision Debugger

Vision Simulator

Full version

IAR ARM Compiler

C-SPY^®Debugger

Yes

GNU GCC

GDB debug

Debugger

Instruction Set Simulator

Debug Hardware

FlashPro4

ULINK2^®or ULINK-ME

J-LINK™ or J-LINK Lite

Microsemi's SoftConsole is a free Eclipse-based IDE that enables the rapid production of C and C++

executables for Microsemi FPGAs and cSoCs using Cortex-M3, Cortex-M1, and Core8051s. For

SmartFusion support, SoftConsole includes the GNU C/C++ compiler and GDB debugger. Additional

examples can be found on the SoftConsole page.

Using UART with SmartFusion cSoC: SoftConsole Standalone Flow Tutorial

Displaying POT Level with LEDs: Libero SoC and SoftConsole Flow Tutorial for a SmartFusion cSoC

IAR Embedded Workbench^®for ARM/Cortex is an integrated development environment for building and

debugging embedded ARM applications using assembler, C and C++. It includes a project manager,

editor, build and debugger tools with support for RTOS-aware debugging on hardware or in a simulator.

•

Designing SmartFusion with IAR Systems

IAR Embedded Workbench for ARM

Keil's Microcontroller Development Kit comes in two editions: MDK-ARM and MDK Basic. Both editions

feature µVision^®, the ARM Compiler, MicroLib, and RTX, but the MDK Basic edition is limited to 256K so

that small applications are more affordable.

•

Designing SmartFusion with Keil

Using Keil µVision and Microsemi SmartFusion

Keil Microcontroller Development Kit for ARM Product Manuals

Download Evaluation version of Keil MDK-ARM

Revision 0

3-9

SmartFusion2 Development Tools

Operating Systems

FreeRTOS™ is a portable, open source, royalty free, mini real-time kernel (a free-to-download and free-

to-deploy RTOS that can be used in commercial applications without any requirement to expose your

proprietary source code). FreeRTOS is scalable and designed specifically for small embedded systems.

This FreeRTOS version ported by Microsemi is 6.0.1. For more information, visit the FreeRTOS website:

www.freertos.org

•

SmartFusion Webserver Demo Using uIP and FreeRTOS

•

SmartFusion: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note

Emcraft Systems provides porting of the open-source U-boot firmware and uClinux™ kernel to

SmartFusion, a Linux-based cross-development framework, and other complementary components.

Combined with the release of its A2F-Linux Evaluation Kit, this provides a low-cost platform for

evaluation and development of Linux (uClinux) on the Cortex-M3 CPU core of Microsemi SmartFusion2

devices.

•

Emcraft Linux on Microsemi's SmartFusion

Keil offers the RTX Real-Time Kernel as a royalty-free, deterministic RTOS designed for ARM and

Cortex-M devices. It allows you to create programs that simultaneously perform multiple functions and

helps to create applications which are better structured and more easily maintained.

•

The RTX Real-Time Kernel is included with MDK-ARM. Download the Evaluation version of Keil

MDK-AR.

•

RTX source code is available as part of Keil/ARM Real-Time Library (RL-ARM), a group of tightly-

coupled libraries designed to solve the real-time and communication challenges of embedded

systems based on ARM-powered microcontroller devices. The RL-ARM library now supports

SmartFusion devices and designers with additional key features listed in the "Middleware" section

on page 3-11.

Micrium supports SmartFusion with the company's flagship µC/OS family, recognized for a variety of

features and benefits, including unparalleled reliability, performance, dependability, impeccable source

code and vast documentation. Micrium supports the following products for SmartFusion devices and

continues to work with Microsemi on additional projects.

•

µC/OS-III, Micrium's newest RTOS, is designed to save time on your next embedded project and

puts greater control of the software in your hands.

•

SmartFusion Quickstart Guide for Micrium µC/OS-III Examples

RoweBots provides an ultra tiny Linux-compatible RTOS called Unison for SmartFusion. Unison consists

of a set of modular software components, which, like Linux, are either free or commercially licensed.

Unison offers POSIX^®and Linux compatibility with hard real-time performance, complete I/O modules

and an easily understood environment for device driver programming. Seamless integration with FPGA

and analog features are fast and easy.

•

Unison V4-based products include a free Unison V4 Linux and POSIX-compatible kernel with

serial I/O, file system, six demonstration programs, upgraded documentation and source code for

Unison V4, and free (for non-commercial use) Unison V4 TCP/IP server. Commercial license

upgrade is available for Unison V4 TCP/IP server with three demonstration programs, DHCP

client and source code.

•

Unison V5-based products include commercial Unison V5 Linux- and POSIX-compatible kernel

with serial I/O, file system, extensive feature set, full documentation, source code and more than

20 demonstration programs, Unison V5 TCP/IPv4 with extended feature set, sockets interface,

multiple network interfaces, PPP support, DHCP client, documentation, source code and six

demonstration programs, and multiple other features.

3-10

Revision 0

SmartFusion2 System-on-Chip FPGAs

Middleware

Microsemi has ported both uIP and IwIP for Ethernet support as well as including TFTP file service.

•

SmartFusion Webserver Demo Using uIP and FreeRTOS

•

SmartFusion: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note

The Keil/ARM Real-Time Library (RL-ARM)* in addition to RTX source includes:

•

RL-TCPnet (TCP/IP) – The Keil RL-TCPnet library, supporting full TCP/IP and UDP protocols, is a

full networking suite specifically written for small ARM and Cortex-M processor-based

microcontrollers. TCPnet is now ported to and supports SmartFusion Cortex-M3. It is highly

optimized, has a small code footprint, and gives excellent performance, providing a wide range of

application level protocols and examples such as FTP, SNMP, SOAP, and AJAX. An HTTP server

example of TCPnet working in a SmartFusion design is available.

•

The Flash File System (RL-Flash) allows your embedded applications to create, save, read, and

modify files in standard storage devices such as ROM, RAM, or FlashROM, using a standard

serial peripheral interface (SPI). Many ARM-based microcontrollers have a practical requirement

for a standard file system. With RL-FlashFS you can implement new features in embedded

applications such as data logging, storing program state during standby modes, or storing

firmware upgrades.

Note: * The CAN and USB functions within RL-ARM are not supported for SmartFusion.

Micrium in addition to their µC/OS-III offers the following support for SmartFusion:

•

µC/TCP-IP™ is a compact, reliable and high-performance stack built from the ground up by

Micrium and has the quality, scalability and reliability that translates into a rapid configuration of

network options, remarkable ease-of-use and rapid time-to-market.

•

µC/Probe™ is one of the most useful tools in embedded systems design and puts you in the

driver's seat, allowing you to take charge of virtually any variable, memory location, and I/O port in

your embedded product, while your system is running.

Revision 0

3-11

SmartFusion2 Development Tools

SmartFusion2 Development Kit

The SmartFusion2 Development Kit allows access to the peripherals of the SmartFusion2 SoC FPGA.

This board is designed to support full application development and prototyping. The kit will also serve as

a motherboard for several application-specific daughtercards that will be rolled over the next year.

•

Motor control interface card supports up to 6 motor daughtercards

System Management daughtercard

Aviation daughtercard

Figure 3-7 • SmartFusion2 Development Kit

Figure 3-8 • SmartFusion2 Applications

3-12

Revision 0

4 – Pin Descriptions

SmartFusion2 devices support multi-standard I/Os (MSIO), microcontroller serial interfaces, high speed

serial interfaces, and a debugging JTAG interface. SmartFusion2 devices require all the power supplies

listed in Table 4-1.

Supply Pins

Table 4-1 • Supply Pins

Name

Type

Description

Min. (V)

Max. (V)

VSS

Ground Ground pad for core and I/Os

PLL0_VSSA

Ground VDDA to on-die VSSA high pass filter connection

for PLL0. If unused, it must be grounded.

PLL0_VDDA

PLL1_VSSA

Supply Analog power pad for PLL0

2.5

3.3

Ground VDDA to on-die VSSA high pass filter connection

for PLL1. If unused, it must be grounded.

PLL1_VDDA

PLL2_VSSA

Supply Analog power pad for PLL1

Ground VDDA to on-die VSSA high pass filter connection

for PLL2. If unused, it must be grounded.

PLL2_VDDA

PLL3_VSSA

Supply Analog power pad for PLL2

Ground VDDA to on-die VSSA high pass filter connection

for PLL3. If unused, it must be grounded.

PLL3_VDDA

PLL4_VSSA

Supply Analog power pad for PLL3

Ground VDDA to on-die VSSA high pass filter connection

for PLL4. If unused, it must be grounded.

PLL4_VDDA

PLL5_VSSA

Supply Analog power pad for PLL4

Ground VDDA to on-die VSSA high pass filter connection

for PLL5. If unused, it must be grounded.

PLL5_VDDA

Supply Analog power pad for PLL5

PLL_PCIE_0_VSSA

Ground VDDA to on-die VSSA high pass filter connection

for PLL PCIe0. If unused, it must be grounded.

PLL_PCIE_0_VDDA

PLL_PCIE_1_VSSA

PLL_PCIE_1_VDDA

Notes:

Supply High supply voltage for PLL PCIe0. If unused,

should be connected to +3.3 V.

Ground VDDA to on-die VSSA high pass filter connection

for PLL PCIe1. If unused, it must be grounded

Supply High supply voltage for PLL PCIe1. If unused,

should be connected to +3.3 V.

2.5

3.3

1. PCIe0 for SERDESIF_0 and PCIe1 for SERDESIF_1

2. VREF is not used in differential mode.

3. The M2S050T device has two SERDESIFs (SERDESIF_0, SERDESIF_1), which reside on 2 I/O banks (bank 6 and

bank 9) out of a total of 10 I/O banks.

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4-1

Pin Descriptions

Table 4-1 • Supply Pins (continued)

Name

Type

Description

Min. (V)

Max. (V)

PCIE0VDD

Supply PCIe/PCS supply. If unused, should be connected

to +1.2 V.

1.2

PCIE0VDDIOL¹

Supply Tx/Rx analog I/O voltage. Low voltage power for

PCIe0 for lane0 and lane1 of SERDESIF_0, located

on the left side. If unused, should be connected to

+1.2 V.

1.2

PCIE0VDDIOR¹

Supply Tx/Rx analog I/O voltage. Low voltage power for

PCIe0 for lane2 and lane3 of SERDESIF_0, located

on the right side. If unused, should be connected to

+1.2 V.

PCIE0PLLREFRETL¹

Local

on-chip

ground

return

path

for

PCIE0VDDPLLL for lane0 and lane1 of

SERDESIF_0, located on the left side. DO NOT

short to GND on the package or PCB. For details,

refer to the "High speed board design guidelines”-

SERDES I/Os section. If unused, it can be left

floating.

PCIE0VDDPLLL¹

Supply Analog power for SERDES PLL of PCIe0 lanes

0&1. If unused, should be connected to +2.5 V

2.5

PCIE0PLLREFRETR¹

Local

on-chip

ground

return

path

for

PCIE0VDDPLLR for lanes 2 and 3 of SERDESIF_0

that is located on right side. DO NOT short to GND

on the package or PCB. If unused, it can be left

floating.

PCIE0VDDPLLR¹

PCIE1VDD

Supply Analog power for SERDES PLL of PCIe0 lane2 and

lane3. If unused, should be connected to +2.5 V.

2.5

1.2

Supply PCIe/PCS supply. If unused, should be connected

to +1.2 V.

PCIE1VDDIOL¹

Supply Tx/Rx analog I/O voltage. Low voltage power for

PCIe1 for lane0 and lane1 of SERDESIF_1, located

on the left side. If unused, should be connected

to+1.2 V.

1.2

PCIE1VDDIOR¹

Supply Tx/Rx analog I/O voltage. Low voltage power for

PCIe1 for lane2 and lane3 of SERDESIF_1, located

on the right side. If unused, should be connected to

+1.2 V.

1.2

PCIE1PLLREFRETL¹

Local

on-chip

ground

return

path

for

PCIE1VDDPLLL for lane0 and lane1 of

SERDESIF_1, located on left side. DO NOT short

to GND on the package or PCB. If unused, it can be

left floating.

PCIE1VDDPLLL¹

Supply Analog power for SERDES PLL of PCIe1 lane0 and

lane1. If unused, connect to +2.5 V.

2.5

Notes:

1. PCIe0 for SERDESIF_0 and PCIe1 for SERDESIF_1

2. VREF is not used in differential mode.

3. The M2S050T device has two SERDESIFs (SERDESIF_0, SERDESIF_1), which reside on 2 I/O banks (bank 6 and

bank 9) out of a total of 10 I/O banks.

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SmartFusion2 System-on-Chip FPGAs

Table 4-1 • Supply Pins (continued)

Name

Type

Description

ground return

Min. (V)

Max. (V)

PCIE1PLLREFRETR¹

Local

on-chip

path

for

PCIE1VDDPLLR for lane2 and lane3 of

SERDESIF_1, located on right side. DO NOT short

to GND on the package or PCB. If unused, it can be

left floating.

PCIE1VDDPLLR¹

Supply Analog power for SERDES PLL of PCIe1 lane2 and

lane3. If unused, should be connected to +2.5 V.

2.5

PLL_MDDR_VSSA

PLL_MDDR_VDDA

PLL_FDDR_VSSA

PLL_FDDR_VDDA

VREF0²

Ground Analog ground pad for PLL MDDR

Supply Analog power pad for PLL MDDR

Ground Analog ground pad for PLL of FDDR

Supply Analog power pad for PLL of FDDR

Supply Reference voltage for FDDR (bank 0)

Supply Reference voltage for MDDR (bank 5)

Ground eNVM ground

2.5

3.3

0.50 * VDDI0 0.50 * VDDI0

0.50 * VDDI5 0.50 * VDDI5

VREF5²

VSSNVM

VPPNVM

Supply eNVM power pad

2.5

1.2

3.3

2.5

3.3

2.5

VDDI0

Supply VDDI port 0, bank 0 power

Supply VDDI port 1, bank 1 power

Supply VDDI port 2, bank 2 power

Supply VDDI port 3, bank 3 power

Supply VDDI port 4, bank 4 power

Supply VDDI port 5, bank 5 power

Supply VDDI port 6, bank 6 power

VDDI1

VDDI2

VDDI3

VDDI4

VDDI5

VDDI6

VDDI7

VDDI8

VDDI9

Supply VDDI port 7, bank 7 power

Supply VDDI port 8, bank 8 power

Supply VDDI port 9, bank 9 power

1.2

2.5

3.3

2.5

VDD

Supply Low voltage supply port

Supply Power for charge pumps

1.2

3.3

VPP

2.5

Notes:

1. PCIe0 for SERDESIF_0 and PCIe1 for SERDESIF_1

2. VREF is not used in differential mode.

3. The M2S050T device has two SERDESIFs (SERDESIF_0, SERDESIF_1), which reside on 2 I/O banks (bank 6 and

bank 9) out of a total of 10 I/O banks.

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4-3

Pin Descriptions

Dedicated Global I/O Naming Conventions

Dedicated global I/Os are dual-use I/Os which can drive the global blocks either directly or through clock

conditioning circuits (CCC) or virtual clock conditioning circuits (VCCC). They can also be used as

regular I/Os. These global I/Os are the primary source for bringing in the external clock inputs into the

SmartFusion2 device. In the M2S050T device, there are 16 global blocks located in the center of the

fabric and 32 global I/Os located 8 each on the north, east, south, and west sides of the fabric. There are

6 CCC blocks, located 2 each on northwest, northeast, and southwest side of the fabric and 2 VCCC

blocks on the southeast side of the fabric.

Dedicated global I/Os that drive the global blocks (GB) directly are named as GBn, where

n is 0 to 15.

Dedicated global I/Os that drive GBs through CCCs are named as CCC_xyz_lw, where:

xy is the location—NE, SW, or NW.

z is 0 or 1.

I represents I/O

w refers to one of the four possible output clocks of the associated CCC_xyz—GL0, GL1, GL2, or

GL3.

Dedicated global I/Os that drive GBs through VCCCs are named as VCCC_SEz, where:

SE is southeast.

z is 0 or 1.

Unused global pins are configured as inputs with pull-up resistors by Libero software.

For further details, refer to the "Fabric Global Routing Resources" chapter of the SmartFusion2 FPGA

Fabric Architecture User’s Guide.

User I/O Naming Conventions

The naming convention used for each FPGA user I/O is IOxyBz, where:

IO is the type of I/O—MSIO, MSIOD, or DDRIO

For the M2S050T device:

MSIO x is the I/O pair number in bank z, starting at 0 from bank 3 (southeast) and

proceeding in a counter-clockwise direction to bank 2 and bank 1.

MSIOD x is the I/O pair number in bank z, starting at 93 from bank9 (northwest) and proceeding in a

counter-clockwise direction to bank7 and bank6.

DDRIO x is the I/O pair number in bank z, starting at 49 from bank0 (north) to bank5 (south).

y is P (positive) or N (negative). In single-ended mode, the I/O pair operates as two separate I/Os

named P and N. Differential mode is implemented with a fixed I/O pair and cannot be split with an

adjacent I/O.

B is bank.

z is the bank number—0 to 9.

Differential standards are implemented as true differential outputs and complementary single-ended

outputs for SSTL/HSTL. In the single-ended mode, the I/O pair operates as two separate I/Os named P

and N. All the configuration and data inputs/outputs are then separate and use names ending in P and N

to differentiate between the two I/Os.

For more information, refer to the "I/Os" chapter of the SmartFusion2 FPGA Fabric Architecture User’s

Guide.

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SmartFusion2 System-on-Chip FPGAs

Multi-Standard I/O

SmartFusion2 devices feature a flexible I/O structure that supports a range of mixed voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, and 3.3 V) through bank selection. The MSIO, MSIOD, and DDRIO can be configured

as differential I/Os or two single-ended I/Os. These I/Os use one I/O slot to implement single-ended

standards and two I/O slots for differential standards. The DDRIO is shared between fabric logic and

MDDR/FDDR whereas MSIO/MSIOD is shared between MSS peripherals and fabric logic. When you do

not use an MDDR/FDDR controller or MSS peripherals, the respective I/Os are available to fabric logic.

For functional block diagrams of MSIO, MSIOD, and DDRIO, refer to the SmartFusion2 FPGA Fabric

Architecture User’s Guide.

For supported I/O standards, refer to the Supported Voltage Standards table in the SmartFusion2 FPGA

Fabric Architecture User’s Guide.

Bank 0

DDRIO (MDDR)

(44 pairs)

Bank 9

Bank 1

MSIOD/SERDES_1

(2 pairs)

MSIO

(11 pairs)

Bank 8

Bank 2

MSIO

(23 pairs)

MSIO

(13 pairs)

SmartFusion2 SoC FPGA

Bank 7

Bank 3

MSIOD

(27 pairs)

MSIO

(25 pairs)

Bank 4

Bank 6

MSIOD/SERDES_0

(2 pairs)

MSIOD/JTAG

(3 pairs)

Bank 5

DDRIO (FDDR)

(44 pairs)

Figure 4-1 • SmartFusion2 (M2S050T) I/O Bank Location and Naming

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4-5

Pin Descriptions

Table 4-2 • Multi-Standard I/O Types

Name

Type

Description

MSIOxyBz

In/out MSIOs provide programmable drive strength, weak pull-up, and weak-pull-down. In single-

ended mode, the I/O pair operates as two separate I/Os named P and N. Some of these pins

are also multiplexed with integrated peripherals in the MSS (I2C, USB, SPI, UART, CAN, and

fabric I/Os).This allows MSIO pins to be multiplexed as I/Os for the FPGA fabric, the ARM

Cortex-M3 processor, or for given integrated MSS peripherals. MSIOs can be routed to

dedicated I/O buffers (MSSIOBUF) or in some cases to the FPGA fabric interface through an

IOMUX. SmartFusion2 I/O ports also support ESD protection.

MSIODxyBz In/out MSIOD is very similar to MSIO, but drops 3.3 V and hot-plug support and adds pre-emphasis,

in order to achieve higher speeds. MSIODs provide programmable drive strength, weak

pull-up, and weak pull-down. MSIOD I/O cells operate at up to 2.5 V and are capable of

high-speed LVDS operation. Some of these pins are also multiplexed with the SERDES

interface. SmartFusion2 I/O ports support ESD protection.

DDRIOxyBz In/out The double data input output (DDRIO) is

multi-standard I/O optimized for

LPDDR/DDR2/DDR3 performance. In SmartFusion2 devices there are two DDR subsystems:

the fabric DDR and MSS DDR controllers. All DDRIOs can be configured as differential I/Os or

two single-ended I/Os. If you select MDDR/FDDR, Libero SoC automatically connects

MDDR/FDDR signals to the DDRIOs. DDRIOs can be connected to the respective DDR

subsystem PHYs or can be used as user I/Os. Depending on the memory configuration, only

the required DDRIOs are used by Libero SoC. The unused DDRIOs are available to connect

to the fabric.

I/O Programmable Features

SmartFusion2 devices support different I/O programmable features for MSIO, MSIOD, and DDRIO. Each

I/O pair (P, N) supports the following programmable features:

•

Programmable drive strength

Programmable weak pull-up and pull-down

Configurable ODT and driver impedance

Programmable input delay

Programmable Schmitt input and receiver

For more information on SmartFusion2 I/O programmable features, refer to the SmartFusion2 I/O

Feature table of the SmartFusion2 FPGA Fabric Architecture User's Guide.

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SmartFusion2 System-on-Chip FPGAs

Impedance Calibration

There are two DDRIO calibration blocks in each SmartFusion2 M2S050T device. The MDDR and FDDR

have a DDRIO calibration block. The DDRIO can use fixed impedance calibration for different drive

strengths, and these values can be programmed using Libero SoC for the selected I/O standard. These

values are fed to the pull-up/pull-down reference network to match the impedance with an external

resistor.

Table 4-3 • Reference Resistors

Pin Name

Reference Resistor (Ohm)

FDDR_IMP_CALIB_ECC

Pulled down with 240, 150, 300, or 191 Ohms, depending on

voltage/standard desired for optimization.

MDDR_IMP_CALIB_ECC

Pulled down with 240, 150, 300, or 191 Ohms, depending on

voltage/standard desired for optimization.

For the different drive modes, refer to the SmartFusion2 FPGA Fabric Architecture User’s Guide for

reference resistor values.

Dedicated I/Os

Dedicated I/Os (Table 4-4 and Table 4-6 on page 4-8) can be used for a single purpose such as

SERDES, device reset, or clock functions. SmartFusion2 dedicated I/Os:

•

Device reset I/Os

Crystal oscillator I/Os

SERDES I/Os

Table 4-4 • Device Reset and Crystal Oscillator Pin Types and Descriptions

Type

I/O

Description

Device Reset I/Os

DEVRST_N

Analog

Input

Device reset; asserted Low and powered by VPP

Crystal Oscillator I/Os

EXTLOSC

XTLOSC

Analog

Input

Crystal connection or external RC network.

Input clock from the main crystal oscillator

Table 4-5 • Programming SPI Interface

Name

Type

Out

Description

SC_SPI_SS

SC_SPI_SDO

SC_SPI_SDI

SC_SPI_CLK

FLASH_GOLDEN

SPI slave select

SPI data output

SPI data input

SPI clock

Out

If pulled High, this indicates that the device is to be re-programmed from an

image in the external SPI Flash attached to the SPI interface. If pulled Low, the

SPI is put into slave mode.

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4-7

Pin Descriptions

SERDES I/Os

The SERDES I/Os available in SmartFusion2 devices are dedicated for high speed serial communication

protocols. The SERDES I/Os support protocols such as PCI Express 2.0, XAUI, serial gigabit media

independent interface (SGMII), serial rapid IO (SRIO), and any user-defined high speed serial protocol

implementation in fabric.

Table 4-6 • SERDES I/O Port Names and Descriptions

Port Name

Type

Description

Data / Reference Pads

PCIE_x_RXDP0

PCIE_x_RXDP1

PCIE_x_RXDP2

PCIE_x_RXDP3

PCIE_x_RXDN0

PCIE_x_RXDN1

PCIE_x_RXDN2

PCIE_x_RXDN3

PCIE_x_TXDP0

PCIE_x_TXDP1

PCIE_x_TXDP2

PCIE_x_TXDP3

PCIE_x_TXDN0

PCIE_x_TXDN1

PCIE_x_TXDN2

PCIE_x_TXDN3

Input

Receive data. SERDES differential positive input for each lane.

Each SERDESIF consists of 4 RX signals. Here x = 0 for SERDESIF_0 and

x = 1 for SERDESIF_1. If unused, can be left floating.

Input

Receive data. SERDES differential negative input for each lane.

Each SERDESIF consists of 4 RX signals. Here x = 0 for SERDESIF_0 and

x = 1 for SERDESIF_1. If unused, can be left floating.

Output

Transmit data. SERDES differential positive output for each lane.

Each SERDESIF consists of 4 TX signals. Here x = 0 for SERDESIF_0 and

x = 1 for SERDESIF_1. If unused, can be left floating.

Transmit data. SERDES differential negative output for each lane.

Each SERDESIF consists of 4 TX signals. Here x = 0 for SERDESIF_0 and

x = 1 for SERDESIF_1. If unused, can be left floating.

Common I/O Pads per SERDES Interface

PCIE_x_REXTL

Reference External reference resistor connection to calibrate TX/RX termination value.

Each SERDESIF consists of 2 REXT signals—one for lane0 and lane1, and

another for lane2 and lane3. Here x = 0 for SERDESIF_0 and x = 1 for

SERDESIF_1. If unused, can be left floating.

PCIE_x_REXTR

PCIE_x_REFCLK0P

Clock

Reference clock differential positive. Each SERDESIF consists of two signals

(REFCLK0_P, REFCLK1_P). These are dual purpose I/Os; you can use

these lines for MSIOD fabric, if SERDESIF is not activated. Here x = 0 for

SERDESIF_0 and x = 1 for SERDESIF_1. If unused, can be left floating.

PCIE_x_REFCLK1P

PCIE_x_REFCLK0N

Reference clock differential negative. Each SERDESIF consists of two

signals (REFCLK0_P, REFCLK1_P). These are dual purpose I/Os; you can

use these lines for MSIOD fabric, if SERDESIF is not activated. Here x = 0 for

SERDESIF_0 and x = 1 for SERDESIF_1. If unused, can be left floating.

PCIE_x_REFCLK1N

4-8

Revision 0

SmartFusion2 System-on-Chip FPGAs

JTAG Pins

SmartFusion2 devices have dedicated JTAG pins in bank 4. JTAG pins can be run at any voltage from

1.5 V to 3.3 V (nominal).

The debug port is implemented using a serial wire JTAG debug port (SWJ-DP) rather than a serial wire

debug port (SW-DP). This enables either the M3 JTAG or the SW protocol to be used for debugging.

Table 4-7 • JTAG Pin Names and Descriptions

Bus

Size

Name

Type

Description

JTAGSEL

JTAG controller selection.

Depending on the state of the JTAGSEL pin, an external JTAG controller will

see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug

interface (Low).

The JTAGSEL pin should be connected to an external pull-up resistor such

that the default configuration selects the FPGA fabric TAP.

JTAG_TCK/

M3_TCK

Test clock.

Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not

have an internal pull-up/pull-down resistor. If JTAG is not used,

Microsemi recommends tying it off.

Connect TCK to GND or +3.3 V through a resistor placed close to the FPGA

pin. This prevents totem-pole current on the input buffer and operation in case

TMS enters an undesired state. Note that to operate at all +3.3 V voltages,

500 Ω to 1 kΩ will satisfy the requirements.

JTAG_TDI/

M3_TDI

Test data.

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an

internal weak pull-up resistor on the TDI pin.

JTAG_TDO/

M3_TDO/

M3_SWO

Out

Test data.

Serial output for JTAG boundary scan, ISP, and UJTAG usage. The TDO pin

does not have an internal pull-up/-down resistor.

M3_SWO: Serial Wire Viewer output

Test mode select.

JTAG_TMS/

M3_TMS/

M3_SWDIO

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI,

TDO, and TRST). There is an internal weak pull-up resistor on the TMS pin.

M3_SWDIO: Serial Wire Debug data input/output

Boundary scan reset pin.

JTAG_TRSTB/

M3_TRSTB

The TRST pin functions as an active low input to asynchronously initialize (or

reset) the boundary scan circuitry. There is an internal weak pull-up resistor on

the TRST pin. If JTAG is not used, an external pull-down resistor (1K) could be

included to ensure the TAP is held in Reset mode. In critical applications, an

upset in the JTAG circuit could allow entering an undesired JTAG state. In

such cases, Microsemi recommends that you tie off TRST to GND through a

resistor (1K) placed close to the FPGA pin. The TRSTB pin also resets the

serial wire JTAG debug port (SWJ-DP) circuitry within the Cortex-M3

processor.

Revision 0

4-9

Pin Descriptions

Microcontroller Subsystem (MSS)

Table 4-8 • MSS Pin Names and Descriptions

Name

Type

Description

Inter-Integrated Circuit (I2C) Peripherals

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

In/out

in/out

I2C bus serial clock output. Can also be used as an MSS GPIO or

USB_DATA1_C or fabric I/O.

I2C bus serial data input/output. Can also be used as an MSS GPIO or

USB_DATA0_C or fabric I/O.

I2C bus serial clock output. Can also be used as an MSS GPIO or

USB_DATA4_A.

I2C bus serial data input/output. Can also be used as an MSS GPIO or

USB_DATA3_A.

Universal Asynchronous Receiver/Transmitter (UART) Peripherals

MMUART_0_CLK

MMUART_0_TXD

Out

UART clock. Can also be used as an MSS GPIO or USB_NXT_C or fabric I/O.

UART transmit data.

Can also be used as an MSS GPIO or USB_DIR_C or fabric I/O.

MMUART_0_RXD

MMUART_0_CTS

MMUART_0_RTS

MMUART_0_DTR

UART receive data.

Can also be used as an MSS GPIO or USB_STP_C or fabric I/O.

UART clear to send.

Can also be used as an MSS GPIO or USB_DATA7_C or fabric I/O.

Out

UART request to send.

Can also be used as an MSS GPIO or USB_DATA5_C or fabric I/O.

Modem data terminal ready. Can also be used as an MSS GPIO or

USB_DATA6_C or fabric I/O.

MMUART_0_DCD

MMUART_0_DSR

Modem data carrier detects. Can also be used as an MSS GPIO or fabric I/O.

Modem data set ready.

Can also be used as an MSS GPIO or fabric I/O.

MMUART_0_RI

Out

Modem ring indicator.

Can also be used as an MSS GPIO or fabric I/O.

MMUART_1_CLK

MMUART_1_TXD

MMUART_1_RXD

MMUART_1_CTS

MMUART_1_RTS

MMUART_1_DTR

UART Clock.

Can also be used as an MSS GPIO or USB_DATA4_C.

UART transmit data.

Can also be used as an MSS GPIO or USB_DATA2_C or fabric I/O.

UART receive data.

Can also be used as an MSS GPIO or USB_DATA3_C or fabric I/O.

UART clear to send.

Can also be used as an MSS GPIO or fabric I/O.

Out

UART request to send.

Can also be used as an MSS GPIO or fabric I/O.

Modem data terminal ready.

Can also be used as an MSS GPIO or fabric I/O.

4-10

Revision 0

SmartFusion2 System-on-Chip FPGAs

Table 4-8 • MSS Pin Names and Descriptions (continued)

Name

Type

Description

MMUART_1_DCD

Modem data carrier detects.

Can also be used as an MSS GPIO or fabric I/O.

MMUART_1_DSR

MMUART_1_RI

Modem data set ready.

Can also be used as an MSS GPIO or fabric I/O.

Modem ring indicator.

Can also be used as an MSS GPIO or fabric I/O.

Serial Peripheral Interface (SPI) Controllers

SPI_0_SS0

SPI_0_SS1

SPI_0_SS2

SPI_0_SS3

SPI_0_SS4

Out

SPI slave select0.

Can also be used as an MSS GPIO or USB_NXT_A or fabric I/O.

SPI slave select1.

Can also be used as an MSS GPIO or USB_DATA5_A or fabric I/O.

SPI slave select2.

Can also be used as an MSS GPIO or USB_DATA6_A or fabric I/O.

SPI slave select3.

Can also be used as an MSS GPIO or USB_DATA7_A or fabric I/O.

SPI slave select4.

Can also be used as an MSS GPIO or fabric I/O.

SPI_0_SS5

SPI_0_SS6

Out

SPI slave select5. Can also be used as an MSS GPIO or fabric I/O.

SPI slave select6.

Can also be used as an MSS GPIO or fabric I/O.

SPI_0_SS7

SPI_0_CLK

SPI_0_SDO

SPI_0_SDI

SPI_1_SS0

SPI_1_SS1

SPI_1_SS2

SPI_1_SS3

SPI_1_SS4

Out

SPI slave select7.

Can also be used as an MSS GPIO or fabric I/O.

SPI clock.

Can also be used as an MSS GPIO or USB_XCLK_A.

SPI data output.

Can also be used as an MSS GPIO or USB_STP_A or fabric I/O.

SPI data input.

Can also be used as an MSS GPIO or USB_DIR_A or fabric I/O.

Out

SPI slave select0.

Can also be used as an MSS GPIO or fabric I/O.

SPI slave select1.

Can also be used as an MSS GPIO or fabric I/O.

SPI slave select2.

Can also be used as an MSS GPIO or fabric I/O.

SPI slave select3.

Can also be used as an MSS GPIO or fabric I/O.

SPI slave select4.

Can also be used as an MSS GPIO or fabric I/O.

Revision 0

4-11

Pin Descriptions

Table 4-8 • MSS Pin Names and Descriptions (continued)

Name

Type

Description

SPI_1_SS5

Out

SPI slave select5.

Can also be used as an MSS GPIO or fabric I/O.

SPI_1_SS6

SPI_1_SS7

SPI_1_CLK

SPI_1_SDO

SPI_1_SDI

Out

SPI slave select6.

Can also be used as an MSS GPIO or fabric I/O.

SPI slave select7.

Can also be used as an MSS GPIO or fabric I/O.

SPI clock.

Can also be used as an MSS GPIO.

SPI data output.

Can also be used as an MSS GPIO or fabric I/O.

SPI data input.

Can also be used as an MSS GPIO or fabric I/O.

Multi-Function I/Os

Certain I/Os can have more than one function. Users select the functionality through Libero configuration

tools.

The name of a pin shows the functionalities for which that pin can be configured and used.

Example pin name: MSIO48NB1/I2C_0_SCL/GPIO_31_B/USB_DATA1_C

This I/O port is multi-purpose and can be configured as MSIO, I2C0 clock, fabric I/O, or USB_DATA1_C.

4-12

Revision 0

SmartFusion2 System-on-Chip FPGAs

Pin Assignment Tables

FG896

A1 Ball Pad Corner

30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 6 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

Revision 0

4-13

Pin Descriptions

FG896

M2S050T Function

Pin Number

PCIE_1_TXDN0

VSS

PCIE_1_TXDN1

VSS

PCIE_1_TXDN2

VSS

PCIE_1_TXDN3

DDRIO91PB0/GB0/CCC_NW0_I3

DDRIO90PB0/MDDR_DQS_ECC

DDRIO88PB0/MDDR_DQ32_ECC

DDRIO86PB0/MDDR_DQ0

DDRIO84PB0/MDDR_DQS0

DDRIO83NB0/MDDR_DQ4

DDRIO80PB0/MDDR_DQ8

DDRIO78PB0/GB8/CCC_NE0_I3/MDDR_DQS1

DDRIO76PB0/GB12/CCC_NE1_I2/MDDR_DQ12

DDRIO74PB0/MDDR_DQ16

DDRIO72PB0/MDDR_DQS2

DDRIO71NB0/MDDR_DQ20

DDRIO68PB0/MDDR_DQ24

DDRIO66NB0/MDDR_DQS3_N

DDRIO64PB0/MDDR_DQ28

DDRIO60PB0/MDDR_RST_N

DDRIO59PB0/MDDR_CLK

DDRIO57PB0/MDDR_BA2

DDRIO55PB0/MDDR_ADDR3

DDRIO55NB0/MDDR_ADDR4

VSS

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

MSIOD134NB7

MSIOD134PB7

MSIOD129NB7

MSIOD136NB7

MSIOD141NB7

PCIE_0_REXTL

PLL_PCIE_0_VSSA

PLL_PCIE_0_VDDA

4-14

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

AA9

PCIE_0_REXTR

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AB1

PLL4_VSSA

PCIE0VDDIOL

PCIE0VDDIOR

VDDI5

VDD

VSS

PLL_FDDR_VSSA

VDDI4

JTAGSEL

MSIO2PB3/USB_STP_B

MSIO2NB3/USB_NXT_B

MSIO7NB3/CAN_TX/GPIO_2_A/USB_DATA0_A

MSIO8NB3/CAN_TX_EN_N/GPIO_4_A/USB_DATA2_A

SC_SPI_CLK

MSIOD135NB7

MSIOD135PB7

VDDI7

AB2

AB3

AB4

MSIOD137NB7

PCIE0VDD

VSS

AB5

AB6

AB7

VSS

AB8

PCIE_0_RXDP0

PCIE_0_RXDN0

PCIE_0_RXDP2

PCIE_0_RXDN2

PCIE0VDD

VSS

AB9

AB10

AB11

AB12

AB13

AB14

VSS

Revision 0

4-15

Pin Descriptions

FG896

M2S050T Function

Pin Number

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AC1

VSS

VREF5

XTLOSC

EXTLOSC

PLL_FDDR_VDDA

VSS

JTAG_TRSTB/M3_TRSTB

MSIO0NB3/USB_DATA7_B

JTAG_TMS/M3_TMS/M3_SWDIO

VSS

MSIO6PB3/USB_DATA6_B

MSIO6NB3

MSIOD138NB7

MSIOD138PB7

MSIOD140NB7

MSIOD143PB7

VSS

AC2

AC3

AC4

AC5

AC6

VSS

AC7

PCIE0VDDPLLL

PCIE0PLLREFRETL

PCIE_0_RXDP1

PCIE_0_RXDN1

VPP

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

VSS

VDD

VSS

4-16

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AD1

VSS

VDDI4

JTAG_TDO/M3_TDO/M3_SWO

JTAG_TCK/M3_TCK

DEVRST_N

MSIO1PB3/USB_XCLK_B

MSIO1NB3/USB_DIR_B

MSIO5NB3/USB_DATA5_B

MSIOD139NB7

AD2

MSIOD139PB7

AD3

MSIOD143NB7

AD4

VSS

AD5

VSS

AD6

VSS

AD7

VSS

AD8

VSS

AD9

PCIE0PLLREFRETR

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

PCIE_0_RXDP3

PCIE_0_RXDN3

DDRIO150PB5/FDDR_FIFO_WE_IN_ECC

VREF5

VSS

VREF5

VSS

Revision 0

4-17

Pin Descriptions

FG896

M2S050T Function

Pin Number

AD27

AD28

AD29

AD30

AE1

VSS

MSIO5PB3/USB_DATA4_B

MSIOD146NB6/PCIE_0_REFCLK1N

AE2

MSIOD144NB7

AE3

VSS

AE4

VSS

AE5

VSS

AE6

VSS

AE7

VSS

AE8

VSS

AE9

PCIE0VDDPLLR

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

AF1

VDDI5

DDRIO147PB5/FDDR_FIFO_WE_OUT_ECC

VSS

VDDI5

DDRIO158NB5/FDDR_FIFO_WE_OUT1

DDRIO162PB5/FDDR_FIFO_WE_IN1

VDDI5

VSS

DDRIO170NB5/FDDR_FIFO_WE_OUT3

VDDI5

VSS

DDRIO174PB5/FDDR_FIFO_WE_IN3

VDDI5

DDRIO185NB5/FDDR_ADDR6

DDRIO185PB5/FDDR_ADDR5

VDDI5

VSS

DDRIO189PB5/FDDR_ADDR12

VDDI5

DDRIO178NB5/FDDR_CS_N

MSIO4NB3/USB_DATA3_B

MSIOD146PB6/PCIE_0_REFCLK1P

VSS

AF2

4-18

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

AF3

VSS

AF4

VSS

AF5

VSS

AF6

VSS

AF7

VSS

AF8

VSS

AF9

FDDR_IMP_CALIB_ECC

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AF30

AG1

VDDI5

DDRIO152PB5/GB3/CCC_SW0_I3/FDDR_DQ34_ECC

DDRIO154NB5/FDDR_DQ3

VDDI5

DDRIO157NB5/FDDR_DQ6

DDRIO160NB5/FDDR_DQ11

VDDI5

DDRIO164PB5/VCCC_SE1/FDDR_DQ14

DDRIO166NB5/FDDR_DQ19

VDDI5

DDRIO169NB5/FDDR_DQ22

DDRIO172NB5/FDDR_DQ27

VDDI5

DDRIO176PB5/FDDR_DQ30

DDRIO186NB5/FDDR_ADDR7

DDRIO186PB5/FDDR_ODT

VSS

DDRIO189NB5/FDDR_ADDR13

VDDI5

DDRIO178PB5/FDDR_CKE

VSS

AG2

AG3

AG4

AG5

AG6

AG7

AG8

Revision 0

4-19

Pin Descriptions

FG896

M2S050T Function

Pin Number

AG9

DDRIO147NB5/CCC_SW0_I2

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AH1

DDRIO150NB5/FDDR_DM_RDQS4_ECC

DDRIO152NB5/GB7/CCC_SW1_I2/FDDR_DQ35_ECC

DDRIO154PB5/FDDR_DQ2

DDRIO156PB5/FDDR_DM_RQDS0

DDRIO157PB5/FDDR_DQ5

DDRIO160PB5/VCCC_SE0/FDDR_DQ10

DDRIO162NB5/FDDR_DM_RQDS1

DDRIO164NB5/FDDR_DQ15

DDRIO166PB5/FDDR_DQ18

DDRIO168PB5/FDDR_DM_RQDS2

DDRIO169PB5/FDDR_DQ21

DDRIO172PB5/FDDR_DQ26

DDRIO174NB5/FDDR_DM_RQDS3

DDRIO176NB5/FDDR_DQ31

DDRIO181PB5/FDDR_BA0

DDRIO181NB5/FDDR_BA1

VDDI5

DDRIO187PB5/FDDR_ADDR8

DDRIO187NB5/FDDR_ADDR9

DDRIO190PB5/FDDR_ADDR14

DDRIO177PB5/FDDR_RAS_N

VSS

VDDI5

VSS

VDDI5

VSS

AH2

AH3

AH4

AH5

AH6

AH7

AH8

AH9

AH10

AH11

AH12

AH13

AH14

4-20

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AJ1

VSS

VDDI5

VSS

VDDI5

VSS

VDDI5

VSS

VDDI5

VSS

DDRIO183PB5/FDDR_ADDR1

VDDI5

DDRIO190NB5/FDDR_ADDR15

DDRIO177NB5/FDDR_WE_N

VSS

AJ2

PCIE_0_TXDP0

AJ3

VSS

AJ4

PCIE_0_TXDP1

AJ5

VSS

AJ6

PCIE_0_TXDP2

AJ7

VSS

AJ8

PCIE_0_TXDP3

AJ9

DDRIO148NB5/PROBE_B

DDRIO149NB5/FDDR_DQS_ECC_N

DDRIO151NB5/FDDR_DQ33_ECC

DDRIO153NB5/FDDR_DQ1

DDRIO155NB5/FDDR_DQS0_N

DDRIO158PB5/FDDR_DQ7

DDRIO159NB5/FDDR_DQ9

DDRIO161NB5/FDDR_DQS1_N

DDRIO163NB5/FDDR_DQ13

DDRIO165NB5/FDDR_DQ17

DDRIO167NB5/FDDR_DQS2_N

DDRIO170PB5/FDDR_DQ23

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

Revision 0

4-21

Pin Descriptions

FG896

M2S050T Function

Pin Number

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AK2

DDRIO171NB5/FDDR_DQ25

DDRIO173PB5/FDDR_DQS3

DDRIO175NB5/FDDR_DQ29

DDRIO179NB5/FDDR_CAS_N

DDRIO180NB5/FDDR_CLK_N

DDRIO182NB5/FDDR_ADDR0

DDRIO183NB5/FDDR_ADDR2

DDRIO188NB5/FDDR_ADDR11

DDRIO188PB5/FDDR_ADDR10

VSS

PCIE_0_TXDN0

AK3

VSS

AK4

PCIE_0_TXDN1

AK5

VSS

AK6

PCIE_0_TXDN2

AK7

VSS

AK8

PCIE_0_TXDN3

AK9

DDRIO148PB5/PROBE_A

DDRIO149PB5/FDDR_DQS_ECC

DDRIO151PB5/FDDR_DQ32_ECC

DDRIO153PB5/FDDR_DQ0

DDRIO155PB5/FDDR_DQS0

DDRIO156NB5/FDDR_DQ4

DDRIO159PB5/CCC_SW1_I3/FDDR_DQ8

DDRIO161PB5/GB11/VCCC_SE0/FDDR_DQS1

DDRIO163PB5/GB15/VCCC_SE1/FDDR_DQ12

DDRIO165PB5/FDDR_DQ16

DDRIO167PB5/FDDR_DQS2

DDRIO168NB5/FDDR_DQ20

DDRIO171PB5/FDDR_DQ24

DDRIO173NB5/FDDR_DQS3_N

DDRIO175PB5/FDDR_DQ28

DDRIO179PB5/FDDR_RST_N

DDRIO180PB5/FDDR_CLK

DDRIO182PB5/FDDR_BA2

DDRIO184PB5/FDDR_ADDR3

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

4-22

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

AK28

AK29

DDRIO184NB5/FDDR_ADDR4

VSS

PCIE_1_TXDP0

VSS

PCIE_1_TXDP1

VSS

PCIE_1_TXDP2

VSS

PCIE_1_TXDP3

DDRIO91NB0/GB4/CCC_NW1_I2

DDRIO90NB0/MDDR_DQS_ECC_N

DDRIO88NB0/MDDR_DQ33_ECC

DDRIO86NB0/MDDR_DQ1

DDRIO84NB0/MDDR_DQS0_N

DDRIO81PB0/MDDR_DQ7

DDRIO80NB0/MDDR_DQ9

DDRIO78NB0/MDDR_DQS1_N

DDRIO76NB0/MDDR_DQ13

DDRIO74NB0/MDDR_DQ17

DDRIO72NB0/MDDR_DQS2_N

DDRIO69PB0/MDDR_DQ23

DDRIO68NB0/MDDR_DQ25

DDRIO66PB0/MDDR_DQS3

DDRIO64NB0/MDDR_DQ29

DDRIO60NB0/MDDR_CAS_N

DDRIO59NB0/MDDR_CLK_N

DDRIO57NB0/MDDR_ADDR0

DDRIO56NB0/MDDR_ADDR2

DDRIO51NB0/MDDR_ADDR11

DDRIO51PB0/MDDR_ADDR10

VSS

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

VSS

Revision 0

4-23

Pin Descriptions

FG896

M2S050T Function

Pin Number

VSS

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

VDDI0

VSS

VDDI0

VSS

VDDI0

VSS

VDDI0

VSS

VDDI0

VSS

VDDI0

VSS

DDRIO56PB0/MDDR_ADDR1

VDDI0

DDRIO49NB0/MDDR_ADDR15

DDRIO62NB0/MDDR_WE_N

VSS

DDRIO92NB0/CCC_NW0_I2

DDRIO89NB0/MDDR_DM_RQDS4_ECC

D10

4-24

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

DDRIO87NB0/MDDR_DQ35_ECC

DDRIO85PB0/MDDR_DQ2

DDRIO83PB0/MDDR_DM_RQDS0

DDRIO82PB0/MDDR_DQ5

DDRIO79PB0/CCC_NE0_I2/MDDR_DQ10

DDRIO77NB0/MDDR_DM_RQDS1

DDRIO75NB0/MDDR_DQ15

DDRIO73PB0/MDDR_DQ18

DDRIO71PB0/MDDR_DM_RQDS2

DDRIO70PB0/MDDR_DQ21

DDRIO67PB0/MDDR_DQ26

DDRIO65NB0/MDDR_DM_RQDS3

DDRIO63NB0/MDDR_DQ31

DDRIO58PB0/MDDR_BA0

DDRIO58NB0/MDDR_BA1

VDDI0

DDRIO52PB0/MDDR_ADDR8

DDRIO52NB0/MDDR_ADDR9

DDRIO49PB0/MDDR_ADDR14

DDRIO62PB0/MDDR_RAS_N

MSIOD94NB9/PCIE_1_REFCLK0N

VSS

MDDR_IMP_CALIB_ECC

VDDI0

E10

E11

E12

E13

E14

E15

E16

DDRIO87PB0/CCC_NW1_I3/MDDR_DQ34_ECC

DDRIO85NB0/MDDR_DQ3

VDDI0

DDRIO82NB0/MDDR_DQ6

DDRIO79NB0/MDDR_DQ11

VDDI0

Revision 0

4-25

Pin Descriptions

FG896

M2S050T Function

Pin Number

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

DDRIO75PB0/CCC_NE1_I3/MDDR_DQ14

DDRIO73NB0/MDDR_DQ19

VDDI0

DDRIO70NB0/MDDR_DQ22

DDRIO67NB0/MDDR_DQ27

VDDI0

DDRIO63PB0/MDDR_DQ30

DDRIO53NB0/MDDR_ADDR7

DDRIO53PB0/MDDR_ODT

VSS

DDRIO50NB0/MDDR_ADDR13

VDDI0

DDRIO61PB0/MDDR_CKE

VSS

MSIOD94PB9/PCIE_1_REFCLK0P

MSIO108NB8

VSS

PCIE1VDDPLLR

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

VDDI0

DDRIO92PB0/MDDR_FIFO_WE_OUT_ECC

VSS

VDDI0

DDRIO81NB0/MDDR_FIFO_WE_OUT1

DDRIO77PB0/MDDR_FIFO_WE_IN1

VDDI0

VSS

DDRIO69NB0/MDDR_FIFO_WE_OUT3

VDDI0

VSS

DDRIO65PB0/MDDR_FIFO_WE_IN3

VDDI0

4-26

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

F23

F24

F25

F26

F27

F28

F29

F30

DDRIO54NB0/MDDR_ADDR6

DDRIO54PB0/MDDR_ADDR5

VSS

VDDI0

DDRIO50PB0/MDDR_ADDR12

VDDI0

DDRIO61NB0/MDDR_CS_N

MSIO45NB1/MMUART_0_DCD/GPIO_22_B

MSIO100NB8

MSIO95PB8

MSIO95NB8

VSS

PCIE1PLLREFRETR

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

PCIE_1_RXDP3

PCIE_1_RXDN3

DDRIO89PB0/MDDR_FIFO_WE_IN_ECC

VREF0

VSS

VREF0

VSS

FLASH_GOLDEN

Revision 0

4-27

Pin Descriptions

FG896

M2S050T Function

Pin Number

G29

G30

MSIO42NB1/MMUART_1_RXD/GPIO_26_B/USB_DATA3_C

MSIO45PB1/MMUART_0_RI/GPIO_21_B

MSIO99PB8

MSIO99NB8

VDDI8

MSIO96NB8

VSS

PCIE1VDDPLLL

PCIE1PLLREFRETL

PCIE_1_RXDP1

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

PCIE_1_RXDN1

VSS

VDD

VSS

PLL0_VDDA

PLL0_VSSA

MSIO47NB1/MMUART_0_CLK/GPIO_29_B/USB_NXT_C

MSIO46NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C

MSIO40NB1/MMUART_1_DCD/GPIO_16_B

MSIO42PB1/GB14/VCCC_SE1/MMUART_1_CLK/GPIO_25_B/USB_DATA4_C

MSIO41NB1/MMUART_1_TXD/GPIO_24_B/USB_DATA2_C

MSIO102PB8

MSIO102NB8

MSIO98PB8

MSIO98NB8

4-28

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

VSS

PCIE_1_RXDP0

PCIE_1_RXDN0

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

PCIE_1_RXDP2

PCIE_1_RXDN2

PCIE1VDD

VSS

VREF0

VSS

PLL_MDDR_VDDA

PLL_MDDR_VSSA

PLL1_VSSA

PLL1_VDDA

MSIO43NB1/MMUART_0_DTR/GPIO_18_B/USB_DATA6_C

MSIO35NB2/GPIO_6_B

MSIO38NB1/MMUART_1_DTR/GPIO_12_B

MSIO38PB1/MMUART_1_RTS/GPIO_11_B

MSIO41PB1/GB10/VCCC_SE0/USB_XCLK_C

VSS

VDDI8

MSIO101NB8

VSS

MSIO97NB8

PCIE_1_REXTL

PLL_PCIE_1_VSSA

PLL_PCIE_1_VDDA

PCIE_1_REXTR

PLL3_VDDA

K10

Revision 0

4-29

Pin Descriptions

FG896

M2S050T Function

Pin Number

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

PCIE1VDDIOL

PCIE1VDDIOR

VDDI0

VDD

VSS

MSIO48PB1/I2C_0_SDA/GPIO_30_B/USB_DATA0_C

MSIO48NB1/I2C_0_SCL/GPIO_31_B/USB_DATA1_C

MSIO44NB1/MMUART_0_DSR/GPIO_20_B

VDDI1

VSS

MSIO34NB2/GPIO_4_B

MSIO37NB2/GPIO_10_B

MSIO37PB2/GPIO_9_B

MSIO104NB8

MSIO103PB8

MSIO103NB8

MSIO113NB8

VSS

MSIOD93PB9/PCIE_1_REFCLK1P

MSIOD93NB9/PCIE_1_REFCLK1N

PCIE1VDD

PLL2_VSSA

PLL3_VSSA

VSS

L10

L11

L12

L13

L14

L15

L16

VSS

4-30

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L30

VSS

VDDI1

VDD

MSIO47PB1/MMUART_0_RXD/GPIO_28_B/USB_STP_C

VSS

VDDI1

MSIO39NB1/MMUART_1_DSR/GPIO_14_B

VDDI2

MSIO34PB2/GPIO_3_B

MSIO33NB2/GPIO_2_B

MSIO33PB2/GPIO_1_B

MSIO107PB8

MSIO107NB8

MSIO106PB8

MSIO106NB8

05NB8

VDDI8

VDDI9

MSIO97PB8

PLL2_VDDA

VDD

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

VSS

Revision 0

4-31

Pin Descriptions

FG896

M2S050T Function

Pin Number

M23

M24

M25

M26

M27

M28

M29

M30

MSIO44PB1/MMUART_0_CTS/GPIO_19_B/USB_DATA7_C

MSIO43PB1/MMUART_0_RTS/GPIO_17_B/USB_DATA5_C

MSIO40PB1/CCC_NE1_I1/MMUART_1_RI/GPIO_15_B

MSIO36NB2/GPIO_8_B

MSIO32NB2/GPIO_0_B

MSIO30NB2/USB_DATA7_D/GPIO_23_B

VSS

MSIO29NB2/USB_DATA5_D

MSIO111PB8

MSIO111NB8

MSIO110PB8

MSIO110NB8

MSIO109NB8

MSIO100PB8

MSIO96PB8

MSIO101PB8

MSIO104PB8

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

N27

N28

VDDI8

VSS

VDDI1

VDD

MSIO39PB1/CCC_NE0_I1/MMUART_1_CTS/GPIO_13_B

MSIO36PB2/GPIO_7_B

MSIO35PB2/GPIO_5_B

MSIO31NB2/GPIO_30_A

MSIO30PB2/USB_DATA6_D

MSIO29PB2/USB_DATA4_D

4-32

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

N29

N30

MSIO28NB2/USB_DATA3_D

MSIO26NB2/USB_NXT_D

MSIO115PB8/GB2/CCC_NW0_I1

MSIO115NB8

MSIO114PB8/GB6/CCC_NW1_I1

MSIO114NB8

MSIO112NB8

MSIO105PB8

MSIO108PB8

MSIO112PB8

MSIO116PB8/CCC_NW1_I0

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

VDD

VSS

VDDI2

VSS

MSIO32PB2/GPIO_31_A

MSIO31PB2/GPIO_29_A

MSIO28PB2/USB_DATA2_D

MSIO27PB2/USB_DATA0_D

MSIO27NB2/USB_DATA1_D

MSIO26PB2/USB_STP_D

MSIO25NB2/USB_DIR_D

MSIO25PB2/USB_XCLK_D

MSIOD119PB7/GB1/CCC_SW0_I1

MSIOD119NB7

MSIOD118PB7/GB5/CCC_SW1_I1

MSIOD118NB7

Revision 0

4-33

Pin Descriptions

FG896

M2S050T Function

Pin Number

MSIO116NB8

MSIO117NB8

MSIO109PB8

MSIO113PB8

MSIO117PB8/CCC_NW0_I0

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

VDDI8

VSS

VDDI2

VDD

VPP

MSIO24PB3/SPI_1_SS2/GPIO_15_A

MSIO23PB3/SPI_0_SS3/GPIO_10_A/USB_DATA7_A

VDDI2

VSS

MSIO24NB3/SPI_1_SS3/GPIO_16_A

MSIO23NB3/SPI_1_SS1/GPIO_14_A

MSIO22NB3/SPI_0_SS2/GPIO_9_A/USB_DATA6_A

MSIOD120NB7

VSS

VDDI7

MSIOD121NB7

MSIOD125NB7

MSIOD128PB7

MSIOD120PB7/CCC_SW1_I0

MSIOD124PB7

MSIOD133PB7

T10

VDD

4-34

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

VSS

VSSNVM

MSIO20PB3/GB9/VCCC_SE0/GPIO_25_A

VDDI3

MSIO21PB3/GPIO_27_A

MSIO21NB3/GPIO_28_A

MSIO20NB3/GB13/VCCC_SE1/GPIO_26_A

VPPNVM

MSIO22PB3/SPI_0_SS1/GPIO_8_A/USB_DATA5_A

MSIOD122NB7

MSIOD122PB7

MSIOD123NB7

MSIOD123PB7

MSIOD136PB7

MSIOD121PB7/CCC_SW0_I0

MSIOD125PB7

MSIOD132PB7

VDDI7

VSS

U10

U11

U12

U13

U14

U15

U16

U17

VSS

Revision 0

4-35

Pin Descriptions

FG896

M2S050T Function

Pin Number

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

VSS

VDDI3

VDD

MSIO16PB3/SPI_1_CLK

MSIO15PB3/SPI_0_SS6/GPIO_21_A

MSIO19PB3/SPI_1_SS6/GPIO_23_A

MSIO15NB3/SPI_0_SS7/GPIO_22_A

MSIO16NB3/SPI_1_SDI/GPIO_11_A

VDDI3

VSS

MSIO19NB3/SPI_1_SS7/GPIO_24_A

MSIOD127PB7

MSIOD127NB7

MSIOD126NB7

MSIOD126PB7

MSIOD130PB7

MSIOD129PB7

MSIOD144PB7

MSIOD140PB7

MSIOD145PB6/PCIE_0_REFCLK0P

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

MSIOD145NB6/PCIE_0_REFCLK0N

VSS

MSIO12PB3/SPI_0_CLK/USB_XCLK_A

MSIO11PB3/CCC_NE0_I0/I2C_1_SDA/GPIO_0_A/USB_DATA3_A

4-36

Revision 0

SmartFusion2 System-on-Chip FPGAs

FG896

M2S050T Function

Pin Number

V24

MSIO8PB3/CAN_RX/GPIO_3_A/USB_DATA1_A

V25

VPP

V26

MSIO11NB3/CCC_NE1_I0/I2C_1_SCL/GPIO_1_A/USB_DATA4_A

V27

MSIO17PB3/SPI_1_SDO/GPIO_12_A

V28

MSIO17NB3/SPI_1_SS0/GPIO_13_A

V29

MSIO18PB3/SPI_1_SS4/GPIO_17_A

V30

MSIO18NB3/SPI_1_SS5/GPIO_18_A

MSIOD128NB7

VSS

VDDI7

MSIOD132NB7

MSIOD130NB7

MSIOD133NB7

MSIOD141PB7

MSIOD137PB7

VDDI6

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

W27

W28

W29

VDDI7

VSS

VDDI3

VDD

MSIO7PB3

MSIO3PB3/USB_DATA0_B

MSIO4PB3/USB_DATA2_B

SC_SPI_SS

MSIO13PB3/SPI_0_SDO/GPIO_6_A/USB_STP_A

MSIO13NB3/SPI_0_SS0/GPIO_7_A/USB_NXT_A

MSIO14PB3/SPI_0_SS4/GPIO_19_A

Revision 0

4-37

Pin Descriptions

FG896

M2S050T Function

Pin Number

W30

MSIO14NB3/SPI_0_SS5/GPIO_20_A

MSIOD131NB7

MSIOD131PB7

VDDI7

VSS

MSIOD142NB7

MSIOD142PB7

PLL5_VSSA

PLL4_VDDA

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

PLL5_VDDA

VSS

VDDI4

MSIO0PB3

JTAG_TDI/M3_TDI

VPP

MSIO3NB3/USB_DATA1_B

VDDI3

VSS

SC_SPI_SDI

SC_SPI_SDO

MSIO12NB3/SPI_0_SDI/GPIO_5_A/USB_DIR_A

4-38

Revision 0

5 – Datasheet Information

Datasheet Categories

M2S025TS-1VFG144YES [MICROSEMI]

相关型号：

M2S025TS-1VFG144YI

M2S025TS-1VFG256I

M2S025TS-1VFG256T2

M2S025TS-FG144Y

M2S025TS-FG144YES

M2S025TS-FG144YI

M2S025TS-FGG144Y

M2S025TS-FGG144YES

M2S025TS-FGG144YI

M2S025TS-VF144Y

M2S025TS-VF144YES

M2S025TS-VF144YI