MDS113CG [MICROSEMI]
Network Interface, CMOS, PBGA456;
| 型号： | MDS113CG |
| 厂家： | 
Microsemi |
| 描述： | Network Interface, CMOS, PBGA456 局域网 电信 开关 电信集成电路 |
| 文件： | 总72页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MDS113CG
13-Port 10/100/1000 Mbps Ethernet
Distributed Switch
DS5440
ISSUE 1.0
February 2001
1 Features
Ordering Information
•
12 10/100 Mbps Autosensing, Fast Ethernet
ports with reduced MII interface and a single
Gigabit Ethernet port with GMII or TBI interface
•
•
Full wire speed Layer 2 Switching
Internal Switch Database Memory supports up
to 2k MAC addresses, up to 16K MAC
addresses, using external memory
•
•
Single Gigabit Ethernet port
Supports both GMII and integrated Physical
Coding Sublayer (TBI) logic to interface directly
with Gigabit transceivers
•
•
Automatic Source learning and age-out
Port Trunking and Load Sharing for high
bandwidth links between switches
•
•
Two-chip solution for 24+2 configuration
•
•
Full duplex Ethernet IEEE 802.3x flow control
32-bit wide bi-directional pipe at 100Mhz
provides 6.4Gbps pipe to connect two DS113
chips
Supports back-pressure flow control for half-
duplex mode
•
•
Supports up to 6.548 Mpps system throughput
using non-blocking architecture
•
•
•
Flooding and Broadcasting control
Parallel Flash interface in fast self-initialization
High performance Layer 2 packet forwarding
and filtering at full wire speed.
Port Mirroring Support
12 10/100 Mbps Autosensing, Fast Ethernet
ports with Reduced MII Interface
Flash
Control BUS
DS113
DS113
SRAM
64bit
SRAM
64bit
XPipe 32 bit
12+1
12+1
1G
1G
4x10/100
4x10/100
F
t
FastEthernet
FastEthernet
G Ethernet
G Ethernet
MDS113CG 24+2 System Configuration
Figure 1 - MDS113CG System Diagram
1
MDS113CG
•
Port Trunking and Load Sharing for high
bandwidth links between switches
Very low latency through single store and
forward at ingress port and cut-through
switching at destination ports
•
•
Full duplex Ethernet IEEE 803.2x flow control
minimizes traffic congestion
Supports back-pressure flow control for half
duplex mode
•
•
Flooding and Broadcasting control
•
On-chip address lookup engine and memory for
up to 2K MAC addresses
Link status and TX/RX activity through serial
LED interface
•
•
Up to 16K using external memory via HISC
Parallel Flash interface for fast self initialization
•
•
Port Mirroring
Packaged in 456-Pin Ball Grid Array
2
MDS113CG
2 Description
The Zarlink MDS113CG is a 13-port 10/100/1000
Mbps high-performance, non-blocking Ethernet
switch with on-chip address memory and address
lookup engine. A single chip provides 12 - 10/100
sharing can be used to group ports between inter-
linked switches for increased system bandwidth.
Ports within a trunk must reside within a single
MDS113CG, such that trunks may not be configured
across two switches.
Mbps ports and 1 - 1000 Mbps port.
The
MDS113CG is utilized in unmanaged switching
applications.
The on-chip address lookup engine supports up to
2K MAC addresses and up to 16K MAC address
using the external memory.
The 3.2 Gbps XPipe allows a high-speed connection
between two MDS113CG chips, providing an
optimal, low-cost, workgroup switch with 24 10/100
Fast Ethernet ports and 2 Gigabit Ethernet ports.
The MDS113CG utilizes cost effective, high
performance, pipelined synchronous burst RAM to
achieve full wire speed on all ports simultaneously.
Data is buffered into memory, using 0-128 byte
bursts, from the ingress ports, and transferred to an
internal transmit FIFO, before being sent from the
frame memory to the egress output ports. Extremely
high memory bandwidth is therefore achieved, which
allows each of the ports to be active without creating
a memory bottleneck.
In half-duplex mode, all ports support backpressure
flow control to minimize the risk of losing data for
long activity bursts. In full-duplex mode, IEEE
802.3x frame based flow control is used. With full-
duplex capabilities, the Fast Ethernet ports supports
200 Mbps aggregate bandwidth connections, while
the Gigabit Ethernet port supports 2 Gbps to
desktops, servers, or other high-performance
switches. The Physical Coding Sublayer (TBI) is
integrated on-chip to provide a direct 10-bit Gigabit
Media Independent Interface (GMII). The on-chip
TBI may be bypassed to provide a Ten Bit Interface
(TBI) to an existing fiber-based Gigabit Transceiver.
The MDS113CG is fabricated with 2.5 V technology,
where the inputs are 3.3V tolerant and the outputs
are capable of directly interfacing to Low-Voltage
TTL levels. The Zarlink Semiconductor MDS113CG
is packaged in a 456-pin Ball Grid Array.
The MDS113CG supports port trunking/load sharing
on the 10/100 Mbps ports.
Port trunking/load
3
MDS113CG
3 MDS113CG Block Diagram
Control BUS Interface
HISCTM
Registers
Switch
Control
Memory
2k CAM
Search Engine
SBRAM
3.2Gb/s
XpressFlowTM
Pipe
Xpipe
Engine
32
Frame Engine
Frame
Memory
Interface
Frame
Buffer
Memory
64
GMAC
Twelve
10/100 MACs
GMII/PMA
Interface
LED Xface
RMII
GMII or PMA
Figure 2 - System Block Diagram
Notes: All registers are 32-bit width
The Control Bus is 32-bits wide and the Memory Bus is 64-bits wide
The MDS113CG contains 12 Fast Ethernet Ports and 1 Gigabit Ethernet Port
The LED interface has 3 output signals (1 data and 2 control)
The XPipe is 32-bits wide
4
MDS113CG
4 Ball - Signal Description and Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X_
DCLK
O
L_
L_
L_
L_
A8
L_
A4
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
P_#
CSI
P_#
P_#
A
B
AGND
A20
A19
A11
DO29
DO25
DO20
DO16
DO13
DO8
DO5
DO2
DI29
DI25
DI21
DI17
DI12
DI8
DI4
DI2
BRGI
GNTC
RESE
RVED
RESE
RVED
L_
A18
L_
A14
L_
A10
L_
A5
X_
DO30
X_
DO26
X_
DO21
X_
DO18
X_
DO14
X_
DO10
X_
DO4
X_
DO3
X_
FCO
X_
DI28
X_
DI23
X_
DI20
X_
DI16
X_
DI11
X_
DI7
X_
DI3
X_
P_
NC
P_
NC
DCLKI #CSO
RESE
RVED
RESE
RVED
L_
A17
L_
A13
L_
A6
X_
DO31
X_
DO28
X_
DO24
X_
DO19
X_
DO15
X_
DO12
X_
DO6
X_
DO1
X_
DI31
X_
DI27
X_
DI22
X_
DI18
X_
DI14
X_
DI10
X_
DI6
X_
DNI
FS_
CS#
P_#
P_#
C
AVDD
REQC #BRDY BLAST
L_
D4
L_
D1
L_
CLK
L_
A16
L_
A12
L_
A7
L_
A3
X_
DO27
X_
DO23
X_
DO17
X_
DO11
X_
DO7
X_
DENO
X_
DI30
X_
DI24
X_
DI19
X_
DI15
X_
DI9
X_
DI5
X_
DI1
X_
FCI
P_
INT#
P_
RDY#
P_
RST#
P_
A8
D
NC
L_
D6
L_
D5
L_
D2
L_
D0
L_
A15
L_
A9
X_
DO22
X_
DO9
X_
DO0
X_
DI26
X_
DI13
X_
DI0
P_#
BRGO
P_
ADS#
P_
A10
P_
CLK
P_
A7
E
GND
VCC
VDD
VCC
GND
VCC
VDD
VCC
GND
T_
MODE
#
L_
D11
L_
D10
L_
D8
L_
D3
P_
RWC#
P_
A9
P_
A4
P_
A3
P_
A2
F
L_
L_
L_
L_
P_
A6
P_
P_
P_
G
H
VCC
L_D9
VDD
VCC
D15
D14
D13
D7
D31
D30
D29
P_
A5
P_
A1
P_
D28
P_
D26
P_
D24
L_D20 L_D18 L_D16 L_D12
L_D24 L_D23 L_D21 L_D17
P_
D27
P_
D23
P_
D21
P_
D20
J
VDD
L_
D29
L_
D27
L_
D26
L_
D22
L_
D19
P_
D25
P_
D22
P_
D19
P_
D18
P_
D16
K
L_
L_
L_
L_
P_
P_
P_
P_
L
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
WE0#
D31
D30
D28
D17
D14
D13
D12
L_
BW0#
L_
OE0#
L_
WE1#
L_
OE1#
L_
D25
P_
D15
P_
D10
P_
D11
P_
D9
P_
D8
M
N
L_
BW3#
L_
ADS#
L_
BW2#
L_
BW1#
S_
CLK
P_
D7
P_
D6
P_
D4
P_
D5
VDD
L_
BW5
L_
BW4
L_
BW7
L_
BW6
P_
D0
T_
D0
P_
D1
P_
D3
P_
D2
P
VDD
L_
D33
L_
D34
L_
D36
L_
D35
L_
D32
T_
D10
T_
D4
T_
D3
T_
D2
T_
D1
R
L_
D37
L_
D38
L_
D39
L_
D41
T_
D9
T_
D7
T_
D6
T_
D5
T
VCC
VCC
L_
D40
L_
D42
L_
D43
L_
D46
L_
D47
T_
D20
T_
D15
T_
D12
T_
D11
T_
D8
U
L_
D44
L_
D45
L_
D48
L_
D51
T_
D19
T_
D16
T_
D14
T_
D13
V
VDD
VDD
L_
L_
L_
L_
L_
PM_
T_
T_
T_
T_
W
Y
D49
D50
D52
D56
D57
DO[1]
D25
D21
D18
D17
L_
D53
L_
D54
L_
D55
L_
D61
PM_
DENO
T_
D24
T_
D23
T_
D22
VCC
VCC
L_
L_
L_
M_
M0_
M12_
LE_#
PM_
DI[1]
PM_
DI[0]
PM_
AA
AB
AC
AD
AE
AF
D58
D59
D60
CLKI
TXD0
RXD5 SYNCI
DENI
M0_
CRS_
DV
M3_
CRS_
DV
LE_
SYNC
O
L_
D62
L_
D63
M0_
TXEN
M2_
LNK
M5_
LNK
M6_
M8_
M9_
M10_
RXD1
M11_
TXD0
M12_
TXER
M_
GND
LE_#
CLKO
PM_
DO[0]
GND
VCC
VDD
VCC
GND
VCC
VDD
VCC
TXD1
TXD0
TXD1
MDC
M7_
CRS_
DV
M0_
LNK
M0_
TXD1
M0_
RXD1
M1_
TXEN
M2_
TXD1
M2_
RXD1
M3_
TXD1
M4_
LNK
M4_
RXD1
M5_
TXD0
M6_
TXEN
M7_
LNK
M8_
RXD1
M9_
TXEN
M10_
TXEN
M10_
RXD0
M11_
RXD1
M12_
TXD0
M12_
TXD3
M12_
TXD6
M12_
RXER
M12_
RXD4
M_
MDIO
LE_
DI
LE_
DO
M2_
CRS_
DV
M4_
CRS_
DV
M6_
CRS_
DV
M8_
CRS_
DV
M12_
RX
CLK
M0_
RXD0
M1_
TXD1
M2_
TXEN
M3_
TXD0
M4_
TXEN
M5_
TXD1
M5_
RXD0
M7_
TXEN
M7_
RXD1
M9_
TXD0
M9_
RXD0
M10_
TXD0
M11_
TXEN
M11_
RXD0
M12_
LNK
M12_
TXD2
M12_
TXD7
M12_
RXDV
M12_
RXD3
M12_
RXD0
NC
NC
M5_
CRS_
DV
M11_
CRS_
DV
M1_
LNK
M1_
RXD0
M2_
TXD0
M3_
LNK
M3_
RXD1
M4_
TXD1
M4_
RXD0
M6_
LNK
M6_
RXD1
M7_
TXD1
M8_
LNK
M8_
TXEN
M9_
LNK
M9_
RXD1
M10_
TXD1
M11_
LNK
M12_
M12_
TXCLK TXD1
M12_
TXD5
M12_
TXEN
M12_
RXD7
M12_
RXD1
NC
NC
25
M1_
CRS_
DV
M9_
CRS_
DV
M10_
CRS_
DV
M1_
TXD0
M1_
RXD1
M2_
RXD0
M3_
TXEN
M3_
RXD0
M4_
TXD0
M5_
TXEN
M5_
RXD1
M6_
TXD0
M6_
RXD0
M7_
TXD0
M7_
RXD0
M8_
TXD1
M8_
RXD0
M10_
LNK
M11_
TXD1
M12_
CRS
M12_
COL
M12_
TXD4
GREF
_CLK
M12_
RXD6
M12_
RXD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
VCC
VDD
GND
AVDD
AGND
NC
=
=
=
=
=
=
=
3.3VDC for I/O
2.5VDC for core logic
(16 balls)
(10 balls)
(42 balls)
(1 ball)
Digital Ground for both VCC and VDD
2.5VDC for Analog PLL
Isolated Analog Ground for AVDD
No connection
(1 ball)
Reserved
DO NOT CONNECT
5
MDS113CG
Power and Ground Distribution
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X_
DCLK
O
L_
L_
L_
L_
A8
L_
A4
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
X_
P_#
CSI
P_#
P_#
A
B
AGND
A20
A19
A11
DO29
DO25
DO20
DO16
DO13
DO8
DO5
DO2
DI29
DI25
DI21
DI17
DI12
DI8
DI4
DI2
BRGI
GNTC
RESE
RVED
RESE
RVED
L_
A18
L_
A14
L_
A10
L_
A5
X_
DO30
X_
DO26
X_
DO21
X_
DO18
X_
DO14
X_
DO10
X_
DO4
X_
DO3
X_
FCO
X_
DI28
X_
DI23
X_
DI20
X_
DI16
X_
DI11
X_
DI7
X_
DI3
X_
P_
NC
P_
NC
DCLKI #CSO
RESE
RVED
RESE
RVED
L_
A17
L_
A13
L_
A6
X_
DO31
X_
DO28
X_
DO24
X_
DO19
X_
DO15
X_
DO12
X_
DO6
X_
DO1
X_
DI31
X_
DI27
X_
DI22
X_
DI18
X_
DI14
X_
DI10
X_
DI6
X_
DNI
FS_
CS#
P_#
P_#
C
AVDD
REQC #BRDY BLAST
L_
D4
L_
D1
L_
CLK
L_
A16
L_
A12
L_
A7
L_
A3
X_
DO27
X_
DO23
X_
DO17
X_
DO11
X_
DO7
X_
DENO
X_
DI30
X_
DI24
X_
DI19
X_
DI15
X_
DI9
X_
DI5
X_
DI1
X_
FCI
P_
INT#
P_
RDY#
P_
RST#
P_
A8
D
NC
L_
D6
L_
D5
L_
D2
L_
D0
L_
A15
L_
A9
X_
DO22
X_
DO9
X_
DO0
X_
DI26
X_
DI13
X_
DI0
P_#
BRGO
P_
ADS#
P_
A10
P_
CLK
P_
A7
E
GND
VCC
VDD
VCC
GND
VCC
VDD
VCC
GND
T_
MODE
#
L_
D11
L_
D10
L_
D8
L_
D3
P_
RWC#
P_
A9
P_
A4
P_
A3
P_
A2
F
L_
L_
L_
L_
P_
A6
P_
P_
P_
G
H
VCC
L_D9
VDD
VCC
D15
D14
D13
D7
D31
D30
D29
P_
A5
P_
A1
P_
D28
P_
D26
P_
D24
L_D20 L_D18 L_D16 L_D12
L_D24 L_D23 L_D21 L_D17
P_
D27
P_
D23
P_
D21
P_
D20
J
VDD
L_
D29
L_
D27
L_
D26
L_
D22
L_
D19
P_
D25
P_
D22
P_
D19
P_
D18
P_
D16
K
L_
L_
L_
L_
P_
P_
P_
P_
L
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
WE0#
D31
D30
D28
D17
D14
D13
D12
L_
BW0#
L_
OE0#
L_
WE1#
L_
OE1#
L_
D25
P_
D15
P_
D10
P_
D11
P_
D9
P_
D8
M
N
L_
BW3#
L_
ADS#
L_
BW2#
L_
BW1#
S_
CLK
P_
D7
P_
D6
P_
D4
P_
D5
VDD
L_
BW5
L_
BW4
L_
BW7
L_
BW6
P_
D0
T_
D0
P_
D1
P_
D3
P_
D2
P
VDD
L_
D33
L_
D34
L_
D36
L_
D35
L_
D32
T_
D10
T_
D4
T_
D3
T_
D2
T_
D1
R
L_
D37
L_
D38
L_
D39
L_
D41
T_
D9
T_
D7
T_
D6
T_
D5
T
VCC
VCC
L_
D40
L_
D42
L_
D43
L_
D46
L_
D47
T_
D20
T_
D15
T_
D12
T_
D11
T_
D8
U
L_
D44
L_
D45
L_
D48
L_
D51
T_
D19
T_
D16
T_
D14
T_
D13
V
VDD
VDD
L_
L_
L_
L_
L_
PM_
T_
T_
T_
T_
W
Y
D49
D50
D52
D56
D57
DO[1]
D25
D21
D18
D17
L_
D53
L_
D54
L_
D55
L_
D61
PM_
DENO
T_
D24
T_
D23
T_
D22
VCC
VCC
L_
L_
L_
M_
M0_
M12_
LE_#
PM_
DI[1]
PM_
DI[0]
PM_
AA
AB
AC
AD
AE
AF
D58
D59
D60
CLKI
TXD0
RXD5 SYNCI
DENI
M0_
CRS_
DV
M3_
CRS_
DV
LE_
SYNC
O
L_
D62
L_
D63
M0_
TXEN
M2_
LNK
M5_
LNK
M6_
M8_
M9_
M10_
RXD1
M11_
TXD0
M12_
TXER
M_
GND
LE_#
CLKO
PM_
DO[0]
GND
VCC
VDD
VCC
GND
VCC
VDD
VCC
TXD1
TXD0
TXD1
MDC
M7_
CRS_
DV
M0_
LNK
M0_
TXD1
M0_
RXD1
M1_
TXEN
M2_
TXD1
M2_
RXD1
M3_
TXD1
M4_
LNK
M4_
RXD1
M5_
TXD0
M6_
TXEN
M7_
LNK
M8_
RXD1
M9_
TXEN
M10_
TXEN
M10_
RXD0
M11_
RXD1
M12_
TXD0
M12_
TXD3
M12_
TXD6
M12_
RXER
M12_
RXD4
M_
MDIO
LE_
DI
LE_
DO
M2_
CRS_
DV
M4_
CRS_
DV
M6_
CRS_
DV
M8_
CRS_
DV
M12_
RX
CLK
M0_
RXD0
M1_
TXD1
M2_
TXEN
M3_
TXD0
M4_
TXEN
M5_
TXD1
M5_
RXD0
M7_
TXEN
M7_
RXD1
M9_
TXD0
M9_
RXD0
M10_
TXD0
M11_
TXEN
M11_
RXD0
M12_
LNK
M12_
TXD2
M12_
TXD7
M12_
RXDV
M12_
RXD3
M12_
RXD0
NC
NC
M5_
CRS_
DV
M11_
CRS_
DV
M1_
LNK
M1_
RXD0
M2_
TXD0
M3_
LNK
M3_
RXD1
M4_
TXD1
M4_
RXD0
M6_
LNK
M6_
RXD1
M7_
TXD1
M8_
LNK
M8_
TXEN
M9_
LNK
M9_
RXD1
M10_
TXD1
M11_
LNK
M12_
M12_
TXCLK TXD1
M12_
TXD5
M12_
TXEN
M12_
RXD7
M12_
RXD1
NC
NC
25
M1_
CRS_
DV
M9_
CRS_
DV
M10_
CRS_
DV
M1_
TXD0
M1_
RXD1
M2_
RXD0
M3_
TXEN
M3_
RXD0
M4_
TXD0
M5_
TXEN
M5_
RXD1
M6_
TXD0
M6_
RXD0
M7_
TXD0
M7_
RXD0
M8_
TXD1
M8_
RXD0
M10_
LNK
M11_
TXD1
M12_
CRS
M12_
COL
M12_
TXD4
GREF
_CLK
M12_
RXD6
M12_
RXD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
VCC
VDD
GND
AVDD
AGND
NC
=
=
=
=
=
=
=
3.3VDC for I/O
2.5VDC for core logic
(16 balls)
(10 balls)
(42 balls)
(1 ball)
Digital Ground for both VCC and VDD
2.5VDC for Analog PLL
Isolated Analog Ground for AVDD
No connection
(1 ball)
Reserved
DO NOT CONNECT
6
MDS113CG
Ball - Signal Assignments
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Ball
No.
Signal Name
D4
C3
A1
B1
C1
F5
C2
D3
E4
D2
E3
F4
D1
E2
E1
G4
F3
H5
F2
F1
H4
G3
G2
G1
H3
J4
NC
R2
L_D34
AC7
M3_TXD1
M3_TXD0
M3_CRS_DV
M3_RXD1
M3_RXD0
M4_LNK
AF19
AB19
AE19
AC18
AD19
AF20
AE20
AD20
AC19
AF21
AE21
AD21
AC20
AF22
AE22
AF23
AC21
AD22
AE23
AB21
AC22
AD23
AE24
AF24
AF25
AE25
AA22
AC23
AD24
AF26
AE26
AD26
AD25
AC24
AB23
AC25
AB24
AA23
AC26
AB25
W22
M11_TXD1
RESERVED
AGND
R4
L_D35
AD6
M11_TXD0
R3
L_D36
AB8
M11_CRS_DV
RESERVED
AVDD
T1
L_D37
AE6
M11_RXD1
T2
L_D38
AF6
M11_RXD0
T_MODE#
RESERVED
L_CLK
L_D0
T3
L_D39
AC8
M12_CRS
U1
L_D40
AD7
M4_TXEN
M4_TXD1
M4_TXD0
M4_CRS_DV
M4_RXD1
M4_RXD0
M5_LNK
M12_TXCLK / GP_TXCLK
M12_LNK / GP_LNK
M12_TXD0 / GP_TXD9
M12_COL / GP_RXCLK1
M12_TXD1 / GP_TXD8
M12_TXD2 / GP_TXD7
M12_TXD3 / GP_TXD6
M12_TXD4 / GP_TXD5
M12_TXD5 / GP_TXD4
GREF_CLK
T4
L_D41
AE7
U2
L_D42
AF7
L_D1
U3
L_D43
AD8
L_D2
V1
L_D44
AC9
L_D3
V2
L_D45
AE8
L_D4
U4
L_D46
AB10
AF8
L_D5
U5
L_D47
M5_TXEN
M5_TXD1
M5_TXD0
M5_CRS_DV
M5_RXD1
M5_RXD0
M6_LNK
L_D6
V3
L_D48
AD9
L_D7
W1
W2
V4
L_D49
AC10
AE9
L_D8
L_D50
M12_TXD6 / GP_TXD3
M12_TXD7 / GP_TXD2
M12_TX_EN / GP_TXD1
M12_TX_ER / GP_TXD0
M12_RX_ER / GP_RXD0
M12_RX_DV / GP_RXD1
M12_RXD7 / GP_RXD2
M12_RXD6 / GP_RXD3
NC
L_D9
L_D51
AF9
L_D10
L_D11
L_D12
L_D13
L_D14
L_D15
L_D16
L_D17
L_D18
L_D19
L_D20
L_D21
L_D22
L_D23
L_D24
L_D25
L_D26
L_D27
L_D28
L_D29
L_D30
L_D31
L_WE0#
L_OE0#
L_WE1#
L_OE1#
L_BW0#
L_BW1#
S_CLK
L_BW2#
L_BW3#
L_ADS#
L_BW4#
L_BW5#
L_BW6#
L_BW7#
L_D32
L_D33
W3
Y1
L_D52
AD10
AE10
AC11
AB12
AF10
AD11
AE11
AF11
AC12
AD12
AE12
AF12
AC13
AD13
AF13
AE13
AE14
AF14
AB13
AD14
AC14
AF15
AE15
AC15
AB15
AD15
AF16
AE16
AD16
AF17
AC16
AE17
AD17
AF18
AB17
AC17
AE18
AD18
L_D53
Y2
L_D54
M6_TXEN
M6_TXD1
M6_TXD0
M6_CRS_DV
M6_RXD1
M6_RXD0
M7_LNK
Y3
L_D55
W4
W5
AA1
AA2
AA3
Y4
L_D56
L_D57
L_D58
L_D59
NC
H2
K5
H1
J3
L_D60
M12_RXD5 / GP_RXD4
M12_RXD4 / GP_RXD5
M12_RXD3 / GP_RXD6
M12_RXD2 / GP_RXD7
M12_RXD1 / GP_RXD8
M12_RXD0 / GP_RXD9
M12_RXCLK / GP_RXCLK0
M_MDIO
L_D61
M7_TXEN
M7_TXD1
M7_TXD0
M7_CRS_DV
M7_RXD1
M7_RXD0
M8_LNK
AB1
AB2
AC1
AA4
AB3
AC2
AA5
AB4
AC3
AD2
AD1
AE1
AE2
AC4
AD3
AF1
AF2
AF3
AE3
AB6
AD4
AC5
AE4
AD5
AC6
AF4
AE5
AF5
L_D62
L_D63
K4
J2
M0_LNK
M_CLKI
M0_TXEN
M0_TXD1
M0_TXD0
M0_CRS_DV
M0_RXD1
M0_RXD0
NC
J1
M5
K3
K2
L4
M8_TXEN
M8_TXD1
M8_TXD0
M8_CRS_DV
M8_RXD1
M8_RXD0
M9_LNK
M_MDC
LE_DI
LE_CLKO
K1
L3
LE_SYNCI
LE_DO
L2
NC
LE_SYNCO
L1
M1_LNK
M1_TXEN
M1_TXD1
M1_TXD0
M1_CRS_DV
M1_RXD1
M1_RXD0
M2_LNK
M2_TXEN
M2_TXD1
M2_TXD0
M2_CRS_DV
M2_RXD1
M2_RXD0
M3_LNK
M3_TXEN
T_D31/PM_DO1
T_D30/PM_DO0
T_D29/PM_DENO
T_D28/PM_DI1
T_D27/PM_DI0
T_D26/PM_DENI
T_D25
M2
M3
M4
M1
N4
N5
N3
N1
N2
P2
P1
P4
P3
R5
R1
M9_TXEN
M9_TXD1
M9_TXD0
M9_CRS_DV
M9_RXD1
M9_RXD0
M10_LNK
M10_TXEN
M10_TXD1
M10_TXD0
M10_CRS_DV
M10_RXD1
M10_RXD0
M11_LNK
M11_TXEN
AB26
Y23
AA24
AA25
AA26
W23
Y24
T_D24
Y25
T_D23
Y26
T_D22
W24
T_D21
U22
T_D20
V23
T_D19
W25
T_D18
W26
T_D17
V24
T_D16
7
MDS113CG
Ball
Ball
No.
Ball
No.
Ball
No.
Signal Name
No.
Signal Name
Signal Name
Signal Name
U23
V25
V26
U24
U25
R22
T23
U26
T24
T25
T26
R23
R24
R25
R26
P23
P22
P24
P26
P25
N25
N26
N24
N23
M26
M25
M23
M24
L26
L25
L24
M22
K26
L23
K25
K24
J26
T_D15
T_D14
E24
D25
F22
E23
D24
C25
C26
B26
B25
D23
C24
A26
A25
E21
A24
B24
C23
D22
B23
C22
E19
D21
A23
B22
A22
D20
C21
B21
A21
D19
C20
B20
A20
E17
C19
D18
B19
A19
C18
D17
B18
A18
C17
B17
D16
A17
E15
C16
B16
A16
D15
C15
B15
A15
D14
E14
C14
A14
P_A10 / FS_A10
P_RST#
P_RWC#
P_ADS#
P_RDY#
P_BRDY#
P_BLAST#
NC
B14
B13
A13
C13
D13
A12
E12
B12
D12
C12
A11
B11
C11
A10
D11
B10
C10
A9
X_DO3
X_DO4
X_DO5
X_DO6
X_DO7
X_DO8
X_DO9
X_DO10
X_DO11
X_DO12
X_DO13
X_DO14
X_DO15
X_DO16
X_DO17
X_DO18
X_DO19
X_DO20
X_DO21
X_DO22
X_DO23
X_DO24
X_DO25
X_DO26
X_DO27
X_DO28
X_DO29
X_DO30
X_DO31
L_A3
Y5
Y22
AB7
AB11
AB16
AB20
E9
VCC
VCC
VCC
VCC
VCC
VCC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T_D13
T_D12
T_D11
T_D10
T_D9
T_D8
E18
J5
T_D7
NC
T_D6
P_INT
J22
T_D5
P_REQC#
P_GNTC#
P_BRQI#
P_BRQO#
P_CSI#
P_CSO#
FLS_CS#
X_FCI
N22
P5
T_D4/BS_RDYOP
T_D3/BS_PSD
T_D2/BS_SWM
T_D1/BS_RW
T_D0/BS_BMOD
P_D0 / FS_D0
P_D1 / FS_D1
P_D2 / FS_D2
P_D3 / FS_D3
P_D4 / FS_D4
P_D5 / FS_D5
P_D6 / FS_D6
P_D7 / FS_D7
P_D8 / FS_D8
P_D9 / FS_D9
P_D10 / FS_D10
P_D11 / FS_D11
P_D12 / FS_D12
P_D13 / FS_D13
P_D14 / FS_D14
P_D15 / FS_D15
P_D16
V5
V22
AB9
AB18
E5
E13
E22
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16
AB5
AB14
AB22
X_DCLKI
X_DNI
B9
E10
D10
C9
X_DI0
X_DI1
X_DI2
A8
X_DI3
B8
X_DI4
D9
X_DI5
C8
X_DI6
A7
X_DI7
B7
X_DI8
C7
X_DI9
D8
X_DI10
X_DI11
X_DI12
X_DI13
X_DI14
X_DI15
X_DI16
X_DI17
X_DI18
X_DI19
X_DI20
X_DI21
X_DI22
X_DI23
X_DI24
X_DI25
X_DI26
X_DI27
X_DI28
X_DI29
X_DI30
X_DI31
X_FCO
X_DCLKO
X_DENO
X_DO0
X_DO1
X_DO2
A6
L_A4
B6
L_A5
C6
L_A6
P_D17
D7
L_A7
P_D18
A5
L_A8
P_D19
E8
L_A9
P_D20
B5
L_A10
L_A11
L_A12
L_A13
L_A14
L_A15
L_A16
L_A17
L_A18
L_A19
L_A20
RESERVED
VCC
J25
P_D21
A4
K23
J24
P_D22
D6
P_D23
C5
H26
K22
H25
J23
P_D24 / FS_A11
P_D25 / FS_A12
P_D26 / FS_A13
P_D27 / FS_A14
P_D28 / FS_A15
P_D29 / FS_A16
P_D30 / FS_A17
P_D31 / FS_A18
P_A1 / FS_A1
P_A2 / FS_A2
P_A3 / FS_A3
P_A4 / FS_A4
P_A5 / FS_A5
P_A6 / FS_A6
P_A7 / FS_A7
P_CLK
B4
E6
D5
C4
H24
G26
G25
G24
H23
F26
F25
F24
H22
G23
E26
E25
D26
F23
B3
A3
A2
B2
E7
E11
E16
E20
G5
VCC
VCC
VCC
VCC
G22
L5
VCC
VCC
L22
T5
VCC
P_A8 / FS_A8
P_A9 / FS_A9
VCC
T22
VCC
8
MDS113CG
Ball - Signal Descriptions
The Type of All pins is CMOS.
All Input pins are 5-Volt Tolerance.
All Output Pins are 3.3 CMOS Drive
CONTROL BUS INTERFACE
Ball No(s)
Symbol
I/O
Description
G24, G25, G26, H24,
J23, H25, K22, H26,
J24, k23, J25, J26,
K24, K25, L23, K26,
M22, L24, L25, L26,
M24, M23, M25, M26,
N23, N24, N26, N25,
P25, P26, P24, P22
P_D[31:0]
I/O-TS, U
Control Data Bus- Data Bit[31:0]
E24, F23, D26, E26,
G23, H22, F24, F25,
F26, H23
P_A[10:1]
Input/
Output-U
Control Address Bus-Address Bit[14: 1]
D25
F22
P_RST#
P_RWC#
Input-ST
Control Bus – Master Reset
Input/Output-
TS, U
Control Bus – Read/Write Control
Programmable polarity
Control Address Strobe
E23
D24
P_ADS#
P_RDY#
Input/Output-
TS, U
Output-OD-
TS, U
Control Bus – Data Ready
E23
C26
D23
P_BRDY#
P_BLAST#
P_INT
Input- TS, U
Input- TS, U
Output
Control Bus – Burst Ready
Control Bus – Burst Last
Control Bus – Interrupt Request
Programmable polarity
Control Bus – Bus Clock
E25
C24
A26
A25
P_CLK
Input
Input
Output
Input
P_REQC#
P_GNTC#
P_BRGI#
Control Bus Request from CPU: Used for debug purpose
Control BUS Grant to CPU: Used for debug purpose
Control Bus Request/Grant Input:
At Primary Device, it receives process bus Request signal
At Secondary Device, it receives process bus Grant signal
Control Bus Request/Grant Output:
E21
P_BRGO#
Output
At Primary Device, it sends process bus Grant signal
At Secondary Device, it sends process bus Request signal
Chip Select: Input
A24
B24
P_CSI#
Input- U
Output
P_CSO#
Chip Select: Output
Note that the primary or secondary device is determined by bootstrap pin, BS_PSD.
NOTES:
#
=
=
=
=
=
=
=
=
=
=
Active low signal
Input signal
Input
In-ST
Output
Out-OD
I/O-TS
I/O-OD
U
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Internal weak pull-up
TS
ST
Tri-state
Schmitt-Trigger
9
MDS113CG
Flash BUS INTERFACE: used for initialization
Ball No(s)
Symbol
I/O
Description
M22, L24, L25, L26, M24, M23, M25,
M26, N23, N24, N26, N25, P25, P26,
P24, P22
FS_D[15:0]
I/O-TS
Flash Data Bit[15:0]
Share with P_D[15:0]
G24, G25, G26, H24, J23, H25, K22,
H26,E24, F23, D26, E26, G23, H22,
F24, F25, F26, H23
FS_A[18:1]
FS_CS
Input /Output
Output
Flash Address Bit[18:1]
share with P_A[10:1] and P_D[31:24]
C23
Flash Memory Chip Select
Frame Buffer Interface
Ball No(s)
Symbol
I/O
Description
AB2, AB1, Y4, AA3, AA2, AA1, W5, W4,
Y3, Y2, Y1, W3, V4, W2, W1, V3, U5,
U4, V2, V1, U3, U2, T4, U1, T3, T2, T1,
R4, R3, R2, R1, R5, L2, L3, K1, L4, K2,
K3, M5, J1, J2, K4, J3, H1, K5, H2, J4,
H3, G1, G2, G3, H4, F1, F2, H5, F3,
G4, E1, E2, D1, F4, E3, D2, E4.
L_D[63:0]
I/O-TS, U
Frame Buffer – Data Bit[63:0]
A2, A3, B3, C4, D5, E6, C5, D6, A4, B5,
E8, A5, D7, C6, B6, A6, D8.
L_A[20:3]
Output
Frame Buffer – Address Bit[20:3]
D3
L_CLK
Output
Output
Output
Output
Output
Frame Buffer Clock
N2
L_ADS#
Frame Buffer Address Status Control
Frame Buffer Individual Byte Write Enable[7:0]
Frame Buffer Write Chip Select[1:0]
Frame Buffer Read Chip Select[1:0]
P3, P4, P1, P2, N1, N3, N4, M1
L_BW[7:0]#
L_WE[1:0]#
L_OE[1:0]#
M3, L1
M4, M2
BALL NO(S)
RMII Ethernet Access Ports[11:0]
AB23
M_MDC
Output
MII Management Data Clock – (Common for all MII
Ports[12:0])
AB24
AA4
M_MDIO
IO-TS
MII Management Data I/O – (Common for all MII
Ports[12:0])
M_CLKI
Input
Reference Input Clock
AC18, AB17, AE16, AC14, AD13, AE11,
AF9, AC9, AE6, AC6, AF3, AC3.
M[11:0]_RXD[1]
Input- U
Ports[11:0] – Receive Data Bit[1]
AD19, AC17, AD16, AF15, AF13, AF11,
AD10, AE8, AF6, AF4, AE3, AD2.
M[11:0]_RXD[0]
Input- U
Input- U
Output
Ports[11:0] – Receive Data Bit[0]
Ports[11:0] – Carrier Sense and Receive Data Valid
Ports[11:0] – Transmit Enable
AE19, AF18, AF16, AD14, AC13, AD11,
AE9, AD8, AB8, AD5, AF2, AB4.
M[11:0]_CRS_D
V
AD18, AC16, AC15, AE14, AD12, AC11,
AF8, AD7, AF5, AD4, AC4, AB3.
M[11:0]_TXEN
M[11:0]_TXD[1]
M[11:0]_TXD[0]
M[11:0]_LNK
AF19, AE17, AB15, AF14, AE12, AB12,
AD9, AE7, AC7, AC5, AD3, AC2.
Output
Ports[11:0] – Transmit Data Bit[1]
Ports[11:0] – Transmit Data Bit[0]
Ports[11:0] -- Link Status
AB19, AD17, AD15, AB13, AF12, AF10,
AC10, AF7, AD6, AE4, AF1, AA5.
Output
AE18, AF17, AE15, AE13, AC12, AE10,
AB10, AC8, AE5, AB6, AE2, AC1.
Input- ST, U
10
MDS113CG
BALL NO(S)
GMII Gigabit Ethernet Access Port[12]
AE24, AF24, AA22, AC23,
AD24, AF26, AE26, AD26
M[12]_RXD[7:0]
Input- U
Port[12] -- Receive Data Bit[7:0]
AD23
AC22
AF20
AF21
AD25
M[12]_RX_DV
M[12]_RX_ER
M[12]_CRS
Input- U
Input- U
Input- U
Input- U
Input- U
Output
Port[12] -- Receive Data Valid
Port[12] -- Receive Error
Port[12] – Carrier Sense
M[12]_COL
Port[12] – Collision Detected
Port[12] – Receive Clock
M[12]_RXCLK
M[12]_TXD[7:0]
AD22, AC21, AE22, AF22,
AC20, AD21, AE21, AC19.
Port[12] -- Transmit Data Bit[7:0]
AE23
AB21
AE20
AD20
AF23
M[12]_TX_EN
M[12]_TX_ER
M[12]_ TXCLK
M[12]_LNK
Output
Port[12] -- Transmit Data Enable
Port[12] -- Transmit Error
Output
Output
Port[12] – Gigabit Transmit Clock
Port[12]-- :Link Status
Input-ST, U
Input- U
GREF_CLK
Port[12] – Gigabit Reference Clock
BALL NO(S)
PCS (TBI) Interface Gigabit Ethernet Access Port[12]
AD26, AE26, AF26, AD24,
AC23, AA22,AF24, AE24,
AD23, AC22,
GP_RXD[9:0]
Input- U
Port[12] – PCS Receive Data Bit[9:0]
AF21
AD25
GP_RXCLK1
GP_RXCLK0
GP_TXD[9:0]
Input- U
Input- U
Output
Port[12] – PCS Receive Clock 1
Port[12] – PCS Receive Clock 0
AC19, AE21, AD21, AC20,
AF22, AE22, AC21, AD22,
AE23, AB21
Port[12] – PCS Transmit Data Bit[9:0]
AE20
AD20
AF23
GP_TXCLK
GP_LNK
Output
Port[12] – PCS Gigabit Transmit Clock
Port[12] – PCS Link Status
Input- ST, U
Input – U
GREF_CLK
Port[12] – PCS Gigabit Reference Clock
11
MDS113CG
XPipe Interface
I/O
Function
B23
C22
D22
X_DCLKI
X_DENI
X_FCI
Input
Input
Input
Input
Xpipe Data Clock Input
Xpipe Data Enable Input
Xpipe Flow Control Input
Xpipe Data Input Bits[31:0]
C15, D15, A16, B16, C16, E15, A17, D16,
B17, C17, A18, B18, D17, C18, A19, B19,
D18, C19, E17, A20, B20, C20, D19, A21,
B21, C21, D20, A22, B22, A23, D21, E19.
X_DI[31:0]
A15
B15
D14
X_DCLKO
X_FCO
Output
Output
Output
Output
Xpipe Data Clock Output
Xpipe Flow Control Output
Xpipe Data Enable Output
Xpipe Data Output Bit[31:0]
X_DENO
X_DO[31:0]
C7, B7, A7, C8, D9, B8, A8, C9, D10, E10,
B9, A9, C10, B10, D11, A10, C11, B11,
A11, C12, D12, B12, E12, A12, D13, C13,
A13, B13, B14, A14, C14, E14.
Port Mirroring
AA26
PM_DENI
Input- TS, U
Input- TS, U
Output
Port Mirroring Data Enable Input
Port Mirroring Input Data Bit[1:0]
Port Mirroring Data Enable Output
Port Mirroring Output Data Bit[1:0]
AA25, AA24
Y23
PM_DI[1:0]
PM_DENO
PM_DO[1:0]
AB26, W22
Output
TEST FACILITY
Use for debug purpose
F5
T_MODE#
IO-TS, U
Test Pin – Set Mode upon Reset, and provides test
status output
W22, AB26, Y23, AA24, AA25, AA26, W23,
Y24, Y25, Y26, W24, U22, V23, W25, W26,
V24, U23, V25, V26, U24, U25, R22, T23,
U26, T24, T25, T26, R23, R24, R25, R26,
P23
T_D[31:0]
Output
Test Output
LED Interface
AC25
AA23
AB24
AC26
AB25
LE_DI
Input- U
Input- U
Output
Output
Output
LED Serial Data Input Stream
LED Input Data Stream Envelop
LED Serial Interface Output Clock
LED Serial Data Output Stream
LED Output Data Stream Envelop
LE_SYNCI#
LE_CLKO
LE_DO
LE_SYNCO#
12
MDS113CG
System Clock, Power, and Ground Pins
N5
S_CLK
VDD
Input
System Clock at 100 MHz
+2.5 Volt DC Supply
E9, E18, J5, J22, N22,
P5, V5, V22, AB9,
AB18
Power
E7, E11, E16, E20,
G22, L22, T22, Y22,
AB20, AB16, AB11,
AB7, Y5, T5, L5, G5
VCC
VSS
Power
+3.3 Volt DC Supply
Ground
E5, E13, E22, L11,
L12, L13, L14, L15,
L16, M11, M12, M13,
M14, M15, M16, N11,
N12, N13, N14, N15,
N16, P11, P12, P13,
P14, P15, P16, R11,
R12, R13, R14, R15,
R16, T11, T12, T13,
T14, T15, T16, AB5,
AB14, AB22
Power Ground
C1, C1
A1, A1
AVDD[1:0]
AVSS[1:0]
Analog Power
Used for the PLL
Used for the PLL
Analog
Ground
Bootstrap Pins
P23
BS_BMOD
BS_RW
Input
Input
Input
Input
Control Bus mode
MUST BE SET TO 0
R26
R24
R23
Control Bus Read/Write Control Polarity Selection Default=1
0=R/W# ; 1=W/R#
Primary Device Enable Pin Default=1
0=Secondary 1=Primary
Option of merge the RDY_ and B_RDY as one pin Default=1
0=Merged pin 1=Separated pins
BS_PSD
BS_RDYOP
NOTES:
#
=
=
=
=
=
=
=
=
=
=
Active low signal
Input signal
Input
In-ST
Output
Out-OD
I/O-TS
I/O-OD
U
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Internal weak pull-up
TS
ST
Tri-state
Schmitt-Trigger
13
MDS113CG
5 The Media Access Control (MAC)
The MDS113CG MAC/GMAC contains twelve Fast
Ethernet MACs and one Gigabit Ethernet MAC,
defined by the IEEE Standard 802.3 CSMA/CD.
Each Fast Ethernet MAC is connected to a Physical
Layer (PHY) via the Reduced Media Independent
Interface (RMII), and the Gigabit Ethernet MAC is
The Inter-frame Gap
The Inter-Frame Gap (IFG), defined as 96 bit times,
is the interval between successive Ethernet frames
for the MAC/GMAC. Depending on traffic conditions,
the measurement reference for the IFG changes. If a
frame is successfully transmitted without a collision,
the IFG measurement starts from the assertion of
the Transmit Enable (TXEN) signal. However, if a
frame suffers a collision, the IFG measurement
starts from the deassertion of the Carrier Sense
(CRS) signal.
connected to
a
PHY via the Gigabit Media
Independent Interface (GMII) or the Ten Bit Interface
(TBI). The MAC/GMAC sublayer consists of a
Transmit and Receive section and is responsible for
data encapsulation/decapsulation.
Data encapsulation/decapsulation involves framing
(frame alignment and frame synchronization),
handling source and destination addresses, and
detecting physical medium transmission errors. The
MAC/GMAC also manages half-duplex collisions,
including collision avoidance and contention
resolution (collision handling). The MDS113CG
includes an optional MAC Control sublayer ("MAC
Control") used for IEEE Flow Control functions.
Ethernet Frame Limits
A legal Ethernet frame size, defined by the IEEE
specification, must be between 64 and 1518 bytes,
referring to the packet length on the wire. For frames
whose data lengths do not meet the minimum
requirements, the MAC/GMAC appends extra bytes
(padding) from the PAD field. Frames, longer than
the maximum length may either be forwarded or
discarded, depending on the register configuration.
The maximum frame size is 1518 bytes without
VLAN tag and 1522 bytes with VLAN tag.
During frame transmission, the MAC transmit section
encapsulates the data by prepending a preamble
and a Start of Frame Delimiter (SFD), inserts a
destination and source address, and appends the
Frame Check Sequence (FCS) for error detection.
Collision and Avoidance
During frame reception, the MAC receive section
verifies that the CRC is valid, de-serializes the data,
and buffers the frame into the Receive FIFO. The
MAC/GMAC then signals the Frame Engine, using
Receive Direct Memory Access (RxDMA), that data
is available in the FIFO and is ready for storage.
When necessary, the MAC/GMAC regenerates the
Frame Check Sequence and performs "padding" for
frames less than 64 bytes.
If multiple stations on the same network attempt to
transmit at the same time, interference could occur
causing a collision. The MAC/GMAC monitors the
Carrier Sense (CRS) signal to determine if the
medium is available before attempting to transmit
data. If the transmission medium is busy, the MAC/
GMAC defers (delays) its own transmissions to
decrease the load on the network. This is called
collision avoidance.
MAC/GMAC Configuration
If a collision occurs, after the first 64 bytes of data,
the MAC/GMAC ceases data transmission and sends
the jam sequence to notify all connected nodes of a
collision. This jam sequence will persist for 32 bit
times. The jam sequence is a 32 bit predetermined
pattern used to notify others of a collision on the
network.
MAC/GMAC operations are configured through the
global Device Configuration Register (DCR2) and/or
the MAC/GMAC Control and Configuration Registers
(ECR1), defined in the Register Definition Section of
the MDS113CG Datasheet. The default settings for
autonegotiation, flow control, frame length, and
duplex mode may be changed and configured by the
user on a per-port basis, either in hardware or
software.
If a collision occurs during preamble generation, or
within the first 64 bytes, the transmitter waits until the
preamble is completed and then "backsoff" (that is,
stops transmitting) for a specific period (defined by
the IEEE 802.3 Binary Exponential Backoff
Algorithm) before sending the jam sequence and
rescheduling transmission. A frame with a size of no
14
MDS113CG
less than 96 bits (64 bits of preamble and 32 bits of
jam pattern), is sent to guarantee that the duration of
the collision is long enough to be detected by the
transmitting ports involved.
MDS113CG initiates the flow control mechanism
appropriate to the current mode of operation.
Setting the Flow Control (FC_Enable) bit in the MAC
Port Configuration Register (ERC1) turns this
operation on, thereby initiating PAUSE frames or
applying backpressure flow control when necessary.
Autonegotiation
Collision-BasedFlow Control
The default value of the MDS113CG MAC/GMAC
enables Autonegotiation.
The default value is
overwritten if the PHY lacks the ability to support
Autonegotiation, which is ascertained through its
respective management interface, RMII/GMII. The
Autonegotiation process detects the different modes
of operation (i.e. speed selection, duplex mode)
supported by the system at the other end of the link
segment. Upon power on/reset, the PHY generates
a special sequence of fast link pulses (FLPs) to
Collision-based Flow Control, also referred to as
Backpressure Flow Control, inhibits frame reception
for ports operating in half-duplex mode by "jamming"
the link. When the free buffer space drops below a
user-defined
buffer
memory
threshold,
the
MDS113CG sends a jam sequence to all non
transmitting ports, after approximately eight bytes of
payload data has been received, to generate a
collision. The jam sequence is a predefined serial
data stream sent to all ports to indicate that there
has been a collision on the network. These ports will
delay (defer) the transmission of data onto the
network until the sequence has been completed.
begin Autonegotiation.
The MDS113CG MAC/
GMAC, supporting autonegotiation, reads the results
of the operation from the MAC/GMAC configuration
registers.
MAC Control Frame
IEEE 802.3x Flow Control
MAC Control Frames, as defined by the IEEE, are
used for specific control functions within the MAC
Control sublayer "MAC Control." Similar to data
frames, control frames are also encapsulated by the
CSMA/CD MAC, meaning that they are prepended
by a Preamble and Start of Frame delimiter and
appended by a Frame Check Sequence. These
frames may be distinguished from other MAC frames
by their length/type field identifier (88.08h). The
control functions are distinguished by an opcode
contained in the first two bytes of the frame. Upon
receipt, MAC control parses the incoming frame and
determines, by looking at the opcode and the MAC
address, whether it is destined for the MAC (a data
frame) or for a specific function within MAC Control.
After performing the specified functions, the
MDS113CG discards all MAC control frames it
receives, regardless of the port configuration. These
control frames are not forwarded to any other port
and are not used to learn source addresses.
IEEE 802.3x Flow Control reduces network
congestion on ports that are operating in full duplex
mode using MAC Control PAUSE frames and is
managed by the Flow Control Management
Registers.
The full-duplex PAUSE operation
instructs the MAC to enable the reception of frames
with a destination address equal to a globally
assigned 48-bit reserved multicast address of 01-80-
C2-00-00-01. These PAUSE frames are subsets of
MAC Control frames with an opcode field of 0x0001
and are used by the MAC Control to request that the
recipient stops transmitting non-control frames for a
specific period. The PAUSE Timer is loaded from the
PAUSE frame and is started upon the reception of a
PAUSE frame. It will request a length of time for
which it wishes to inhibit data frame transmission.
In general, the IEEE standard allows pause frames
longer than 64 bytes to be discarded or interpreted
as valid. The MDS113CG recognizes all MAC
Control frames (PAUSE frames) between 64 and
1518 bytes long. Any PAUSE frames presented to
the MAC outside of these parameters are discarded.
Flow Control
Flow control reduces the risk of data loss during long
bursts of activity, by saturating the buffer memory
with backlogged frames. The MDS113CG supports
two types of Flow Control: Collision-based for half-
duplex mode and IEEE 802.3x Flow Control for full
Frame Carrier Extension
At speeds faster than 100 Mbps and operating in
half-duplex mode, it is possible for the receiving port
to begin frame transmission before the source frame
from the sending port reaches the receiving end, if
duplex mode.
In both cases, the MDS113CG
recognizes congestion by constantly monitoring
available frame buffer memory. When the amount of
free buffer space has been depleted, the
15
MDS113CG
the frame is less than 512 bytes. The slot time is
defined as the round trip delay between the sending
port and the receiving port. The frame must be long
enough to reach the destination port before it
decides to transmit. This is eliminated when using
Carrier Extension.
Frame Bursting
At speeds faster than 100 Mbps and operating in
half-duplex mode, the MAC/GMAC can transmit a
series of frames without relinquishing control of the
transmission medium. This is called Frame Bursting.
Frame Bursting is utilized when a frame must be
extended to the length of the slot time. With Frame
bursting, only the first transmitted frame requires
extension. Once a frame has been successfully
transmitted, the Transmit section may submit
consecutive frames onto the medium without
contention, provided that no idle conditions exist
between frames (e.g., no inter-frame Gap). The
transmitting MAC/GMAC inserts extension bits to be
detected and extracted by the receiving MAC/GMAC,
into the inter-frame space interval. The MAC/GMAC
may continuously initiate burst frame transmission up
to the burst limit of 65,536 bits.
Carrier extension allows the slot time to be increased
to a sufficient value for accommodating the faster
speeds of Gigabit operation without increasing the
standard 64-byte minimum frame size. Extension
bits, recognized and extracted by the receiving MAC,
are appended to frames that are less than 4096 bits
(i.e., the Gigabit Ethernet slot time). This ensures
that the transmitted frame is received before the
receiving port begins transmission, thereby avoiding
a collision result. To utilize Carrier Extension, the
Physical Layer (PHY) must implement an encoding/
decoding scheme (i.e., Block Encoding) that
distinguishes between data and non-data bits. Once
the first frame has been extended, the MAC/GMAC
sends frames continuously using a method called
Frame Bursting.
Preamble
SFD
DA
SA
DATA
PAD
FCS
Carrier Extension
Mlb Frame Size: 512 bits
Slot Time:
4096 bits
FCS
Coverage
Late Collision Threshold:
Slot Time- Header Size
- 4032 bits
GMAC Frame with Carrier Extension
Mac frame mv Extension
Inter Frame
Mac Frame
Inter Frame
Mac Frame
Burst Limit
65,536 bits
Carrier Beat Duration
GMAC Frame Bursting
Figure 3 - Frame with Carrier Extension and Frame Bursting
16
MDS113CG
6 Frame Engine Description
The Frame Engine is the heart of the MDS113CG. It
coordinates all data movements, ensuring fair
allocation of the memory bandwidth and the XPipe
bandwidth.
granule at a time through the XPipe until the end of
file (EOF) safely arrives at the remote port's MAC
TxFIFO.
A frame is stored in a Frame Data Buffer (FDB) until
it is transmitted. FDBs are external, located in a
MDS113CG's frame buffer memory. To keep track of
per-frame control information, the Frame Engine
maintains one Frame Control Buffer (FCB) per frame.
FCBs are internal. Since the Frame Engine does not
access the external memory for frame control
information, this conserves memory bandwidth for
better performance.
When frame data is received from a MAC port, it is
temporarily stored in the MAC RxFIFO until the
Frame Engine moves it to the chip's external memory
one granule (128-byte-or-less fragment of frame
data) at a time. The Frame Engine then issues the
Search Engine a switching request that includes the
source MAC address and the destination MAC
address. After the Search Engine has resolved the
address, it transfers the information back to the
Frame Engine via a switching response that includes
the destination port.
The receiving DMA (RxDMA) moves frame data from
the MAC RxFIFO to the FDB. Before the RxDMA
writes frame data into the FDB, it must obtain a free
buffer handle from the buffer manager. A free buffer
handle points to an empty or released frame buffer,
ensuring that no stored frame data will get
overwritten. After the EOF has been safely stored in
the FDB, it writes the frame information to the FCB
and issues a switching request to the Search Engine.
If the frame is found to be bad (e.g., bad CRC), the
buffer handle will be released and nothing will be
written to the Search Engine or the FCB. This
returns the buffer back to circulation and the frame is
discarded.
When the destination port is idle, the frame data is
fetched from the memory and is written to the
destination port's MAC TxFIFO. However, when the
destination port is busy transmitting another frame,
the Frame Engine writes a transmission job that
includes a frame handle for future identification.
These transmission jobs are stored in the destination
port's transmission scheduling queue (TxQ). When
the destination port is ready, the Frame Engine
selects the head-of-line job from a TxQ. The frame,
specified by the job, will be fetched from the memory
and will be written to the MAC TxFIFO.
The RxDMA can fail to obtain a free buffer handle for
one reason. All buffers are currently occupied. In
this case, the RxDMA will discard the frame, without
getting a handle. The maximum TxQ lengths are
configurable from 128 entries to 1024 entries per
queue per queue. 13 TxQs are located in the
external memory.
For unicast frames, if the destination device is local
(i.e., the destination port is located in the same
device), the Frame Engine writes a job into the
destination port's transmission scheduling queue
(TxQ). The Transmit DMA (TxDMA) moves the frame
data to the MAC TxFIFO once the frame's
transmission job is selected for transmission.
If all buffers are used, no more frames can enter the
device. The Frame Engine keeps buffer counters
that limit the number of buffers occupied by frames
destined for each output port. If a buffer counter
exceeds a programmable threshold, its associated
output port is "blacklisted." Entering frames destined
to this output port are discarded, until the counter
If the destination device is remote (i.e., the
destination port is located on another device, and
can only be reached through the XPipe), all signaling
between the two devices are sent as XPipe
messages. The Frame Engine sends a scheduling
request message via the XPipe to the destination
port. This message asks the remote Frame Engine
to write a job into the destination port's TxQ. When
that job is selected, the remote Frame Engine sends
a data request message via the XPipe to the local
goes below the threshold.
This threshold is
configurable via registers BCT and BCHL. These
counters prevent complete depletion of buffers due
to an overloaded port, thus allow frames destined for
non-congested ports to enter the system. This
effectively avoids head-of-line blocking.
Frame Engine.
Reception of a data request
message triggers the forwarding engine module to
forward the frame data to the destination port, one
17
MDS113CG
7 Frame Buffer Memory
Frame Buffer Memory Configuration
The MDS113CG system utilizes external SRAM for its Frame Buffer Memory configuration, where the size of
memory supported is ∫ MB, 1MB and 2MB configurations. The following table shows four memory configuration
examples for the MDS113CG system.
SRAM
Type
One Bank
Two Bank
Address # pin
Size
∫ MB
1MB
Address #pin
Size
1M
64Kx32
19
20
20
21
128Kx32
2M
Table 1 - Type and Size of Memory Chips
The following figure shows the connections between the Frame Buffer Memory and the MDS113CG for one-
bank and two-bank memory configurations:
Note: LA[1:0] = 00
L_D[31:0]
L_D[31:0]
SRAM
64Kx32
RAM
Kx32
L_D[31:0]
SRAM
64Kx32
CE
L_A[18:2]
L_A[18:2]
L_A[19]
CE
DS113
DS113
L_D[63:32]
L_D[63:32]
L_D[63:32]
SRAM
64Kx32
RAM
Kx32
SRAM
64Kx32
One Bank 0.5M
64Kx 32
Two-Bank 1M
64Kx 32
L_D[31:0]
L_D[31:0]
SRAM
128Kx32
RAM
Kx32
L_D[31:0]
SRAM
128Kx32
CE
L_A[19:2]
L_A[19:2]
L_A[19]
CE
DS113
DS113
L_D[63:32]
L_D[63:32]
L_D[63:32]
SRAM
128Kx32
RAM
Kx32
128Kx32
SRAM
One Bank 1M
128Kx 32
Two-Bank 2M
128Kx 32
Figure 4 - Frame Buffer Memory Configuration
18
MDS113CG
Frame Buffer Memory Usage
Description:
Unit Size:
Unit Count:
Total Size
Frame Data Buffer
(FDB)
1.5 Kbytes
256 to 1K
384 K bytes to 1.5M bytes
Transmission Queue
4 bytes x128 to
4 bytes x 1K
13
6.5 Kbytes to 52 Kbytes
HISC Mailing List
32 Bytes to
64Bytes
(Configurable)
128 to 1K
4K bytes to 32 Kbytes (at 32 Bytes
each)
Table 2 - Frame Buffer Memory Usage
System Memory Allocation
63
0
0
FDB block
must start from 0.
FDB
Frame Data Buffers
(1.5KB x # of frame buffers)
Transmission queues
(13 queues)
(each entry = 1DW)
Configurable Size
Configurable Size
(# entry of Queue =128 to 1K)
HISC Mailing List
(# entry=128 to 1K)
(each mail entry=32 bytes to 64 bytes)
MAX
Byte Byte Byte Byte Byte Byte Byte Byte
1/2MB, 1MB or 2MB
7
6
5
4
3
2
1
0
Figure 5 - Memory Map of a System
19
MDS113CG
Each queue consists of one double word (4-bytes)
transmission entry, containing a FDB handle pointing
to the corresponding frame in the buffer. The size of
the Transmission Queue is 128, 256, 512, or 1K
entries, while the location is setup during Power On/
Reset in an internal table called the Queue Control
Table (located inside the MDS113CG).
Frame Data Buffers
Frame Data Buffers (FDBs) accommodate incoming
data frames and partition them into data blocks,
consisting of 1.5K bytes. The number of data blocks
in FDBs is configured by setting the value in the
register FCBSL[9:0]. Since the MDS113CG can
support up to 2M Bytes memory, the maximum
number of data blocks is 1K.
Mailing List
Note: FDBs must start at location 0.
The Mailing List provides a communication channel
between two HISC in two-chip configuration. The
size of a mail entry is 32 bytes. When the HISC
writes mail, the HISC can obtain a free mail by the
hardware. Conversely, when the HISC reads its
mail, the HISC accesses the mail by the hardware,
as well.
Transmission Queues
Transmission Queues control the scheduling of
transmitting ports. The Search Engine maintains the
contents of these queues, consisting of up to 13
Transmission Queues and representing each of the
13 ports in the MDS113CG.
Local SBRAM Memory Interface
L_CLK
L_CLK
L3-max
L3-min
L1
L2
L_D[63:0]
L_D[63:0]
L4-max
L4-min
Figure 6 - Local Memory Interface -
Input Setup and Hold Timing
L_A[19:2]
L6-max
L6-min
L_ADSC#
L7-max
L7-min
L_BW[7:0]#
L8-max
L8-min
L_WE[1:0]#
L9-max
L9-min
L_OE#
Figure 7 - Local Memory Interface -
Output Valid Delay Timing
20
MDS113CG
When two MDS113CG chips are connected and are
operating with synchronized MCT entries, the HISC
processor has the ability to send a request to the
Search Engine, instructing it to learn a new address
received from the other MDS113CG. The HISC
processor can also use this method to make simple
edits to the MCT entries for port changes (i.e. source
MAC address is now connected to a different port on
the MDS113CG).
8 Search Engine
The Search Engine is responsible for determining
the destination information for all packet traffic that
enters the MDS113CG. The results from all address
searches are passed to the Frame Engine to be
forwarded, or on to the HISC block for further
processing. Either way, the resulting messages
provide all the needed information to allow the
destination block to process the packet.
Flooding and Packet Control
The Search Engine has been optimized for high
throughput searching, utilizing the integrated Switch
Packets, for which there are no matching destination
MCT entries, are by default flooded to all output
ports. This can result in broadcast storms and cause
the number of flooded packets to increase rapidly.
The MDS113CG provides the user a means for
setting a level of flooding, by providing a Flooding
Control Register (FCR). The FCR allows the user to
define a time base (100us to 12.8ms) during which
packet flooding at each output port will be counted.
The flood control field allows the user to specify
limits for the number of flooded packets per source
port.
Database Memory (SDM).
The internal SDM
contains up to 2k MAC Control Table (MCT) entries.
These MCT entries are searched utilizing a Hashing
algorithm.
The search process begins when the Frame Engine
transfers the first 64 bytes of a packet header to the
Search Engine. These bytes are parsed to extract
the information needed to perform the search for the
MCT entries that match the source and destination
MAC address, generate the search hash keys, and
lookup other packet status information.
During the time base period, the counter at each port
counts the number of flooding packets. Once a
counter exceeds the allowed quantity, the Search
Engine discards any flooding packets that enter the
port during the remainder of the time base flooding
period. When the time base period is completed, the
flood counter at each port is reset, and the counting
process starts over.
Layer 2 Search Process
The search process begins when packet header
information is transferred to the Search Engine from
the Frame Engine.
The Search Engine will search for the destination
and source MAC addresses.
The flooding control register is global for setting the
limits on all ports, but the individual ports have
separate counters to keep track of the number of
flooded.
Address Learning
Address learning can be performed by either the
HISC or the Search Engine.
Address Aging
Entries in the MCT database are removed if they
have not been used within a user selectable
When the Search Engine is learning and a match is
not found to a source address search, it can create a
new MCT with the necessary information, and then
notify the HISC that a new address has been
timeframe.
This aging process is handled by
inspecting a single MCT entry during each clock
period. If the entry is valid and subject to aging, an
aging flag in the MCT entry is cleared. If the aging
flag is already set to zero during the inspection, an
aging message is sent to the HISC processor to
delete and free up the aged MCT entry. Each time
an MCT entry is matched by way of a Search Engine,
source search process, the aging flag is asserted to
restart the aging process for that entry.
learned.
If the Search Engine request queue
becomes 3/4th full, the Search Engine will ignore
address learning until the request queue is less full.
In that case, packets are forwarded as usual, and a
message is sent to the HISC requesting that the
HISC learn the new address. If the Search Engine
request queue is too full, and the HISC request
queue is full, then no learning will take place.
21
MDS113CG
9 The High-Density Instruction Set
Computer (HISC)
Resource Management
The HISC can enforce a replacement policy when
the number of free data structure for new MAC
address entries is lower than the predefined
threshold.
Description
The High Density Instruction Set CPU (HISC) is
specifically designed to implement highly efficient
management functions for the MDS113CG switching
hardware, minimizing the management activity
intervention during frame processing. The HISC is
also designed with a powerful instruction set and
dedicated hardware interfaces for packet processing
and transmission to provide high performance packet
Switching Database Management
One of the major management tasks required of the
HISC is to create, delete, and modify MAC address
entries upon requests from the Search Engine.
Generally, the Search Engine performs the learning
of new MAC addresses identified in the packet
streams.
transfers
between
the
switching
hardware
components.
Communicaton Between HISC and
Search Engine
HISC Architecture
The HISC is designed with an advanced pipeline
architecture that combines the advantages of both
RISC and VLIW architectures. The HISC core
combines a rich instruction set with 88 general-
purpose registers and support for multiple-way jump.
The 88 registers are divided into three parts, eight
common general-purpose registers and two banks of
40 registers for two different task contexts. All
registers are directly connected to the Arithmetic
Logic Unit (ALU), allowing two independent registers
to be accessed in one single instruction execution.
Each HISC instruction may have up to three sub-
instructions, which can be executed in one clock
cycle. The resulting architecture is more code
efficient, while achieving throughputs up to ten times
faster than a CISC processor or up to three times
faster than a RISC processor. For a MDS113CG
running at 100MHz, the HISC can produce up to
300MIPs processing power.
High-speed communication channels are required to
provide fast message deliveries between the HISC
and switching hardware. One high-performance
FIFO provides the required communication channels
between the HISC and the Frame Engine.
The high-speed FIFO is used by the Search Engine
to send messages, management requests or
received packets, to the HISC.
Whenever a
message is sent to the FIFO, the HISC is notified of
the new event. Each message may contain up to two
command codes, processed by the HISC
sequentially. The HISC can also request the Search
Engine to do operations such as search or learn via
a HISC I/O interface. After processing the requests,
the Search Engine sends the response back to the
HISC via the FIFO.
Mailbox
HISC Operations
The second communication mechanism is
a
hardware mailbox that can support variable size
messages, exchanged between two HISCs in 2-chip
configuration. A major use of the mailbox is to
exchange information required for updating the
switching database.
With an event-driven operation model, upon the
request from the Search Engine, the HISC
dynamically manages and maintains the Switch
Database including MAC address entries.
The HISC performs the following major operations:
HISC-HISC Mail
•
•
•
Resource initialization
Resource management
When one HISC sends a mail message to the other
HISC, the first HISC acquires an address of a free
mail from the free mail list (maintained by hardware),
it writes the mail content to the given memory
address. Whenever a management mail message is
received from the remote HISC, an event is
generated to inform the HISC to process the mail
message.
Switching database management
Resource Initialization
The HISC initializes all internal data structures,
including the mailbox and switching database data
structures, which are used by the HISC and
switching hardware.
22
MDS113CG
10 The XPIPE
The XPipe provides a high-speed link between
systems utilizing two MDS113CG devices. The
XPipe incorporates a 32-bit-wide data pipe, with a
high-speed point-to-point connection, and a full-
duplex interface between devices. While operating
at a 100MHz, this interface can provide 3.2G bits per
second (Gbps) of bandwidth per pipe in both
directions.
XPIPE Connection
X_DO[31:0]
X_DI[31:0]
X_DCLKO
X_DCLKI
Transmit FIFO
Receive FIFO
X_DENO
X_DENI
X_FCLKO
Xmit
Ctrl
Rcvd
Ctrl
X_FCLKI
Source
Target
X_DI[31:0]
X_DLCKI
X_DENI
X_DO[31:0]
X_DCLKO
X_DENO
Receive FIFO
Transmit FIFO
Xmit
Ctrl
Recd
Ctrl
X_FCO
X_FCI
Target
Source
MDS113CG
MDS113CG
Figure 9 - XPipe System Block Diagram for the MMDS113CGCG
The XPipe interface employs 32 data signals and
three control signals for each direction. The pin
connections between two MDS113CG devices are
depicted in Figure 7. These 32 data signals form a
32-bit-wide transmission data pipe that carries
XpressFlow messages to and from the devices. The
direction of all signals are from the source to the
target device, except for the flow control signal,
which sends messages in the opposite direction;
from the target to the source. The three control
signals consist of a Transmit Clock signal, a Transmit
Data Enable signal, and a Flow Control signal.
an entire XPipe message (including the Header and
the Payload) and is used to identify the message
boundary from the received data stream. The timing
relationship between the data clock and data enable
signals is described in the XPipe Timing (see XPIPE
Timing).
The Flow Control signal (X_FC) monitors the state of
the receiving queue at the target end to prevent
XPipe message loss. When the target end does not
have enough space to accommodate an entire XPipe
message, the target device sends a XOFF signal by
driving the X_FC signal to LOW. The source device
will stop further transmission until the X_FC signal
asserts the XON state, which is an active HIGH
(refer to the following table).
The Transmit Clock signal (X_CLK) provides a
synchronous clock to sample the data signals at the
target device. The source device provides the
Transmit Data Enable signal (X_DEN) that envelops
23
MDS113CG
Signal Name
Source End
Target End
Description
X_DO[31:0]
X_DI[31:0]
32-bit-wide Transmit Data Bus – Includes an XPipe Message Header and
follows by the data payload.
X_DCLKO
X_DENO
X_DCLKI
X_DENI
Transmit Clock – Synchronous data clock provided by the source end.
Transmit Data Enable – Provided by the source end to envelop the entire
XPipe message.
X_FCI
X_FCO
Flow Control Signal– A flow control pin from the target end to signal the
source end to active XON/XOFF.
Table 4 - Summary Description of the Source and Target End Signals
The XPipe Message Header provides the payload size, type of message, routing information, and control
information for the XPipe incoming message. The routing information includes the device ID and port ID. The
header size is dependent upon the message types and may be 2 to 4 words in length.
2-4 Words Header
0-64 Words Payload
Data Payload
XpipeFlow Message
Header
Figure 10 - XPipe Message Header
24
MDS113CG
XPIPE Timing
The source device generates the X_CLK signal to
provide a synchronous transmit data clock. The
Receiver will then sample the data on the falling
(negative) edge of the clock, as shown in Figure 9.
beginning of the first double word (4 bytes) and a
falling (negative) edge at the beginning of the last
double word of an XPipe message as shown in
Figure 10.
To identify the boundary between the XPipe
messages and the data stream, the source device
uses the X_DEN signal to envelop the entire XPipe
message. That is, a rising (positive) edge at the
Note: The negative edge does not occur at the end of
the last double word, but instead, at the beginning of
the last double word. This allows XPipe messages to
be sent consecutively (back-to-back).
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
..........
Last Cycle
Idle
X_CLK
X_DEN
*1
X_D[31:0]
D Word 0 D Word 1 D Word 2 D Word 3
.........
.........
.........
D Word N
Note 1: Positive edge at the beginning of the first Double Word
Negative edge at the beginning of the last Double Word
Figure 11 - Basic Timing Diagram of XPipe
XPIPE Interface
X_DCLK
I
X1-max
X1-min
X_DI[31:0]
X_DENI
X_FCI
X2-max
X2-min
X_DCLK
I
X17
X19
X21
X18
X20
X22
X24
X3-max
X3-min
X_DCLKI
X_DI[31:0]
X_DENI
X4-max
X4-min
X_DCLK
O
X5-max
X5-min
X_FCO
X_DENO
X23
X6-max
X6-min
X_FCI
X7-max
X7-min
X_DO[31:0]
X8-max
X8-min
Figure 12 - LXPipe Interface - Output Valid
Delay Timing
Figure 13 - XPipe Interface - Input Set
and Holding Time
25
MDS113CG
management interface (MDIO/MDC) is assumed
identical to that defined in IEEE 802.3u.
11 Physical Layer (PHY) Interface
The RMII supports both 10 and 100 Mbps data rates
across a two-bit Transmit Data (TXD) path and a two-
bit Receive Data (RXD) path.
The Physical Layer Interface is designed to interface
Zarlink Semiconductor chipsets to a variety of
Physical Layer devices.
Reduced Media
Independent Interface (RMII) is used for 10/100
interfaces, while Gigabit connections can use either
Gigabit Media Independent Interfaces (GMII) or
Physical Coding Sublayer (TBI).
The RMII uses a single synchronous clock reference
sourced from the Media Access Controller (MAC), or
an external clock source, to the Physical Layer
(PHY). Doubling the clock frequency to 50 MHz
allows a reduction of required data and control
signals, thereby providing a low cost alternative to
the IEEE Std 802.3u Media Independent Interface
(MII). The RMII functions to make the differences
between copper and optical PHYs transparent to the
MAC sublayer.
The chip ball names for the MAC use M as the first
letter of the name, followed by their pin number, and
then their function. M1_RXD0 refers to Mac port 1,
receive data 0 of the receive data pair.
Reduced MII (RMII))
The RMII specification has the following
characteristics:
The MDS113CG implements the Reduced Media
Independent Interface (RMII) signals, REF_CLK,
CRS_DV, RXD[1:0], TX_EN, and TXD[1:0], defined in
Section 5 of the RMII Consortium Specification. The
purpose of this interface is to provide a low cost
alternative to the IEEE 802.3u MII interface. Under
IEEE 802.3u, an MII comprised of 16 pins for data
and control is defined. In devices incorporating
many MACs or PHY interfaces such as switches, the
number of pins can add significant cost as the port
•
•
•
•
It is capable of supporting 10Mb/s and 100Mb/s
data rates
A single clock reference is sourced from the
MAC to PHY (or from an external source)
It provides independent 2 bit wide (di-bit)
transmit and receive data paths
It uses TTL signal levels, compatible with
common digital CMOS ASIC processes.
counts increase.
Architecturally, the RMII
specification provides for an additional reconciliation
layer on either side of the MII but can be
implemented in the absence of an MII.
The
Direction
(with respect to the PHY)
Direction
(with respect to the MAC)
Signal Name
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive,
transmit and control interface
M[0:11]_CRS_DV
M[0:11]_RXD[1:0]
M[0:11]_TX_EN
M[0:11]_TXD[1:0]
M[0:11]_RX_ER
Output Input
Output Input
Carrier Sense/Receive Data Valid
Receive Data
Input
Input
Output
Output
Transmit Enable
Transmit Data
Output Input (Not required)
Receive Error
Table 5 - RMII Specification Signals
26
MDS113CG
interface incorporates all the functions required by
the GMII, to include encoding/decoding serial data
to/from 8B/10B for PHY communication and
generating Collision Detect (COL) signals for half-
THE Gigabit Media Independent
Interface (GMII)
The GMII supports the 1000 Mbps full-duplex
operations of the MDS113CG, based on the Media
Independent Interface (MII) defined by IEEE Std
802.3 (Clause 22). The GMII retains the names and
functions of most of the MII signals, but defines valid
signal combinations for 1000 Mbps operations. The
GMII transfers data in each direction for the
Data[7:0], Delimiter, Error, and Clock signals. The
GMII implementation extends the Transmit Data
(TXD) and Receive Data (RXD) signals of the MII
from four bits wide to eight bits wide and
synchronizes the data and the delimiters using a
Gigabit Transmit Clock (GTX_CLK) instead of the
duplex mode.
Autonegotiation
In addition, it manages the
process by informing the
management entity via the GMII that the PHY is
ready for communications. The on-chip TBI may be
disabled, using the Device Configuration Register
(DCR2), if TBI exists within the Gigabit PHY. The TBI
interface provides a uniform interface for all 1000
Mbps PHY implementations.
The TBI Interface comprises of the TBI Transmit,
Synchronization, TBI Receive, and Autonegotiation
processes for 1000BASE-X. The TBI communicates
with the GMII using a byte-wide synchronous data
path, where packet delimiting is provided by separate
Transmit (TX_EN and TX_ER) and Receive signals
(RX_EN and RX_ER). This interface also provides
the functions necessary to map packets between the
GMII and the physical medium.
MIIs' Transmit Clock (TX_CLK).
The GMII is
designed to make the differences between various
media transparent to the MAC.
The MII Management Interface
The TBI Transmit process sends the GMII signals
TXD[7:0], TX_EN, and TX_ER to the physical
medium and generates the GMII Collision Detect
(COL) signal based on whether a reception is
The GMII uses the MII Management Interface to
control and gather status information from the
Gigabit Physical Layer (PHY) to configure
MDS113CG operations using Autonegotiation. The
management interface consists of a pair of signals,
called the M_MDIO and M_MDC management pins,
that will physically transport the management
information across the GMII, format frames,
exchange management frames, and read from or
write to specific MDS113CG management registers.
Both of these pins have internal pull-up resistors and
may be placed in a high impedance state to allow
another master to manage the devices on the
interface.
occurring
Additionally, the Transmit process generates an
internal "transmitting" flag and monitors
simultaneously
with
transmission.
Autonegotiation to determine whether to transmit
data or to reconfigure the link.
The TBI Synchronization process determines
whether or not the receive channel is operational.
The TBI Receive process generates RXD[7:0],
RX_DV, and RX_ER on the GMII, and the internal
"receiving" flag for use by the Transmit processes.
MII Command and Status Registers
The TBI Autonegotiation process provides the means
to exchange configuration information between two
The GMII utilizes the MII Command and Status
registers defined in the 10/100 Mbps Specification
and additional extended registers to support
Autonegotiation (IEEE Std 802.3, Clause 37). The
commonality of the MII management registers will
allow the MDS113CG to determine the capabilities
supported by the PHY and to implement such
functions as "Start of Frame" and "Determine PHY
Address."
devices that share
a
link segment and to
automatically configure the link for the appropriate
speed of operation for both devices.
The Physical Coding Sublayer (TBI)
Interface
For the Zarlink Semiconductor MDS113CG, the
1000BASE-X TBI Interface is designed internally and
may be utilized in absence of a GMII. The TBI
27
MDS113CG
12 The Control Bus
The Control bus provides the communication path between the Switch Devices and Flash Memory, and
between any two MDS113CG Switches (see the following figure).
Control Bus
Primary DEV
Secondary DEV
DS113
DS113
Flash
memory
Arbitrator
Figure 14 - Control Bus Configuration
Power On/Reset Configuration
On power-up, the following four Bootstrap bits of the following table are used:
Name
Default
Functional Description
BS_BMOD
1
Bus Mode
Must be 0
BS_RW
1
1
Selects R/W Control polarity
0=R/W# 1=W/R#
BS_PSD
Primary Device Enable
0=Secondary Mode 1=Primary Mode
(The arbiter is activated in the chip with Primary Device.)
BS_RDYOP
1
Option of merger the RDY and B_RDY
0=merged RDY and B_RDY pin
1=Separated RDY and B_RDY pins
Table 6 - Bootstrapping Options
28
MDS113CG
Control Bus Clock Interface
Bus Master
The Control BUS Interface allows the Control BUS
clock to operate at clock rates different from the
system clock rate. The Control BUS Clock rate is
always less than or equal to the System Clock rate.
The nomenclatures "Master" and "Slave" refer to the
device that possesses the Control BUS Interface,
while the designations of "Primary" and "Secondary"
refer to the device that possesses the Bus Arbiter.
The primary or secondary device is determined
during Power On/Reset, bootstrap options, while the
master or slave device changes dynamically, and will
be determined by the Arbiter. The arbiter (located
within the primary device) selects one of the devices
as the Master.
Address and Data Buses
•
The data bus is a synchronous, 32-bit bus that
can receive 16 or 32-bit wide data. The Flash
memory uses a 16-bit data bus. The data bus
supports 32 bit wide data.
Note: The primary device may be the Master or the
Slave. The master device is the bus master (controls
the bus), while the other device is a slave device.
•
•
The address buses supports 10 address bits
([10:1]).
Each device occupies 2048 bytes of Input/
Output space.
Control Bus Cycle Waveforms
Sample
Write cycle
Read cycle
Burst
P_CLK
P_ADS
P_RDY
P_[10:1]
P_[31:0]
P_BRDY
P_BLAST
wait
wait Read
wait Read Read Read Read
one-wait state
Flash read timing
P_CLK
FS_CS
FS_OE
FS_[18:1]
FLS_[15:0]
Sample
point
sample point
Read cycle = 8 clks
Figure 15 - Control Bus I/O and Flash Bus Access Operations
29
MDS113CG
activates the arbiter of that device. At most, three
devices, two MDS113CG devices and one CPU (in
debug mode), can operate on the Control BUS
Interface at the same time.
The Control Bus Interface
TThe HISC processor of the Master device
communicates with the slave device as a CPU
function.
Each device may request access to the Control BUS
Interface by sending a Request signal to the arbiter.
The arbiter then sends a Grant signal acknowledging
which device has been chosen.
Arbiter
The arbiter of the MDS113CG is an internal logic
device used to determine which device will function
as the master device. The connections between the
master device, slave device, and the CPU are used
for debugging purposes only (see the following
figure).
An arbitrate scheduler, located within the arbiter,
decides which device functions as the Master device.
If the Master is the secondary device, the arbiter will
send a Grant signal and a Chip Select (P_CS) signal
to the device. If the Master is the primary device, the
Grant signal is sent directly to the Master State
Machine (MSM) by an internal signal. The scheduler
then performs a round robin configuration and allows
each device to be the Master device.
Note: A CPU is used only for debugging purposes
and cannot be involved in switching decisions or
management activities.
Note: During Power On/Reset, the arbiter always
selects the primary device to be master device.
During Power On/Reset, the bootstrap pin, BS_PSD,
determines which device will be the primary and
Only for Debug
CPU
P_GNTC
P_REQC
DS113
DS113
Primary
Secondary
Bus
Request
Master the
State
Machine
Master the
State
Machine
Bus Request
Bus Grant
Bus Grant
Arbiter
Chip Select
Figure 16 - Block Diagram of the Arbiter
30
MDS113CG
Control Bus Timing
P_CLK
P1
P3
P2
P_RST#
P_CLK
P_D[31:0]
P_RDY#
P_INT
P4
P_ADS#
P_RWC
P_CSI
P16-max
P16-min
P5
P7
P9
P6
P17-max
P17-min
P8
P18-max
P18-min
P10
P12
P_A[10:1]
P_D[31:0]
P11
Figure 17 - Control Bus -
Output Valid Delay Timing
Figure 18 - Control Bus -
Input Setup and Hold Timing
31
MDS113CG
13 The LED Interface
LED Interface
The MDS113CG LED interface supports the status
per port in a serial stream that may be daisy-chained
to connect two MDS113CG chips. Daisy-chaining
greatly reduces the pin count and number of board
traces routed from the Physical Layer to the LEDs,
thus simplifying system design and reducing overall
system cost. For a large port configuration such as
the 24+2 in the MDS113CG, a large number of LED
signals is needed, which may induce noise and
layout issues in the system. The LED information is
transmitted in a frame-structured format with a
synchronization pulse at the start of each frame.
MDS113CG
Master
MDS113CG
Slave
LE_CLKO
LED-
DECODER
LE_SYNCI
LE_DI
LE_SYNO
LE_DO
LE_SYNCO
LE_DO
LED DISPLAY
Figure 19 - LED Interface Connections
To provide the port status information from our
MDS113CG chips via a serial output channel, six
additional pins are required.
The port status of the MDS113CG is transmitted to
an external decoder via a serial output channel. In
the MDS113CG, we support cascading of this serial
output channel between two devices.
One
•
MDS113CG is configured as the master; this initiates
the start of LED information frames, and serializes
information bits. The MDS113CG slave repeats the
information sent from the master and appends its
own information bits. To cascade these two devices,
we will need to extend the number of LED pins from
3 to 6. The following table shows two cascaded LED
interfaces and the connections between the
MDS113CGs, the LED decoder, and the LED display.
•
•
LE_CLKI/O at 25 MHz
LE_SYNI/O a sync pulse — defines the
boundary between frames
•
LE_DI/O
a continuous serial stream of data
for all status LEDs which repeat
once every frame time
A low cost external device (i.e. a 44-pin FPGA-like
device) decodes the LED framed data and drives the
LED array for display.
This device may be
customized for different system configurations.
32
MDS113CG
Function Description
Signal Name
Description
Master
Slave Device
Device
LE_CLKI
LE_CLKO
LED Clock-Synchronous LED clock provided by the slave device to LED
decoder at the system clock divided by 8 (~97.5Khz)
LE_SYNI
LE_SYNO
A synchronous pulse — defines the boundary between frames
The length of each LED data frame is about 256 bits that shift out by
LED_CLK per bit
LE_DI
LE_DO
A continuous serial stream of data for all status LEDs, which repeats once
every frame time
Table 7 - LED Signal Names and Descriptions
Port Status
In the MDS113CG, each port consists of 8 different LED status, represented by separate bits:
1. Flow Control
2. Transmitting Data
3. Receiving Data
4. Action (TxD or RxD)
5. Link UP/DOWN
6. Speed
7. Full-Duplex/Half-Duplex
8. Collision.
In addition to the 13 ports of the MDS113CG, three extra user-defined status sets may be sent through the LED
serial channel for debugging or other applications, where each user-defined status set is also represented by 8
bits.
33
MDS113CG
LED Interface Time Diagram
The Master needs to shift out (13+3)*8 status bits periodically. Thus, slave needs to shift out (13+3)*8 +
(13+3)*8 status bits, which includes the status of the master device and itself.
31 30
SS
28 27 26 25 24 23
HT LCLK
16 15
8 7
0
UDEF3
UDEF2
UDEF1
Bit [7:0]
UDEF1
UDEF2
UDEF3
LCLK
User defined information status 1 for debug purpose
User defined information status 2 for debug purpose
User defined information status 3 for debug purpose
LED Clock frequency (Default=00)
Bit [15:8]
Bit [23:16]
Bit [25:24]
00=100M/8=12.5Mhz
01=100M/16=6.25Mhz
10=100M/32=3.125Mhz
11=100M/64=1.5625Mhz
Bit [27:26]
HT
Holding time for LED signal (Default=00)
00=8msec
01=16msec
10=32msec11=64msec
Bit [30:28]
Bit [31]
Reserve
SS
Start Shift out the status bits out from the master device. This
bit has no effect on slave chip.
Note that UDEF1-UDEF3 are used for debug purpose. The contents of UDEF1-3 are loaded by CPU and the
usage of these are up to software.
34
MDS113CG
The status of each port will be sampled by the LED State Machine every 20.5 ms, the period of the frame. That
is, each LED data frame length equals 256 * 80 nsec. Each frame is divided into two sub-frames: a master and
a slave sub-frame. Furthermore, each sub-frame is partitioned into 16 slots (13 MAC ports plus 3 user-defined
sets) and each slot will carry 8 status bits. The following figure shows the signal from the slave chip to LED
decoder.
One Frame
256x80nsec
Master dev sub-frame
16 slots
Slave dev sub-frame
16 slots
Cycle #0
Cycle #1
Cycle #2
Cycle #3
Cycle #4 Cycle #5 Cycle #6
Cycle #7
Cycle #8
LED_CLK
LED_SYN
LED_Data
*1
P0
P1
bit0
Bit1
bit 2
bit 3
Bit 4
Bit 5
Bit 6
Bit7
bit0
Bit 1
1* one pluse for every 256 cycles
Figure 20 - Time Diagram of LED Interface
35
MDS113CG
14 Data Forwarding Protocol and Data Flow
Frame Reception
For normal frame reception, a 128-byte block of
frame data is stored in the RxFIFO. This block may
be shorter if an End of Frame (EOF) arrives. At that
point, the RxDMA will request the use of the internal
memory bus. When this memory request is granted,
the RxDMA will move the block from the RxFIFO to
the Frame Data Buffer (FDB).
The port will send the jobs to the transmission
scheduling queues according to a first in first out
(FIFO) order.
To start data transmission, the port obtains a job
from the transmission scheduling queue and notifies
the Transmit DMA (TxDMA) to move the data from
the FDB to the MAC Transmit FIFO (TxFIFO) in 128-
byte granules (for local forwarding). Otherwise, the
device sends a DATA_REQ command message via
the XPipe to the source device to request remote
forwarding. The data forwarding engine module in
the Frame Engine of the source device will then
forward the frame in 128-byte granules via the XPipe.
The MAC ports are partitioned into two groups, one
for the Gbps Port and one for all 12 of the 100Mbps
Ports. The service discipline is round robin for both
the Gbps Port and 100/10Mbps group. After the
entire frame is moved to the frame data buffer (FDB),
a switch request will be sent to the Search Engine
(Reference Search Engine Section)
Flow for Data Frame
Unicast Frame Forwarding
The following subsections describe the flow of
information during transfers of unicast data frames.
For forwarding of the unicast frame, the Search
Engine first resolves the destination device and the
destination port, and sends a switch response back
to the Frame Engine. The Frame Engine will obtain
the type (unicast or multicast), the destination port,
and the destination device from the search response.
After processing the search response, the Frame
Engine will notify the destination port that it has a
frame to forward to the destination port's TxFIFO.
Unicast Data Frame to Local Device
In the simplest case, the data frame is destined for a
port on the local device. The Frame Engine moves
the received frame to the local FDB. The Search
Engine forms a switch request with the frame header
(includes source MAC and Destination MAC) and
passes it to the Switch Engine to resolve the
destination. The Switch Engine then provides a
destination port address to the Frame Engine via a
For local forwarding (e.g. the destination port is in
the local device), the Frame Engine will send the job
to the Transmission Scheduling queue of the
destination port.
switch response message.
The Frame Engine
transmits to put a transmission job in transmission
scheduling. After the port is ready to send the frame,
the Frame Engine starts to move the frame to the
TxFIFO. If the Switch Engine cannot resolve the
MAC address, the HISC is queried to resolve the
address.
For remote forwarding (i.e. the destination port is in
the remote device), the Frame Engine will create a
data forwarding request command message
(DATA_FWD_REQ), which is sent via the XPipe to
the remote device. The remote Frame Engine, after
receiving this DATA_FWD_REQ message, will place
a job in the Transmission Scheduling queue of the
destination port.
The port will serve the next job from the
Transmission Scheduling queue when the following
two conditions are met:
•
•
There is enough room for a 1.5Kbyte frame (a
maximum-sized frame) within the TxFIFO.
The end-of-frame (EOF) of the current frame
has arrived at the TxFIFO.
36
MDS113CG
•
•
When the destination port is ready to send the
frame, the destination Frame Engine send a
Data Request message to the source Frame
Engine.
Unicast Data Frame to Remote Device
In another case, the data frame is destined for a port
on a remote device. First, the Frame Engine moves
the received frame to the local FDB. A switch
request with a frame header (includes source MAC
and Destination MAC) is passed to the Switch
Engine to resolve the destination. The Switch
Engine then provides a destination port address to
the Frame Engine. If the Switch Engine cannot
resolve the address, the HISC is queried. Once the
address is resolved, the two Frame Engines perform
the following interactive handshaking procedures via
the XPipe:
After the source Frame Engine receives the
Data Request Message, it starts to move the
frame in granule form, which is directly written
in the destination TxFIFO.
Note that, at the remote device, the frame is written
into the transmit FIFO of the remote destination port.
In order to reduce the latency, the frame is not stored
in the FDB of the remote device again.
•
Source Frame Engine sends a Data Forwarding
Request message to Destination, where the
destination Frame Engine puts a job in the
associated transmission scheduling queue.
37
MDS113CG
15 Port Trunking
Port trunking groups a set of 8 MDS113CG 10/100
Mbps physical ports into one logical link; however, all
ports in the trunk group must be within the same
access device, and each port can only belong to one
trunk group. All ports in the Trunk group must and
share the same MAC Address. Each system can
support up to 4 groups.
Load distribution for unicast traffic is done based on
a hash key, a hash function of the Source Address
and the Destination Address.
Note: Refer to the "MDS113CG/DS113 Port Trunking
and Port Mirroring Application Note." In this
document, we describe how to specify the trunk
groups on line via DIP switches.
Unicast Packet Forwarding
ECR1 - MAC Port Configuration Register
31
24 23
17 16 15
8
7
6 5
4 3 2
0
IF BKUC TE TGID
Trunking
Configuration Bits
Figure 21 - ECR1 - MAC Port Configuration Register
Port Trunking ID Bits
Bit [0:2]
Bit [3]
TGID
TE
Group ID
Trunk Enable
0= Trunk disable
1= Trunk Enable
A trunked port will need to have its ECR1 MAC Port
Configuration Register set by CPU software to
contain its associated Trunk Group ID. Later on,
when a new source MAC Address is learned through
that port, the Trunk Group ID will be recorded in the
MCT entry by either the Search Engine or the
microcode in the HISC. The Trunk Group ID will be
used for forwarding decision when the destination
MCT entry of a received packet is found by the
Search Engine, if the status field indicates that the
address found is on a Trunk Group.
contains the device and port IDs for the physical port
used to transmit this packet. Software needs to set
these entries, using TPMXR and TPMTD registers, to
distribute the traffic load across the ports in the Trunk
Group.
If the source MAC Address of an incoming packet is
on a Trunk Group (based on the MCT information),
the receiving port's TGID will be compared against
the Trunk Group ID in the source MCT to decide
whether the source MAC address has moved to
another Trunk Group or not.
The Trunk Group ID is used by the Search Engine,
along with the "hash key" (3 bits result of a hash
operation between source address and destination
MAC address), to access a Trunk Port Mapping Table
entry in the internal RAM. Each entry in this table
The Trunk Port Mapping Table is 32 entries deep (4
groups * 8 hash entries), and each entry is 5 bits
wide (1-bit device ID, 4-bit port ID), as show in the
following format.
38
MDS113CG
TG provided by
Search Eng
Dev
ID
Port
ID
(1bit)
(4bit)
TG
(2bits)
Hash Key
(3bits)
.
.
.
.
.
.
Hash Key=
Figure 22 - Port Mapping Table
MAC Address Assignment
In MDS113CG, there are three ways to assign the MAC address to each port. All the ports in the same device
share the 44 MSBs, MAC[47:4], which are shown in ADAR0 and ADAR1 registers, while the 4 LSBs, MAC[3:0]
are specified in ADOR0 and ADOR1 registers for port 0-port 6 and port 8-port 11, respectively. The 4 LSBs
MAC[3:0] can be assigned as follows:
1. If the switch does not support Port Trunking, MAC[3:0]= port number
2. If the switch supports multiple MAC addresses and Port Trunking, the ports in the same Trunk Group share the
same MAC[3:0]. The value of MAC[3:0] is assigned by the Trunk Group (TG) Table.
3. If the switch supports only a single MAC address, all the 4 LSBs of MAC will be set the same value in ADOR0
and ADOR1 register.
39
MDS113CG
16 Port Mirroring
Features
The received or transmitted data of any 10/100 port
in any MDS113CG chip, connected by Port Mirror
signal pins, PM_DO and PM_DI, can be chosen to
be mirrored to the "Mirror Port." The mirror port can
be the first port in a MDS113CG with RMII or a
dedicated mirror port with MII, driven by the pin,
PM_DO[0:1]. Once the first RMII port of a chip is
selected to be the mirror port, it cannot be used to
serve as a data port. The configuration of port
mirroring is shown in the following diagram, based on
the current evaluation board design.
PM_DO[1:0]
PM_DI[1:0]
PM_DO[1:0]
MDS113CG
MDS113CG
PM_DENO
PM_DENI
PM_DENO
Chip 0
Chip 1
4 FE
RMII
4 FE
RMII
4 FE
RMII
1
GMII
4 FE
RMII
4 FE
RMII
4 FE
RMII
1
GMII
MII
PHY
Port 0 1 2 3
4 5 6 7
8 9 10 11
12
13 14 15 16
17 18 19 20
21 22 23 24
25
Mirror
Port
Mirror
Port
Mirror
Port
-Port 0 can be a RMII mirror port and mirror port 1-11.
-Port 13 can be a RMII mirrot port and mirror port 0-11, 14-24.
-Dedicated MII mirror port can mirror port 0-11, 13-24.
Figure 23 - Configuration of Mirror Port for MDS113CG
Physical Pins
There are 6 related pins to Port Mirroring functions:
PM_DI [1:0]
Port Mirroring Input Data Bit [1:0]
Receive the mirrored data signal from the remote MDS113CG.
PM_DENI
Port Mirroring Data Enable signal for PM_DI Input
Provide Data Enable signal for PM_DI signals
PM_DO[1:0]
PM_DENO
Port Mirroring Output Data Bit [1:0]
Transmit the mirrored data signal to remote MDS113CG.
Port Mirroring Data Enable Output.
Provide Data Enable signal for PM_DO signals
Refer to the figure on this page for connecting above pins.
40
MDS113CG
Setting Register for Port Mirroring
APMR register controls the mirrored port and the designated mirroring port. The definition of the register is
shown as follows:
31
15 14
13
12
11
0
MP Rx/ L/R
Mirror Port
0
Tx
Bit [11:0]
Bit [12]
Mirr_Port
10/100 port is chosen to be mirrored, (port bit map)
Local/Remote Indicate the mirrored port from local or remote device.
0=local 1=remote
(Note: Not support 1G port Mirroring.)
Note that at most one of bits in Bit[12:0] can be set to 1.
Bit [13]
Bit [14]
Chose_rx
MP0
Whether mirror receiving data or transmitting data
0= Transmission Mirroring, 1=Receiving Mirroring
Mirror to Port 0 (Default=0)
MP0=1 Mirror to port 0
MP0=0 Mirror not go to port 0. I.e., to PM_DO pins.
Bit [31:14]
Reserve
The following examples, based on the configuration of the figure on the previous page, illustrate how to set the
register:
Example 1: Mirroring port 1 to port 0 and Mirror transmission direction.
For Chip 0
Set APMR[11:0]=0x002 Mirrored port=1
Set APMR[12]=0
Set APMR[13]=0
Set APMR[14]=1
Local mirrored port
Transmission mirroring
Port 0 is the mirroring port
For Chip 1:
Don't Care
41
MDS113CG
Example 2: Mirroring port 1 to port 12 and Mirror receiving direction.
For Chip 0
Set APMR[11:0]= 0x002 Mirrored port= 1
Set APMR[12]=0
Set APMR[13]=1
Set APMR[14]=0
Local mirrored port
Receiving mirroring
Port 0 is not the mirroring port
For Chip 1:
Set APMR[11:0]=0x000
Set APMR[12]=1
Remote mirrored port
Set APMR[13]=Don't care Bit[13] has meaning only in the chip of mirrored port
Set APMR[14]=1 Port 13 is the mirroring port
Example 3: Mirroring port 1 to MII Mirroring port Mirror receiving direction.
For Chip 0
Set APMR[11:0]= 0x002 Mirrored port= 1
Set APMR[12]=0
Set APMR[13]=1
Set APMR[14]=0
Local mirrored port
Receiving mirroring
Port 0 is not the mirroring port
For Chip 1:
Set APMR[11:0]= 0x000
Set APMR[12]=1
Remote mirrored port
Set APMR[13]= Don't care Bit[13] has meaning only in the chip of mirrored port
Set APMR[14]=0 Port 13 is not the mirroring port
Note: Refer to “MDS113CG/MDS113CG Port Trunking and Port Mirroring Application Note”. This document
describes how to programming the port mirroring register on line via DIP switches.
42
MDS113CG
17 Register Definitions
Register Map
All registers are grouped into sets.
•
•
•
•
•
•
DEVICE CONFIGURATION
BUFFER MEMORY INTERFACE
FRAME CONTROL BUFFER
SWITCHING CONTROL
ACCESS CONTROL FUNCTIONS
MAC PORT CONTROL
Access Control:
•
•
•
•
•
•
W/R = These register bits may be read from and written to by software
W/-- = These register bits may be written to by software, but not read. Write Only
(--/R) = These register bits may be read but not written to by software. Read Only
Latched and held bits
Clear bits
Permanently set bits
All registers are 32-bit wide. They are classified in the following tables:
Tag Description
1. Device Configuration Registers (DCR)
ADDRESS
W/R
GCR
Global Control Register
7C0
7C0
7C4
7C8
W/--
--/R
DCR0
DCR1
DCR2
Device Status Register
Signature & Revision & ID Register
Device Configuration Register
W/R
W/R
2. Buffer Memory Interface
MBCR
Multicast Buffer Control Register
79C
7B8
7BC
W/R
W/R
W/R
Reserve
Reserve
Must Set to “0x0001 0008”
Must Set to “0x0001 0000”
3. Frame Control Buffers Management
FCBSL
FCBST
BCT
FCB Stack Size Limit
740
744
74C
750
W/R
W/R
W/R
W/R
Frame Ctrl Buffer Stack – Buffer Low Threshold
Buffer Counter Threshold
BCHL
Buffer Counter Hi-Low Selection
4. Switching Control
FCR
MCAT
PTR
Flooding Control Register
6DC
6E0
6EC
W/R
W/R
W/R
MCT Aging Timer
Pacing Time Regulation
Table 8 - MDS113CG Register Map (1 of 2)
43
MDS113CG
Tag
Description
ADDRESS
W/R
5. Access Control Function Group 1 (Chip Level controls)
ATTL
Transmission Timing & Threshold Control Register
Flow Control Register
650
670
67C
600
604
608
60C
610
614
618
61C
620
624
628
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
AFCR
AMCT
MAC Control Frame Type Code Register
Base MAC Address Register – Byte[3,0]
Base MAC Address Register – Byte[5,4]
MAC Offset Address Register Port[0:7]
MAC Offset Address Register Port[12:8]
Timer For SOF Check
ADAR0
ADAR1
ADAOR0
ADAOR1
ACKTM
AFCOFT10
AFCOFT100
AFCOFT1000
AFCHT10
AFCHT100
AFCHT1000
Flow Control Off Time for 10 port
Flow Control Off Time for 100 port
Flow Control Off Time for Gig port
Flow Control Holding Time for 10 port
Flow Control Holding Time for 100 port
Flow Control Holding Time for Gig port
6. Access Control Function Group 2 (Chip Level controls)
APMR
Port Mirroring Register
5C0
5C8
5CC
5D0
5D4
5D8
5DC
5E0
5E4
598
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
THKM0
THKM1
THKM2
THKM3
THKM4
THKM5
THKM6
THKM7
LEDR
Trunking Forward Port Mask 0 (hash key=0)
Trunking Forward Port Mask 1 (hash key=1)
Trunking Forward Port Mask 2 (hash key=2)
Trunking Forward Port Mask 3 (hash key=3)
Trunking Forward Port Mask 4 (hash key=4)
Trunking Forward Port Mask 5 (hash key=5)
Trunking Forward Port Mask 6 (hash key=6)
Trunking Forward Port Mask 7 (hash key=7)
LED Register
7. Ethernet MAC Port Control Registers – (substitute [N] with Port Number, N = {0..12})
ECR1 MAC Port Configuration Register [N*4]4
W/R
44
MDS113CG
Register Definitions
Device Configuration Register
GCR - Global Control Register
•
•
Access:
Zero-Wait-State,Direct Access,Write only
Address: h7C0
31
24 23
20 19
16 15
12 11
8 7
4 3 2
0
Op-Code
Bit[2:0] Op-Code 3-bit Operation Control Code
Op-Code
Command
Description
000
001
Clr RST
Clear Device Reset: — Allows state machines to exit from RESET state and to
initialize their internal control parameters if necessary.
RESET
Device Reset: — Resets all internal state machines of each device and stays
in RESET state (except the Processor Bus Interface logic)
010
011
1XX
EXEC
Execution: — Allows state machines to start their normal operations.
--
--
No-Op
No-Op
Bit[31:4] Reserved
DCR0 - Device Status Register
•
•
Access:
Zero-Wait-State,Direct Access,Read only
Address: h7C0
31
8 7
6
5
4 3
2
0
Status
Bit[1:0] Status
2-bit Device Operation Status Code
Status State
Description
01
10
RESET
EXEC
Device Reset: — Device is in RESET state
Execution: — Device is under normal operation
45
MDS113CG
DCR1 - Signature, Revision, & ID Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h7C4
31
25 24
20 19
16 15
12 11
8 7
4 3
2
0
Dev_ID
Signature
Rev
Bit[3:0] Device Revision Code
Bit[7:4] Reserved
Bit[15:8] Signature 8-bit Device Signature
Bit[19:16] Reserved
Bit[24:20] DEV_ID
Bit[31:25] Reserved
5-bit Device ID (Read/Write)
DCR2 - Device Configuration Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h7C8
31
27 26 25
22 21 20 19 18 17
10 9 8
7 6 5 4
3
2 1
0
FE and MAC
MT ML SM
SC
Bit[1:0] SC
System Clock Rate
Default = 00
00= 100Mhz
10=90Mhz
01 = 120Mhz
11= 80Mhz
Bit[2]
Bit[3]
Reserved
SM
System Configuration mode
0=Nonblocking (For MDS113CG, Always equal to 0)
1=Blocking
SRAM Memory Characteristics
Bit[4]
ML
Buffer Memory Level, which can be either 2 chips or 4 chips.
0 = 2 memory chips (one bank)
1 = 4 memory chips (two banks)
Default = 0
Bit[6:5] MT
Memory Chip Type
Default = 01
00 = 64K x 32-bit
10 = 256K x 32-bit
01 = 128K x 32-bit
11 = 512K x 32-bit
Bit[8:7] Reserved
46
MDS113CG
Search Engine Configuration
Bit[9]
SE_AGEN Aging enable, if which is true, the old MCT can be aged out.
Default = 1
0 = disable aging
1 = enable aging
Frame Engine and MAC Configuration
Bit[21:10]
Bit[22]
Reserved
BC_EN
Buffer counter enable
0 = Disable (no head of
line control
1 = enable
Bit[23]
Bit[24]
Reserved
SEL_PCS
Default =0
0 = Use external PCS
1 = Use internal PCS in
the chip
Bit[25]
Link_GT
TX LED will be off when the link is down Default =0
and this bit is 0
0 = Gate 0ff TX_En when
Link down
1 = Not Gate off TX_En
when Link down
Bit[31:26]
Reserved
47
MDS113CG
Buffer Memory Interface Register
MBCR- Multicast Buffer Control Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h79C
31
22 21 20 19
11 10
5 4
0
MAX_CNT_LMT
RMC_BUF_RSV
MAX_MC_FD
Bit[4:0]
MAX_MC_FD
Maximum Number of Multicast Frames
allowed for forwarding.
Bit[10:5]
Bit[19:11]
Bit[31:20]
RMC_BUF_RSV
MAX_CNT_LMT
Reserved
Number of buffers reserved for receiving remote
Multicast Frames.
Maximum Number of Multicast Frames allowed
per device
Reserve Register 1
•
•
Access
Non-Zero-Wait-StateDirect-AccessWrite/Read
Address: h7B8
31
16 15
4 3
2 1
0
0x0001
0x0008
MUST BE SET TO “0X00010008”
Reserve Register 2
•
•
•
Access
Non-Zero-Wait-StateDirect-AccessWrite/Read
Address: h7BC
3116
15
3 2
1
0
0x0001
0x0008
MUST BE SET TO “0X00010000”
48
MDS113CG
Frame Control Buffers Management Register
FCBSL - FCB QUEUE
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h740
18 17 16
11 10
9
0
Aging Timer Base
Max# of FCB Buffer
Bit[10:0]
Defines Max # of FCB Buffers
Size Range: 1 entry, to 1024 entries
Bit[17:11]
Aging Timer
Base
Defines the time interval between scanning of FCB
Buffers for aged buffers
Aging Time = (Number of valid FCB Buffers* Aging Timer
Base) msec
FCBST - FCB Queue - Buffer Low Threshold
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h744
31
23
16 15
11
7
6
5
0
BLowTH
Bit[5:0]
Buf_Low_Th Buffer Low Threshold – The number of frame control buffer
handles left in the Queue to be considered as running low
and trigger the interrupt to the HISC.
Bit[31:6]
Reserved
49
MDS113CG
BCT - (FCB) Buffer Counter Threshold
•
•
Access
Non-Zero-Wait-StateDirect-AccessWrite/Read
Address: h74C
31
19
10 9
0
Hi Limit
Low Limit
Bit[9:0]
Low_Limit
HI_Limit
Low limit number of frames to each destination port (i.e.,
Source port limits the # of FCB used by each destination
port)
Bit[10:19]
High limit number of frames to each destination port (i.e.,
Source port limits the # of FCB used by each destination
port)
BCHL - Buffer Control Hi-Low Selection
•
•
Access
Non-Zero-Wait-StateDirect-AccessWrite/Read
Address: h750
31
25
13 12
0
Bit[12:0]
Lp_Hi_Low
Sel
Selection for Low or High Limit of Buffer
Counter for Local device
13 bits maps to 13 ports in Local Device
1 = select hi limit
0 = select low limit
Bit[25:13]
Rp_Hi_Low
Sel
Selection for Low or High Limit of Buffer
Counter for Remote device
13 bits maps to 13 ports in Remote
Device
1 = select hi limit
0 = select low limit
50
MDS113CG
Switching Control Register
Flooding Control Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h6DC
31
24 23
16 15 14 12 11
8
7
0
Time
Base
FLDR
Bit[0:7] Reserved
Bit[11:8] FLDR
Flooding Rate
Restricts the number of flooding unicast frames within the Time window
Bit[14:12]Time Base Defines the time window used by FLDR
000 = 100us
100 = 1.6ms
001 = 200us
101 = 3.2ms
010 = 400us
110 = 6.4ms
011 = 800us
111 = 100us
Bit[31:15] Reserved
MCAT- MCT Aging Timer
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h6E0
31
20 19
0
MCT Aging Timer
Bit[19:0] When the value is reached, it ages out
Default=0 msec (unit=msec) Must be configured to not zero value.
Suggestion value: 5msec.
PTR - Pacing Time Regulation
•
•
•
Access
Non-Zero-Wait-StateDirect-AccessWrite/Read
Address: h6EC
Use for Pacing traffic to Remote Ports via XpressFlow Pipe or Local transmission
31
15
12 11
MC_TM
8 7
4 3
0
UC_TM
Default =5
Gigabit port timer Default =6
G_TM
100_TM
Bit[3:0] 100_TM
Bit[7:4] g_TM
Bit[11:8] mc_TM
Bit[15:12] uc_TM
100M port timer
Multicast timer
Unicast timer
Default =5
Default =5
Unit time = 80 nsec (for 64Bytes Frame).
Note that Frame Engine determine the tic value dependent upon the frame. If short frame, it takes above value.
For long frame (> 64 frame), it will double the above value as the reference.
51
MDS113CG
Access Control Function
ATTL - Transmission Timing Control
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h650
24
22 21
14 13
5 4
0
TxFIFO
depart_time
qmt_cnt
Threshold[7:0]
Bit[4:0]
Transmission queue aging time out counter
frame latest departure time
Bit[13:5]
Bit[21:14]
TXFIFOT
Transmission FIFO Threshold in Bytes (Default =0) Only for
100M ports
Unit=8Bytes
0= Cut Through at the destination 100M port
When the value does not equal zero, it indicates the port cannot start sending frames out, until the TxFIFO
reaches the threshold or EOF.
52
MDS113CG
AFCR - Flow Control Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h670
31
24 23
16 15 14 13 12
10 98 7
0
X
F
A
XON_thd
N
E
E
Bit[9:0] Reserved
Bit[12:10] XON_Thd Defines the minimum # of free Frame Buffers before transmitting XON flow
control frame.
min.#offreeFCB
--------------------------------------
XON_Thd =
8
Bit[13]
Bit[14]
Queue Aging EnableTX queue aging function enable
Flush EnableWhen stack is full, enable flush procession
0 = disable
XON EnableFull Duplex XON enable
0 = disable 1 = enable
1 = enable
Bit[15]
Bit[31:16] Reserved
AMCT - MAC Control Frame Type Code Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h67C
31
24 23
16 15
8 7
0
Frame Type
• 2-byte MAC Control Frame Type Code defined by IEEE 802.3X Full Duplex Flow Control Standard
53
MDS113CG
ADAR[1:0] - Base MAC Address Registers
•
The 6-byte MAC Address is stored in two 32-bit registers
• ADAR0
• Address:
• ADAR1
• Address:
Access:
MAC Address Byte[3:0]
h600
MAC Address Byte[5:4]
h604
•
Non-Zero-Wait-State,Direct Access,Write/Read
31
24 23
16 15
11
MAC 1
8 7
3
MAC 0
MAC 4
0
ADAR0
ADAR1
MAC3
MAC 2
MAC 5 0 0 0 0
•
•
•
These two registers define the base MAC address of the device.
Bit[3:0] of Byte 0 is always set to 0.
MAC address for each port is defined by
• MAC Address for Port n = Base MAC Address + MAC Offset[n] where n = {0..12}
• MAC Offset[n] is defined by the following registers
ADAOR0 - MAC Offset Address Register 0
•
•
•
MAC Offset Address for Port[7:0], 4-bit per port
Access: Non-Zero-Wait-State,Direct Access,Write/Read
Address: h608
31
28 27
24 23
20 19
16 15
12 11
8 7
4 3
0
Port7_offset Port6_offset Port5_offset Port4_offset Port3_offset Port2_offset Port1_offset Port0_offset
Bit[3:0] MAC Offset address for Port 0
Bit[7:4] MAC Offset address for Port 1
Bit[11:8] MAC Offset address for Port 2
Bit[15:12] MAC Offset address for Port 3
Bit[19:16] MAC Offset address for Port 4
Bit[23:20] MAC Offset address for Port 5
Bit[27:24] MAC Offset address for Port 6
Bit[31:28] MAC Offset address for Port 7
Usage: All ports in the same device share the 44 MSBs, MAC[47:4] in ADAR[0:1], while the 4 LSBs, MAC
Offset[3:0] can be assigned as follows: If the device supports port-trunking, the ports in the same trunk group
share the same MAC[3:0]. The value of MAC[3:0] is assigned by the smallest port nubmer in the Trunk Group.
Otherwise, MAC[3:0] is fixed for all devices ( i.e. only one MAC[3:0] address for the whole system).
54
MDS113CG
ADAOR1- MAC Offset Address Register 1
•
•
•
MAC Offset Address for Port[12:8], 4-bit per port
Access: Non-Zero-Wait-State,Direct Access,Write/Read
Address: h60C
31
28 27
24 23
20 19
16 15
12 11
8 7
4 3
0
Port12_
offset
Port11_
offset
Port10_
offset
Port9_
offset
Port8_
offset
Bit[3:0] MAC Offset address for Port 8
Bit[7:4] MAC Offset address for Port 9
Bit[11:8] MAC Offset address for Port 10
Bit[15:12] MAC Offset address for Port 11
Bit[19:16] MAC Offset address for Port 12
Bit[31:20] Reserved
ACKTM - Timer for SOF Checking
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h610
31
9
0
XOFF_CKTM
Bit[9:0] XOFF_CKTMThe time out value to check SOF after XOFF
Bit[31:10] Reserved
AFCHT10 - Flow Control Hold Time of 10MBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h620
31
16 15
0
HBK_TM_10
Bit[15:0] HBK_TM_10Holding time to remote station for head of line blocking control for 10M port.
Bit[31:16] Reserved
55
MDS113CG
AFCHT 100 - Flow Control Hold Time of 100MBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h624
31
24 23
16 15
8 7
0
FL_OFF_100M
Bit[15:0] HBK_TM_100Holding time to remote station for head of line blocking control for 100M port.
Bit[31:16] Reserved
AFCHT1000 - Flow Control Hold Time of GIGBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h628
31
16 15
0
HBK_TM_G
Bit[15:0] HBK_TM_GHolding time to remote station for head of line blocking control for 1G port.
Bit[31:16] Reserved
Flow Control Off Time of 10MBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h614
31
24 23
16 15
8 7
0
FL_OFF_10M
Bit[15:0] FL_OFF_10MOff time to remote station for 10M Port.
Bit[31:16] Reserved
AFCOFT100 - Flow Control Off Time of 100MBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h618
31
24 23
16 15
8 7
0
FL_OFF_100M
Bit[15:0] FL_OFF_100MOff time to remote station for 100M Port.
Bit[31:16] Reserved
56
MDS113CG
AFCOFT100 - Flow Control Off Time of GIGBS Port
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h61c
31
24 23
16 15
8 7
0
FL_OFF_G
Bit[15:0] FL_OFF_G Off time to remote station for 1G Port.
Bit[31:16] Reserved
Access Control Function Group 2 (Chip Level)
APMR- Port Mirroring Register
•
•
Access:
Non-Zero-Wait-State,Direct Access,Write/Read
Address: h5C0
31
15 14 13 12 11
MP Rx/ L/R
0
Mirror Port
0
Tx
Bit[11:0] Mirr_Port
The 10/100 port chosen to be mirrored
Bit[12]
Local/Remote
Indicates the mirrored port is from a local or remote device.
0=local1=remote
(Note: Does not support 1G port Mirroring.)
Indicates whether the mirror is receiving data or transmitting data
Mirror to Port 0 (Default=0)
Bit[13]
Bit[14]
Chose_rx
MP0
MP0=1 Mirror to port 0
MP0=0 Mirror not go to port 0
Bit[31:15] Reserved
57
MDS113CG
THKM[0:7] - Trunking Forwarding Port Mask 0-7
•
•
•
•
•
•
•
•
Eight Trunking Hash Key Mask Registers shared the same format.
• THKM0
Forwarding Port mask for hash key 0
Forwarding Port mask for hash key 1
Forwarding Port mask for hash key 2
Forwarding Port mask for hash key 3
Forwarding Port mask for hash key 4
Forwarding Port mask for hash key 5
Forwarding Port mask for hash key 6
Forwarding Port mask for hash key 7
Address: h5C8
• THKM1
Address: h5CC
• THKM2
Address: h5D0
• THKM3
Address: h5D4
• THKM4
Address: h5D8
• THKM5
Address: h5DC
• THKM6
Address: h5E0
• THKM7
•
•
Address: h5E4
Access: Non-Zero-Wait-State,Direct Access,Write/Read
31
11
0
TK_MSK
Bit[11:0] TK_MSK Port trunk mask for trunking hash key
Bit[31:12] Reserved
•
CPU sets up this table as follows:
1. Set all bits not in Trunk Groups to 1
2. Set all bits in the Trunk Group to 0
3. Pick one forwarding port per trunk group and turn the corresponding bit to 1 (each Hash Key may have differ-
ent forwarding ports, the rule to pick forwarding ports is up to the CPU).
Usage: These masks are used to prevent flooded or multicast packets from being transmitted out with more
than one port on a trunk. The Trunking Hash Key is used to select the proper mask(for load distribution). The
mask value will be set up to mask off all but one port within each trunk group.
58
MDS113CG
LEDR - LED Register
•
•
Access: Non-Zero-Wait-State,Direct Access,Write/Read
Address:h598
31 30
SS
28 27 26 25 24 23
LCLK HT
16 15
8 7
0
Bit[23:0] Reserved
Bit[25:24] HT
Holding time for LED signal (Default=00)
00=8msec
01=16msec
11=64msec
10=32msec
Bit[27:26] LCLK
Bit[30:28] Reserved
LED Clock frequency (Default=00)
00=100M/64=1.56Mhz 01=100M/128=0.78Mhz
10=100M/512=0.195Mhz11=100M/1024=0.0976Mhz
Bit[31]
SS
Start Shift the status bits out from the master device.
This bit has no effect on the slave chip.
Refer to LED design document for detail.
59
MDS113CG
Ethernet MAC Port Control Registers
•
•
•
•
One set for each Ethernet MAC Port[12:0]
MII related controls applies to Port[1:0] only
Port 12 is always dedicated to GMAC
Port is disabled when both RR & XR bits are set.
ECR1 - MAC Port Configuration Register
•
•
Access: Non-Zero-Wait-State,Direct Access,Write/Read
Address:h0x1*4x: port number
h004
h044
h084
h0c4
h104
h144
h184
h1c4
h204
h244
h284
h2c4
h304
ECR1_p0
ECR1_p1
ECR1_p2
ECR1_p3
ECR1_p4
ECR1_p5
ECR1_p6
ECR1_p7
ECR1_p8
ECR1_p9
ECR1_p10
ECR1_p11
ECR1_p12
31
24 23
17 16 15
8
7 6 5 4 3 2
0
T
TG ID
E
Configuration Bits
Trunking
Port Trunking ID Bits
Bit[0:2]
Bit[3]
TGID
TE
Group ID
Trunk Enable
0= Trunk disable
1 = Trunk Enable
Unicast Blocking Control Bits
Bit[6:4]
Reserved
60
MDS113CG
Physical Layer Control Bits
Bit[7]
10M
10M or 100M
1 = 10Mbps
0 = 100Mbps
Bit[8]
Bit[9]
Bit[10]
Reserved
Full_Duplex Enables full duplex mode Default = 0 - Half Duplex
FDX_PolaritySelects the output polarity of Full_Duplex control signal
0 = Low true (Default)
1 = High true
Bit[11]
Bit[12]
Bit[13]
Int_Lpback Setting this bit causes internal connect
TXCLK, TXD, TXD[0:3] to RXCLK, RXD, RXD[0:3]
Default =0 - Disable
Ext_Lpback Setting this bit indicate an external loop-back
(Connection of TXCLK, TXD[0:3] to RXCLK, RXD[0:3] are required)
Default =0 - Disable
FC_Enable Flow Control Enable
Default =0 - Disable
When enabled:
•
In Half Duplex mode, the MAC Transmitter applies backpressure for flow control.
• In Full Duplex mode, the MAC Transmitter sends Flow-Control frames when necessary. The MAC
Receiver interprets and processes incoming Flow Control frames. The MAC Receiver marks all Flow
Control Frames. Receive DMA discards the received Flow Control Frame and send status reports to
the Switch Manager for statistic collection.
When Disabled:
• The MAC Transmitter asserts flow control neither by sending Flow Control frames nor by jamming
collision.
• The MAC Receiver still interprets and processes the Flow-Control frames. The MAC Receiver marks
all Flow Control frames. Receive DMA discards the received Flow Control frames and send a status
report to the Switch Manager for statistic collection.
Bit[14]
Link_PolaritySelects the input polarity of Link Status signal
0 = Low true (Default)1 = High true
Bit[15]
Tx_Enable Enables MAC Transmitter for transmission
Default =0 - Disable
Bit[31:16]
Reserved
61
MDS113CG
Note: When external heat sink is attached, qJA is
reduced by about 8-12% in still air.
18 DC Electrical Characteristics
Absolute Maximum Ratings
Heat Resistance
Voltage
Package
BGA)
456 HBGA (Heatslug
Supply Voltage VDD21 with Respect to VSS
V to +3.6 V
+3.0
Storage Temperature
Operating Temperature
qJC: 3.3 C/W
-65C to +150C
0C to +70C
Supply Voltage VDD22 with Respect to VSS
+2.38 V to +2.75 V
Voltage on 5V Tolerant Input Pins
(VDD21 + 3.3 V)
-0.5
-0.5
-0.5
V
to
to
to
Maximum Junction Temperature125C
Voltage on 5V Tolerant Input Pins
(VDD22 + 2.5 V)
V
V
Air Velocity
θ
(C/W)
JA
Voltage on Other Pins
(VDD2 + 0.3 V)
0 m/s
1 m/s
2 m/s
12.0
11.0
9.6
Caution: Stresses above those listed may cause
permanent device failure. Functionality at or above
these limits is not implied. Exposure to the Absolute
Maximum Ratings for extended periods may affect
device reliability.
Table 1 - Thermal Data for Cooled Chip
DC Electrical Characteristics
VDD21 = 3.0 V to 3.6 V (3.3v +/- 10%)TAMBIENT = 0 C to +70 C. VDD22 = 2.5V +10% - 5%
Preliminary
Symbol
Parameter Description
Min
TypE
Max
Unit
f
I
I
Frequency of Operation ( -50)
100
MHz
mA
osc
Supply Current – @ 100 MHz (VDD2 =3.3 V)
Supply Current – @ 100 MHz (VDD2 =2.5 V)
Output High Voltage (CMOS)
TBD
DD1
DD2
V
V
V
VDD2 - 0.5
V
V
V
OH
Output Low Voltage (CMOS)
0.5
OL
Input High Voltage (TTL 5V tolerant)
VDD2 x
VDD2 +
2.0
IH-TTL
1
70%
V
Input Low Voltage (TTL 5V tolerant)
VDD2 x
30%
V
IL-TTL
IH-5VT
I
Input Leakage Current (0.1 V < V < VDD2)
TBD
µA
IN
(all pins except those with internal pull-up/pull-
down resistors)
I
I
Output Leakage Current (0.1 V < V
< VDD2)
TBD
TBD
µA
µA
IL-5VT
LI
OUT
Input Leakage Current V = VDD2 - 0.1 V
IH
(pins with internal pull-down resistors)
I
Input Leakage Current V = 0.1 V
TBD
µA
LO
IL
(pins with internal pull-up resistors)
C
C
C
Input Capacitance
5
5
7
pF
pF
pF
IN
Output Capacitance
OUT
I/O
I/O Capacitance
Table 9 - Recommended Operation Conditions
62
MDS113CG
19 AC Specifications
XPipe Interface
X_DCLK
I
X_DCLK
I
X17
X19
X21
X23
X1-max
X1-min
X18
X20
X22
X24
X_DI[31:0]
X_DENI
X_FCI
X_DCLK
0
X4-max
X4-min
L_A[19:2]
L_ADSC#
X3-max
X3-min
X2-max
X2-min
L_BW[7:0]#
Figure 24 - XPIPE Interface -
Output Valid Delay Timing
Figure 25 - XPIPE Interface -
Output Valid Delay Timing
S_CLK
X15
X18
X_DCLKI
-100MHz
Symbol
Parameter
MIN (ns)
MAX (ns) Note:
X1
X_DCLKO output valid delay
X_DO[31:0] output valid delay
X_DENO output valid delay
X_FCO output valid delay
X_DCLKI input set-up time
X_DCLKI input hold time
X_DI[31:0] input set-up time
X_DI[31:0] input hold time
X_DENI input set-up time
X_DENI input hold time
1
1
1
1
3
0
3
0
3
0
3
0
5
5
5
5
C = 30pf
L
X2
C = 30pf
L
X3
C = 30pf
L
X4
C = 30pf
L
X15
X16
X17
X18
X19
X20
X21
X22
Reference S-CLK
Reference S-CLK
X_FCI input set-up time
X_FCI input hold time
Table 10 - AC Characteristics - XPIPE Interface
63
MDS113CG
Control Bus Interface
P_CLK
P_RST#
P_ADS#
P1
P3
P2
P4
P_CLK
P_D[31:0]
P_RDY#
P_INT
P16-max
P16-min
P5
P7
P9
P6
P8
P_RWC
P_CSI
P17-max
P17-min
P18-max
P18-min
P10
P_A[10:1]
P_D[31:0]
P11
P12
Figure 26 - Control Bus Interface -
Output Valid Delay Timing
Figure 27 - Control Bus Interface - Input
Setup and Hold Timing
64
MDS113CG
-66MHz
Min Max
(ns) (ns)
Symbol
Parameter
Note:
P_CLK
P1
P2
P_RST# input setup time
P_RST# input hold time
P_ADS# input setup time
P_ADS# input hold time
P_RWC# input setup time
P_RWC# input hold time
P_CSI# input setup time
P_CSI# input hold time
P_A[10:1] input setup time
P_A[10:1] input hold time
P_D[31:0]# input setup time
P_D[31:0]# input hold time
P_REQC# input setup time
P_REQC# input hold time
P_BRGI# input setup time
P_BRGI# input hold time
P_D[31:0] output valid delay
P_A[10:1] output valid delay
P_RWC# output valid delay
P_ADS# output valid delay
P_RDY# output valid delay
P_INT output valid delay
P_GNTC output valid delay
P_BRGO# output valid delay
P_CSO# output valid delay
P_RDY#
P3
6
2
6
2
6
2
6
2
6
2
6
2
6
2
P4
P5
P6
P7
P8
P9
P10
P11
P12
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
2
2
2
2
2
2
2
2
2
12 C = 65pf
L
9
9
9
9
9
9
9
9
C = 50pf
L
C = 50pf
L
C = 50pf
L
C = 50pf
L
C = 30pf
L
C =20pF
L
C =20pF
L
C =20Pf
L
P_RDY#
FS_CS
P_BRDY#
P_BLAST#
65
MDS113CG
Local SBRAM Memory Interface
L_CLK
L_D[63:0]
L_A[19:2]
L_ADSC#
L_BW[7:0]#
L_WE[1:0]#
L_OE#
L3-max
L3-min
L4-max
L4-min
L6-max
L6-min
L_CLK
L1
L2
L7-max
L7-min
L_D[63:0]
L8-max
L8-min
L9-max
L9-min
Figure 28 - Local Memory Interface -
Input Setup and Hold Timing
Figure 29 - Local Memory Interface -
Output Valid Delay Timing
-100MHz
Symbol
Parameter
Min (ns)
Max (ns)
Note:
C = 50pf
L_CLK
L
L1
L2
L3
L4
L6
L7
L8
L9
L_D[63:0] input set-up time
L_D[63:0] input hold time
3
1.5
2
L_D[63:0] output valid delay
L_A[20:3] output valid delay
L_ADSC# output valid delay
L_BW[7:0]# output valid delay
L_WE[1:0]#output valid delay
L_OE[1:0]# output valid delay
7
7
7
7
7
1
C = 30pf
L
2
C = 50pf
L
2
C = 50pf
L
2
C = 30pf
L
2
C = 30pf
L
0
C = 30pf
L
Table 11 - AC Characteristics - Local Memory Interface
66
MDS113CG
-50MHz
Symbol
Parameter
MIN (ns)
MAX (ns)
Note:
PM1
M_CLKI
Reference Input
Clock
PM2
PM3
PM4
PM5
PM6
PM7
PM_DENI Input Setup Time
PM_DENI Input Hold Time
PM_DI[1:0] Input Setup Time
PM_DI[1:0] Input Hold Time
PM_DENO Output Delay Time
PM_DO[1:0] Output Delay Time
1.5
2
1.5
2
2
11
11
C = 30 pF
L
2
C = 30 pF
L
Table 12 - AC Characteristics - Port Mirroring Interface
-50MHz
Symbol
Parameter
MIN (ns)
MAX (ns)
Note:
M1
M_CLKI
Reference Input
Clock
M2
M3
M4
M5
M6
M7
M[11:0]_RXD[1:0] Input Setup Time
M[11:0]_RXD[1:0] Input Hold Time
M[11:0]_CRS_DV Input Hold Time
M[11:0]_TXEN Output Delay Time
M[11:0]_TXD[1:0] Output Delay Time
M[11:0]_LINK Input Setup Time
1.5
2
1.5
2
11
11
C = 30 pF
L
2
C = 30 pF
L
Table 13 - AC Characteristics - Reduced Media Independent Interface
67
MDS113CG
-125Mhz
Symbol
Parameter
MIN (ns)
MAX (ns)
Note:
GREF_CLK GREF_CLK
Gigabit Ref Clock
G1
M[12]_RXD[7:0] Input Setup Times
M[12]_RXD[7:0] Input Hold Times
M[12]_RX_DV Input Setup Times
M[12]_RX_DV Input Hold Times
M[12]_RX_ER Input Setup Times
M[12]_RX_ER Input Hold Times
M[12]_CRS Input Setup Times
M[12]_CRS Input Hold Times
2
0
2
0
2
0
2
0
2
0
1
1
1
G2
G3
G4
G5
G6
G7
G8
M[12]_COL Input Setup Times
M[12]_COL Input Hold Times
G9
G12
G13
G14
G16
M[12]_TXD[7:0] Output Delay Times
M[12]_TX_EN Output Delay Times
M[12]_TX_ER Output Delay Times
M[12]_LNK Input Setup Times
5
5
5
C = 20pf
L
C = 20pf
L
C = 20pf
L
Table 14 - AC Characteristics - Giabit Media Independent Interface
68
MDS113CG
-125Mhz
Symbol
Parameter
MIN (ns)
MAX (ns)
Note:
GREF_CLK GREF_CLK
Gigabit Reference
Clock
GP1
GP2
GP_RXD[7:0] Input Setup Times
GP_RXD[7:0] Input Hold Times
GP_RXD[8] Input Setup Times
GP_RXD[8] Input Hold Times
GP_RXD[9] Input Setup Times
GP_RXD[8] Input Hold Times
GP_RXCLK1 Input Setup Times
GP_RXCLK1 Input Hold Times
GP_RXCLK0 Input Setup Times
GP_RXCLK0 Input Hold Times
GP_TXD[7:0] Output Delay Times
GP_TXD[8] Output Delay Times
GP_TXD[9] Output Delay Times
GP_TXCLK Output Delay Times
GP_LNK Input Setup Times
2
0
2
0
2
0
2
0
2
0
1
1
1
GP3
GP4
GP5
GP6
GP7
GP8
GP9
GP10
GP11
GP12
GP13
GP14
GP15
5
5
5
C = 20pf
L
C = 20pf
L
C = 20pf
L
C = 20pf
L
Table 15 - AC Characteristics - Physical Media Attachment Interface
69
MDS113CG
Variable FREQ.
MIN (ns) MAX (ns)
Note:
Symbol
Parameter
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE_DI Input Setup Times
LE_DI Input Hold Times
LE_SYNCI Input Setup Times
LE_SYNCI Input Hold Times
LE_CLKO Output Valid Delay
LE_DO Output Valid Delay
LE_SYNCO Output Valid Delay
C = 30pf
L
C = 30pf
L
C = 30pf
L
Table 16 - AC Characteristics - LED Interface
70
MDS113CG
20 Mechanical Data
Packaging Information
- B -
26 24 22 20 18 16 14 12 10
25 23 21 19 17 15 13 11
8
6
4
2
9
7
5
3
1
Pin 1 I.D.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
- A -
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
35.00
31.75
0.05
- C -
0.50 / 0.70
2.50
max
Figure 30 - 456-PIN BGA Packaging Diagram
71
http://www.zarlink.com
World Headquarters - Canada
Tel: +1 (613) 592 0200
Fax: +1 (613) 592 1010
North America - West Coast
North America - East Coast
Tel: (978) 322-4800
Tel: (858) 675-3400
Fax: (858) 675-3450
Fax: (978) 322-4888
Asia/Pacific
Tel: +65 333 6193
Europe, Middle East,
and Africa (EMEA)
Fax: +65 333 6192
Tel: +44 (0) 1793 518528
Fax: +44 (0) 1793 518581
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is
believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any
such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights
owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in
combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any
order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information
appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or
suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of
use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such
information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or
parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and
materials are sold and services provided subject to Zarlink Semiconductor’s conditions of sale which are available on request.
2
2
2
Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in an I C System, provided that the system conforms
2
to the I C Standard Specification as defined by Philips
Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001, Zarlink Semiconductor Inc. All rights reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明