PD63000AC-0400 [MICROSEMI]
Microcontroller,;
| 型号： | PD63000AC-0400 |
| 厂家： | 
Microsemi |
| 描述： | Microcontroller, 微控制器 |
| 文件： | 总4页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD63000
8-bit PoE Microcontroller Unit
Source Control Drawing
Description _________________
System Connectivity __________
PowerDsine’s™ Microcontroller Unit, PD63000, is a
member of Motorola’s HCS08 Family of 8-bit
microcontroller units (MCUs). This MCU uses the
enhanced HCS08 core and is pre-programmed with a
special proprietary application. It is used in
conjunction with PowerDsine’s PD64012 PoE
Manager in Ethernet switches and Midspans to allow
next generation network devices to share power and
data over the same cable, according to IEEE 802.3af.
When used in conjunction with the PD63000, the
PD64012 operates in Enhanced mode.
In order to properly relate to the MCU in this
document, a diagram of basic system connectivity is
presented, hereafter. The various port groups are
depicted along with their respective port lines. This
block diagram can be compared with the application
schematics from PowerDsine’s Application Notes and
Data Sheets, so as to understand the circuits used.
V
V
REFH
DDAD
MC9S08GBxx
C
BYAD
0.1uF
PTA0/KBIP0
PTA1/KBIP1
PTA2/KBIP2
V
SSAD
SYSTEM
POWER
V
V
DD
REFL
PORT
A
PTA3/KBIP3
PTA4/KBIP4
PTA5/KBIP5
PTA6/KBIP6
PTA7/KBIP7
V
DD
SS
C
BLK
10uF
C
BY
0.1uF
3V
The MCU features a 1 Mb/s SPI to each of the PoE
Managers and a communication interface with the
host CPU via UART or I2C protocol. The I/O lines, the
SPI bus and the control signals are loaded by 50-
ohm serial resistors. The MCU runs at about 10 MHz,
providing a 1 MHz clock frequency to the SPI bus. An
external resonator is used for clock generation.
V
PTB0/AD0
R
R
S
F
PTB1/AD1
PTB2/AD2
XTAL
X1
PORT
B
PTB3/AD3
C1
C2
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
EXTAL
BACKGROUND HEADER
I/0 AND
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
V
DD
1
BKGD/MS
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PORT
C
PTC3/SCL
PTC4
RESET
IRQ
OPTIONAL
MANUAL
RESET
The device is a Motorola’s MC9S08GB60CFU
microprocessor control unit – this is an 8-bit device
composed of standard on-chip peripherals including:
an 8-bit CPU, a 60-kbyte flash EEPROM, a 4-kbyte
RAM, an asynchronous serial communications
interface, a serial peripheral interface, a 3-channel
timer and a 5-channel timer. In addition this chip
includes: an 10-bit analog-to-digital converter.
PTC5
PTC6
ASYNC INTERRUPT
INPUT
PTC7
PTG0/BKDG/MS
PTG1/XTAL
PTG2/EXTAL
PTD0/TPM1CH0
PTD1/TPM1CH1
PTD2/TPM1CH2
PORT
D
PORT
G
PTG3
PTG4
PTD3/TPM2CH0
PTD4/TPM2CH1
PTD5/TPM2CH2
PTD6/TPM2CH3
PTG5
PTG6
PTG7
PTD7/TPM2CH4
PTF0
PTF1
PTF2
PTE0/TxD1
PTE1/RxD1
PORT
F
PTE2/SS
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
PTE6
PTF3
PORT
E
PTF4
PTF5
PTF6
PTF7
PTE7
Pin Configuration _____________
Program Burn-in ______________
Initial burn-in is accomplished via the background
header (BDM), by PowerDsine. Thereafter the MCU
is downloaded with a special Powerdsine program
referred to as the PD64012 Enhanced Mode
Software. This software can be downloaded via the
UART port (pins 14 & 15, PTE0/TxD1 & PTE1/RxD1)
or via the I2C port (pins 5 & 6, SDA & SCL.).
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48 PTA2/KBIP2
PTA1/KBIP1
PTA0/KBIP0
PTF7
RESET
PTG7
47
46
2
PTC0/TxD2
PTC1/RxD2
3
4
45
PTF6
PTC2/SDA
PTC3/SCL
PTC4
44
43
42
5
6
PTF5
V
7
REFL
41
V
REFH
PTC5
8
9
40
39
38
PTB7/AD7
PTB6/AD6
PTC6
Applicable Documents ________
10
PTC7
PTF2
PTF3
IEEE 802.3af-2003 standard, DTE Power via MDI
PowerDsine PD64012 Data Sheet, Cat. No. 06-0003-058
Serial Communication Protocol, Cat. No. 06-0032-056
PowerDsine Application Note 129 for Designing a
48-port Enhanced PoE System
11
12
PTB5/AD5
PTB4/AD4
37
36
35
34
13
PTB3/AD3
PTB2/AD2
PTF4
PTE0/TxD1
PTE1/RxD1
14
15
PTB1/AD1
IRQ 16
33 PTB0/AD0
18 19 20 21 22 23 24 25 26 27 28 29 30 31
17
32
MC9S08GB/GT Data sheet (V1.5) 8-/16-Bit
Products Division, Motorola, Inc.
Obtain from: http://e-
www.motorola.com/files/microcontrollers/doc/data_sheet/MC9S0
8GB60.pdf
PowerDsine
The Power over Ethernet Pioneers
This document contains information that is proprietary to PowerDsine. As such, it is confidential and its disclosure is strictly prohibited by applicable law. If you and/or your company and PowerDsine
have executed a Non-Disclosure Agreement, then this document is being provided in connection with the Agreement, and the information contained herein is covered by the Agreement and under its
terms may not be disclosed or used and must be protected by you and/or your company.
PD63000
8-bit PoE Microcontroller Unit
Package Information
The PD63000 is housed in a 64-pin LQFP plastic package, 10 x 10 x 1.4 mm, meeting JEDEC’s MS-026 package
outline and dimensions.
7
0.2
C
A-B
D
4 Pls
64
0.2
H
A-B
D
D
49
PIN 1
IDENTIFIER
(S)
0.05
1
48
0.25
GAGE
PLANE
A 2
A
R
B
E
E1
VIEW Y
L
R1
A1
Z
(L1)
E/2
E1/2
16
VIEW AA
33
17
32
D1/2
D/2
SECTION AB - AB
D1
8
°
ROTATED 90CW
BASE
D
b1
METAL
c
1
c
b
PLATING
VIEW AA
Z2
A
Notes:
1. Dimensions are in millimeters.
(x4)
0.08
C
H
C
2. Interpret dimensions and tolerances per ASME
Y14.5m-1994.
J
J
SEATING
PLANE
0.08
C A-B D
b (x64)
Z3
(x4)
3. Datums A, B and D to be determined at datum
plane H.
4. Dimensions D and E to be determined at seating
plane C.
5. Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall not cause the
lead width to exceed the maximum b dimension
by more than 0.08 mm. Dambar cannot be
located on the lower radius or the foot. Minimum
space between protrusion and adjacent lead or
protrusion 0.07mm.
AB
AB
X=A,B or D
X
e/2
6. Dimensions D1 and E1 do not include mold
protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch.
e (x60)
VIEW Y
7. Exact shape of each corner is optional.
8. These dimensions apply to the flat section of the
lead between 0.10mm and 0.25mm from the lead
tip.
Min.
---
Max.
1.60
Dim.
Min.
0.45
Max.
0.75
Dim.
A
L
L1
1.00 REF.
0.15
1.45
0.27
0.23
0.20
0.16
A1
A2
b
0.05
G
---
---
---
R1
R2
0.08
0.08
0.20
6.00
6.00
0 °
1.35
0.17
0.17
0.09
0.09
b1
c
S
F
7.00
7.00
7 °
c1
G
D
12.00 BSC
Z
D1
e
---
10.00 BSC
0.50 BSC
Z1
Z2
Z3
0 °
EXPOSED
PAD
11 °
11 °
13 °
13 °
12.00 BSC
10.00 BSC
E
E1
F
VIEW J-J
2
www.powerdsine.com
© PowerDsine 2004
Information in this document subject
to change without prior notice.
06-0008-058(Rev. 1.4) / 10 March 2004
PD63000
8-bit PoE Microcontroller Unit
Pin Functionality _______________________________________________
PIN PIN NAME PIN TYPE
PIN DESCRIPTION
PIN PIN NAME PIN TYPE
PIN DESCRIPTION
HW VER
1. Reset
Digital input xRESET_IN (1)
34 PTB1/AD1
35 PTB2/AD2
36 PTB3/AD3
37 PTB4/AD4
38 PTB5/AD5
39 PTB6/AD6
40 PTB7/AD7
41 VREFH
A/D input
A/D input
A/D input
A/D input
A/D input
A/D input
A/D input
A/D ref.
2. PTG7
3. PTC0/TxD2 Digital I/O
4. PTC1/RxD2 Digital I/O
5. PTC2/SDA Digital I/O
6. PTC3/SCL Digital I/O
I2C_Init_E
GND_Analog_CPU
SDA
SCL
7. PTC4
8. PTC5
9. PTC6
10 PTC7
11 PTF2
12 PTF3
13 PTF4
Digital I/O
Digital I/O
Digital I/O
Digital I/O
VREFH
GND_Analog_CPU
42 VREFL
A/D ref.
43 PTF5
44 PTF6
45 PTF7
46 PTA0/KBIP0 Digital I/O xASIC_RESET (1)
14 PTE0/TxD1 Digital I/O
15 PTE1/RxD1 Digital I/O
TX_3_3_V
RX_3_3_V
47 PTA1/KBIP1 Digital I/O xDISABLE_PORTS_TO_ASIC (1)
48 PTA2/KBIP2 A/D input
49 PTA3/KBIP3 A/D input
50 PTA4/KBIP4 A/D input
51 PTA5/KBIP5 A/D input
52 PTA6/KBIP6
Power Good PG3 (2)
Power Good PG2 (2)
Power Good PG1 (2)
16 IRQ
17 PTE2/SS
Digital input xInt_in
Digital I/O
18 PTE3/MISO Digital I/O
19 PTE4/MOSI Digital I/O
20 PTE5/SPSCK Digital I/O
MISO
MOSI
SCK
53 PTA7/KBIP7
21 PTE6
22 PTE7
23 VSS
24 VDD
Digital I/O
Digital I/O
Digital
xDISABLE_PORTS
54 PTF0
55 PTF1
56 VDDAD
57 VSSAD
D (ground)
3_3VCPU
Analog
Analog
VDDAD
GND_Analog_CPU
Digital
25 PTD0/TPM1
26 PTD1/TPM1
27 PTD2/TPM1
28 PTD3/TPM2
29 PTD4/TPM2 Digital I/O
30 PTD5/TPM2 Digital I/O
31 PTD6/TPM2 Digital I/O
32 PTD7/TPM2 Digital I/O
Shorted to pin 28
58 PTG0/BKGD/ Digital I/O
59 PTG1/XTAL Resonator/o XTAL
60 PTG2/EXTAL Resonator/o EXTAL
Shorted to pin 25
xSPI_CS0
xSPI_CS1
xSPI_CS2
xSPI_CS3
61 PTG3
62 PTG4
63 PTG5
64 PTG6
Digital I/O
Digital I/O
Digital output xInt_Out (future use)
Digital I/O
SELF RESET
33 PTB0/AD0
A/D input
(1). Upon receiving an active low reset level via pin 1 (xRESET_IN) from the switch host, the PD63000 MCU immediately disables all
PoE Manager (PD64012) output ports. The MCU does this using the xDISABLE_PORTS_TO_ASIC signal (pin 47). During this
process, the PoE Managers are still actively operational, although their ports are disabled. Once the active low is released, the MCU
performs a software reboot. After the reboot, the MCU sends a reset to all PoE Managers, via pin 46 (xASIC_RESET).
(2) Refer to Tech Note TN-113 for information on power management.
3
www.powerdsine.com
© PowerDsine 2004
Information in this document subject
to change without prior notice.
06-0008-058(Rev. 1.4) / 10 March 2004
PD63000
8-bit PoE Microcontroller Unit
Notice ________________________________________________________
PowerDsine assumes no responsibility or liability arising from the use of this Data Sheet, as described herein, nor does it convey any license under its patent rights or the rights
of others.
The information contained herein is believed to be accurate and reliable at the time of printing. However, due to ongoing product improvements and revisions,
PowerDsine cannot accept responsibility for inadvertent errors, inaccuracies, subsequent changes or omissions of printed material.
PowerDsine Ltd. reserves the right to make changes to products and to their specifications as described in this document, at any time, without prior notice. No rights to
any PowerDsine Ltd. Intellectual property are licensed to any third party, directly, by implication or by any other method.
No Use with Life-Support or Critical Applications _____________________________________________________________________
PowerDsine’s products are not designed, intended, or authorized for use as components in systems intended for:
(1) surgical implant into the body, or other applications intended to support or sustain life, or
(2) any other applications whereby a failure of the PowerDsine’s product could create a situation where personal injury, death or damage to persons, systems, data or
business may occur.
PowerDsine assumes no liability in connection with use in these situations and the disclaimers provided below in this manual shall apply. Should a buyer purchase or use
PowerDsine’s products for any such unintended use or unauthorized applications, buyer shall indemnify PowerDsine and its officers and employees against any and all claims
arising out of or in connection with any claim of personal injury, death or other damage of the type described above, associated with such use.
DISCLAIMERS __________________________________________________________________________________________________
POWERDSINE MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE REGARDING THE SUITABILITY OF THE PRODUCTS
CONTAINED HEREIN FOR ANY PARTICULAR PURPOSE, NOR DOES POWERDSINE ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCTS OR CIRCUIT, AND SPECIFICALLY DISCLAIMS ANY AN ALL LIABILITY, INCLUDING,
WITHOUT LIMITATION, CONSEQUENTIAL OR INCIDENTAL DAMAGES. BY USING OUR PRODUCTS USER AGREES NOT TO MAKE ANY
CLAIM FOR PUNITIVE DAMAGES.
POWERDSINE MAKES NO REPRESENTATION OR WARRANTY, EXPRESSED OR IMPLIED, WITH RESPECT TO THE SUFFICIENCY OR
ACCURACY OR UTILITY OF ANY INFORMATION CONTAINED HEREIN. POWERDSINE EXPRESSLY ADVISES THAT ANY USE OF OR
RELIANCE UPON SAID INFORMATION IS AT THE RISK OF THE USER AND THAT POWERDSINE SHALL NOT BE LIABLE FOR ANY
DAMAGE OR INJURY INCURRED BY ANY PERSON OR ORGANIZATION ARISING OUT OF THE SUFFICIENCY, ACCURACY, OR UTILITY
OF ANY INFORMATION CONTAINED HEREIN OR IN CONNECTION WITH THE USE OF ANY OF THE PRODUCTS DESCRIBED HEREIN.
POWERDSINE IS NOT RESPONSIBLE FOR ANY CHANGES IN THE SPECIFICATIONS OR ERRATA OF THIS PRODUCT. INFORMATION
ON THE BASIC PRODUCT CAN BE FOUND AT MOTOROLA'S HOMEPAGE.
Revision History
Revision Level / Date
Para. Affected
Description
1.2 / 9 Feb. 04
1.3 / 12 Feb. 04
1.4 / 10 Mar. 04
Front & back pages
Added policy statement and replaced Cat. no.
Pin Functionality (page 3)
Pin Functionality (page 3)
Added pin descriptions and explanation related to reset.
Added definitions for power management pins (Power Good)
© 2004 PowerDsine Ltd.
All rights reserved.
PowerDsine is a registered trademark of PowerDsine LTD.
All other products or trademarks are property of their respective owners.
The product described by this manual is a licensed product of PowerDsine.
4
www.powerdsine.com
© PowerDsine 2004
Information in this document subject
to change without prior notice.
06-0008-058(Rev. 1.4) / 10 March 2004
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