RP1280A-CQ172B_技术文档

P r e l i m i n a r y v 1 . 1

®

RadTolerant RAD-PAK

Field Programmable Gate Arrays

F e a t u r e s

• Highly Predictable Performance with 100% Automatic

Place and Route

R a d ia t io n C h a r a c t e r is t ic s

• 100% Resource Utilization with 100% Pin-Locking

• RAD-PAK^®Package Technology from Space Electronics,

Inc.

• Secure Programming Technology Prevents Reverse

Engineering and Design Theft

• Improved Total Ionizing Dose (TID) Survivability

– Can Improve TID 2-10x Over Standard Package

– Can Achieve > 100 KRads (Si) in Some Orbits

• Packages: 172-Pin and 256-Pin RAD-PAK^®Ceramic Quad

Flat Pack

• Permanently Programmed for Instantaneous Operation on

Power-Up

• Unique In-System Diagnostic and Debug Facility with

Silicon Explorer

• Actel Designer Series Design Tools, Supported by

Cadence, Exemplar, Mentor Graphics, Model Tech,

Synopsys, Synplicity and Viewlogic Design Entry and

Simulation Tools

• Offered as E-Flow (Actel Space Level Flow) and Class B

H ig h De n s it y a n d P e r fo r m a n c e

• 16,000 and 20,000 Gates

• 8,000 and 10,000 ASIC Equivalent Gates

• Up to 85 MHz On-Chip Performance

• Up to 228 User I/Os

G e n e r a l D e s c r i p t i o n

Actel builds the most reliable field programmable gate arrays

(FPGAs) in the industry, with overall antifuse reliability

ratings of less than 10 failures-in-time (FITs), corresponding

to a useful life of more than 40 years. Actel FPGAs are

production-proven, with more than five million devices

shipped and more than one trillion antifuses manufactured.

Actel devices are fully tested prior to shipment, with an

out-going defect level of only 122 ppm. (Further reliability

data is available in the “Actel Device Reliability Report” at

http://www.actel.com/products/devices/hireldev.html.)

• Up to Four Fast, Low-Skew Clock Networks

E a s y Lo g ic In t e g r a t io n

• Non-Volatile, User Programmable

• Pin-Compatible Commercial Devices Available for

Prototyping

P r o d u c t F a m i l y P r o f i l e

Device

RP1280A

RP14100A

Gates

16,000

8,000

20,000

200

20,000

10,000

25,000

250

ASIC Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Package

20-Pin PAL Equivalent Packages

80

100

Logic Modules

S-Modules

1,232

624

1,377

697

C-Modules

608

680

User I/Os

140

172

228

256

CQFP Package Pin Count

Performance System Speed (Maximum)

40 MHz

60 MHz

Ordering Information

Part Number (Class B)

Part Number (E-Flow)

Commercial Equivalent for Prototyping

RP1280A-CQ172B

RP1280A-CQ172E

A1280A-CQ172C

RP14100A-CQ256B

RP14100A-CQ256E

A14100A-CQ256C

J a n u a r y 1 9 9 9

1

Additionally, the programmable architecture of both the

RP1280A and RP14100A offers high performance, design

flexibility, and fast and inexpensive prototyping—all without

the expense of test vectors, NRE charges, long lead times, and

schedule and cost penalties for design refinements.

the Actel Web site at:

http://www.actel.com/products/devices/radhard/radperf.pdf.

R a d i a t i o n P e r f o r m a n c e

®

o f R A D -P A K F P G A s

Recently, Actel joined with Space Electronics, Inc. (SEi) to

combine Actel’s antifuse-based FPGAs with SEi’s RAD-PAK^®

package shielding technology. This technology incorporates

radiation shielding in the FPGA package, eliminating the

requirement for box- or board-level shielding and significantly

improving the total ionizing dose survivability of Actel

devices. The RP1280A and the RP14100A provide a

high-reliability, low-risk, and fast time-to-launch solution that

survives in a wide subset of Earth orbits and deep space

environments.

The components of natural radiation in space consist of

trapped electrons, trapped protons, galactic cosmic rays, solar

flare protons, and alpha particles. Depending on the orbit or

deep space probe mission, the energy levels and magnitude of

each component will vary. Since shielding effectiveness is

dependent on the radiation component type and its energy

level, the overall performance of RAD-PAK^®FPGAs will vary

with the application. Typical applications for two different

orbits are shown below. Figure 1 and Figure 2 show the

amount of mission dose which can be expected when a given

amount of shielding is utilized for the two sample orbits.

A closer examination of the box shielding and RAD-PAK^®

shielding shows how the specific requirements for

components are originated. Figure 3 below shows a typical

orbit of 705 km, 98 degrees, for 5 years. Under these

conditions, typical satellite designers might have a 40 to 120

mil aluminum box shield between the components and the

outside environment. The figure shows that a shield of

average thickness yields approximately 10 KRad (Si) inside

the box shield. This specification becomes a design

requirement for all of the active components in the satellite.

When the RAD-PAK^®shielding is added to the box shielding,

as shown by the RP line, the total dose seen by the component

is only 2.4 KRad (Si).

The RP1280A device uses the A1280A die from the ACT 2

Family of Actel FPGAs in a RAD-PAK^®package. It utilizes a

two-module architecture, consisting of combinatorial

modules (C-modules) and sequential modules (S-modules)

optimized for both combinatorial and sequential designs.

Based on Actel’s patented channeled array architecture, the

RP1280A has 8,000 ASIC-equivalent gates and 140 user I/Os.

The RP1280A device is fully pin- and function-compatible

with the commercially-equivalent A1280A-CQ172C device for

easy and inexpensive prototyping.

The RP14100A device uses the A14100A die in a RAD-PAK^®

package. This device is from the ACT 3 Family of Actel

devices, which also utilizes the two-module architecture. The

RP14100A offers additional device resources above the

RP1280A, including increased gates (10,000 gate array When a second orbit (35,790 km, 0 degrees, for 5 years) is

equivalent gates), higher I/Os (228), and faster performance.

examined using the same methodology, similar results can be

achieved at higher total dose levels. Figure 4 below shows that

average box shielding provides protection to 250 KRad(Si).

Use of the RAD-PAK^®design brings the total dose seen at the

device level down to 5.8 KRad (Si).

The RP14100A device is fully pin- and function-compatible

with the commercially-equivalent A14100A-CQ256C device for

easy and inexpensive prototyping.

The above discussion shows how use of RAD-PAK^®products

can shield significant levels of total dose seen at the die level.

The ability of the Actel FPGA die to meet these lower levels of

total dose radiation make the RAD-PAK^®FPGAs a design

choice for many space applications.

For proper application of the RAD-PAK^®FPGA products, the

following information should be available:

R a d i a t i o n S u r v i v a b i l i t y

The bare die of both the RP1280A and RP14100A devices have

some inherent total dose radiation survivability. The levels at

which these bare die are able to survive varies by lot and

device type. Actel provides Group E testing on the bare die

that gives an indication of the lot characteristics. These

results are provided for reference and customer evaluation,

and the testing is performed to MIL-STD-883, Method 1019.5

by Space Electronics, Inc.

The radiation survivability levels of the RAD-PAK^®devices

varies due to a number of factors. The customer must

evaluate and determine the applicability of these devices to

their specific design and environmental requirements.

• Orbit or mission

• Satellite level shielding thickness and type

or

• Mission dose vs. shielding thickness curves

Actel personnel can then assist in determining whether the

RAD-PAK^®FPGA devices are usable for the customers

application and radiation requirements.

A summary of the radiation performance of Actel products

(“Radiation Performance of Actel Products”) can be found on

2

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R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

1.0E+07

1.0E+06

1.0E+05

1.0E+04

1.0E+03

1.0E+02

1.0E+01

1.0E+00

Total Dose

Protons

Solar Protons

Electrons

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Shielding Thickness

Figure 1 • Space-Level Total Dose: Typical Orbit—705km, 98°, 5 years

1.0E+10

Protons

1.0E+09

1.0E+08

1.0E+07

1.0E+06

1.0E+05

1.0E+04

1.0E+03

Total Dose

Solar Protons

Electrons

1.0E+02

1.0E+01

1.0E+00

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Shielding Thickness

Figure 2 • Space-Level Total Dose: Typical Orbit—35,790 km, 0°, 5 years

3

1.0E+07

1.0E+06

1.0E+05

1.0E+04

1.0E+03

1.0E+02

1.0E+01

1.0E+00

Box and Standard

Package Shielding

®

RAD-PAK

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Shielding Thickness

Figure 3 • RAD-PAK^®Total Dose Shielding: Typical Orbit—705 km, 98°, 5 years

1.0E+10

1.0E+09

1.0E+08

1.0E+07

1.0E+06

1.0E+05

1.0E+04

1.0E+03

1.0E+02

1.0E+01

1.0E+00

Box and Standard

Package Shielding

®

RAD-PAK

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Shielding Thickness

Figure 4 • RAD-PAK^®Total Dose Shielding: Typical Orbit—35,790 km, 0°, 5 years

4

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R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

D i s c l a i m e r

Designer Series supports industry-leading VHDL- and

Verilog-based design tools, including synthesis tools from

All radiation performance information is provided for

information purposes only and is not guaranteed. The total

dose effects on the bare die is lot-dependent, and Actel does

not warrant that future devices will continue to exhibit

similar radiation characteristics. In addition, due to the

nature of RAD-PAK^®shielding, actual performance can vary

widely due to a variety of factors, including but not limited to,

characteristics of the orbit, radiation environment, proximity

to satellite exterior, amount of inherent shielding from other

sources within the satellite and actual bare die variations.

For these reasons, Actel does not warrant any level of

radiation survivability, and it is solely the responsibility of the

customer to determine whether the device will meet the

requirements of the specific design.

industry leaders such as Exemplar Logic, Synplicity, and

Synopsys.¹

In addition, the RAD-PAK^®devices are supported by Actel’s

new Silicon Explorer diagnostic and debugging tool kit.

Silicon Explorer dramatically reduces verification time from

several hours per cycle to a few seconds by enabling

real-time, in-circuit debugging. Silicon Explorer includes:

• Probe Pilot, a high-speed signal acquisition and control

tool that samples data at 100 MHz (asynchronous) or 66

MHz (synchronous). Probe Pilot features 18 probing

channels and connects to the user’s PC via a standard

serial port connection.

• Diagnostic software, which turns the PC into a

fully-featured, 100 MHz logic analyzer for easy graphical

analysis of waveforms.

D e s i g n T o o l S u p p o r t

As with all Actel FPGAs, RAD-PAK^®devices are fully

supported by Actel’s Designer Series development tools,

which include:

Silicon Explorer probes 100 percent of the device circuitry

using Probe Pilot’s powerful, 18-channel signal acquisition

capability. Individual bugs are then isolated and passed to the

user interface, providing the user with complete waveform

data.

• DirectTime for automated, timing-driven place and route;

• ACTgen for fast development using a wide range of macro

functions; and

1. Designer Series also supports design entry and simulation tools from Cadence,

Mentor Graphics, and Viewlogic.

• ACTmap for logic synthesis.

®

R A D -P A K D e v i c e O r d e r i n g I n f o r m a t i o n

RP1280A

–

CQ

172

E

Application (Temperature Range)

C = Commercial (0 to +70°C)

M = Military (–55 to +125°C)

B = MIL-STD-883 Class B

E = Extended Flow (Space Level)

Package Lead Count

Package Type

CQ = Ceramic Quad Flat Pack (CQFP)

Speed Grade

Std = Standard Speed

–1 = Approximately 15% Faster than Standard

Part Number

®

RP1280A = 8,000 Gates—RAD-PAK ACT 2

RP14100A = 10,000 Gates—RAD-PAK ACT 3

A1280A = 8,000 Gates—ACT 2

®

A14100A = 10,000 Gates—ACT 3

5

P r o d u c t P l a n

Application

C

M

B

E

ACT 2

®

RP1280A RAD-PAK Device

172-Pin Ceramic Quad Flat Pack (CQFP)

A1280A Device (Prototyping Use)

172-Pin Ceramic Quad Flat Pack (CQFP)

ACT 3

—

✔

—

RP14100A RAD-PAK® Device

256-Pin Ceramic Quad Flat Pack (CQFP)

A14100A Device (Prototyping Use)

256-Pin Ceramic Quad Flat Pack (CQFP)

—

P

✔

—

Applications: C = Commercial

M = Military

Availability: ✔ = Available

= Planned

— = Not Planned

P

B = MIL-STD-883 Class B

E = Extended Flow (Space Level)

D e v i c e R e s o u r c e s

User I/Os

Gate Array

Equivalent Gates

CQFP

172-Pin

CQFP

256-Pin

FPGA Device Type

Logic Modules

RP1280A/A1280A

1232

1377

8000

140

—

RP14100A/A14100A

10000

228

6

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R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

A r c h i t e c t u r a l O v e r v i e w

The RP1280A and RP14100A architecture is composed of

fine-grained logic modules which produce fast, efficient logic

designs. All devices are composed of logic modules, routing

resources, clock networks, and I/O modules which are the

building blocks for fast logic designs.

A0

B0

S0

D00

D10

D11

Y

Lo g ic Mo d u le s

Both devices contain two types of logic modules:

combinatorial (C-modules) and sequential (S-modules).

The C-module, shown in Figure 5, implements the following

function:

S1

A1

B1

Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11

where:

Figure 5 • C-Module Implementation

S0=A0*B0

S1=A1+B1

function as the C-module while adding a sequential element.

The sequential element can be configured as either a D-type

flip-flop or a transparent latch. To increase flexibility, the

S-module register can be by-passed so it implements purely

combinatorial logic.

The S-module shown in Figure 6 is designed to implement

high-speed sequential functions within a single logic module.

The S-module implements the same combinatorial logic

D00

D01

D00

D01

OUT

Y

D

Q

Y

D

Q

D10

S0

D11

S1

D11

S1

S0

GATE

CLR

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D00

D01

D0

Y

OUT

Y

D

Q

D10

S0

D1

D11

S1

GATE

S

CLR

Up to 8-Input Function (Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 6 • S-Module Implementation

7

IO P C L

De d ic a t e d (H a r d -Wir e d ) I/O

P r e s e t /C le a r (In p u t )

Flip-flops can also be created using two C-modules. The single

event upset (SEU) characteristics differ between an

S-module flip-flop and a flip-flop created using two

C-modules. See the Radiation Specifications in this Data

Sheet for details and the Actel Application Note, “Design

RP14100A and A14100A only. TTL input for I/O preset or

clear. This global input is directly wired to the preset and

clear inputs of all I/O registers. This pin functions as an I/O

Techniques for RadHard Field Programmable Gate Arrays” when no I/O preset or clear macros are used.

found at http://www.actel.com/products/radhard.html.

MO DE

Mo d e (In p u t )

The MODE pin controls the use of diagnostic pins (DCLK,

PRA, PRB, SDI). When the MODE pin is HIGH, the special

functions are active. When the MODE pin is LOW, the pins

function as I/Os. To provide ActionProbe capability, the

MODE pin should be terminated to GND through a 10K

resistor so that the MODE pin can be pulled HIGH when

required.

P i n D e s c r i p t i o n

C LK A

C lo c k A (In p u t )

TTL clock input for global clock distribution networks. The

clock input is buffered prior to clocking the logic modules.

This pin can also be used as an I/O.

C LK B

C lo c k B (In p u t )

N C

N o C o n n e c t io n

TTL clock input for global clock distribution networks. The

clock input is buffered prior to clocking the logic modules.

This pin can also be used as an I/O.

This pin is not connected to circuitry within the device.

P R A, I/O

P r o b e A (O u t p u t )

DC LK

Dia g n o s t ic C lo c k (In p u t )

The Probe A pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the Probe B pin to allow

real-time diagnostic output of any signal path within the

device. The Probe A pin can be used as a user-defined I/O

when debugging has been completed. PRA is accessible when

the MODE pin is HIGH. This pin functions as an I/O when the

MODE pin is LOW.

TTL clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

G N D

G r o u n d

LOW supply voltage.

H C LK

De d ic a t e d (H a r d -Wir e d ) Ar r a y

C lo c k (In p u t )

P R B , I/O

P r o b e B (O u t p u t )

RP14100A and A14100A only. TTL clock input for sequential

modules. This input is directly wired to each S-module,

offering clock speeds independent of the number of

S-modules being driven. This pin can also be used as an I/O.

The Probe B pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the Probe A pin to allow

real-time diagnostic output of any signal path within the

device. The Probe B pin can be used as a user-defined I/O

when debugging has been completed. PRB is accessible when

the MODE pin is HIGH. This pin functions as an I/O when the

MODE pin is LOW.

I/O

In p u t /O u t p u t (In p u t , O u t p u t )

I/O pin functions as an input, output, tri-state, or

bi-directional buffer. Input and output levels are compatible

with standard TTL and CMOS specifications. Unused I/O pins

are automatically driven LOW.

S DI

S e r ia l Da t a In p u t (In p u t )

IO C LK

De d ic a t e d (H a r d -Wir e d ) I/O

C lo c k (In p u t )

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH. This

pin functions as an I/O when the MODE pin is LOW.

RP14100A and A14100A only. TTL clock input for I/O

modules. This input is directly wired to each I/O module,

offering clock speeds independent of the number of I/O

modules being driven. This pin can also be used as an I/O.

V

5 V S u p p ly Vo lt a g e

C C

HIGH supply voltage.

8

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

A c t e l M I L -S T D -8 8 3 P r o d u c t F l o w

883—Class B

Step

1.0

Screen

883 Method

Requirement

Internal Visual

2010, Test Condition B

1010, Test Condition C

100%

2.0

3.0

Temperature Cycling

Constant Acceleration

2001, Test Condition E

(Min), Y1, Orientation Only

4.0

Seal

1014

a. Fine

b. Gross

100%

1

5.0

6.0

7.0

Particle Impact Noise Detection

Visual Inspection

2020, Test Condition A

2009

100%

Pre-Burn-In

Electrical Parameters

In accordance with applicable Actel

device speciﬁcation

8.0

9.0

Burn-in Test

1015 Condition D

160 hours @ 125°C Min.

100%

Interim (Post-Burn-In)

Electrical Parameters

In accordance with applicable Actel

device speciﬁcation

10.0

11.0

Percent Defective Allowable

Final Electrical Test

5%

All Lots

In accordance with applicable Actel

device speciﬁcation

a. Static Tests

(1) 25°C

100%

(Subgroup 1, Table I, 5005)

(2) –55°C and +125°C

(Subgroups 2, 3, Table I, 5005)

b. Dynamic and Functional Tests

(1) 25°C

(Subgroup 7, Table I, 5005)

(2) –55°C and +125°C

(Subgroups 8A and 8B, Table I, 5005)

c. Switching Tests at 25°C

(Subgroup 9, Table I, 5005)

100%

12.0

Qualiﬁcation or Quality

Conﬁrmation Inspection Test

Sample Selection (Group A and Group B)

5005

2009

All Lots

13.0

External Visual

100%

Notes:

1. Particle Impact Noise Detection (PIND) is included in the flow for RAD-PAK® devices, although it is not normally required in the

MIL-STD-883 Class B flow.

9

1

A c t e l E x t e n d e d F l o w

Require-

ment

Step Screen

Method

2

1.

2.

3.

4.

5.

6.

7.

8.

9.

Wafer Lot Acceptance

5007 with Step Coverage Waiver

2011, Condition D

All Lots

Sample

100%

3

Destructive In-Line Bond Pull

Internal Visual

2010, Condition A

Serialization

Temperature Cycling

Constant Acceleration

Visual Inspection

1010, Condition C

2001, Condition E (Min), Y Orientation Only

1

2009

Particle Impact Noise Detection

2020, Condition A

2012

4

Radiographic

Not

Performed

10. Pre-Burn-In Test

11. Burn-in Test

In accordance with applicable Actel device speciﬁcation

1015, Condition D, 240 hours @ 125°C minimum

100%

All Lots

12. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device speciﬁcation

13. Reverse Bias Burn-In 1015, Condition C, 72 hours @ 150°C minimum

14. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device speciﬁcation

15. Percent Defective Allowable (PDA)

Calculation

5%, 3% Functional Parameters @ 25°C

16. Final Electrical Test

In accordance with Actel applicable device speciﬁcation

100%

a. Static Tests

(1) 25°C

5005

(Subgroup 1, Table1)

(2) –55°C and +125°C

(Subgroups 2, 3, Table 1)

100%

b. Dynamic and Functional Tests

(1) 25°C

(Subgroup 7, Table 15)

(2) –55°C and +125°C

(Subgroups 5 and 6, 8a and b, Table 1)

5005

c. Switching Tests at 25°C

(Subgroup 9, Table 1)

100%

5005

1014

17. Seal

a. Fine

b. Gross

18. Qualiﬁcation or Quality Conformance

Inspection Test Sample Selection

5005

2009

Group A &

Group B

19 External Visual

100%

Notes:

1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B. Actel is

compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow

incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The exceptions to Method 5004

are shown in notes 2 to 4 below.

2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.

3. Method 5004 requires a 100 percent, non-destructive bond pull to Method 2023. Actel substitutes a destructive bond pull to Method 2011,

Condition D on a sample basis only.

®

4. Radiographic test is not performed since RAD-PAK package technology screens all X-rays and the test results are uninformative.

1 0

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R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

1

A b s o l u t e M a x i m u m R a t i n g s

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

Free Air Temperature Range

Parameter

Commercial Military

Units

Symbol

Parameter

Limits

Units

Temperature

Range

0 to +70

–55 to +125 °C

1

2

V

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

CC

Power Supply

Tolerance

±5

±10

%V

–0.5 to V +0.5

CC

I

CC

V

Output Voltage

–0.5 to V +0.5

V

O

CC

Note:

I

I/O Source Sink

Current

±20

mA

IO

5

1. Ambient temperature (T ) is used for commercial and

A

industrial; case temperature (T ) is used for military.

C

T

Storage Temperature

–65 to +150

°C

STG

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may

affect device reliability. Device should not be operated outside the

recommended operating conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V + 0.5V or less than GND – 0.5V, the internal protection

CC

diode will be forward-biased and can draw excessive current.

P a c k a g e T h e r m a l C h a r a c t e r i s t i c s

The device junction to case thermal characteristic is θ_jc.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power

dissipation allowed for a CQFP 172-pin package at military

temperature is as follows:

Max. junction temp. (°C) – Max. military temp.

150°C – 125°C

------------------------------------------------------------------------------------------------------------------ = ------------------------------------ = 4.2W

θ_jc(°C/W)

6°C/W

Package Type

Pin Count

θ

Units

jc

Ceramic Quad Flat Pack

176

256

6

TBD

°C/W

1 1

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Military

Max.

Symbol Parameter

Test Condition

Min.

Max.

Min.

Units

1, 2

V

HIGH Level Output

I

= –4 mA (CMOS)

= –6 mA (CMOS)

= +6 mA (CMOS)

3.7

V

OH

OL

3.84

1, 2

V

LOW Level Output

HIGH Level Input

LOW Level Input

Input Leakage

0.33

0.4

+ 0.3

CC

V

OL

IH

IL

TTL Inputs

2.0

–0.3

–10

V

+ 0.3

2.0

–0.3

–10

V

CC

0.8

+10

10

0.8

+10

10

V

I

V = V or GND

µA

pF

mA

IN

OZ

I

CC

I

3-State Output Leakage

V = V or GND

O CC

3, 4

C

I/O Capacitance

IO

I

Standby V Supply Current V = V or GND, I = 0 mA

2

20

CC(S)

CC(D)

CC

I

CC

O

Dynamic V Supply Current See “Power Dissipation” Section

CC

Notes:

1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.

2. Tested one output at a time, V = min.

CC

3. Not tested; for information only.

4.

V

= 0V, f = 1 MHz

OUT

G e n e r a l P o w e r E q u a t i o n

P = [I_CCstandby + I_CCactive] * V + I_OL* V * N +

The power due to standby current is typically a small

component of the overall power. Standby power is calculated

below for commercial, worst-case conditions.

CC

OL

I

_OH* (V – V ) * M

CC OH

Family

I_CC

V

Power

CC

Where:

RP1280A, RP14100A,

A1280A, A14100A

I_CCstandby is the current flowing when no inputs or

outputs are changing.

2 mA

5.25V 10.5 mW

The static power dissipated by TTL loads depends on the

number of outputs driving HIGH or LOW and on the DC load

current. Again, this value is typically small. For instance, a

32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all

outputs driving LOW, and 140 mW with all outputs driving

HIGH.

I_CCactive is the current flowing due to CMOS switching.

I_OL, I_OHare TTL sink/source currents.

V , V_OHare TTL level output voltages.

OL

N equals the number of outputs driving TTL loads to V .

OL

M equals the number of outputs driving TTL loads to V .

OH

Ac t iv e P o w e r C o m p o n e n t

An accurate determination of N and M is problematical

because their values depend on the family type, on design

details, and on the system I/O. The power can be divided into

two components: static and active.

Power dissipation in CMOS devices is usually dominated by

the active (dynamic) power dissipation. This component is

frequency-dependent, a function of the logic and the external

I/O. Active power dissipation results from charging internal

chip capacitances of the interconnect, unprogrammed

antifuses, module inputs, and module outputs, plus external

capacitance due to PC board traces and load device inputs.

An additional component of the active power dissipation is

the totem pole current in CMOS transistor pairs. The net

effect can be associated with an equivalent capacitance that

can be combined with frequency and voltage to represent

active power dissipation.

S t a t ic P o w e r C o m p o n e n t

Actel FPGAs have small static power components that result

in power dissipation lower than that of PALs or PLDs. By

integrating multiple PALs or PLDs into one FPGA, an even

greater reduction in board-level power dissipation can be

achieved.

1 2

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

E q u iv a le n t C a p a c it a n c e

where:

The power dissipated by a CMOS circuit can be expressed by

Equation 1

m

n

= Number of logic modules switching at f_m

= Number of input buffers switching at f_n

= Number of output buffers switching at f_p

Power (uW) = C_EQ* V ²* F

(1)

CC

p

where:

C_EQis the equivalent capacitance expressed in pF.

q₁

= Number of clock loads on the first routed

array clock

q₂

r₁

r₂

s₁

s₂

= Number of clock loads on the second routed

array clock

V is the power supply in volts (V).

CC

F is the switching frequency in MHz.

= Fixed capacitance due to first routed array

clock

Equivalent capacitance is calculated by measuring I_CCactive

at a specified frequency and voltage for each circuit

component of interest. Measurements are made over a range

= Fixed capacitance due to second routed array

clock

of frequencies at a fixed value of V . Equivalent capacitance

CC

is frequency-independent, so the results can be used over a

wide range of operating conditions. Equivalent capacitance

values are shown below.

= Fixed number of clock loads on the dedicated

array clock (RP14100A, A14100A only)

= Fixed number of clock loads on the dedicated

I/O clock (RP14100A, A14100A only)

C E Q Va lu e s fo r Ac t e l F P G As

RP1280A RP14100A

A1280A A14100A

C_EQM

C_EQI

= Equivalent capacitance of logic modules in pF

= Equivalent capacitance of input buffers in pF

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads

(C_EQCR

Dedicated Clock Buffer Loads

(C_EQCD

I/O Clock Buffer Loads (C_EQCI

)

5.8

12.9

23.8

6.7

7.2

C_EQO

= Equivalent capacitance of output buffers

in pF

)

10.4

C_EQCR= Equivalent capacitance of routed array clock

in pF

)

3.9

1.6

C_EQCD= Equivalent capacitance of dedicated array

clock in pF

)

n/a

0.7

0.9

C_EQCI

= Equivalent capacitance of dedicated I/O clock

in pF

)

C_L

f_m

f_n

= Output lead capacitance in pF

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic must

be known. Equation 2 shows a piece-wise linear summation

over all components. Since the RP1280A and A1280A have

two routed array clocks, the dedicated_Clk and IO_Clk terms

do not apply. For RP14100A and A14100A devices, all terms

will apply.

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

f_p

f_q1

f_q2

= Average second routed array clock rate in

MHz

Power = V ²* [(m * C_EQM* f_m)_modules+ (n * C_EQI* f_n)_inputs

+

CC

f_s1

f_s2

= Average dedicated array clock rate in MHz

(RP14100A, A14100A only)

(p * (C_EQO+ C_L) * f_p)_outputs+ 0.5 * (q₁* C_EQCR* f_q1)_{routed_Clk1}

+ (r₁* f_q1)_{routed_Clk1}+ 0.5 * (q₂* C_EQCR* f_q2)_{routed_Clk2}

(r₂* f_q2)_{routed_Clk2}+ 0.5 * (s₁* C_EQCD* f_s1)_{dedicated_Clk}

(s₂* C_EQCI* f_s2)_{IO_Clk}(2)

+

= Average dedicated I/O clock rate in MHz

(RP14100A, A14100A only)

]

1 3

F ix e d C a p a c it a n c e Va lu e s fo r

Ac t e l F P G As (p F )

RP14100A, A14100A

Logic Modules (m)

=

80%ofCombinatorial

Modules

r₁

r₂

Device Type

routed_Clk1 routed_Clk2

Input Switching (n)

=

# Inputs/4

RP1280A, A1280A

RP14100A, A14100A

168

195

168

195

Outputs Switching (p)

# Outputs/4

First Routed Array Clock Loads (q₁)= 40% of Sequential

Modules

F ix e d C lo c k Lo a d s (s /s —AC T 3 O n ly )

1

2

s₁

s₂

Second Routed Array Clock Loads = 40% of Sequential

Clock Loads on Clock Loads on

(q₂)

Modules

Dedicated

Array Clock

Dedicated

I/O Clock

Load Capacitance (C_L)

=

35 pF

Device Type

Average Logic Module Switching

Rate (f_m)

F/10

RP14100A, A14100A

697

228

De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y

Average Input Switching Rate (f_n) = F/5

Average Output Switching Rate (f_p) = F/10

To determine the switching frequency for a design, you must

have a detailed understanding of the data input values to the

circuit. The guidelines in the table below are meant to

represent worst-case scenarios; they can be generally used to

predict the upper limits of power dissipation.

Average First Routed Array Clock

Rate (f_q1)

= F/2

Average Second Routed Array Clock = F/2

Rate (f_q2)

RP1280A, A1280A

Average Dedicated Array Clock Rate =

(f_s1)

F

Logic Modules (m)

=

80%ofCombinatorial

Modules

Average Dedicated I/O Clock Rate =

(f_s2)

F

Input Switching (n)

=

# Inputs/4

Outputs Switching (p)

# Outputs/4

First Routed Array Clock Loads (q₁)= 40% of Sequential

Modules

Second Routed Array Clock Loads = 40% of Sequential

(q₂)

Modules

Load Capacitance (C_L)

=

35 pF

Average Logic Module Switching

Rate (f_m)

F/10

Average Input Switching Rate (f_n) = F/5

Average Output Switching Rate (f_p) = F/10

Average First Routed Array Clock

Rate (f_q1)

= F

Average Second Routed Array Clock = F/2

Rate (f_q2)

Average Dedicated Array Clock Rate = n/a

(f_s1)

Average Dedicated I/O Clock Rate = n/a

(f_s2)

1 4

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

R P 1 2 8 0 A , A 1 2 8 0 A T i m i n g M o d e l *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

Combinatorial

Logic Module

I/O Module

t

= 4.3 ns

INYL

t

= 8.4 ns†

IRD2

t

= 16.5 ns

DLH

t

= 2.8 ns

= 4.0 ns

= 6.0 ns

= 10.8 ns

RD1

RD2

D

Q

t

= 6.1 ns

PD1

t

RD4

RD8

I/O Module

G

t

= 16.5 ns

DLH

Sequential

Logic Module

t

= 2.5 ns

= 3.5 ns

= 7.7 ns

INH

t

INSU

INGL

Combin-

atorial

D

Q

Logic

included

t

= 2.8 ns

t

= 11.5 ns

RD1

ENHZ

G

in t

SUD

t

= 0.0 ns

= 0.5 ns

= 14.6 ns

OUTH

t

OUTSU

t

= 6.1 ns

t

= 0.5 ns

= 0.0 ns

CO

SUD

HD

Array

Clocks

t

GLH

t

= 15.7 ns

FO = 32

CKH

F

= 62 MHz

MAX

*Values shown for RP1280A at worst-case military conditions.

† Input module predicted routing delay

1 5

R P 1 4 1 0 0 A , A 1 4 1 0 0 A T i m i n g M o d e l *

Input Delays

I/O Module

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

Combinatorial

Logic Module

t

= 4.9 ns

INY

t

= 2.1 ns

IRD2

t

= 10.8 ns

DHS

t

= 1.5 ns

= 2.9 ns

= 4.9 ns

RD1

RD4

RD8

D

Q

t

= 3.5 ns

PD

I/O Module

t

= 10.8 ns

DHS

Sequential

Logic Module

t

= 0.0 ns

= 2.4 ns

= 8.2 ns

INH

t

INSU

ICKY

Combin-

atorial

D

Q

Logic

included

t

= 1.5 ns

RD1

t

= 9.1 ns

ENZHS

in t

SUD

t

= 1.2 ns

= 16.0 ns

OUTH

t

OUTSU

t

= 3.5 ns

t

= 1.0 ns

= 0.6 ns

CO

SUD

HD

Array

Clock

CKHS

t

= 6.4 ns

HCKH

F

= 85 MHz

HMAX

t

= 4.1 ns

IOCKH

I/O Clock

(pad-to-pad)

= 85 MHz

IOMAX

*Values shown for RP14100A at worst-case military conditions.

1 6

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

P a r a m e t e r M e a s u r e m e n t

O u t p u t B u ffe r De la y s

E

D

PAD

PAD To AC test loads (shown below)

TRIBUFF

V

CC

In

GND

1.5V

50%

E

GND

E

50%

GND

90%

50%

CC

50%

V

OH

1.5V

PAD

1.5V

10%

1.5V

V

GND

OL

t

ENHZ

DLH

DHL

ENZL

ENLZ

ENZH

AC T e s t Lo a d

Load 1

Load 2

(Used to measure propagation delay)

(Used to measure rising/falling edges)

V

GND

CC

To the output under test

50 pF

R to V for t /t

CC

PLZ PZL

R to GND for t

/t

PHZ PZH

R = 1 kΩ

To the output under test

50 pF

In p u t B u ffe r De la y s

C o m b in a t o r ia l Ma c r o De la y s

S

A

B

Y

PAD

INBUF

V

CC

GND

S, A, or B

50% 50%

V

3V

CC

50%

Y

50%

PAD

0V

1.5V

GND

V

CC

t

PHL

PLH

50%

Y

GND

50%

V

CC

Y

GND

t

50%

t

INYL

t

INYH

PHL

PLH

1 7

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s

F lip -F lo p s a n d La t c h e s (R P 1 2 8 0 A, A1 2 8 0 A)

D

E

CLK

Y

PRE

CLR

(Positive Edge-Triggered)

t

HD

1

D

t

A

WCLKA

SUD

G, CLK

t

SUENA

t

HENA

E

t

CO

Q

t

RS

PRE, CLR

t

WASYN

Note:

1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

1 8

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

F lip -F lo p s a n d La t c h e s (R P 1 4 1 0 0 A, A1 4 1 0 0 A)

D

E

Y

CLK

CLR

(Positive Edge-Triggered)

t

HD

1

D

t

A

WCLKA

SUD

G, CLK

t

SUENA

t

HENA

E

t

CO

Q

t

CLR

t

WASYN

Note:

1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

1 9

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

In p u t B u ffe r La t c h e s (R P 1 2 8 0 A, A1 2 8 0 A)

PAD

IBDL

G

PAD

CLK

CLKBUF

PAD

G

t

INH

t

INSU

t

HEXT

CLK

t

SUEXT

O u t p u t B u ffe r La t c h e s (R P 1 2 8 0 A, A1 2 8 0 A)

D

G

PAD

OBDLHS

D

t

OUTSU

G

t

OUTH

2 0

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

R P 1 2 8 0 A , A 1 2 8 0 A T i m i n g C h a r a c t e r i s t i c s

(Wo r s t -C a s e Milit a r y C o n d it io n s )

1

Logic Module Propagation Delays

‘–1 Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

t

Single Module

5.2

6.1

ns

PD1

CO

GO

RS

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

2

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.4

3.4

4.2

5.1

9.2

2.8

4.0

ns

RD1

RD2

RD3

RD4

RD8

4.9

6.0

10.8

3, 4

Sequential Timing Characteristics

t

f

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

0.5

0.0

1.3

0.0

7.4

16.4

2.5

3.5

0.0

0.5

0.0

1.3

0.0

8.6

22.1

2.5

3.5

0.0

0.5

ns

SUD

HD

ns

SUENA

HENA

WCLKA

WASYN

A

ns

Input Buffer Latch Hold

ns

INH

Input Buffer Latch Set-Up

ns

INSU

OUTH

OUTSU

MAX

Output Buffer Latch Hold

ns

Output Buffer Latch Set-Up

ns

Flip-Flop (Latch) Clock Frequency

60

41

MHz

Notes:

1. For dual-module macros, use t + t

+ t

, t + t

+ t

, or t + t

+ t

, whichever is appropriate.

SUD

PD1

RD1

PDn CO RD1

PDn

PD1

RD1

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal set-up (hold) time.

2 1

R P 1 2 8 0 A , A 1 2 8 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s )

Input Module Propagation Delays

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

t

Pad-to-Y HIGH

Pad-to-Y LOW

G-to-Y HIGH

G-to-Y LOW

4.0

3.6

6.9

6.6

4.7

4.3

8.1

7.7

ns

INYH

INYL

INGH

INGL

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

6.2

7.2

7.3

8.4

ns

IRD1

IRD2

IRD3

IRD4

IRD8

7.7

9.1

8.9

10.5

15.2

12.9

Global Clock Network

t

f

Input LOW to HIGH

FO = 32

FO = 384

13.3

17.9

15.7

21.1

CKH

ns

Input HIGH to LOW

FO = 32

FO = 384

13.3

18.2

15.7

21.4

CKL

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

FO = 32

FO = 384

6.9

7.9

8.1

9.3

PWH

PWL

CKSW

SUEXT

HEXT

P

ns

FO = 32

FO = 384

6.9

7.9

8.1

9.3

ns

FO = 32

FO = 384

0.6

3.1

0.6

3.1

ns

Input Latch External Set-Up

Input Latch External Hold

Minimum Period

FO = 32

FO = 384

0.0

ns

FO = 32

FO = 384

8.6

13.8

8.6

13.8

ns

FO = 32

FO = 384

13.7

16.0

16.2

18.9

ns

Maximum Frequency

FO = 32

FO = 384

73

63

62

53

MAX

MHz

Note:

1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.

Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to

determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior

to shipment.

2 2

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

R P 1 2 8 0 A , A 1 2 8 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s )

Output Module Timing

‘–1 Speed

Min. Max.

‘Std’ Speed

Min. Max.

Parameter

Description

Units

1

TTL Output Module Timing

t

Data-to-Pad HIGH

11.0

13.9

12.3

16.1

9.8

13.0

16.4

14.4

19.0

11.5

13.6

14.6

18.2

0.11

0.20

ns

DLH

Data-to-Pad LOW

DHL

Enable-to-Pad Z to HIGH

Enable-to-Pad Z to LOW

Enable-to-Pad HIGH to Z

Enable-to-Pad LOW to Z

G-to-Pad HIGH

ns

ENZH

ENZL

ENHZ

ENLZ

GLH

ns

11.5

12.4

15.5

0.09

0.17

ns

G-to-Pad LOW

ns

GHL

d

Delta LOW to HIGH

ns/pF

TLH

THL

Delta HIGH to LOW

1

CMOS Output Module Timing

t

Data-to-Pad HIGH

14.0

11.7

12.3

16.1

9.8

16.5

13.7

14.4

19.0

11.5

13.6

14.6

18.2

0.20

0.15

ns

DLH

Data-to-Pad LOW

DHL

Enable-to-Pad Z to HIGH

Enable-to-Pad Z to LOW

Enable-to-Pad HIGH to Z

Enable-to-Pad LOW to Z

G-to-Pad HIGH

ns

ENZH

ENZL

ENHZ

ENLZ

GLH

ns

11.5

12.4

15.5

0.17

0.12

ns

G-to-Pad LOW

ns

GHL

d

Delta LOW to HIGH

Delta HIGH to LOW

ns/pF

TLH

THL

Notes:

1. Delays based on 50 pF loading.

2. SSO information can be found in the “Simultaneously Switching Output Limits for Actel FPGAs” application note.

2 3

R P 1 4 1 0 0 A , A 1 4 1 0 0 A T i m i n g C h a r a c t e r i s t i c s

(Wo r s t -C a s e Milit a r y C o n d it io n s )

1

Logic Module Propagation Delays

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

t

Internal Array Module

Sequential Clock-to-Q

3.0

3.5

ns

PD

CO

CLR

Asynchronous Clear-to-Q

2

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.9

2.1

2.6

4.2

1.5

2.1

2.5

2.9

4.9

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Asynchronous Pulse Width

1.0

0.6

1.0

0.6

4.8

9.9

1.0

0.6

1.0

0.6

5.6

11.6

ns

SUD

HD

ns

SUENA

HENA

WASYN

WCLKA

A

ns

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

ns

100

85

MHz

MAX

Notes:

1. For dual-module macros, use t + t

+ t

, t + t

+ t

, or t + t

+ t

, whichever is appropriate.

SUD

PD

RD1

PDn CO RD1

PDn

PD1

RD1

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

2 4

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

R P 1 4 1 0 0 A , A 1 4 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s )

I/O Module Input Propagation Delays

‘–1 Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

t

Input Data Pad-to-Y

4.2

7.0

4.9

8.2

ns

INY

Input Reg IOCLK Pad-to-Y

Output Reg IOCLK Pad-to-Y

Input Asynchronous Clear-to-Y

ICKY

OCKY

ICLRY

OCLRY

Output Asynchronous Clear-to-Y

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.9

2.1

2.6

4.2

1.5

2.1

2.5

2.9

4.9

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input Flip-Flop Data Hold

Input Flip-Flop Data Set-Up

Input Data Enable Hold

0.0

2.1

0.0

8.7

1.2

0.6

2.4

0.0

2.4

0.0

10.0

1.2

0.6

2.4

ns

INH

INSU

IDEH

Input Data Enable Set-Up

Output Flip-Flop Data Hold

Output Flip-Flop Data Set-Up

Output Data Enable Hold

Output Data Enable Set-Up

IDESU

OUTH

OUTSU

ODEH

ODESU

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

2 5

R P 1 4 1 0 0 A , A 1 4 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–1 Speed

Min. Max.

‘Std’ Speed

Min. Max.

Parameter

Description

Units

t

Data-to-Pad, High Slew

7.5

8.9

ns

DHS

Data-to-Pad, Low Slew

11.9

6.0

14.0

7.0

DLS

Enable-to-Pad, Z to H/L, High Slew

Enable-to-Pad, Z to H/L, Low Slew

Enable-to-Pad, H/L to Z, High Slew

Enable-to-Pad, H/L to Z, Low Slew

IOCLK Pad-to-Pad H/L, High Slew

IOCLK Pad-to-Pad H/L, Low Slew

Delta LOW to HIGH, High Slew

Delta LOW to HIGH, Low Slew

Delta HIGH to LOW, High Slew

ns

ENZHS

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

10.9

11.9

10.9

12.2

17.8

0.04

0.07

0.05

0.07

12.8

14.0

12.8

14.0

17.8

0.04

0.08

0.06

0.08

ns

d

ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta HIGH to LOW, Low Slew

1

I/O Module – CMOS Output Timing

t

Data-to-Pad, High Slew

9.2

10.8

20.3

9.1

ns

DHS

Data-to-Pad, Low Slew

17.3

7.7

DLS

Enable-to-Pad, Z to H/L, High Slew

Enable-to-Pad, Z to H/L, Low Slew

Enable-to-Pad, H/L to Z, High Slew

Enable-to-Pad, H/L to Z, Low Slew

IOCLK Pad-to-Pad H/L, High Slew

IOCLK Pad-to-Pad H/L, Low Slew

Delta LOW to HIGH, High Slew

Delta LOW to HIGH, Low Slew

Delta HIGH to LOW, High Slew

Delta HIGH to LOW, Low Slew

ns

ENZHS

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.1

11.6

10.9

14.4

20.2

0.06

0.11

0.04

0.05

15.5

14.0

12.8

16.0

22.4

0.07

0.13

0.05

0.06

ns

d

ns/pF

TLHHS

TLHLS

THLHS

THLLS

Notes:

1. Delays based on 35 pF loading.

2. SSO information can be found in the “Simultaneously Switching Output Limits for Actel FPGAs” application note.

2 6

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

R P 1 4 1 0 0 A , A 1 4 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock Network

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

t

Input LOW to HIGH

IOCKH

(Pad to I/O Module Input)

3.5

4.1

ns

t

f

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Minimum Asynchronous Pulse Width

Maximum Skew

4.8

3.9

5.7

4.4

IOPWH

IOPWL

IOSAPW

IOCKSW

IOP

ns

0.9

1.0

85

ns

Minimum Period

9.9

11.6

ns

Maximum Frequency

100

MHz

IOMAX

Dedicated (Hard-Wired) Array Clock Network

t

Input LOW to HIGH

HCKH

(Pad to S-Module Input)

5.5

6.4

ns

t

Input HIGH to LOW

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

4.8

5.7

HPWH

HPWL

HCKSW

HP

ns

0.9

1.0

85

ns

Minimum Period

9.9

11.6

ns

Maximum Frequency

100

MHz

HMAX

Routed Array Clock Networks

t

f

Input LOW to HIGH (FO=256)

Input HIGH to LOW (FO=256)

Min. Pulse Width HIGH (FO=256)

Min. Pulse Width LOW (FO=256)

Maximum Skew (FO=128)

9.0

10.5

ns

RCKH

RCKL

RPWH

RPWL

RCKSW

RP

6.3

7.1

ns

1.9

75

2.1

65

ns

Minimum Period (FO=256)

12.9

14.5

ns

Maximum Frequency (FO=256)

MHz

RMAX

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

I/O Clock to R-Clock Skew

0.0

3.5

5.0

0.0

3.5

5.0

ns

IOHCKSW

IORCKSW

HRCKSW

H-Clock to R-Clock Skew

(FO = 64)

(FO = 50% max.)

0.0

1.0

3.0

0.0

1.0

3.0

ns

Note:

1. Delays based on 35 pF loading.

2 7

P a c k a g e P i n A s s i g n m e n t s

1 7 2 -P in C Q F P (T o p Vie w )

172 171 170 169 168 167 166 165 164

137 136 135 134 133 132 131 130

Pin #1

Index

1

2

3

4

5

6

7

8

129

128

127

126

125

124

123

122

172-Pin

CQFP

35

36

37

38

39

40

41

42

43

95

94

93

92

91

90

89

88

87

44 45 46 47 48 49 50 51 52

79 80 81 82 83 84 85 86

Function

RP1280A, A1280A Pin Number

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

150

154

171

7, 17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 108, 118, 123, 141, 152, 161

MODE

1

PRA or I/O

PRB or I/O

SDI or I/O

148

156

131

V

12, 23, 24, 27, 66, 80, 107, 109, 110, 113, 136, 151, 166

CC

Notes:

1. Unused I/O pins are designated as outputs by Designer and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.

2 8

®

R a d T o l e r a n t R A D -P A K F i e l d P r o g r a m m a b l e G a t e A r r a y s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 5 6 -P in C Q F P (T o p Vie w )

256 255 254 253 252 251 250 249 248

200 199 198 197 196 195 194 193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121 122 123 124 125 126 127 128

Function

RP14100A, A14100A Pin Number

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

219

220

256

1, 29, 31, 59, 91, 93, 110, 128, 158, 160, 175, 176, 189, 222, 224, 240

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

96

188

127

11

PRA or I/O

PRB or I/O

SDI or I/O

225

90

2

V

28, 30, 46, 92, 94, 141, 159, 161, 174, 221, 223

CC

Notes:

1. Unused I/O pins are designated as outputs by Designer and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.

2 9

P a c k a g e M e c h a n i c a l D r a w i n g s

C e r a m ic Q u a d F la t p a c k (C Q F P —C a v it y U p )

H

D1

D2

No. 1

Ceramic

Tie Bar

L1

K

E2 E1

F

e

b

A

Lid

C

Lead Kovar

A1

Notes:

1. All dimensions are in inches except CQ208 and CQ256 which are in millimeters.

2. Outside leadframe holes (from dimension H) are circular for the CQ208 and CQ256.

3. Seal ring and lid are connected to Ground.

4. Lead material is Kovar with minimum 60 miconiches gold over nickel.

5. Packages are shipped unformed with the ceramic tie bar.

6. 32200DX – CQ208 has heat sink on the backside.

3 0

®

RadTolerant RAD-PAK Field Programmable Gate Arrays

P a c k a g e M e c h a n i c a l D r a w i n g s (c o n t in u e d )

®

R AD-P AK C e r a m ic Q u a d F la t p a c k (1 7 2 -P in C Q F P R AD-P AK

)

2.300" ± 0.010"

D1 (sq)

D2 (sq)

4x

0.08" ± 0.005"

4x

0.06" ± 0.002"

No. 1

L2

2.14" ± 0.005"

0.90" ± 0.002

0.13" ± 0.005

e

b

ø 0.10" ± 0.002"

2 pls

2.140" ± 0.005"

L1 (sq)

A

F1

F4

c

A1

Notes:

1. All dimensions are in inches.

2. Seal ring and lid are connected to Ground.

3. Lead material is Kovar with gold over nickel.

4. Packages are shipped unformed with the ceramic tie bar.

3 1

C e r a m ic Q u a d F la t p a c k (C Q F P )

CQ256

Symbol

Min

Nom.

Max

A

2.28

1.93

0.18

0.11

35.64

2.67

2.29

3.06

2.65

0.22

0.18

36.36

A1

b

c

0.20

0.15

D1/E1

D2/E2

e

36.00

31.5 BSC

0.50 BSC

7.75

F

7.05

8.45

H

70.00 BSC

65.90 BSC

75.00

K

L1

74.60

75.40

Note:

1. All dimensions are in inches.

2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.

®

R AD-P AK C e r a m ic Q u a d F la t p a c k (R AD-P AK C Q F P )

®

RAD-PAK

CQ172

Symbol

Min

Nom.

Max

A

b

0.116

0.007

0.004

1.137

0.133

0.008

0.146

0.130

0.009

1.162

c

0.006

D11

D2

e

1.150

1.050 BSC

0.025 BSC

0.895

F1

F4

L1

0.890

0.881

2.485

1.690

0.079

0.900

0.899

0.890

2.500 2.5095

L2

1.700

0.091

1.710

0.103

A1

Note:

1. All dimensions are in inches.

2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.

3 2

®

RadTolerant RAD-PAK Field Programmable Gate Arrays

3 3

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Europe Ltd.

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

USA

Actel Asia-Paciﬁc

Daneshill House, Lutyens Close

Basingstoke, Hampshire RG24 8AG

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: +44.(0)1256.305600

Fax: +44.(0)1256.355420

Tel: 408.739.1010

Fax: 408.739.1540

Tel: +81.(0)3.3445.7671

Fax: +81.(0)3.3445.7668

5172138-1/1.99


型号：	RP1280A-CQ172B
厂家：	Microsemi
描述：	Field Programmable Gate Array, 41MHz, 1232-Cell, CMOS, CQFP172 时钟栅可编程逻辑
文件：	总34页 (文件大小：437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RP1280A-CQ172B [MICROSEMI]

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