RT14100A-STDCQ256B [MICROSEMI]
Field Programmable Gate Array, 1377 CLBs, 30000 Gates, 85MHz, 1377-Cell, CMOS, CQFP256, CERAMIC, QFP-256;型号: | RT14100A-STDCQ256B |
厂家: | Microsemi |
描述: | Field Programmable Gate Array, 1377 CLBs, 30000 Gates, 85MHz, 1377-Cell, CMOS, CQFP256, CERAMIC, QFP-256 时钟 栅 可编程逻辑 |
文件: | 总54页 (文件大小:333K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v3.1
RadTolerant FPGAs
Features
•
•
•
Up to 60 MHz System Performance
Up to 228 User I/Os
Up to Four Fast, Low-Skew Clock Networks
General Characteristics
•
•
Tested Total Ionizing Dose (TID) Survivability Level
No Single Event Latch-Up Below a Minimum LET
(Linear Energy Transfer) Threshold of 80 MeV-cm2/mg
for All RT (RadTolerant) Devices
Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and
256-Pin Ceramic Quad Flat Pack
Easy Logic Integration
•
•
•
•
Nonvolatile, User Programmable
Pin-Compatible Commercial Devices Available for
Prototyping
Highly Predictable Performance with 100%
Automatic Place-and-Route
100% Resource Utilization with 100% Pin-Locking
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
Offered as Class B and E-Flow (Actel Space Level
Flow)
•
•
•
QML Certified Devices
100% Military Temperature Tested (–55°C to
+125°C)
•
•
•
•
Permanently Programmed for Operation on
Power-Up
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer
High Density and Performance
•
•
•
4,000 to 20,000 Logic Equivalent Gates
2,000 to 10,000 ASIC Equivalent Gates
Up to 85 MHz Internal Performance
Product Family Profile
Table 1 •
Device
RadTolerant Family
RT1020
RT1280A
RT1425A
RT1460A
RT14100A
Capacity
System Gates
6,000
4,000
2,000
5,000
50
24,000
16,000
8.000
20,000
200
7,500
5,000
2,500
6,250
60
18,000
12,000
6,000
15.000
150
30,000
20,000
10,000
25,000
250
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
20
80
25
60
100
Logic Modules
S-Modules
C-Modules
547
N/A
547
1,232
624
608
310
160
150
848
432
416
1,377
697
680
User I/Os (Maximum)
69
20 MHz
84
140
40 MHz
172
100
60 MHz
132
168
60 MHz
196
228
60 MHz
256
Performance
System Speed (Maximum)
Packages (by Pin Count)
CQFP
October 2004
i
© 2004 Actel Corporation
See Actel’s website for the latest version of the datasheet
RadTolerant FPGAs
Ordering Information
RT1280A
CQ
-
172
E
Application (Temperature Range)
C = Commercial (0 to +70˚C)
M = Military (-55 to +125˚C)
B = MIL-STD-883 Class B
E = Extended Flow (Space Level)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack (CQFP)
Speed Grade
Std = Standard Speed
-1 = Approximately 15% Faster than Standard
Part Number
RT1020
= 4,000 Gates—RadTolerant ACT 1
RT1280A = 16,000 Gates—RadTolerant ACT 2
RT1425A = 5,000 Gates—RadTolerant ACT 3
RT1460A = 12,000 Gates—RadTolerant ACT 3
RT14100A = 20,000 Gates—RadTolerant ACT 3
A1020B = 4,000 Gates—ACT 1
A1280A = 16,000 Gates—ACT 2
A1425A = 5,000 Gates—ACT 3
A1460A = 12,000 Gates—ACT 3
A14100A = 20,000 Gates—ACT 3
Device Resources
User I/Os
Gate Array
Equivalent
Gates
CQFP
84-Pin
CQFP
132-Pin
CQFP
172-Pin
CQFP
196-Pin
CQFP
256-Pin
FPGA Device Type
RT1020/A1020B
Logic Modules
547
1,232
310
2,000
8,000
2,500
6,000
10,000
69
–
–
–
–
140
–
–
–
–
–
RT1280A/A1280A
RT1425A/A1425A
RT1460A/A1460A
RT14100A/A14100A
–
100
–
–
–
848
–
–
168
–
–
1,377
–
–
–
228
Note: Package Definition: CQFP = Ceramic Quad Flat Pack
Contact your Actel sales representative for product availability.
ii
v3.1
RadTolerant FPGAs
Product Plan
Speed Grade
Application
Commercial Military MIL-STD-883
Extended
Std
✓
–1*
–
Flow
ACT 1
ACT 2
ACT 3
RT1020 Device
84-Pin Ceramic Quad Flat Pack (CQFP)
A1020B Device (Prototyping Use)
84-Pin Ceramic Quad Flat Pack (CQFP)
RT1280A Device
–
✓
–
–
✓
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
172-Pin Ceramic Quad Flat Pack (CQFP)
A1280A Device (Prototyping Use)
172-Pin Ceramic Quad Flat Pack (CQFP)
RT1425A Device
✓
✓
–
✓
✓
–
✓
–
132-Pin Ceramic Quad Flat Pack (CQFP)
A1425A Device (Prototyping Use)
132-Pin Ceramic Quad Flat Pack (CQFP)
RT1460A Device
✓
✓
–
✓
✓
–
✓
–
196-Pin Ceramic Quad Flat Pack (CQFP)
A1460A Device (Prototyping Use)
196-Pin Ceramic Quad Flat Pack (CQFP)
RT14100A Device
✓
✓
–
✓
✓
–
✓
–
256-Pin Ceramic Quad Flat Pack (CQFP)
A14100A Device (Prototyping Use)
256-Pin Ceramic Quad Flat Pack (CQFP)
✓
✓
–
✓
✓
✓
Note: Contact your Actel sales representative for product availability. Availability: ✔ = Available, – Symbol = Not Planned
* Speed Grade: –1 = Approx. 15% faster than Standard
v3.1
iii
RadTolerant FPGAs
Table of Contents
RadTolerant FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
RadTolerant Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
The RT1020 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
RT1020, A1020B Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
RT1280A, A1280A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
RT1425A, A1425A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
RT1460A, A1460A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
RT14100A, A14100A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Package Pin Assignments
84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
132-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
172-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
196-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Export Administration Regulations (EAR) or International Traffic in Arms
Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
iv
v3.1
RadTolerant FPGAs
RadTolerant FPGAs
General Description
Actel builds the most reliable field programmable gate
arrays (FPGAs) in the industry, with overall antifuse
reliability ratings of less than 10 failures-in-time (FITs),
corresponding to a useful life of more than 40 years.
Actel FPGAs are production-proven, with more than five
million devices shipped and more than one trillion
antifuses manufactured. Actel devices are fully tested
prior to shipment, with an outgoing defect level of only
122 ppm (further reliability data is available in the Actel
Device Reliability Report).
These devices also have fully pin- and function-
compatible commercially-equivalent devices for easy and
inexpensive prototyping. The A1425A-CQ132C is used for
the RT1425A, the A1460A-CQ196C is used for the
RT1460A, and the A14100A-CQ256C is used for the
RT14100A.
Radiation Survivability
Total dose results are summarized in two ways. The first
method summarizes by the maximum total dose level
that is reached when the parts fail to meet a device
specification but remain functional. For Actel FPGAs, the
parameter that exceeds the specification first is the
standby supply current (ICC). The second method
summarizes by the maximum total dose that is reached
prior to the functional failure of the device.
Additionally, the programmable architecture of these
devices offers high performance, design flexibility, and
fast and inexpensive prototyping—all without the
expense of test vectors, NRE charges, long lead times,
and schedule and cost penalties for design refinements.
Device Description
The Actel RT devices have varying total-dose radiation
survivability. The ability of these devices to survive
radiation effects is both device- and lot-dependent. The
user must evaluate and determine the applicability of
these devices for specific design and environmental
requirements.
The RT1020 device contains the same architecture as the
A1020, A1020A, and A1020B devices. The architecture, a
combinatorial logic module, is a logic structure with 8 inputs
and 1 output. The logic itself is comprised of a 4-input MUX,
as described in Figure 1-3 on page 1-4. In addition, since
the RT1020 device contains the same number of gates and
I/Os and has the same operating voltage as its commercial
equivalent (A1020B), an inexpensive commercial grade
A1020B-CQ84 device can be used during the prototype
phase, and replaced by the RT1020 in the flight units.
Typical results for the RT1020 device are ~100krads (Si)
for standby ICC and >100krads for functional failure. The
RT1280A device has results from 4 to 10krads (Si) for
standby ICC, and 7 to 18krads for functional failure.
Typical results for ACT 3 devices are 10 to 28krads for ICC
and 20 to 77krads for functional failure.
,
The RT1280A device uses the A1280A die from the ACT 2
family of FPGAs. It utilizes a two-module architecture,
consisting of combinatorial modules (C-modules) and
sequential modules (S-modules) optimized for both
combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the RT1280A has
8,000 ASIC-equivalent gates and 140 user I/Os.
Actel will provide total dose radiation testing along with
the test data on each pedigreed lot that is available for
sale. These reports are available on our website, or you
can contact your local sales representative to receive a
copy. A listing of available lots and devices is also
provided. These results are provided only for reference
and for customer information.
The RT1280A device is fully pin- and function-compatible
with the commercially-equivalent A1280A-CQ172C device
for easy, inexpensive prototyping.
For a radiation performance summary, see Radiation
Performance of Actel Products on the Actel Website. This
summary also shows single event upset (SEU) and single
event latch-up (SEL) testing that has been performed on
Actel FPGAs.
The RT1425A, RT1460A and RT14100A devices use the
A1425A, A1460A and A14100A dies, respectively. These
devices are derived from the ACT 3 family of FPGAs,
which also utilizes the two-module channeled array
architecture, and offers faster performance than the
RT1280A.
v3.1
1-1
RadTolerant FPGAs
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
QML Certification
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is an example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
timing-driven place-and-route, and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results of
place-and-route. Additionally, the back-annotation flow is
compatible with all the major simulators and the
simulation results can be cross-probed with Silicon Explorer
II, Actel’s integrated verification and logic analysis tool.
Another tool included in the Designer software is the
ACTgen macro builder, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design. Actel's Designer software is
compatible with the most popular FPGA design entry and
verification tools from companies such as Mentor Graphics,
Synplicity, Synopsys, and Cadence Design Systems. The
Designer software is available for both the Windows and
UNIX operating systems.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in
the implementation of advanced technologies, but also
allows for quality, reliable and cost-effective logistics
support throughout the QML products life cycles.
Disclaimer
All radiation performance information is provided for
information purposes only and is not guaranteed. The
total dose effects are lot-dependent, and Actel does not
guarantee that future devices will continue to exhibit
similar radiation characteristics. In addition, actual
performance can vary widely due to a variety of factors,
including but not limited to characteristics of the orbit,
radiation environment, proximity to satellite exterior,
amount of inherent shielding from other sources within
the satellite, and actual bare die variations. For these
reasons, Actel does not guarantee any level of radiation
survivability, and it is solely the responsibility of the
customer to determine whether the device will meet the
requirements of the specific design.
RadTolerant Architecture
The Actel architecture is composed of fine-grained logic
modules that produce fast, efficient logic designs. All
devices are composed of logic modules, routing
resources, clock networks, and I/O modules, which are
the building blocks for fast logic designs.
Logic Modules
These RadTolerant devices contain two types of logic
modules, combinatorial (C-modules) and sequential
(S-modules). RT1020 and A1020B devices contain only C-
modules.
The C-module, shown in Figure 1-1, implements EQ 1-1:
Development Tool Support
Y = !S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
T
he HiRel devices are fully supported by both the Actel
EQ 1-1
Libero™ Integrated Design Environment (IDE) and
Designer FPGA Development software. Actel Libero IDE
where:
is
a
design management environment, seamlessly
S0 = A0 * B0
S1 = A1+ B1
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Libero IDE
allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment. Libero IDE includes Synplify® for
Actel from Synplicity®, ViewDraw® for Actel from
Mentor Graphics, ModelSim® HDL Simulator from
A0
B0
S0
D00
D01
Y
Mentor
Graphics®,
WaveFormer
Lite™
from
D10
D11
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow diagram for more information.
S1
A1
B1
Figure 1-1 • C-Module Implementation
1-2
v3.1
RadTolerant FPGAs
The S-module, shown in Figure 1-2, is designed to
implement high-speed sequential functions within a
single logic module. The S-module implements the same
combinatorial logic function as the C-module while
adding a sequential element. The sequential element can
Flip-flops can also be created using two C-modules. The
SEU characteristics differ between an S-module flip-flop
and a flip-flop created using two C-modules. For details
see the Design Techniques for RadHard Field
Programmable Gate Arrays application note.
be configured as either
a D-type flip-flop or a
transparent latch. To increase flexibility, the S-module
register can be bypassed so it implements purely
combinatorial logic.
D00
D01
D00
D01
OUT
Y
D
Q
Y
D
Q
OUT
D10
D11
S1
D10
D11
S1
S0
S0
GATE
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00
D01
D0
Y
OUT
Y
D
Q
OUT
D10
S0
D1
D11
S1
GATE
CLR
S
Up to 8-Input Function (Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 1-2 • S-Module Implementation
v3.1
1-3
RadTolerant FPGAs
The Actel Designer software development tools provide
a design library of I/O macros. The I/O macro library
provides macro functions that can implement all I/O
configurations supported by the RadTolerant FPGAs.
The RT1020 Logic Module
The RT1020 logic module is an 8-input, 1-output logic
circuit chosen for the wide range of functions it
implements and for its efficient use of interconnect
routing resources (Figure 1-3).
EN
Q
D
PAD
From Array
G/CLK*
Q
D
To Array
G/CLK*
* Can be configured as a Latch or D-Flip-Flop
(Using C-Module)
Figure 1-4 • I/O Module
Routing Structure
Figure 1-3 • RT1020 Logic Module
The RadTolerant device architecture uses vertical and
horizontal routing tracks to interconnect the various
logic and I/O modules. These routing tracks are metal
interconnects that may either be of continuous length or
broken into segments. Varying segment lengths allow
over 90% of the circuit interconnects to be made with
only two antifuse connections. Segments can be joined
together at the ends, using antifuses to increase their
length up to the full length of the track. All
interconnects can be accomplished with a maximum of
four antifuses.
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two,
three, or four inputs. Each function may have many
versions, with different combinations of active low
inputs. The logic module can also implement a variety of
D-latches, exclusivity functions, AND-ORs, and OR-ANDs.
No dedicated hardwired latches or flip-flops are required
in the array, since latches and flip-flops may be
constructed from logic modules wherever needed in the
application.
Horizontal Routing
I/O Modules
Horizontal channels are located between the rows of
modules, and are composed of several routing tracks.
The horizontal routing tracks within the channel are
divided into one or more segments. The minimum
horizontal segment length is the width of a module-pair,
and the maximum horizontal segment length is the full
length of the channel. Any segment that spans more
than one-third the row length is considered a long
horizontal segment. A typical channel is shown in
Figure 1-5 on page 1-5. Non-dedicated horizontal
routing tracks are used to route signal nets. Dedicated
routing tracks are used for the global clock networks,
and for power and ground tie-off tracks.
I/O modules provide the interface between the device
pins and the logic array. A variety of user functions,
determined by a library macro selection, can be
implemented in the module (refer to the Macro Library
Guide for more information). I/O modules contain a
tristate buffer, and input and output latches that can be
configured for input, output, or bidirectional pins
(Figure 1-4).
The RadTolerant devices contain flexible I/O structures in
that each output pin has a dedicated output enable
control. The I/O module can be used to latch input and/or
output data, providing a fast setup time. In addition, the
Actel Designer software tools can build a D-flip-flop,
using a C-module, to register input and/or output
signals.
Vertical Routing
Another set of routing tracks runs vertically through the
module. There are three types of vertical tracks that can
be divided into one or more segments: input, output,
and long. Each segment in an input track is dedicated to
the input of a particular module. Each segment in an
1-4
v3.1
RadTolerant FPGAs
output track is dedicated to the output of a particular
module. Long segments are uncommitted and can be
assigned during routing. Each output segment spans
four channels (two above and two below), except near
the top and bottom of the array where edge effects
occur. Long vertical tracks contain either one or two
segments. An example of vertical routing tracks and
segments is shown in Figure 1-5.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to
the normally closed fuse structure used in PROMs
(programmable read-only memory) or PALs (programmed
array logic). The use of antifuses to implement a PLD
(programmable logic device) results in highly testable
structures, as well as efficient programming algorithms.
The structure is highly testable because there are no pre-
existing connections, enabling temporary connections to
be made using pass transistors. These temporary
connections can isolate individual antifuses to be
programmed, and also isolate individual circuit structures
to be tested. This can be done both before and after
programming. For example, all metal tracks can be tested
for continuity and shorts between adjacent tracks, and
the functionality of all logic modules can be verified.
Logic
Modules
Segmented
Horizontal
Routing
Tracks
Antifuses
Vertical Routing Tracks
Figure 1-5 • Routing Structure
Table 1-1 • Actel MIL-STD-883 Product Flow
883 - Class B
Step
1.
Screen
Internal Visual
883 Method
Requirement
2010, Test Condition B
1010, Test Condition C
100%
2.
Temperature Cycling
Constant Acceleration
100%
3.
2001, Test Condition D or E, Y1, Orientation Only
1014
100%
4.
Seal
a. Fine
b. Gross
100%
100%
5.
6.
7.
8.
Visual Inspection
2009
100%
100%
100%
100%
Pre-Burn-In Electrical Parameters
Burn-in Test
In accordance with applicable Actel device specification
1015, Condition D, 160 hours @ 125°C or 80 hours @ 150°C
In accordance with applicable Actel device specification
Interim (Post-Burn-In) Electrical
Parameters
9.
Percent Defective Allowable
Final Electrical Test
5%
All Lots
100%
10.
In accordance with applicable Actel device specification, which
includes a, b, and c:
a. Static Tests
(1) 25°C (Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
5005
5005
b. Functional Tests
100%
(1) 25°C (Subgroup 7, Table I)
(2) –55°C and +125°C
5005
5005
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
5005
2009
100%
100%
11.
External Visual
Note: When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method
2018 must be waived.
v3.1
1-5
RadTolerant FPGAs
Table 1-2 • Actel Extended Flow1
Step
1.
Screen
Wafer Lot Acceptance2
Method
5007 with Step Coverage Waiver
2011, Condition D
Requirement
All Lots
Sample
100%
2.
Destructive In-Line Bond Pull3
3.
Internal Visual
2010, Condition A
4.
Serialization
100%
5.
Temperature Cycling
1010, Condition C
100%
6.
Constant Acceleration
Particle Impact Noise Detection
Radiographic
2001, Condition D or E, Y1 Orientation Only
2020, Condition A
100%
7.
100%
8.
2012
100%
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
1015, Condition D, 240 hours @ 125°C minimum
In accordance with applicable Actel device specification
1015, Condition C, 72 hours @ 150°C minimum
In accordance with applicable Actel device specification
5%, 3% Functional Parameters @ 25°C
100%
10.
11.
12.
13.
14.
Burn-in Test
100%
Interim (Post-Burn-In) Electrical Parameters
Reverse Bias Burn-In
100%
100%
Interim (Post-Burn-In) Electrical Parameters
100%
Percent Defective Allowable (PDA)
Calculation
All Lots
15.
Final Electrical Test
In accordance with Actel applicable device specification,
which includes a, b, and c:
100%
100%
a. Static Tests
(1) 25°C (Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
5005
5005
100%
b. Functional Tests
(1) 25°C (Subgroup 7, Table 15)
(2) –55°C and +125°C
5005
5005
(Subgroups 8A and B, Table 1)
100%
100%
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
5005
1014
16.
Seal
a. Fine
b. Gross
17.
External Visual
2009
100%
Notes:
1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B.
Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this
extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The
exceptions to Method 5004 are shown in notes 2 and 3 below.
2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be
waived.
3. Method 5004 requires a 100 percent, non-destructive bond pull (Method 2023). Actel substitutes a destructive bond pull (Method
2011), Condition D on a sample basis only.
1-6
v3.1
RadTolerant FPGAs
Absolute Maximum Ratings
Stresses beyond those listed in this table may cause permanent damage to the device. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
recommended operating conditions.
Table 1-3 • Free Air Temperature Range
Symbol
VCC
Parameter
DC Supply Voltage1, 2, 3
Limits
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
20
Units
V
VI
Input Voltage
V
VO
Output Voltage
I/O Source Sink Current4
V
IIO
mA
°C
TSTG
Notes:
Storage Temperature
–65 to +150
1. VPP = VCC, except during device programming
2. VSV = VCC, except during device programming
3. VKS = GND, except during device programming
4. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V
or less than GND – 0.5 V, the internal protection diode will be forward-biased and can draw excessive current.
Table 1-4 • Recommended Operating Conditions
Parameter
Commercial
Military
–55 to +125
10
Units
°C
Temperature Range1
Power Supply Tolerance2
Notes:
0 to +70
5
%VCC
1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military
2. All power supplies must be in the recommended operating range. For more information, refer to the Power-Up and Power-Down
Behavior of 54SX and RT54SX Devices application note.
Table 1-5 • Electrical Specifications
Commercial
Military
Symbol
Parameter
HIGH Level Output
Test Condition
IOH = –4 mA (CMOS)
IOH = –6 mA (CMOS)
IOL = +6 mA (CMOS)
TTL Inputs
Min.
Max.
Min.
Max.
Units
V
1, 2
VOH
3.7
3.84
V
1, 2
VOL
LOW Level Output
0.33
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
V
VIH
HIGH Level Input
2.0
–0.3
–10
–10
2.0
–0.3
–10
–10
V
VIL
LOW Level Input
TTL Inputs
V
IIN
Input Leakage
VI = VCC or GND
VO = VCC or GND
+10
+10
µA
µA
pF
mA
IOZ
3-State Output Leakage
I/O Capacitance3, 4
Standby VCC Supply Current
Dynamic VCC Supply Current
+10
+10
CIO
10
10
ICC(S)
ICC(D)
Notes:
VI = VCC or GND, IO = 0 mA
2
20
See "Power Dissipation" on page 1-8.
1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.
2. Tested one output at a time, VCC = min.
3. Not tested; for information only
4. VOUT = 0V, f = 1 MHz
v3.1
1-7
RadTolerant FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CQFP 172-pin package at
military temperature is as follows:
Max. junction temp. (°C) – Max. military temp.
150°C – 125°C
---------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 1.0W
θ
(°C/W)
25°C/W
ja
EQ 1-2
Table 1-6 • Package Thermal Characteristics
θja
Still Air
θja
Package Type
Pin Count
θjc
7.8
7.2
6.8
6.4
6.2
300 ft./min.
Units
Ceramic Quad Flat Pack
8
40
35
25
23
20
30
25
20
15
10
°C/W
°C/W
°C/W
°C/W
°C/W
132
172
196
256
Static Power Component
Power Dissipation
Actel FPGAs have small static power components that
result in power dissipation lower than that of PALs or
PLDs. By integrating multiple PALs or PLDs into one
FPGA, an even greater reduction in board-level power
dissipation can be achieved.
General Power Equation
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
IOH * (VCC – VOH) * M
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst-case conditions.
EQ 1-3
where:
•
I
CCstandby is the current flowing when no inputs
ICC
VCC
Power
or outputs are changing.
•
ICCactive is the current flowing due to CMOS
switching.
2 mA
5.25 V
10.5 mW
The static power dissipated by TTL loads depends on the
number of outputs driving HIGH or LOW and on the DC
load current. Again, this value is typically small. For
instance, a 32-bit bus sinking 4 mA at 0.33 V will
generate 42 mW with all outputs driving LOW, and
140 mW with all outputs driving HIGH.
•
•
•
I
OL, IOH are TTL sink/source currents.
OL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads
to VOL
M equals the number of outputs driving TTL loads
to VOH
V
.
•
.
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
1-8
v3.1
RadTolerant FPGAs
Active Power Component
Equivalent Capacitance
Power dissipation in CMOS devices is usually dominated
by the active (dynamic) power dissipation. This
component is frequency-dependent, a function of the
logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitance due to PC
board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in CMOS transistor pairs. The net effect can
be associated with an equivalent capacitance that can be
combined with frequency and voltage to represent
active power dissipation.
The power dissipated by a CMOS circuit can be expressed
by EQ 1-4:
Power (uW) = CEQ * VCC2 * F
EQ 1-4
where:
CEQ = Equivalent capacitance in pF
VCC = Power supply in volts (V)
F
= Switching frequency in MHz
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a
range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency-independent, so the results can
be used over a wide range of operating conditions.
Equivalent capacitance values are shown in Table 1-7
.
Table 1-7 • CEQ Values for Actel FPGAs
RT1020,
A1020B
RT1280A,
A1280A
RT1425A, A1425A, RT1460A,
A1460A, RT14100A, A14100A
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer Loads (CEQCR
Dedicated Clock Buffer Loads (CEQCD
I/O Clock Buffer Loads (CEQCI
)
3.7
22.1
32.1
4.6
5.8
12.9
23.8
3.9
6.7
7.2
)
)
10.4
1.6
)
)
n/a
n/a
0.7
)
n/a
n/a
0.9
v3.1
1-9
RadTolerant FPGAs
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic
must be known. EQ 1-5 shows a piece-wise linear summation over all components. Since the RT1280A and A1280A
have two routed array clocks, the dedicated_Clk and IO_Clk terms do not apply. For all other devices all terms apply.
Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1
*fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk
EQ 1-5
Table 1-8 • Fixed Capacitance Values for Actel FPGAs (pF)
r1 r2
]
where:
m
n
=
=
=
=
Number of logic modules switching at fm
Number of input buffers switching at fn
Number of output buffers switching at fp
Device Type
routed_Clk1 routed_Clk2
RT1020, A1020B
RT1280A, A1280A
RT1425A, A1425A
RT1460A, A1460A
RT14100A, A14100A
69
168
75
n/a
168
75
p
q1
Number of clock loads on the first routed array
clock
165
195
165
195
q2
=
Number of clock loads on the second routed array
clock (not applicable for RT1020 or A1020B)
r1
r2
=
=
Fixed capacitance due to first routed array clock
Table 1-9 • Fixed Clock Loads (s1/s2 – ACT 3 Only)
Fixed capacitance due to second routed array clock
(not applicable for RT1020 or A1020B)
s1
s2
Clock Loads
on Dedicated on Dedicated
Clock Loads
s1
=
=
Fixed number of clock loads on the dedicated array
clock (not applicable for RT1020, A1020B,
RT1280A, or A1280A)
Device Type
Array Clock
I/O Clock
RT1425A, A1425A
RT1460A, A1460A
RT14100A, A14100A
160
432
697
100
s2
Fixed number of clock loads on the dedicated
I/O clock (not applicable for RT1020, A1020B,
RT1280A, or A1280A)
168
228
CEQM
CEQI
=
=
=
=
=
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Equivalent capacitance of routed array clock in pF
CEQO
CEQCR
CEQCD
Equivalent capacitance of dedicated array clock
in pF
CEQCI
CL
=
=
=
=
=
=
=
Equivalent capacitance of dedicated I/O clock in pF
Output lead capacitance in pF
fm
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
Average output buffer switching rate in MHz
Average first routed array clock rate in MHz
fn
fp
fq1
fq2
Average second routed array clock rate in MHz (not
applicable for RT1020 or A1020B)
fs1
=
=
Average dedicated array clock rate in MHz (not
applicable for RT1020, A1020B, RT1280A, or
A1280A)
fs2
Average dedicated I/O clock rate in MHz
(not applicable for RT1020, A1020B, RT1280A, or
A1280A)
1-10
v3.1
RadTolerant FPGAs
Determining Average Switching Frequency
To determine the switching frequency for a design, you must have a detailed understanding of the data input values
to the circuit. The guidelines below are meant to represent worst-case scenarios; they can be generally used to predict
the upper limits of power dissipation.
RT1020, A1020B, RT1280A, A1280A
Logic Modules (m)
=
=
=
=
=
=
=
=
=
=
=
=
=
80% of Combinatorial Modules
Input Switching (n)
# Inputs/4
Outputs Switching (p)
# Outputs/4
First Routed Array Clock Loads (q1)
Second Routed Array Clock Loads (q2)
Load Capacitance (CL)
40% of Sequential Modules
40% of Sequential Modules
35 pF
F/10
F/5
Average Logic Module Switching Rate (fm)
Average Input Switching Rate (fn)
Average Output Switching Rate (fp)
Average First Routed Array Clock Rate (fq1
F/10
F
)
Average Second Routed Array Clock Rate (fq2
Average Dedicated Array Clock Rate (fs1)
Average Dedicated I/O Clock Rate (fs2)
)
F/2
n/a
n/a
RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A
Logic Modules (m)
=
=
=
=
=
=
=
=
=
=
=
=
=
80% of Combinatorial Modules
Input Switching (n)
# Inputs/4
Outputs Switching (p)
# Outputs/4
First Routed Array Clock Loads (q1)
Second Routed Array Clock Loads (q2)
Load Capacitance (CL)
40% of Sequential Modules
40% of Sequential Modules
35 pF
F/10
F/5
F/10
F/2
F/2
F
Average Logic Module Switching Rate (fm)
Average Input Switching Rate (fn)
Average Output Switching Rate (fp)
Average First Routed Array Clock Rate (fq1
)
Average Second Routed Array Clock Rate (fq2
Average Dedicated Array Clock Rate (fs1)
Average Dedicated I/O Clock Rate (fs2)
)
F
v3.1
1-11
RadTolerant FPGAs
Input Delay
Internal Delays
Predicted
Routing
Delays
Output Delay
Logic Module
I/O Module
I/O Module
t
IRD2 = 1.9 ns
t
INYL = 3.9 ns
t
t
DLH = 8.3 ns
t
IRD1 = 1.1 ns
RD1 = 1.1 ns
t
t
t
t
t
IRD4 = 3.9 ns
PD = 3.6 ns
RD2 = 1.8 ns
ENHZ = 12.3 ns
t
t
IRD8 = 8.1 ns
CO = 3.6 ns
RD4 = 3.9 ns
t
RD8 = 8.1 ns
ARRAY
CLOCK
t
FO = 128
CKH = 6.9 ns
F
MAX = 55 MHz
Figure 1-6 • RT1020, A1020B Timing Model
Predicted
Routing
Delays
Input Delays
Output Delays
Internal Delays
I/O Module
Combinatorial
Logic Module
I/O Module
t
t
†
IRD2 = 7.2 ns
INYL = 3.6 ns
t
DLH = 14.0 ns
t
t
t
t
RD1 = 2.4 ns
RH2 = 3.4 ns
RD4 = 5.1 ns
RD8 = 9.2 ns
D
G
Q
t
PD1 = 5.2 ns
I/O Module
t
DLH = 14.0 ns
Sequential
t
t
t
INH = 2.5 ns
INSU = 3.5 ns
INGL = 6.6 ns
Logic Module
Combin-
D
Q
D
G
Q
atorial
Logic
t
t
RD1 = 2.4 ns
ENHZ = 9.8 ns
included
in SUD
t
t
t
t
OUTH = 0.0 ns
OUTSU = 0.5 ns
GLH = 12.5 ns
t
t
t
SUD = 0.5 ns
HD = 0.0 ns
CO = 5.2 ns
ARRAY
CLOCKS
FO = 32
t
CKH = 13.3 ns
F
MAX = 73 MHz
Notes:
1. *Values shown for RT1280A –1 at worst-case military conditions.
2. † Input module predicted routing delay
Figure 1-7 • RT1280A, A1280A Timing Model*
1-12
v3.1
RadTolerant FPGAs
Predicted
Routing
Delays
Input Delays
Internal Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
t
t
IRD2 = 1.9 ns
INY = 4.2 ns
t
DHS = 9.2 ns
t
t
t
RD1 = 1.3 ns
RD4 = 2.6 ns
RD8 = 4.2 ns
t
PD = 3.0 ns
D
Q
I/O Module
t
DHS = 9.2 ns
t
Sequential
Logic Module
INH = 0.0 ns
t
t
INSU = 2.1 ns
ICKY = 7.0 ns
t
RD1 = 1.3 ns
D
Q
D
Q
Combinatorial
Logic
included
t
ENZHS = 7.7 ns
t
in SUD
t
t
t
OUTH = 1.2 ns
OUTSU = 1.2 ns
CKHS = 14.4 ns
t
t
t
SU = 1.0 ns
HD = 0.6 ns
CO = 3.0 ns
ARRAY
CLOCK
t
HCKH = 5.5 ns
F
HMAX = 100 MHz
t
I/O CLOCK
IOCKH = 3.5 ns
(pad-to-pad)
F
IOMAX = 100 MHz
Note: *Values shown for RT14100A –1 at worst-case military conditions.
Figure 1-8 • RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Timing Model*
v3.1
1-13
RadTolerant FPGAs
Parameter Measurement
E
D
PAD To AC Test Loads (shown below)
TRIBUFF
VCC
VCC
VCC
GND
GND
GND
90%
E
In
50% 50%
VOH
E
50% 50%
VCC
50% 50%
VOH
1.5V
1.5V
PAD
VOL
PAD
PAD
GND
1.5V
10%
1.5V
VOL
t
t
t
t
t
t
DLH
DHL
ENZL
ENLZ
ENZH
ENHZ
Figure 1-9 • Output Buffer Delays
Load 2
Load 1
(Used to measure propagation delay)
(Used to measure rising/falling edges)
VCC
GND
To the Output under Test
t
t
R to VCC for PLZ/ PZL
50 pF
To the Output under Test
t
t
R to GND for PHZ/ PZH
R = 1 k
Ω
50 pF
Figure 1-10 • AC Test Load
S
A
B
Y
Y
PA D
INBUF
VCC
S, A or B 50% 50%
GND
3V
VCC
50%
PAD
0V
Y
50%
1.5V 1.5V
VCC
GND
t
t
50%
PLH
PHL
Y
GND
50%
VCC
50%
Y
50%
GND
t
t
INYL
INYH
t
t
PHL
PLH
Figure 1-11 • Input Buffer Delays
Figure 1-12 • Combinatorial Macro Delays
1-14
v3.1
RadTolerant FPGAs
Sequential Timing Characteristics
D
E
PRE
CLR
Y
CLK
(Positive Edge Triggered)
t
HD
D1
t
t
t
A
SUD
WCLKA
G, CLK
t
SUENA
t
HENA
E
t
co
Q
t
RS
PRE, CLR
t
WASYN
D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-13 • Flip-Flops and Latches (RT1280A, A1280A)
D
E
PRESET
CLR
Y
CLK
(Positive Edge Triggered)
t
HD
D1
t
t
t
A
SUD
WCLKA
G, CLK
t
SUENA
t
HENA
E
t
CO
Q
t
CLR
CLR
t
WASYN
D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-14 • Flip-Flops and Latches (RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A)
v3.1
1-15
RadTolerant FPGAs
PAD
G
IBDL
PAD
CLK
CLKBUF
PAD
G
t
INH
t
INSU
t
HEXT
CLK
t
SUEXT
Figure 1-15 • Input Buffer Latches (R1280A, A1280A)
D
G
PAD
OBDLHS
D
t
OUTSU
G
t
OUTH
Figure 1-16 • Output Buffer Latches (RT1280A, A1280A)
1-16
v3.1
RadTolerant FPGAs
RT1020, A1020B Timing Characteristics
Table 1-10 • RT1020, A1020B Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
Std Speed
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
3.6
8.4
3.6
3.6
3.6
ns
ns
ns
ns
ns
Dual Module Macros
Sequential Clock to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.8
2.6
3.9
8.1
ns
ns
ns
ns
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
6.9
0.0
6.9
0.0
8.4
8.4
17.5
ns
ns
3
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
Flip-Flop (Latch) Enable Setup
ns
Flip-Flop (Latch) Enable Hold
ns
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
Flip-Flop Clock Input Period
ns
ns
ns
fMAX
Flip-Flop (Latch) Clock Frequency (FO = 128)
55
MHz
Input Module Propagation Delays
tINYH
Pad to Y High
3.9
3.9
ns
ns
tINYL
Pad to Y Low
Input Module Predicted Routing Delays1, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.8
2.6
3.9
8.1
ns
ns
ns
ns
ns
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. Optimization techniques may further reduce delays by 0 to 4ns.
4. The hold time for the DFME1A macro may be greater than 0ns. Use the Designer software 3.0 (or later) Timer to check the hold
time for this macro.
v3.1
1-17
RadTolerant FPGAs
Table 1-11 • RT1020, A1020B Output Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
Std Speed
Parameter
Description
Min.
Max.
Units
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input Low to High
FO = 16
FO = 128
6.0
6.9
ns
ns
Input High to Low
FO = 16
FO = 128
7.9
8.7
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 16
FO = 128
8.0
8.4
ns
FO = 16
FO = 128
1.5
2.2
ns
FO = 16
FO = 128
1.5
2.3
ns
Minimum Period
FO = 16
FO = 128
16.3
17.5
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
60
50
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
8.3
9.3
ns
ns
tDHL
Data to Pad Low
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
8.1
ns
9.8
ns
12.3
11.1
0.07
0.10
ns
ns
ns/pF
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
9.8
7.9
ns
ns
tDHL
Data to Pad Low
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
7.4
ns
10.2
12.3
11.1
0.13
0.07
ns
ns
ns
ns/pF
ns/pF
dTHL
Notes:
1. Delays based on 35pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
1-18
v3.1
RadTolerant FPGAs
RT1280A, A1280A Timing Characteristics
Table 1-12 • RT1280A, A1280A Logic Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
5.2
5.2
5.2
5.2
6.1
6.1
6.1
6.1
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.4
3.4
4.2
5.1
9.2
2.8
4.0
ns
ns
ns
ns
ns
4.9
6.0
10.8
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
Flip-Flop Clock Input Period
0.5
0.0
1.3
0.0
7.4
7.4
16.4
2.5
3.5
0.0
0.5
0.5
0.0
1.3
0.0
8.6
8.6
22.1
2.5
3.5
0.0
0.5
ns
ns
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
ns
ns
ns
ns
ns
tINH
Input Buffer Latch Hold
ns
tINSU
Input Buffer Latch Setup
ns
tOUTH
tOUTSU
fMAX
Notes:
Output Buffer Latch Hold
ns
Output Buffer Latch Setup
ns
Flip-Flop (Latch) Clock Frequency
60
41
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
v3.1
1-19
RadTolerant FPGAs
Table 1-13 • RT1280A, A1280A Input Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G-to-Y HIGH
G-to-Y LOW
4.0
3.6
6.9
6.6
4.7
4.3
8.1
7.7
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
6.2
7.2
7.3
8.4
ns
ns
ns
ns
ns
7.7
9.1
8.9
10.5
15.2
12.9
Global Clock Network
tCKH Input LOW to HIGH
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
13.3
18.2
15.7
21.4
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Note:
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may
further reduce delays by 0 to 4ns.
1-20
v3.1
RadTolerant FPGAs
Table 1-14 • RT1280A, A1280A Output Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Min. Max.
Std Speed
Min. Max.
Parameter
TTL Output Module Timing1
Description
Units
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
dTLH
dTHL
Data-to-Pad HIGH
Data-to-Pad LOW
11.0
13.9
12.3
16.1
9.8
13.0
16.4
14.4
19.0
11.5
13.6
14.6
18.2
0.11
0.20
ns
ns
Enable-to-Pad Z to HIGH
Enable-to-Pad Z to LOW
Enable-to-Pad HIGH to Z
Enable-to-Pad LOW to Z
G-to-Pad HIGH
ns
ns
ns
11.5
12.4
15.5
0.09
0.17
ns
ns
G-to-Pad LOW
ns
Delta LOW to HIGH
ns/pF
ns/pF
Delta HIGH to LOW
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
14.0
11.7
12.3
16.1
9.8
16.5
13.7
14.4
19.0
11.5
13.6
14.6
18.2
0.20
0.15
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
tGLH
Enable-to-Pad Z to HIGH
Enable-to-Pad Z to LOW
Enable-to-Pad HIGH to Z
Enable-to-Pad LOW to Z
G-to-Pad HIGH
ns
ns
ns
11.5
12.4
15.5
0.17
0.12
ns
ns
tGHL
G-to-Pad LOW
ns
dTLH
dTHL
Notes:
Delta LOW to HIGH
Delta HIGH to LOW
ns/pF
ns/pF
1. Delays based on 50pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
v3.1
1-21
RadTolerant FPGAs
RT1425A, A1425A Timing Characteristics
Table 1-15 • RT1425A, A1425A Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
0.0
0.9
0.0
3.8
3.8
7.9
1.0
0.0
1.0
0.0
4.4
4.4
9.3
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
125
100
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
tOCKY
tICLRY
tOCLRY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
Input Asynchronous Clear to Y
Output Asynchronous Clear to Y
Input Module Predicted Routing Delays2, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4ns.
1-22
v3.1
RadTolerant FPGAs
Table 1-16 • RT1425A, A1425A Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold (w.r.t. IOCLK Pad)
Input F-F Data Setup (w.r.t. IOCLK Pad)
Input Data Enable Hold (w.r.t. IOCLK Pad)
Input Data Enable Setup (w.r.t. IOCLK Pad)
Output F-F Data Hold (w.r.t. IOCLK Pad)
Output F-F Data Setup (w.r.t. IOCLK Pad)
Output Data Enable Hold (w.r.t. IOCLK Pad)
Output Data Enable Setup (w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.1
1.1
0.5
2.0
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
11.9
6.0
8.9
ns
ns
tDLS
Data to Pad, Low Slew
14.0
7.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
9.9
12.8
11.6
11.6
11.6
17.4
0.04
0.08
0.06
0.08
ns
ns
9.9
ns
10.5
15.7
0.04
0.07
0.05
0.07
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
17.3
7.7
10.8
20.3
9.1
ns
ns
tDLS
Data to Pad, Low Slew
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
13.1
9.9
15.5
11.6
11.6
13.7
20.1
0.07
0.13
0.05
0.06
ns
ns
10.5
12.5
18.1
0.06
0.11
0.04
0.05
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35pF loading.
v3.1
1-23
RadTolerant FPGAs
Table 1-17 • RT1425A, A1425A Clock Networks
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Min. Max.
Std Speed
Parameter
Description
Min.
Max.
Units
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
3.0
3.5
ns
(Pad to I/O Module Input)
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
3.9
3.9
3.9
4.4
4.4
4.4
ns
ns
ns
0.5
0.5
ns
Minimum Period
7.9
9.3
ns
fIOMAX
Maximum Frequency
125
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
4.6
4.6
5.3
5.3
ns
ns
(Pad to S-Module Input)
tHCKL
Input High to Low
(Pad to S-Module Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.9
3.9
4.4
4.4
ns
ns
0.4
0.4
ns
Minimum Period
7.9
9.3
ns
fHMAX
Maximum Frequency
125
100
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=64)
5.5
6.0
6.4
7.0
ns
ns
Input High to Low (FO=64)
Minimum Pulse Width High (FO=64)
Minimum Pulse Width Low (FO=64)
Maximum Skew (FO=128)
4.9
4.9
5.7
5.7
ns
ns
1.1
1.2
85
ns
Minimum Period (FO=64)
10.1
11.6
ns
fRMAX
Maximum Frequency (FO=64)
100
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.0
3.0
0.0
0.0
3.0
3.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
Note: SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
1-24
v3.1
RadTolerant FPGAs
RT1460A, A1460A Timing Characteristics
Table 1-18 • RT1460A, A1460A Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
0.0
0.9
0.0
4.8
4.8
9.9
1.0
0.0
1.0
0.0
5.6
5.6
11.6
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
tOCKY
tICLRY
tOCLRY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
Input Asynchronous Clear to Y
Output Asynchronous Clear to Y
Predicted Input Routing Delays2, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4ns.
v3.1
1-25
RadTolerant FPGAs
Table 1-19 • RT1460A, A1460A I/O and Output Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold (w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.1
1.1
0.5
2.0
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input F-F Data Setup (w.r.t. IOCLK Pad)
Input Data Enable Hold (w.r.t. IOCLK Pad)
Input Data Enable Setup (w.r.t. IOCLK Pad)
Output F-F Data Hold (w.r.t. IOCLK Pad)
Output F-F Data Setup (w.r.t. IOCLK Pad)
Output Data Enable Hold (w.r.t. IOCLK Pad)
Output Data Enable Setup (w.r.t. IOCLK Pad)
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
8.9
ns
ns
tDLS
Data to Pad, Low Slew
11.9
6.0
14.0
7.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
11.5
10.9
11.6
17.8
0.04
0.07
0.05
0.07
12.8
13.5
12.8
13.4
19.8
0.04
0.08
0.06
0.08
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
20.3
9.1
ns
ns
tDLS
Data to Pad, Low Slew
17.3
7.7
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
13.1
10.9
10.9
14.1
20.2
0.06
0.11
0.04
0.05
15.5
12.8
12.8
16.0
22.4
0.07
0.13
0.05
0.06
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35pF loading.
1-26
v3.1
RadTolerant FPGAs
Table 1-20 • RT1460A, A1460A Clock Networks
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Min. Max.
Std Speed
Parameter
Description
Min.
Max.
Units
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Input Low to High (Pad to I/O Module Input)
3.5
4.1
ns
ns
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
4.8
4.8
3.9
5.7
5.7
4.4
ns
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
5.5
6.4
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
4.8
4.8
5.7
5.7
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fHMAX
Maximum Frequency
100
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=256)
9.0
9.0
10.5
10.5
ns
ns
Input High to Low (FO=256)
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
Maximum Skew (FO=128)
6.3
6.3
7.1
7.1
ns
ns
1.9
75
2.1
65
ns
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.0
5.0
0.0
0.0
3.0
5.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
Note: SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
v3.1
1-27
RadTolerant FPGAs
RT14100A, A14100A Timing Characteristics
Table 1-21 • RT14100A, A14100A Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock-to-Q
Asynchronous Clear-to-Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
1.0
0.6
1.0
0.6
4.8
4.8
9.9
1.0
0.6
1.0
0.6
5.6
5.6
11.6
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad-to-Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
tOCKY
tICLRY
tOCLRY
Input Reg IOCLK Pad-to-Y
Output Reg IOCLK Pad-to-Y
Input Asynchronous Clear-to-Y
Output Asynchronous Clear-to-Y
Input Module Predicted Routing Delays2, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4ns.
1-28
v3.1
RadTolerant FPGAs
Table 1-22 • RT14100A, A14100A I/O and Output Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input Flip-Flop Data Hold
0.0
2.1
0.0
8.7
1.2
1.2
0.6
2.4
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input Flip-Flop Data Setup
Input Data Enable Hold
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input Data Enable Setup
Output Flip-Flop Data Hold
Output Flip-Flop Data Setup
Output Data Enable Hold
Output Data Enable Setup
TTL Output Module Timing1
tDHS
Data-to-Pad, High Slew
7.5
8.9
ns
ns
tDLS
Data-to-Pad, Low Slew
11.9
6.0
14.0
7.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable-to-Pad, Z to H/L, High Slew
Enable-to-Pad, Z to H/L, Low Slew
Enable-to-Pad, H/L to Z, High Slew
Enable-to-Pad, H/L to Z, Low Slew
IOCLK Pad-to-Pad H/L, High Slew
IOCLK Pad-to-Pad H/L, Low Slew
Delta LOW to HIGH, High Slew
Delta LOW to HIGH, Low Slew
Delta HIGH to LOW, High Slew
Delta HIGH to LOW, Low Slew
ns
10.9
11.9
10.9
12.2
17.8
0.04
0.07
0.05
0.07
12.8
14.0
12.8
14.0
17.8
0.04
0.08
0.06
0.08
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
CMOS Output Module Timing1
tDHS
Data-to-Pad, High Slew
9.2
10.8
20.3
9.1
ns
ns
tDLS
Data-to-Pad, Low Slew
17.3
7.7
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable-to-Pad, Z to H/L, High Slew
Enable-to-Pad, Z to H/L, Low Slew
Enable-to-Pad, H/L to Z, High Slew
Enable-to-Pad, H/L to Z, Low Slew
IOCLK Pad-to-Pad H/L, High Slew
IOCLK Pad-to-Pad H/L, Low Slew
Delta LOW to HIGH, High Slew
Delta LOW to HIGH, Low Slew
Delta HIGH to LOW, High Slew
Delta HIGH to LOW, Low Slew
ns
13.1
11.6
10.9
14.4
20.2
0.06
0.11
0.04
0.05
15.5
14.0
12.8
16.0
22.4
0.07
0.13
0.05
0.06
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35 pF loading.
v3.1
1-29
RadTolerant FPGAs
Table 1-23 • RT14100A, A14100A Clock Networks
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input LOW to HIGH
(Pad to I/O Module Input)
3.5
4.1
ns
ns
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Minimum Asynchronous Pulse Width
Maximum Skew
4.8
4.8
3.9
5.7
5.7
4.4
ns
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to S-Module Input)
5.5
5.5
6.4
6.4
ns
tHCKL
Input HIGH to LOW
(Pad to S-Module Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
4.8
4.8
5.7
5.7
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fHMAX
Maximum Frequency
100
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input LOW to HIGH (FO=256)
9.0
9.0
10.5
10.5
ns
ns
Input HIGH to LOW (FO=256)
Min. Pulse Width HIGH (FO=256)
Min. Pulse Width LOW (FO=256)
Maximum Skew (FO=128)
6.3
6.3
7.1
7.1
ns
ns
1.9
75
2.1
65
ns
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.5
5.0
0.0
0.0
3.5
5.0
ns
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
Note: SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
1-30
v3.1
RadTolerant FPGAs
Pin Descriptions
CLK
Clock (Input)
IOPCL
Dedicated (Hard-Wired) I/O
Preset/Clear (Input)
RT1020 and A1020B only. TTL clock input for global clock
distribution networks. The clock input is buffered prior
to clocking the logic modules. This pin can also be used
as an I/O.
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL input for I/O preset or clear. This global
input is directly wired to the preset and clear inputs of all
I/O registers. This pin functions as an I/O when no I/O
preset or clear macros are used.
CLKA
Clock A (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the
pins function as I/Os. To provide debugging capability,
the MODE pin should be terminated to GND through a
10 kΩ resistor so that the MODE pin can be pulled HIGH
when required.
CLKB
Clock B (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
NC
No Connection
DCLK
Diagnostic Clock (Input)
This pin is not connected to circuitry within the device.
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-Wired) Array Clock
(Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for sequential modules. This
input is directly wired to each S-module, offering clock
speeds independent of the number of S-modules being
driven. This pin can also be used as an I/O.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
A pin to allow real-time diagnostic output of any signal
path within the device. The Probe B pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRB is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications.
In the RT1020, A1020B, RT1280, and A1280A devices,
unused I/O pins are automatically driven LOW. In the
RT1425, A1425A, RT1460, A1460A, RT14100, and
A14100A devices, unused I/O pins are automatically
tristated.
SDI
Serial Data Input (Input)
IOCLK
Dedicated (Hard-Wired) I/O Clock (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for I/O modules. This input is
directly wired to each I/O module, offering clock speeds
independent of the number of I/O modules being driven.
This pin can also be used as an I/O.
V
5.0 V Supply Voltage
CC
HIGH supply voltage.
v3.1
1-31
RadTolerant FPGAs
Package Pin Assignments
84-Pin CQFP
Pin #1
Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
84-Pin
CQFP
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Figure 2-1 • 84-Pin CQFP (Top View)
v3.1
2-1
RadTolerant FPGAs
84-Pin CQFP
A1020B
84-Pin CQFP
84-Pin CQFP
Pin
RT1020
Pin
A1020B
RT1020
Pin
A1020B
RT1020
Number
Function
NC
I/O
Function
Number
Function
Function
Number
Function
Function
1
NC
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
3
I/O
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
7
GND
GND
I/O
GND
GND
I/O
I/O
I/O
8
I/O
I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
VCC
VCC
I/O
GND
GND
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
I/O
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCC
VCC
I/O
MODE
VCC
VCC
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDI, I/O
SDI, Input
I/O
I/O
DCLK, I/O DCLK, Input
I/O
I/O
PRA, I/O
PRB, I/O
I/O
PRA, I/O
PRB, I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
2-2
v3.1
RadTolerant FPGAs
132-Pin CQFP
132131130129128127126125124
107106105104103102101100
Pin #1
Index
1
2
3
4
5
6
7
8
99
98
97
96
95
94
93
92
132-Pin
CQFP
25
75
74
73
72
71
70
69
68
67
26
27
28
29
30
31
32
33
34 35 36 37 38 39 40 41 42
59 60 61 62 63 64 65 66
Figure 2-2 • 132-Pin CQFP (Top View)
v3.1
2-3
RadTolerant FPGAs
132-Pin CQFP
A1425A
132-Pin CQFP
132-Pin CQFP
Pin
Number
RT1425A
Function
Pin
Number
A1425A
Function
RT1425A
Function
Pin
Number
A1425A
Function
RT1425A
Function
Function
1
NC
NC
GND
SDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
I/O
GND
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
I/O
I/O
I/O
I/O
2
GND
SDI, I/O
I/O
3
I/O
I/O
I/O
I/O
4
I/O
I/O
GND
VCC
I/O
GND
VCC
I/O
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
GND
VCC
I/O
GND
VCC
I/O
I/O
I/O
8
I/O
I/O
VCC
I/O
VCC
I/O
9
MODE
GND
VCC
I/O
MODE
GND
VCC
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK, I/O
I/O
HCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
VCC
GND
I/O
VCC
GND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
GND
VCC
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOCLK, I/O
NC
IOCLK, I/O
NC
I/O
I/O
IOPCL, I/O
GND
NC
IOPCL, I/O
GND
NC
I/O
I/O
NC
NC
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-4
v3.1
RadTolerant FPGAs
132-Pin CQFP
Pin
Number
A1425A
Function
RT1425A
Function
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
GND
VCC
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
NC
DCLK, I/O
NC
v3.1
2-5
RadTolerant FPGAs
172-Pin CQFP
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1
Index
1
2
3
4
5
6
7
8
129
128
127
126
125
124
123
122
172-Pin
CQFP
35
36
37
38
39
40
41
42
43
95
94
93
92
91
90
89
88
87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
Figure 2-3 • 172-Pin CQFP (Top View)
2-6
v3.1
RadTolerant FPGAs
172-Pin CQFP
172-Pin CQFP
172-Pin CQFP
Pin
Number
A1280A
Function
RT1280A
Function
Pin
Number
A1280A
Function
RT1280A
Function
Pin
Number
A1280A
Function
RT1280A
Function
1
MODE
I/O
MODE
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
2
3
I/O
I/O
4
I/O
I/O
5
I/O
I/O
6
I/O
I/O
7
GND
I/O
GND
I/O
8
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
VCC
I/O
GND
VCC
VCC
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
v3.1
2-7
RadTolerant FPGAs
172-Pin CQFP
A1280A
172-Pin CQFP
Pin
Number
RT1280A
Function
Pin
Number
A1280A
Function
RT1280A
Function
Function
GND
VCC
GND
VCC
VCC
I/O
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
GND
VCC
GND
VCC
VCC
I/O
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
PRA, I/O
I/O
PRA, I/O
I/O
I/O
I/O
CLKA, I/O
VCC
GND
I/O
CLKA, I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-8
v3.1
RadTolerant FPGAs
196-Pin CQFP
196 195 194 193 192 191 190 189 188
155 154 153 152 151 150 149 148
Pin #1
Index
1
2
3
4
5
6
7
8
147
146
145
144
143
142
141
140
196-Pin
CQFP
41
42
43
44
45
46
47
48
49
107
106
105
104
103
102
101
100
99
50 51 52 53 54 55 56 57 58
91 92 93 94 95 96 97 98
Figure 2-4 • 196-Pin CQFP (Top View)
v3.1
2-9
RadTolerant FPGAs
196-Pin CQFP
A1460A
Function
GND
SDI, I/O
I/O
196-Pin CQFP
196-Pin CQFP
Pin
Number
RT1460A
Function
Pin
Number
A1460A
Function
RT1460A
Function
Pin
Number
A1460A
Function
RT1460A
Function
1
GND
SDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
GND
VCC
VCC
I/O
I/O
GND
VCC
VCC
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
I/O
I/O
I/O
I/O
2
3
I/O
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
HCLK, I/O
I/O
HCLK, I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCC
GND
I/O
MODE
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
GND
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
IOPCL, I/O
GND
I/O
IOPCL, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-10
v3.1
RadTolerant FPGAs
196-Pin CQFP
196-Pin CQFP
196-Pin CQFP
Pin
Number
A1460A
Function
RT1460A
Function
Pin
Number
A1460A
Function
RT1460A
Function
Pin
Number
A1460A
Function
RT1460A
Function
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
I/O
I/O
I/O
I/O
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
I/O
I/O
I/O
I/O
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
GND
I/O
VCC
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOCLK, I/O
GND
I/O
IOCLK, I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
DCLK, I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
GND
VCC
VCC
GND
GND
VCC
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
v3.1
2-11
RadTolerant FPGAs
256-Pin CQFP
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
Figure 2-5 • 256-Pin CQFP (Top View)
2-12
v3.1
RadTolerant FPGAs
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
Pin
Number
A14100A
Function
RT14100A
Function
Pin
Number
A14100A
Function
RT14100A
Function
Pin
Number
A14100A
Function
RT14100A
Function
1
GND
SDI, I/O
I/O
GND
SDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
I/O
I/O
I/O
I/O
2
3
I/O
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
MODE
I/O
MODE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCC
GND
VCC
I/O
PRB, I/O
GND
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK, I/O
I/O
HCLK, I/O
I/O
I/O
I/O
VCC
GND
VCC
GND
I/O
VCC
GND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v3.1
2-13
RadTolerant FPGAs
256-Pin CQFP
A14100A
256-Pin CQFP
256-Pin CQFP
Pin
Number
RT14100A
Function
Pin
Number
A14100A
Function
RT14100A
Function
Pin
Number
A14100A
Function
RT14100A
Function
Function
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
I/O
I/O
I/O
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
VCC
I/O
VCC
I/O
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOCLK, I/O
GND
I/O
IOCLK, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
VCC
I/O
GND
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOPCL, I/O
GND
I/O
IOPCL, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
2-14
v3.1
RadTolerant FPGAs
256-Pin CQFP
256-Pin CQFP
Pin
Number
A14100A
Function
RT14100A
Function
Pin
Number
A14100A
Function
RT14100A
Function
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
I/O
I/O
I/O
I/O
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
CLKB, I/O
VCC
GND
VCC
GND
PRA, I/O
I/O
CLKA, I/O
CLKB, I/O
VCC
GND
VCC
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
DCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v3.1
2-15
RadTolerant FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v3.1)
Page
The following pins changed in the "84-Pin CQFP" table:
v3.0
2-2
•
•
Pin 61 change to SDI, Input for the RT1020 device.
Pin 62 change to DCLK, Input for the RT1020 device.
The following pins changed in the "256-Pin CQFP" table:
2-14
•
•
Pin 124 change to I/O for the A14100A and RT14100A devices.
Pin 127 changed to IOPCL for the A14100A and RT14100A devices.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Export Administration Regulations (EAR) or International Traffic in
Arms Regulations (ITAR)
The product described in this datasheet could be subject to either the Export Administration Regulations (EAR) or in
some cases the International Traffic in Arms Regulations (ITAR). They could require an approved export license prior to
export from the United States. An export includes release of product or disclosure of technology to a foreign national
inside or outside the United States.
v3.1
3-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
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Actel Japan
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Phone +852.227.35712
Fax +852.227.35999
5172139-4/10.04
相关型号:
RT14100A-STDCQG256B
Field Programmable Gate Array, 1377 CLBs, 30000 Gates, 85MHz, CMOS, CQFP256, CERAMIC, QFP-256
ACTEL
RT14100A-STDCQG256B
Field Programmable Gate Array, 1377 CLBs, 30000 Gates, 85MHz, CMOS, CQFP256, CERAMIC, QFP-256
MICROSEMI
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