SG1842L/DESC-TR [MICROSEMI]
Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, CQCC20;
| 型号： | SG1842L/DESC-TR |
| 厂家： | 
Microsemi |
| 描述： | Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, CQCC20 |
| 文件： | 总24页 (文件大小：716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SG1842/SG1843
Current Mode PWM Controller
Features
Description
.
.
.
.
.
.
.
Optimized For Off-Line Control
The SG1842/43 family of control IC's provides all the
necessary features to implement off-line fixed
frequency, current-mode switching power supplies
with a minimum number of external components.
Low Start-Up Current (<1mA)
Automatic Feed Forward Compensation
Trimmed Oscillator Discharge Current
Pulse-By-Pulse Current Limiting
Current-mode architecture demonstrates improved
line regulation, improved load regulation, pulse-by-
pulse current limiting and inherent protection of the
power supply output switch. The bandgap reference
is trimmed to ±1% over temperature.
Enhanced Load Response Characteristics
Under-Voltage Lockout with 6V Hysteresis (SG1842
only)
.
.
.
.
.
Double-Pulse Suppression
Oscillator discharge current is trimmed to less than
±10%. The SG1842/43 has under-voltage lockout,
current limiting circuitry and start-up current of less
than 1mA. The totem-pole output is optimized to drive
the gate of a power MOSFET. The output is low in
the off state to provide direct interface to an
N-channel device. The SG1842/43 is specified for
operation over the full military ambient temperature
range of -55°C to 125°C. The SG2842/43 is specified
for the industrial range of -25°C to 85°C, and the
SG3842/43 is designed for the commercial range of
0°C to 70°C.
High-Current Totem-Pole Output (1A Peak)
Internally Trimmed Bandgap Reference
500kHz Operation
Undervoltage Lockout
SG1842 - 16 volts
SG1843 - 8.4 volts
.
Low Shoot-Through Current <75mA Over
Temperature
Application
.
.
Available To MIL-STD – 883, ¶ 1.2.1
Available to DSCC
- Standard Microcircuit Drawing (SMD)
Product Highlight
RST
IST
AC
INPUT
Vcc
SG3842/43
Figure 1 · Product Highlight
October 2014 Rev. 1.7
www.microsemi.com
1
© 2014 Microsemi Corporation
Current Mode PWM Controller
Connection Diagrams and Ordering Information
Ambient
Temperature
Type
Packaging
Type
Package
Part Number
Connection Diagram
VREF
COM
VFB
SG3842M
SG3843M
SG2842M
VCC
0°C to 70°C
OUTPUT
GND
ISENSE
RT/CT
8-PIN PLASTIC
DUAL INLINE
PACKAGE
M
Plastic DIP
M PACKAGE
(Top View)
-25°C to 85°C
M Package: RoHS / Pb-free 100% Matte Tin Lead Finish
SG2843M
SG3842Y
SG3843Y
SG2842Y
SG2843Y
0°C to 70°C
VREF
COM
VFB
-25°C to 85°C
VCC
OUTPUT
GND
ISENSE
RT/CT
8-PIN
SG1842Y
SG1843Y
-55°C to
125°C
CERAMIC
DUAL INLINE
PACKAGE
Y
CERDIP
Y PACKAGE
(Top View)
SG1842Y-883B
SG1843Y-883B
MIL-STD/883
DESC
PbSn Tin Lead Finish
SG1842Y-DESC
SG1843Y-DESC
COM
VREF
SG3842DM
SG3843DM
SG2842DM
SG2843DM
VFB
ISENSE
RT/CT
0°C to 70°C
VCC
8-PIN SMALL
OUTLINE
INTEGRATED
CIRCUIT
OUTPUT
GND
DM
SOIC
DM PACKAGE
(Top View)
-25°C to 85°C
RoHS / Pb-free 100% Matte Tin Lead Finish
VREF
N.C.
COM
N.C.
SG3842D
SG3843D
SG2842D
0°C to 70°C
VCC
VC
VFB
14-PIN SMALL
OUTLINE
INTEGRATED
CIRCUIT
N.C.
ISENSE
N.C.
OUTPUT
GND
D
SOIC
PWR GND
RT/CT
-25°C to 85°C
0°C to 70°C
D PACKAGE
(Top View)
SG2843D
SG3842N
SG3843N
SG2842N
RoHS / Pb-free 100% Matte Tin Lead Finish
COM
N.C.
VREF
N.C.
VCC
VC
VFB
N.C.
14-PIN DUAL
INLINE
PLASTIC
PACKAGE
OUTPUT
GND
PLASTIC
DIP
ISENSE
N.C.
N
POWER GND
RT/CT
-25°C to 85°C
N PACKAGE
(Top View)
SG2843N
N Package: RoHS / Pb-free 100% Matte Tin Lead Finish
2
Connection Diagrams and Ordering Information (continued)
Connection Diagrams and Ordering Information (continued)
Ambient
Temperature
Type
Packaging
Type
Package
Part Number
Connection Diagram
SG1842J
SG1843J
COM
-55°C to
125°C
VREF
N.C.
N.C.
VCC
VC
VFB
N.C.
14-PIN
CERAMIC
DUAL INLINE
PACKAGE
SG1842J-883B
ISENSE
N.C.
OUTPUT
GND
MIL-STD/883
DESC
J
CERDIP
SG1843J-883B
SG1842J-DESC
SG1843J-DESC
RT/CT
PWR GND
J PACKAGE
(Top View)
PbSn Lead Finish
SG1842F
SG1843F
-55°C to
125°C
COM
VFB
ISENSE
VREF
VCC
VC
OUTPUT
GND
10-PIN
RT/CT
SG1842F-883B
CERAMIC
FLAT PACK
PACKAGE
FLAT
PACK
MIL-STD/883
DESC
PWR
GND
F
SG1843F-883B
SG1842F-DESC
F PACKAGE
(Top View)
PbSn Lead Finish
SG1843F-DESC
3
19
1 20
2
1. N.C.
11. N.C.
SG1842L
SG1843L
-55°C to
125°C
2. COMP 12.
.
13. N.C.
GROUND
18
17
16
15
14
3. N.C.
4. N.C.
4
5
6
7
8
14. N.C.
15. OUTPUT
16.
VFB
5.
6. N.C.
7. ISENSE 17. Vcc
Ceramic
Leadless
Chip
Carrier
(LCC)
N.C.
SG1842L-883B
8.
N.C.
9. N.C.
18. N.C.
MIL-STD/883
19.
N.C.
20-PIN
CERAMIC
L
20.
VREF
R /C
T
10.
T
SG1843L-883B
SG1842L-DESC
SG1843L-DESC
9
13
10 11 12
L PACKAGE
(Top View)
DESC
PbSn Lead Finish
Notes:
1. Contact factory for JAN and DESC part availability.
2. All parts are viewed from the top.
3. Available in Tape & Reel. Append the letters “TR” to the part number (SG3842N-TR).
3
Current Mode PWM Controller
Absolute Maximum Ratings1 - 2
Parameter
Value
Units
V
Supply Voltage (ICC < 30mA)
Self-limiting
Supply Voltage (Low Impedance Source)
Output Current (Peak)
30
V
±1
A
350
mA
µJ
V
Output Current (Continuous)
Output Energy (Capacitive Load)
5
Analog Inputs (VFB, ISENSE
)
-0.3 to +6.3
10
1
mA
W
Error Amplifier Output Sink Current
Power Dissipation at TA = 25°C (DIL-8)
Operating Junction Temperature
Hermetic (J, Y, F, L Packages)
150
150
°C
°C
°C
°C
Plastic (N, M, D, DM Packages)
Storage Temperature Range
-65 to +150
300
Lead Temperature (Soldering, 10 Seconds)
RoHS / Pb-free Peak Package Solder Reflow Temp. (40 second
max. exposure)
260 (+0, -5)
°C
Notes:
1. Exceeding these ratings could cause damage to the device.
2. All voltages are with respect to Pin 5. All currents are positive into the specified terminal.
Thermal Data
Parameter
Value
Units
M Package:
Thermal Resistance-Junction to Ambient, θJA
N Package:
95
°C/W
°C/W
°C/W
65
Thermal Resistance-Junction to Ambient, θJA
DM Package:
165
120
130
80
Thermal Resistance-Junction to Ambient, θJA
D Package:
°C/W
°C/W
°C/W
Thermal Resistance-Junction to Ambient, θJA
Y Package:
Thermal Resistance-Junction to Ambient, θJA
J Package
Thermal Resistance-Junction to Ambient, θJA
F Package
°C/W
°C/W
80
Thermal Resistance-Junction to Case, θJC
Thermal Resistance-Junction to Ambient, θJA
L Package
145
°C/W
°C/W
Thermal Resistance-Junction to Case, θJC
35
120
Thermal Resistance-Junction to Ambient, θJA
Notes:
1. Junction Temperature Calculation: TJ = TA + (PD × θJA).
2. The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no
ambient airflow.
4
Recommended Operating Conditions
Recommended Operating Conditions
Recommended Operating Conditions
Symbol
Parameter
Units
Min
Typ
30
Max
VS
Supply Voltage Range
V
A
IPK
Output Current (Peak)
±1
IOUT
Output Current (Continuous)
200
mA
V
Analog Inputs (VFB, ISENSE
)
0
2.6
EASINK
OSCFR
RT
Error Amp Output Sink Current
Oscillator Frequency Range
Oscillator Timing Resistor
Oscillator Timing Capacitor
5
mA
kHz
kΩ
µF
0.1
0.52
0.001
500
150
1.0
CT
Operating Ambient Temperature Range
SG1842/43
SG2842/43
-55
-25
0
125
85
°C
°C
°C
SG3842/43
70
Note: Range over which the device is functional.
5
Current Mode PWM Controller
Electrical Characteristics
Unless otherwise specified, these specifications apply over the operating ambient temperatures for
SG1842/SG1843 with -55°C ≤ TA ≤ 125°C, SG2842/SG2843 with -25°C ≤ TA ≤ 85°C, SG3842/SG3843 with
0°C ≤ TA ≤ 70°C, VCC = 15V, RT = 10kΩ, and CT = 3.3nF. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.
SG1842/43
SG2842/43
SG3842/43
Symbol
Parameter
Test Conditions
Units
Min Typ Max Min Typ Max Min Typ Max
Reference Section
VREF
VREG
IREG
Output Voltage
TJ = 25°C, IO = 1mA
12V ≤ VIN ≤ 25V
1 ≤ IO ≤ 20mA
4.95 5.00 5.05 4.95 5.00 5.05 4.90 5.00 5.10
V
Line Regulation
6
6
20
6
6
20
6
6
20
25
mV
mV
Load Regulation
Temperature Stability1
Total Output Variation1 Line, Load, Temperature 4.90
25
25
0.2
0.4
0.2
0.4
0.2
0.4 mV/°C
5.10 4.90
5.10 4.82
5.18
V
10Hz ≤ f ≤ 10kHz, TJ
25°C
=
VN
Output Noise Voltage1
50
5
50
5
50
5
µV
mV
Long Term Stability1
TA = 125°C, 1000hrs
25
25
25
VREFOSC
Output Short Circuit
-30
47
-100 -180 -30 -100 -180 -30 -100 -180 mA
Oscillator Section3
f
Initial Accuracy5
TJ = 25°C
52
0.2
5
57
1
47
52
0.2
5
57
1
47
52
0.2
5
57
1
kHz
%
fREG
Voltage Stability
12V ≤ VCC ≤ 25V
Temperature Stability1 TMIN ≤ TA ≤ TMAX
OSCPP Amplitude VRT/CT (Peak to Peak)
%
1.7
8.3
1.7
8.4
1.7
8.4
V
TJ = 25°C
7.8
7.0
8.8
9.0
7.5
7.2
9.3
9.5
7.5
7.2
9.3
9.5
mA
mA
IDSG
Discharge Current
TMIN ≤ T A ≤ TMAX
Error Amp Section
EAIN
EAIB
AVOL
EABW
Input Voltage
VCOMP = 2.5V
2.45 2.50 2.55 2.45 2.50 2.55 2.42 2.50 2.58
V
µA
Input Bias Current
-0.3
90
1
-1
-0.3
90
1
1
-0.3
90
1
-2
Open Loop Gain
Unity Gain Bandwidth1 TJ = 25°C
2V ≤ VO ≤ 4V
65
65
65
dB
0.7
0.7
0.7
MHz
Power Supply Rejection
Ratio
PSRR
12V ≤ VCC ≤ 25V
60
70
60
2
70
6
60
2
70
6
dB
VVFB = 2.7V,
VCOMP = 1.1V
EASINK Output Sink Current
2
-0.5
5
6
-0.8
6
mA
mA
V
EASRC Output Source Current VVFB = 2.3V, VCOMP = 5V
-0.5 -0.8
-0.5 -0.8
VVFB = 2.3V,
EAVOH VOUT High
5
6
5
6
RL = 15k to GND
VVFB = 2.7V,
EAVOL VOUT Low
0.7
1.1
0.7
1.1
0.7
1.1
V
RL = 15k to VREF
6
Electrical Characteristics (continued)
Electrical Characteristics (continued)
SG1842/43
SG2842/43
SG3842/43
Typ Max
Symbol
Parameter
Test Conditions
Units
Min
Typ Max Min Typ Max Min
Current Sense Section
CSAVOL Gain 2, 3
2.85
0.9
3
1
3.15 2.85
3
1
3.15 2.85
3
1
3.15 V/V
Maximum Input Signal2 VCOMP = 5V
1.1
0.9
1.1
0.9
1.1
V
Power Supply Rejection
Ratio2
PSRR
CSIB
12V ≤ VCC ≤ 25V
70
70
-2
70
-2
dB
Input Bias Current
-2
-10
-10
-10
µA
ns
CSDELAY Delay to Output1
150
300
150 300
150 300
Output Section
VOL
Output Low Level
ISINK = 20mA
0.1
1.5
0.4
2.2
0.1
1.5
0.4
2.2
0.1
1.5
0.4
2.2
V
V
ISINK = 200mA
VOH
Output High Level
ISOURCE = 20mA
ISOURCE = 200mA
TJ = 25°C, CL = 1nF
TJ = 25°C, CL = 1nF
13
12
13.5
13.5
50
13 13.5
12 13.5
50
13
12
13.5
13.5
50
V
V
RS
FT
Rise Time
Fall Time
150
150
150
150
150
150
ns
ns
50
50
50
Under-Voltage Lockout Section
1842/2842/3842
1843/2843/3843
1842/2842/3842
1843/2843/3843
15
7.8
9
16
8.4
10
17
9.0
11
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
16 17.5
8.4 9.0
10 11.5
V
V
V
V
UVLO Start Threshold
8.5
Min. Operation Voltage
VSMIN
After Turn-On
7.0
7.6
8.3
7.0
7.6
8.2
7.0
7.6
8.2
PWM Section
DCMAX Maximum Duty Cycle
DCMIN Minimum Duty Cycle
Power Consumption Section
93
95
100
0
90
95
100
0
90
95
100
0
%
%
IS
Start-Up Current
0.5
11
34
1
0.5
11
34
1
0.5
11
34
1
mA
mA
V
Operating Supply
Current
I
VFB = VISENSE = 0V
ICC = 25mA
17
17
17
Z
VCC Zener Voltage
Notes:
1. These parameters, although guaranteed, are not 100% tested in production.
2. Parameter measured at trip point of latch with VVFB = 0.
3. Gain defined as: A = ∆VCOMP / ∆VISENSE ; 0 ≤ VISENSE ≤ 0.8V
4. Adjust VCC above the start threshold before setting at 15V.
7
Current Mode PWM Controller
Block Diagram
VCC
*
34V
VREF
5.0V
50mA
5V
REF
S/R
GROUND**
6V (1842)
0.8V (1843)
16V (1842)
8.4V (1843)
INTERNAL BIAS
VREF
GOOD LOGIC
VC*
RT/CT
OSCILLATOR
ERROR AMP
OUTPUT
S
R
2R
R
+
POWER
GROUND**
PWM
LATCH
_
VFB
COMP
1V
CURRENT SENSE
COMPARATOR
CURRENT SENSE
* - VCC and VC are internally connected for 8-pin packages.
** - POWER GROUND and GROUND are internally connected for 8-pin packages.
Figure 2 · Block Diagram
8
Characteristic Curves
Characteristic Curves
2
0
VIN = 15V
Duty Cycle = 50%
10.0
SG1842
-2
-4
-6
9.6
9.2
8.8
8.4
-8
8.0
SG1843
0
-10
-75 -50 -25
25
50
75
100 125
-75
-50
-25
0
25
50
75
100
125
Junction Temperature - (°C)
Junction Temperature - (°C)
Figure 3 · Dropout Voltage vs. Temperature
Figure 4 · Oscillator Temperature Stability
200kHz
50
220
49
200
180
100kHz
50kHz
50kHz
48
VPIN3
=
1.1V
160
100kHz
200kHz
46
45
44
140
120
-75
-50 -25
0
25
50
75
100 125
-75
-50
-25
0
25
50
75
100
125
Junction Temperature - (°C)
Junction Temperature - (°C)
Figure 5 · Current Sense to Output Delay vs.
Temperature
Figure 6 · Output Duty Cycle vs. Temperature
5.02
0.7
5.01
SG1842
V
CC = 15V
0.6
0.5
0.4
5.00
4.99
4.98
0.3
SG1843
0.2
75
Junction Temperature - (°C)
100
125
-75
-25
0
25
50
-50
125
-25
0
25
50
75
100
-50
-75
Junction Temperature - (°C)
Figure 7 · Start-Up Current vs. Temperature
Figure 8 · Reference Voltage vs. Temperature
9
Current Mode PWM Controller
16.08
16.06
16.04
16.02
8.32
SG1843
8.30
SG1842
8.28
8.26
8.24
8.22
8.20
8.18
16.00
15.98
-75 -50 -25
0
25
50
75 100 125
-75 -50 -25
0
25
50
75 100 125
Junction Temperature - (°C)
Junction Temperature - (°C)
Figure 9 · Start-Up Voltage Threshold vs. Temperature
Figure 10 · Start-Up Voltage Threshold vs. Temperature
8.2
2.5
8.0
7.8
7.6
2.0
-55°C
+25°C
1.5
+125°C
1.0
VIN = 15 V
Duty Cycle < 5%
7.4
7.2
0.5
0
-75
25
50
75
100
0
125
-50
-25
100
200
300
400
500
Junction Temperature - (°C)
Output Current - (mA)
Figure 12 · Output Saturation Voltage vs. Output Current
Figure 11 · Oscillator Discharge Current vs.
and Temperature (Sink Transistor)
Temperature
1.0
0.9
0.8
0.7
VIN = 15 V
UTY YCLE < 5%
4.0
D
C
125°C
25°C
+125°C
3.0
2.0
-55°C
0.6
-55°C
0.5
0.4
0.3
0.2
+125°C
1.0
0
0.1
0
100
200
300
400
500
1.0
2.0
3.0
4.0
5.0
Error Amp Output Voltage - (V)
Output Current - (mA)
Figure 14 · Output Saturation Voltage vs. Output Current
Figure 13 · Current Sense Threshold vs. Error Amplifier
and Temperature
Output
10
Application Information
Application Information
The oscillator of the 1842/43 family of PWM's is designed such that many values of RT and CT will give the
same oscillator frequency, but only one combination will yield a specific duty cycle at a given frequency.
Given:
Frequency ≡ f
Maximum Duty Cycle ≡ Dm
ꢀ/D
m
(1.76)
−1
Calculate: RT = 267 �(1.76)
−1ꢂ (Ω)
m
( ꢀꢁD )/D
m
where 0.3 < Dm < 0.95
1.86 ∗ Dꢃ
(µF)
CT =
f ∗ RT
For Duty-Cycles above 95% use:
VREF
RT
CT
/CT
RT
GND
1.86
F
Where RT ≥ 5kΩ
≈
RTCT
Figure 15 · Oscillator Timing Circuit
11
Current Mode PWM Controller
A set of formulas are given to determine the values of RT and CT for a given frequency and maximum duty
cycle. (Note: These formulas are less accurate for smaller duty cycles or higher frequencies. This will require
trimming of RT or CT to correct for this error.)
Example:
A Flyback power supply requires a maximum of 45% duty cycle at a switching frequency of 50 kHz. What
are the values of RT and CT?
Given:
f = 50kHz
Dm = 0.45
ꢀ
.45
Calculate: RT = 267 �(1.76 − 1ꢁ = 674 Ω
)
.55
.45
(
)
1.76
− 1
1.86 ∗ 0.45
CT =
= .025 (µF)
50000 ∗ 674
1000
100
10
1
.001
.01
.05
0.1
.002
.005
CT Value - (µF)
Figure 16 · Oscillator Frequency Vs. RT For Various CT
12
Typical Application Circuits
Typical Application Circuits
Pin numbers referenced are for 8-pin package and pin numbers in parenthesis are for 14-pin package.
VCC VIN
7 (12)
7 (11)
Q1
6 (10)
SG1842/43
IPK
5 (8)
R
1.0V
RS
3 (5)
=
IPK(MAX)
RS
C
Figure 17 · Current Sense Spike Suppression
The RC low-pass filter eliminates the leading edge current spike caused by parasitic of Power MOSFET.
VCC
VIN
7 (12)
7 (11)
6 (10)
Q1
R1
SG1842/43
5 (8)
RS
3 (5)
Figure 18 · MOSFET Parasitic Oscillations
A resistor (R1) in series with the MOSFET gate reduce overshoot and ringing caused by the MOSFET input
capacitance and any inductance in series with the gate drive. (Note: It is very important to have a low
inductance ground path to insure correct operation of the I.C. This can be done by making the ground paths
as short and as wide as possible.)
13
Current Mode PWM Controller
IB
VC
R2
+
VIN
VC1
R1 II R2
_
VC1
C1
VC
7 (11)
6 (10)
R2
Q1
SG1842/43
R1
5 (8)
3 (5)
RS
Figure 19 · Bipolar Transistor Drive
The 1842/43 output stage can provide negative base current to remove base charge of power transistor (Q1)
for faster turn off. This is accomplished by adding a capacitor (C1) in parallel with a resistor (R1). The resistor
(R1) is to limit the base current during turn on.
VCC
VIN
Isolation
Boundary
7 (12)
7 (11)
6 (10)
Q1
VGS Waveforms
50% DC
+
0
SG1842/43
_
5 (8)
3 (5)
+
R
0
_
25% DC
RS
NS
NP
C
V (PIN 1) – 1.4
3RS
NP
NS
IPK
=
( )
Figure 20 · Isolated MOSFET Drive
Current transformers can be used where isolation is required between PWM and Primary ground. A drive
transformer is then necessary to interface the PWM output with the MOSFET.
14
Typical Application Circuits
VIN
VCC
7 (12)
8 (14)
4 (7)
2 (3)
7 (11)
6 (10)
Q1
I
SG1842/43
5 (8)
3 (5)
R2
R1
1 (1)
2N2907
5 (9)
C
RS
Figure 21 · Adjustable Buffered Reduction of Clamp Level with Softstart
VCS
=
IPK
RS
R
1
Where, VCS=1.67 ꢄ
ꢅ and VC.S.MAX = 1V (Typ.)
R +R
1
2
VEAO ꢇ 1.3
R1R2
tSOꢆTSTART = ꢇln ꢈ1 ꢇ
ꢋ ꢄ
ꢅ C
R1
R1 + R2
5 ꢉ
ꢊ
R1 + R2
Where, VEAO ≡ voltage at the Error Amp Output under minimum line and maximum load conditions
Softstart and adjustable peak current can be done with the external circuitry shown above.
8 (14)
RA
8
4
6
2
SG1842/43
4 (7)
3
555
TIMER
RB
C
1
5 (9)
To other
SG1842/43
1.44
(RA + 2RB) C
f =
RB
RA + 2RB
f =
Figure 22 · External Duty Cycle Clamp and Multi-Unit Synchronization
Precision duty cycle limiting as well as synchronizing several 1842/1843's is possible with the above
circuitry.
15
Current Mode PWM Controller
5V
8 (14)
2.8V
1.1V
RT
_
+
4 (7)
CT
SG1842/43
Discharge
Current
Id = 8.2 mA
Figure 23 · Oscillator Connection
The oscillator is programmed by the values selected for the timing components RT and CT. Refer to
application information for calculation of the component values.
2.5V
SG1842/43
0.5 mA
2 (3)
R1
1 (1)
RF
RF 10k
Figure 24 · Error Amplifier Connection
Error amplifier is capable of sourcing and sinking current up to 0.5mA.
16
Typical Application Circuits
VCC
VIN
SG1842/43
7 (12)
VO
5V
8 (14)
+
5V
UVLO
5V
REF
S
R
+
RT
INTERNAL
BIAS
2.5V
2N222A
VREF
GOOD LOGIC
7 (11)
6 (10)
R
SLOPE
4 (7)
OSCILLATOR
Q1
From VO
CT
CS
COMP
2 R
+
Ri
2 (3)
ERROR
AMP
5 (8)
3 (5)
R
1V
PWM
LATCH
Rd
CF
RF
R
1 (1)
C
RS
5(9)
Figure 25 · Slope Compensation
Due to inherent instability of current mode converters running above 50% duty cycle, slope
compensation should be added to either current sense pin or the error amplifier. Figure 25 shows a
typical slope compensation technique.
17
Current Mode PWM Controller
VREF
RT
A
VCC
SG1842/43
2N 2222
4.7k
1k
8
7
6
1
2
3
4
COMP
VREF
100k
VFB
VCC
0.1µF
0.1µF
1k
ERROR AMP
ADJUST
4.7k
5k
OUTPUT
OUTPUT
GROUND
ISENSE
ISENSE
ADJUST
GROUND
RTCT
5
CT
Figure 26 · Open Loop Laboratory Fixture
High-peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected to pin 5 in a single point ground.
The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable
ramp to pin 3.
18
Typical Application Circuits
USD735
T1
4.7Ω 1W
+
+
220µF
250V
0.01pF
400V
+
4700µF
5V
673-3
56kΩ
1 W
10V
2 – 5A
AC
1N3613
INPUT
-
1N3613
16V
SG1842
20kΩ
+
10µF
20V
0.01 µF
820pF
T1: Coilcraft E - 4140 – b
Primary - 97 turns
single AWG 24
V
CC
VFB
27Ω
Secondary - 4 turns
4 parallel AWG 22
Control - 9 turns
150kΩ
COMP
2.5kΩ
OUT
3.6kΩ
100 pF
20kΩ
3 parallel AWG 28
VREF
1kΩ
CUR
SEN
10kΩ
470 pF
RT /CT
0.85Ω
GND
0.01 µF
0.0047µF
ISOLATION
BOUNDARY
Figure 27 · Off-line Flyback Regulator
SPECIFICATIONS
Input line voltage:
Input frequency:
90VAC to 130VAC
50 or 60Hz
40kHz ±10%
25W maximum
5V +5%
Switching frequency:
Output power:
Output voltage:
Output current:
2 to 5A
Line regulation:
0.01%/V
Load regulation:
Efficiency @ 25 Watt:
VIN = 90VAC: 70%
VIN = 130VAC: 65%
8%/A*
Output short-circuit current: 2.5 A average
*This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side
control winding is sensed by the SG1842 error amplifier. Load regulation is therefore dependent on the
coupling between secondary and control windings, and on transformer leakage inductance.
19
Current Mode PWM Controller
Package Outline Dimensions
Controlling dimensions are in inches, metric equivalents are shown for general information.
MILLIMETERS
INCHES
D
Dim
MIN
MAX
MIN
MAX
A
A2
b
-
5.08
-
0.200
3.30 Typ.
1.30 Typ.
E1
0.38
0.76
0.20
-
0.51
1.65
0.145
0.030
0.008
-
0.020
0.065
0.015
0.400
b2
c
0.38
D
E
10.16
b2
7.62 BSC
2.54 BSC
0.300 BSC
0.100 BSC
E
e
E1
L
θ
6.10
6.86
-
15°
0.240
0.270
-
15°
A2
A
L
3.05
0°
0.120
0°
c
Note:
Dimensions do not include mold flash or protrusions; these
shall not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
H
e
θ
b
Figure 1 · M 8-Pin PDIP Package Dimensions
MILLIMETERS
INCHES
MIN
Dim
MIN
4.32
0.38
1.04
0.20
9.52
5.59
MAX
5.08
0.51
1.65
0.38
10.29
7.11
MAX
0.200
0.020
0.065
0.015
0.405
0.280
D
A
b
0.170
0.015
0.045
0.008
0.375
0.220
5
4
8
b2
c
E
D
E
1
e
2.54 BSC
0.100 BSC
eA
b2
eA
H
L
7.37
0.63
3.18
-
7.87
1.78
4.06
15°
0.290
0.025
0.125
-
0.310
0.070
0.160
15°
A
α
Q
0.51
1.02
0.020
0.040
c
Q
L
Note:
SEATING
PLANE
H
e
α
Dimensions do not include protrusions; these shall not
exceed 0.155mm (.006”) on any side. Lead dimension shall
not include solder coverage.
b
Figure 2 · Y 8-Pin CERDIP Package Dimensions
20
Package Outline Dimensions
Package Outline Dimensions
MILLIMETERS
INCHES
MIN
Dim
MIN
1.35
0.10
1.25
0.33
0.19
4.83
5.79
MAX
1.75
0.25
1.52
0.51
0.25
5.21
6.20
MAX
0.069
0.010
0.060
0.020
0.010
0.205
0.244
A
A1
A2
b
0.053
0.004
0.049
0.013
0.007
0.189
0.228
c
D
E
e
1.27 BSC
0.050 BSC
H
3.81
0.40
0°
4.01
1.27
8°
0.150
0.016
0°
0.158
0.050
8°
L
θ
*LC
-
.010
-
0.004
*Lead Co-planarity
Note:
Dimensions do not include mold flash or protrusions; these
shall not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage
Figure 3 · DM 8-Pin SOIC Package Dimensions
MILLIMETERS
INCHES
MIN
Dim
MIN
1.35
0.10
1.25
0.33
0.19
8.54
5.79
MAX
1.75
0.25
1.52
0.51
0.25
8.74
6.20
MAX
0.069
0.010
0.060
0.020
0.010
0.344
0.244
A
A1
A2
b
0.053
0.004
0.049
0.013
0.007
0.336
0.228
c
D
E
e
1.27 BSC
0.050 BSC
H
3.81
0.40
0°
4.01
1.27
8°
0.150
0.016
0°
0.158
0.050
8°
L
θ
*LC
-
.010
-
0.004
*Lead Co-planarity
Note:
Dimensions do not include mold flash or protrusions; these
shall not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage
Figure 4 · D 14-Pin SOIC Package Dimensions
21
Current Mode PWM Controller
Package Outline Dimensions
MILLIMETERS
INCHES
Dim
MIN
-
MAX
5.33
-
MIN
MAX
0.210
-
D
A
-
A1
A2
b
0.38
0.015
3.30 Typ.
0.130 Typ.
E1
0.36
1.14
0.56
1.78
0.014
0.045
0.008
0.730
0.022
0.070
0.014
0.810
b1
c
1
0.20
0.36
b1
D
18.54
20.57
E
e
2.54 BSC
0.100 BSC
E
7.62
6.10
2.92
0°
8.26
7.11
3.81
15°
0.300
0.240
0.115
0°
0.325
0.280
0.150
15°
A2
A
E1
L
θ
c
A1
L
e
Note:
S
EATING PLANE
θ
b
Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm (.006”) on any side.
Lead dimension shall not include solder coverage.
Figure 5 · N 14-Pin PDIP Package Dimensions
MILLIMETERS
INCHES
MIN
Dim
MIN
4.32
0.38
1.04
0.20
19.30
5.59
MAX
5.08
0.51
1.65
0.38
19.94
7.11
MAX
0.200
0.020
0.065
0.015
0.785
0.280
D
A
b
0.170
0.015
0.045
0.008
0.760
0.220
8
14
b2
c
E
1
D
E
7
e
2.54 BSC
0.100 BSC
eA
eA
H
L
7.37
0.63
3.18
-
7.87
1.78
4.06
15°
0.290
0.025
0.125
-
0.310
0.070
0.160
15°
A
Q
b2
α
c
L
Q
0.51
1.02
0.020
0.040
H
e
b
Note:
θ
Dimensions do not include protrusions; these shall not
exceed 0.155mm (.006”) on any side. Lead dimension
shall not include solder coverage.
Figure 6 · J 14-Pin CERDIP Package Dimensions
22
Package Outline Dimensions
Package Outline Dimensions
MILLIMETERS
INCHES
MIN
Dim
MIN
1.45
0.25
0.102
-
MAX
1.70
MAX
0.067
0.019
0.006
0.290
0.252
0.272
0.057
0.010
0.004
-
A
b
0.483
0.152
7.37
b
c
6
7
5
4
3
2
D
8
D
E
6.04
-
6.40
0.238
-
9
E1
6.91
10
1
e
1.27 BSC
0.050 BSC
e
E
E1
L
Q
6.35
0.51
0.20
9.40
1.02
0.38
0.250
0.020
0.008
0.370
0.040
0.015
S1
L
L
S1
Notes:
Q
c
A
1. Lead No. 1 is identified by tab on lead or dot on cover.
2. Leads are within 0.13mm (.0005”) radius of the true
position (TP) at maximum material condition.
3. Dimension “e” determines a zone within which all body
and lead irregularities lie.
Figure 7 · F 10-Pin Ceramic Flatpack Package Dimensions
E3
D
MILLIMETERS
INCHES
Dim
MIN
8.64
-
MAX
9.14
MIN
MAX
0.360
0.320
D/E
E3
e
0.340
-
8.128
E
1.270 BSC
0.635 TYP
0.050 BSC
0.025 TYP
B1
L
1.02
1.52
0.040
0.060
0.090
A
1.626
2.286
0.064
h
1.016 TYP
0.040 TYP
A
L2
L
8
A1
A1
A2
1.372
-
1.68
1.168
2.41
0.054
-
0.066
0.046
0.95
3
1
L2
1.91
0.075
B3
Note:
0.203R
0.008R
All exposed metalized area shall be gold plated 60 micro-
inch minimum thickness over nickel plated unless otherwise
specified in purchase order.
13
h
18
A2
B3
e
B1
Figure 8 · L 20-Pin Leadless Chip Carrier Package Dimensions
23
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense and security, aerospace, and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and
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anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
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Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
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