SL1935D/KG/NP4P [MICROSEMI]

Consumer Circuit, PDSO36, 7.50 MM, LEAD FREE, SSOP-36;


型号：	SL1935D/KG/NP4P
厂家：	Microsemi
描述：	Consumer Circuit, PDSO36, 7.50 MM, LEAD FREE, SSOP-36 光电二极管商用集成电路
文件：	总23页 (文件大小：620K)
中文：	中文翻译
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SL1935

Single Chip Synthesized Zero IF Tuner

February 2005

Features

Ordering Information

SP1935D/KG/NP3Q

SL1935D/KG/NP2Q

SL1935D/KG/NP1P

SL1935C/KG/NP1P

SL1935D/KG/NP3P

SL1935D/KG/NP4P

SL1935C/KG/NP1Q

SL1935D/KG/NP2P

SL1935D/KG/NP1Q

SL1935D/KG/NP4Q

36 Pin SSOP

36 Pin SSOP*

36 Pin SSOP

36 Pin SSOP*

36 Pin SSOP

36 Pin SSOP*

Tape & Reel

Tubes

•

Singlechipsynthesisedtunersolutionforquadrature

down conversion, L-band to Zero IF.

DVB compliant, operating dynamic range -70 to

-20dBm.

Compatible with DSS and DVB variable symbol rate

applications.

Tubes

Tape & Reel

Tubes

Tape & Reel

Selectable baseband path, programmable through

*Pb Free Matte Tin

I C bus.

Excellent quadrature balance up to 30MHz

baseband

Excellent immunity to spurious second harmonic

(RF and LO) mixing effects.

Description

•

Low oscillator phase noise and reradiation.

High output referred linearity for low distortion and

multi channel application.

The SL1935 is a complete single chip

bus controlled

I C

Zero IF tuner and operates from 950 to 2150MHz. It

includes an on-board low phase noise PLL frequency

synthesiser and low noise LNA/AGC. The SL1935 is

intendedprimarilyforapplicationindigitalsatellite Network

Interface Modules and performs the complete tuner

function.

•

Integral fast mode compliant I C bus controlled PLL

frequencysynthesiser, designedforhighcomparison

frequencies and low phase noise performance.

Buffered crystal output for clocking QPSK

demodulator.

•

ESD protection (Normal ESD handling procedures

should be observed).

Applications

•

Satellite receiver systems.

Data communications systems.

XTALC AP

P UMP

DR IVE

P ORT P 0

VE E

XTAL

S DA

S C L

BUFR E F

VC C D

VC C

TANKS

TANKS B

VE E

R F

TANKV

TANKVB

VE E

R FB

VC C

IFIA

IFQA

IFIB

IFQB

VC C

OFIA

OFIB

VE E

OFQA

OFQB

VE E

IOUT

ADD

QOUT

AG C C ONT

Figure1. Pin connections

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

SL1935

The device contains all elements necessary, with the

exception of local oscillator tuning network and crystal

reference, to produce a high performance I(n-phase) &

Q(uadrature) downconversion tuner function. Due to the

high signal handling design the device does not require

any front end tracking filters.

The S L1935 includes selectable baseband signal paths,

allowing application with two externally definable filter

bandwidths, facilitating application in variable symbol

rate and simulcast systems. The S L1935 is optimised to

interface with the VP 310 (ADC /QP S K/FE C ) S atellite

C hannel Decoder, available from Zarlink S emiconductor

and offers a full front end solution.

RFB

AGCCONT

23 OFQA

22 OFQB

26 IFQA

25 IFQB

20 QOUT

RF Section

VCC

RF section

AGC

Sender

7,10,13,24

VCCD

VEE

16,21,27,30,33

PLL section

90deg

17 IOUT

11 IFIA

TANKV 29

TANKVB 28

Frequency

Agile

VCOV

Phase

12 IFIB

Splitter

TANKS 32

TANKSB 31

Divide

by 2

0deg

14 OFIA

15 OFIB

VCOS

36 PUMP

35 DRIVE

Fpd

15 bit

Charge

Pump

Programmable

Divider

PLL Section

SDA 3

SCL 4

I²C Bus Interface

34 PORT P0

5 BUFREF

ADD 18

Fpd/2

REF

OSC

XTAL 2

XTALCAP 1

Reference

Divider

Fcomp

Figure 2. Block diagram

SL1935

Table 1. QuickReferenceData

Characteristic

Value

Units

MHz

dBm

950 to 2150

-75 to -15

Operating range

Input dynamic range

VSWR with input match

Input NF

dBm

deg

+20

-5

2.0

0.2

0.7

@ -70dBm operating sensitivity

@ -60dBm operating sensitivity

IPIP3 @ -20dBm operating sensitivity

IPIP2@ -20dBm operating sensitivity

IPP1dB@ -20dBm operating sensitivity

Baseband output limit voltage

Gain match up to 22MHz

Phase match up to 22MHz

Gain flatness up to 30MHz

Local oscillator phase noise

SSB at 10kHz offset

In band LO reradiation from RF input

LO second harmonic interference level at input level of

-20dBm per carrier

dBc/Hz

dBm

dBc

-80

<-70

-55

dBc

-35

LNA second harmonic interference level at input level

of -25dBm per carrier

MHz

dBc/Hz

-152

PLL maximum comparison frequency

PLL phase noise at phase detector

Note: `6dB interstage filter loss assumed in external base band paths.

dBm assumes 75Ω characteristic impedance.

Quadrature Downconverter Section

FunctionalDescription

In normal application the tuner IF frequency of typically

950 to 2150MHz is fed direct to the SL1935 RF input

through an appropriate impedance match (Fig.16) and

LNB switching. The input stage is optimised for both NF

and signal handling.

General

The SL1935 is a complete wideband direct conversion

tuner incorporating an on board frequency synthesiser

andLNA/AGC, optimisedforapplicationindigitalsatellite

receiver systems. The device offers a highly integrated

The signal handling of the front end is designed to offer

immunity to input composite overload without the

requirement of a tracking filter. RF input impedance is

shown in Fig.3.

solutiontoasatellitetunerfunction, incorporatinganI C

businterfacecontroller, alowphasenoisePLLfrequency

synthesiser and all tuner analogue functionality. The

analogue blocks include the reference oscillator,

consistingoftwoindependentoscillators,aphasesplitter,

RF preamplifier with AGC facility, channel mixers and

baseband amplifiers incorporating two selectable

baseband paths, allowing for two externally definable

bandwidths. In this application two varactor tuned tanks,

a reference crystal and baseband filtering components

are required to complete the tuner system.

The RF input amplifier feeds an AGC stage and provides

system gain control. The system AGC gain range will

guarantee anoperating dynamicrange of-70to-20dBm.

TheAGCiscontrolledbytheAGCsenderandisoptimised

for S/N and S/I performance across the full dynamic

range. Details of the AGC characteristics, variations in

IIP3, IIP2, P1dB and NF are illustrated in Figs.4, 5, 6, 7,

and 8 respectively.

A buffered crystal frequency output is available to clock

the QPSK demodulator and powers up in the active

state.

The required I and Q local oscillator frequencies for

quadrature downconversion are generated by the on-

board reference oscillators designated ‘VCOS’ and

‘VCOV’. VCOSoperatesnominallyfrom1900to3000MHz

and is then divided by two to provide 950 to 1500MHz.

VCOV operates nominally from 1400 to 2200MHz. Only

TheI C businterfacecontrolsthefrequencysynthesiser,

the local oscillator, the baseband path selection, the

buffered reference frequency output and an external

switching port.

the oscillator selected via bit VS in the I C data

transmission is powered.

Figure 2 shows the device block diagram and pin

allocations are shown in Figure 1.

SL1935

Quadrature DownconverterSection - continued

The oscillators share a common varactor line drive and

both require an external varactor tuned resonator

optimised for low phase noise performance. The

recommended application circuit for the local oscillators

is detailed in Fig.9 and the typical phase noise

performance is detailed in Fig.10. The local oscillator

frequency is coupled internally to the PLL frequency

synthesiser programmable divider input.

The output of the phase detector feeds a charge pump

and a loop amplifier. When used with an external loop

filterandahighvoltage transistoritintegrates thecurrent

pulses into the varactor line voltage used to control the

selected oscillator.

The programmable divider output Fpd divided by two

and the reference divider output Fcomp are switched to

port P0 by programming the device into test mode. Test

modes are detailed in Table 4.

The mixer outputs are coupled to the baseband buffer

amplifiers, providing for one of two selectable baseband

outputs in each channel. The required output is selected

The crystal reference frequency can be switched to the

BUFREF output by bit RE as detailed in Table 7.

by bit BS in the I C bus transmission (Table 6). These

outputs are fed off chip via ports ‘OPIA’ and ‘OPIB’

(‘OPQA’ and ‘OPQB’), then back on chip through ports

‘IPIA’ and ‘IPIB’ (‘IPQA’ and ‘IPQB’), allowing for the

insertion of two independent user definable filter

bandwidths. Each output provides a low impedance

drive(Fig.11) andeachinputprovides ahighimpedance

load . An example filter for 30MS/s is detailed in Fig.13.

Both path gains are nominally equal. NB 6dB insertion

loss is assumed in each channel, however a different pot

down ratio may be applied.

Programming

The SL1935 is controlled by an I C data bus and is

compatible with both standard and fast mode formats.

Data and Clock are fed on the SDA and SCL lines

respectively as defined by the I C bus format. The

device can either accept data (write mode) or send data

(readmode). TheLSBoftheaddressbyte (R/W)setsthe

device into write mode if it is low and read mode if it is

high. Tables 9a and 9b detail the format of the data. The

SL1935 may be programmed to respond to several

addresses and enables the use of more than one device

Each baseband path is then multiplexed to the final

baseband amplifier stage, providing further gain and a

low impedance output drive. The nominal output load

test condition is detailed in Fig.14.

in an I C bus system. Table 9c details the how the

address is selected by applying a voltage to the ‘ADD’

input. When the device receives a valid address byte, it

pulls the SDA line low during the acknowledge period

and during following acknowledge periods after further

data bytes are received. When the device is

programmed into read mode, the controller accepting

the data must pull the SDA line low during all status byte

acknowledge periods to read another status byte. If the

controller fails to pull the SDA line low during this period,

the device generates an internal‘STOP’ condition which

inhibits further reading.

PLL Frequency Synthesiser Section

The PLL frequency synthesiser section contains all the

elements necessary, with the exception of a reference

frequency source and a loop filter to control the selected

oscillator to produce a complete PLL frequency

synthesised source. The device, produced using high

speed logic, allows for operation with a high comparison

frequency and enables the generation of a loop with

excellent phase noise performance.

Write mode

TheLOsignalfromtheselectedoscillatordrivesfromthe

phasesplitterintoaninternalpreamplifier, providinggain

andreverse isolationfromthedividersignals. Theoutput

of the preamplifier interfaces directly with the 15-bit fully

programmable divider. The programmable divider has

MN+Aarchitecture, thedualmodulusprescaleris16/17,

the A counter is 4-bits and the M counter is 11-bits.

Bytes2and3containfrequencyinformationbits2 to2

inclusive (Table 9). Byte 4 controls the synthesiser

reference divider ratio (Table 3) and the charge pump

setting (Table 5). Byte 5 controls test modes (Table 4),

baseband filter path select BS (Table 6), local oscillator

select VS (Table 8), buffered crystal reference output

select RE (Table 7) and the output port P0.

After reception and acknowledgment of a correct

address (byte 1), the first bit of the following byte

determines whether the byte is interpreted as byte 2 or

4, alogic‘0’ indicatesbyte 2andalogic‘1’indicatesbyte

4. Having interpreted this byte as either byte 2 or 4, the

following byte will be interpreted as byte 3 or 5

respectively. After receiving two complete data bytes,

additional data bytes may be entered and byte

interpretation follows the same procedure without re-

addressing the device. The procedure continues until a

The output of the programmable divider is fed to the

phase comparator and compared in both phase and

frequency domains to the comparison frequency. This

frequency is derived from either the on board crystal

controlledoscillatororfromanexternalreferencesource.

In both cases the reference frequency is divided down to

the comparison frequency by the reference divider,

programmable into 1 of 29 ratios and detailed in Table 3.

The typical application for the crystal oscillator is shown

in Fig.15.

condition is received.

‘STOP’

SL1935

Bit1(POR)isthepower-on resetindicator, andthisisset

The STOP condition can be generated after any data

byte, if however it occurs during a byte transmission, the

previous byte data is retained. To facilitate smooth fine

tuning, the frequency data bytes are only accepted by

the device after all 15 bits of frequency data have been

received, or after the generation of a STOP condition.

to a logic ‘1’ if the Vccd supply to the device has dropped

below3V(at25 C),e.g. whenthedevice isinitiallyturned

ON. The POR is reset to ‘0’ when the read sequence is

terminatedby a STOP command. When POR is set high

this indicates that the programmed information may

have been corrupted and the device reset to the power

up condition.

Read mode

Bit 2 (FL) indicates whether the synthesiser is phase

locked, a logic ‘1’ is present if the device is locked, and

a logic ‘0’ if the device is unlocked.

When the device is in read mode, the status byte read

from the device takes the form shown in Table 9b.

Table 2. Programmable Features

Programmable features

Function

Function as described above

Function as described above.

Synthesiser programmable divider

Reference programmable divider

Baseband filter path select

Local oscillator select

Function as described above.

The charge pump current can be programmed by bits C1 & C0 (Table 5).

The test modes are defined by bits T2 - T0 as described in Table 4.

The general purpose port can be programmed by bit P0;

Logic ‘1’ = on

Charge pump current

Test mode

General purpose port, P0

Logic ‘0’ = off (high impedance)

The buffered crystal reference frequency can be switched to the BUFREF

output by bit RE as described in Table 7. The BUFREF output defaults to

the ‘ON’ condition at device power up.

Buffered crystal reference output,

BUFREF

The typical key performance data at Vcc = 5V and +25 C ambient are detailed in Table 1.

Table 3. Reference division ratios

Ratio

128

256

Illegal state

160

320

Illegal state

192

384

Illegal state

112

224

448

SL1935

Table 4. Test modes

Test mode description

Normal operation

Charge pump sink* (status byte FL set to logic '0')

Charge pump source* (status byte FL set to logic '0')

Charge pump disabled* (status byte FL set to logic '1')

Normal operation and port P0 = Fpd/2

Charge pump sink* (status byte FL set to logic '0'. Port P0 = Fcomp)

Charge pump source* (status byte FL set to logic '0'. Port P0 = Fcomp)

Charge pump disabled* (status byte FL set to logic '1'. Port P0 = Fcomp)

Note: * Clocks need to be present on crystal and RF inputs to enable charge pump test modes and to

toggle status byte bit FL.

Table 5. Charge pump current

Current in µA

min

typ

max

+-194

+-412

+-862

+-116

+-247

+-517

+-155

+-330

+-690

+-1087 +-1450 +-1812

Table 6. Baseband path select

Path Selected

I Channel Q Channel

Baseband Filter drive Baseband

Filter drive

output

amp input output amp input

IFIB

IFIA

OFQB

OFQA

IFQB

IFQA

OFIB

OFIA

Table 7. Buffered crystal

reference output select

BUFREF output

Disabled, high impedance

Enabled

Table 8. Local oscillator select

Local oscillator selected

VCOV

VCOS

SL1935

Table 9a. Write data format (MSB is transmitted first)

MSB

LSB

Address

MA1

MA0

Byte 1

Byte 2

Programmable

divider

Programmable

divider

Byte 3

Control data

Byte 4

Byte 5

Table 9b. Read data format (MSB is transmitted first)

MSB

LSB

Address

Status Byte

POR

MA1

MA0

Byte 1

Byte 2

Table 9c. Address selection

Address input voltage level

0 - 0.1 Vcc

MA1

MA0

Open circuit

0.4 Vcc - 0.6 Vcc*

0.9 Vcc - Vcc

Note:

Programmed by connecting a 30kΩ resistor between pin and Vcc

Key to Tables 9a to 9c

A .........................................Acknowledge bit

MA1, MA0 ........................... Variable address bits (Table 9c)

2¹⁴to 2⁰................................ Programmable division ratio control bits

C1 to C0 .............................. Charge pump current select (Table 5)

R4 to R0 .............................. Reference division ratio select (Table 3)

T2 to T0 .............................. Test modes control bits (Table 4)

BS .......................................Baseband path select (Table 6)

VS .......................................Local oscillator select (Table 8)

RE .......................................Buffered crystal reference output enable (Table 7)

P0 .......................................P0 port output state

POR .................................... Power on reset indicator

FL........................................Phase lock flag

+j1

+j2

+j0.5

+j0.2

+j5

Marker Freq (MHz)

Z real Ω Z imag Ω

950

-100

-75

-65

-45

1400

1600

2150

0.2

0.5

—j5

—j0.2

—j2

—j0.5

START 950MHz

Normalised to 75Ω

—j1

STOP 2150MHz

Figure 3. RF input impedance (typical)

SL1935

70dB minimum, AGC < 0.75V

20dB maximum, AGC > 4.25V

0.5

1.5

2.5

AGCCONT Voltage (V)

3.5

4.5

Figure 4. AGC characteristic (typical)

120

110

100

System gain (dB) assuming 6dB interstage filter loss

Figure 5. Variation in IIP3 with system gain (typical)

170

160

150

140

130

120

110

100

Baseband dominated IP2

LNA dominated IP2

35 55

System gain (dB) assuming 6dB interstage filter loss

Figure 6. Variation in IIP2 with system gain (typical)

SL1935

110

105

100

-10

10 25

Converter gain seting (dB) from RF inputs OFIA/OFQA or OFIB/OFQB outputs

-5

Figure 7. Variation in P1dB with converter gain (typical)

System gain (dB) assuming 6dB interstage filter loss

Figure 8. Variation in NF with system gain (typical)

BB837

4mm STRIPLINE

Tanks

1kΩ

"vcos"

2kΩ

BB837

4mm STRIPLINE

10mm STRIPLINE

Tanksb

Vcnt

BB831

Tankv

"vcov"

2kΩ

10mm STRIPLINE

NOTE:

Stripline width = 0.44mm

(dimensions are approximate)

1kΩ

Tankvb

Figure 9. Local oscillator application circuit

SL1935

LO Frequency (MHz)

1500 1600

900

-70

1000

1100

1200

1300

1400

1700

1800

1900

2000

2100

-72

-74

-76

-78

-80

-82

-84

-86

-88

-90

vcos enabled

cov enabled

Conditions:

Loop filter as per standard application shown in Figure 21

Charge pump = 130uA

Fcomp = 65.5kHz or 125kHz

Figure 10. Local oscillator phase noise variation with frequency (typical)

+j1

+j0.5

+j2

+j0.2

+j5

Marker Freq (MHz)

Z real Ω

Z imag Ω

x^0.5

0.2

—j5

—j0.2

—j2

—j0.5

STOP 30MHz

START 1MHz

Normalised to 50Ω

—j1

Figure 11. Converter output impedance; OFIA, OFIB, OFQA, OFQB (typical)

+j1

+j0.5

+j2

+j0.2

+j5

Freq (MHz)

Z real Ω

9.5

10.0

10.6

12.6

Z imag Ω

Marker

0.1

-2.0

1.3

3.3

5.5

0.2

0.5

—j5

—j0.2

—j2

—j0.5

START 100kHz

Normalised to 50Ω

STOP 30MHz

—j1

Figure 12. Baseband output impedance; IOUT, QOUT (typical)

SL1935

100nF

3.9pF

100nF

1k Ω

OFIA/OFIB

OFQA/OFQB

IFIA/IFIB

IFQA/IFQB

1k Ω

Figure 13. Example baseband interstage filter for 30MS/s

220nF

100 Ω

15pF

1k Ω

Figure 14. Nominal baseband output load test condition

1 XTALCAP

150pF

2 XTAL

82pF

4MHz

Figure 15. Crystal oscillator application (typical)

SL1935

1pF

100pF

33Ω

RFIN

RFB

2.2pF

Figure 16. Input matching network

Table 10. ElectricalCharacteristics

Test conditions (unless otherwise stated); Tamb = -20 to +80 C, Vee= 0V, Vcc =Vccd = 5V+-5%.

These characteristics are guaranteed by either production test or design. They apply within the specified ambient

temperature and supply voltage unless otherwise stated.

Value

Conditions

Units

Characteristic

Supply current

Typ

Min

Max

6,7,10

13,24

8,9

130

175

VCCD (PLL) and VCC

RF input operating frequency

MHz

950

2150

SYSTEM

All system specification items should

be read in conjunction with Note 2

At -70dBm operating sensitivity

At -60dBm operating sensitivity

Above –60dBm operating sensitivity,

(Fig.7)

System noise figure DSB

dB/dB

-1

Variation in system NF with gain

adjust

System input referred IP2

dBµV

121

112

140

At –20dBm operating sensitivity, see

Notes 3 and 4

(Fig.6)

Variation in system input referred

IP2 with operating sensitivity

System input referred IP3

At -20dBm operating sensitivity,

see Note 5

Variation in system input referred

IP3 with operating sensitivity

(Fig.5)

Continued

SL1935

(Continued)

Table 10. ElectricalCharacteristics

Value

Units

Conditions

Characteristic

Typ

Min

Max

System dynamic range

Note 6

AGCCONT = 0.75V

dBm

-70

-20

dBm AGCCONT = 4.25V

System gain roll off

System gain variation with

temperature

Within RF band 950-2150MHz

-20˚C to +80˚C

deg

System I Q gain match

System I Q phase balance

System I and Q channel in band 17,20

ripple

17,20

-1

-3

Interstage filter (Fig.13)

dBc

System baseband path gain

match

LO second harmonic interference

level

LNA second harmonic

interference level

-1

Note 8.

Note 9.

-50

-35

dBc

dBµV

Synthesiser and other spurii on I 17,20

and Q outputs

Within 0-100MHz band under all gain

settings, RF input set to deliver

108dBµV on output

Within RF band 950-2150MHz.

Note 11.

dBm

In band leakage to RF input

8,9

-60

CONVERTER

Ω

dBµV

Converter input impedance

Converter input return loss

System input referred P1dB

8,9

102

With input matching (Fig.16)

Converter gain =-5dBm (to OFIA/

OPQA, OFIB/OPQB outputs. Fig.7)

0.1 to 30MHz (Fig.11)

Ω

Converteroutputimpedance,OFIA, 14,15

OFIB, OPQA and OPQB.

22,23

dBc

Converter output leakage to

unselected output, OFIA, OFIB,

OPQA and OPQB.

Relative to selected output

-26

MHz

Oscillator VCOS operating range 31,32 1900

3000

2150

Giving LO = 950 to 1500MHz

(Application as in Fig.9)

@10kHz offset, PLL loop bw < 1kHz

Applicationismeasuredatbaseband

output frequency of 10MHz (Fig.10).

MHz

dBc/Hz

Oscillator VCOV operating range 28,29 1450

Local oscillator SSB phase noise

-78

AGCONT input current

-150

150

µA

BASEBANDAMPLIFIERS

The baseband inputs must be

externally ac coupled

Baseband input impedance, IFIA, 11,12

0.1- 30MHz bandwidth

IFIB, IFQA And IFQB.

Resistance

Capacitance

25,26

kΩ

dBc

Baseband unselected input 17,20

leakage to output

-40

Relative to selected input.

Ω

Baseband amplifier output 17,20

impedance

Vp-p

MHz

dB/oct

Baseband output limiting

Baseband bandwidth 1dB

Baseband output roll-off

17,20

2.0

Level athardclipping(loadasFig.14)

(Load as Fig.14)

Above 3dB point, no load

Continued

SL1935

Table 10. ElectricalCharacteristics (Continued)

Value

Units

Conditions

Characteristic

Typ

Min

Max

SYNTHESISER

SDA,SCL

Input high voltage

Input low voltage

Input high current

Input low current

3,4

I²C 'fast mode' compliant

µA

5.5

1.5

Input voltage = Vcc

Input voltage = Vee

-10

Leakage current

Hysterysis

SDA output voltage

µA Vcc = Vee = 0V

0.4

+-3

0.4

0.6

400

Isink = 3mA

Isink = 6mA

SCL clock rate

kHz

Charge pump output current

Charge pump output leakage

Charge pump drive output current

Crystal frequency

Vpin36 = 2V. (Table 5)

nA Vpin36 = 2V

mA Vpin35 = 0.7V

MHz (Fig.15 for application)

1,2

+-10

0.5

Recommended crystal series

resistance

200

Ω

4MHz parallel resonant crystal

Externalreferenceinputfrequency

0.5

MHz Sinewave coupled via 10nF blocking

capacitor

External reference drive level

Vpp Sinewave coupled via 10nF blocking

capacitor

MHz

0.2

Phase detector comparison

frequency

Equivalent phase noise at phase

detector

-152

dBc/Hz SSB within loop bandwidth, all

comparison frequencies

Local oscillator programmable

divider division ratio

Reference division ratio

Output port P0

Sink current

Leakage current

32767

240

(Table 3)

(Note 7)

mA Vport = 0.7

µA Vport = Vcc

AC coupled. (Note 10.)

Vpp Enabled by bit RE = 1 and default

BUFREF output

0.45

Output amplitude

Output impedance

Address select

0.25 0.35

250

Ω

state on power-up.

(Table 9c)

Input high curent

Input low current

-0.5

mA Vin = Vcc

mA Vin = Vee

Notes to Table 10

All power levels are referred to 75Ω, and 0dBm = 109dBµV.

System specifications refer to total cascaded system of converter/AGC stage and baseband amplifier stagewith nominal

6dB pad as interstage filter and load impedance as detailed in Figure 14.

Baseband dominated IP2. AGC set for 20dB system gain with two tones for intermodulation test at fc+146and

fc+155MHz at 100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included.

LNA dominated IP2. AGC set for 20dB system gain with two tones for intermodulation test at fc+146 and2*fc+155 MHz at

100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included.

AGC set for 20dB system gain with two tones for intermodulation test at fc+110 and fc+211MHz at 100dBµVgenerating

output intermodulation spur at 9MHz. 30MHz 3dB bandwidth interstage filter included.

Dynamic range assuming termination as detailed in Figure 14, and including 6 dB interstage filter insertion loss,

delivering 700mVp-p at baseband outputs (pins 17,20). AGC monotonic from Vee to Vcc (Fig.4).

Port powers up in high impedance state.

The level of 2.01GHz downconverted to baseband relative to 1.01GHz with the oscillator tuned to 1GHz,measured with

no input pre-filtering.

The level of second harmonic of 1.01GHz input at –25dBm downconverted to baseband relative to 2.01GHz at–40 dBm

with the oscillator tuned to 2GHz, measured with no input pre-filtering.

10.

11.

If the BUFREF output is not used it should be left open circuit or connected to Vccd, and disabled by settingRE = ‘0’.

This parameter is very application dependant. With good RF isolation <-60dBm can be achieved.

SL1935

REF

30K

AGCCONT

RFB

RF inputs

AGC input

REF2

TANK

OFIA

OFIB

OFQA

OFQB

TANKB

Converter outputs (pins 14, 15, 22 and 23)

Oscillator inputs (pins 28, 29 and 31, 32)

IFIA

IFIB

IFQA

IFQB

IOUT

and

QOUT

BIAS

Baseband amplifier inputs

(pins 11, 12, 25 and 23)

Baseband outputs (pins 17 and 20)

Figure 17. Input and output interface circuits (RF section)

SL1935

ccd

PUMP

XTAL

XTALCAP

300

DRIVE

Loop amplifier

Reference oscillator

ccd

60K

47K

ADD

SCL/SDA

]

20K

ACK

]On SDA only

ADD input

SDA/SCL (pins 3 and 4)

ccd

BUFREF

ENABLE/

DISABLE

BUFREF output

Output port

Figure 18. Input and output interface circuits (PLL section)

SL1935

Table 11. Absolute Maximum Ratings(All voltages referred to Vee at 0V and Vcc = Vccd)

Characteristic

Min

Max

Units

Conditions

Supply voltage

-0.3

SDA, SCL DC offsets

All I/O port DC offsets

Port P0 current

Vcc = Vee to 5.25V

Vcc+0.3

150

Storage temperature

-55

Junction temperature

Package thermal resistance,

chip to case

Package thermal resistance,

chip to ambient

C/W

919

Power consumption at 5.25V

ESD protection

3.5

Mil-std 883 method 3015 cat1

SL1935 Demo Board

The demo board contains an SL1935 I²C bus controlled VCOS oscillates at twice the LO frequency (lower band)

Zero IF tuner IC, plus all components necessary to and is then divided by two to provide the required LO

demonstrate operation of the SL1935. The schematic frequency in the range 950MHz to 1500MHz

and PCB layout of the board are shown in Figures 19, 20 (approximately).

and 21.

VCOV oscillates at the LO frequency (upper band) in the

range 1500MHz to 2150MHz (approximately).

Supplies

The board must be provided with the following supplies:

3. Baseband path select.

5V for the synthesiser section (5VD)

5V for the converter and baseband sections (5V)

30V for the varactor line (30V)

TheSL1935hastwofilterpathsselectedby programming

bit BS of the I²Cdata (see Tables 6 and 9a to 9c). The

value of BS is changed by toggling the switch position to

theleftof‘FilterA’and‘FilterB’onthemainsoftware block

diagram.

The supply connector is a 5 pin 0.1” pin header.

The order of connections is 5V – GND – 30V – GND – 5V.

4. AGC control.

I²C busconnections

The conversion gain of the SL1935 is set by the voltage

applied to the AGCCONT input. On the demo board this

is controlled by the potential divider labelled ‘AGC ADJ’

which varies the AGCCONT input from 0V to Vcc.

The board is provided with a RJ11 I²C bus connector

which feeds directly to the synthesiser. This connects to

a standard 4 way cable.

Operating instructions

1. Software.

CAUTION: Care should be taken to ensure the chip is

powered ON if the board is modified to accept an external

AGC inputvoltage. Damagetothedevice may resultifthis

is not complied with as a result of the IC powering itself up

via the AGCCONT input ESD protection diode. It is

recommended that a low current limit is set on any

external AGC voltage source used.

Use the Zarlink Semiconductor synthesiser software. Pull

down the ‘Device’ menu, then select the ‘SL1935’. It is

suggested that the charge pump is set to 130uA with a

reference divider ratio of 32. These settings give a small

loop bandwidth (i.e. 100’s Hz), which allows detailed

phase noise measurements of the oscillators to be taken

if desired.

5. Free running the VCO’s.

SelecttherequiredVCOasdetailedin(2)above. Program

an LO frequency which is above the maximum capability

of the oscillator. 3GHz is suggested. Under this condition

the varactor control voltage is pumped to its maximum

value, ie to the top of the band. The oscillator frequency

can now be manually tuned by varying the 30V supply.

2. VCO control.

The two VCO’s are selected by toggling the oscillator

switch below the two oscillators on the main software

block diagram. Thisswitch programs bitVSoftheI²C data

(see Tables 8 and 9a to 9c).

SL1935

19.

View

Figure 19. Top view

SL1935

Figure 20. Bottom view

30V

CN8

5VD

DC POWER

R20

22K

R18

13K

R19

13K

C30

C28

100nF

C29

100pF

22uF

82pF

C27

15nF

C26

TP6

68pF

C25

2n2

30V

IC1

XTALCAP

XL1

4MHz

CN7

I2C

PUMP

150pF

TP5

TR1

BCW31

R16

R17

5VD

XTAL

SDA

SCL

BUFref

VccD

Vcc

DRIVE

PORT P0

Ve e

TP1

C31

100nF

C32

100pF

SDA

5V0

GND

D1 BB837

TP2

SCL

SK1

RF IN

R23

RFinA

TP3

TANKSa

TANKSb

Ve e

5VD

C40

100pF

C39

100pF

C38

22uF

BB831

C33

100pF

C34

100pF

C35

100pF

C36

100nF

C37

100pF

D2 BB837

1nF

RFinA

R24

RFin

RFinB

Vcc

TANKVa

TANKVb

Ve e

75R

1nF

GND

C24

5VD

BB831

100nF

IFIa

IFQA

IFQB

R21

Q OUT

C23

100nF

SK2

I OUT

620R

IOUT

IFIb

R15

2K7

TP8

AGC

Vcc

R14

R1 1K

C22

C21

C10

100nF

RV1

AGC

OFIa

OFIb

Ve e

OFQA

OFQB

Ve e

PORT 0

R13 1K

OFQB

R2 1K

R22

R11

R12

620R

QOUT

C11

3p9

SK3

Iout

Qout

C12

3p9

C19

3p9

JP1

C20

3p9

ADD

AGC cont

C18

C13

220nF

SL1935

AGC

TP4

100R

TP7

C16

10nF

R10

100R

QOUT

IOUT

C14

15pF

C17

15pF

Figure 21.

SL1935

Purchase of Zarlink Semiconductor I²C components conveys a licence under the Phillips I²C Patent rights to use

these components in an I²C system,provided that the system conforms to the I²C Standard Specification as

defined by Phillips.

For more information about all Zarlink products

visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.

However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such

information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or

use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual

property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in

certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in

significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I²C components conveys a licence under the Philips I²C Patent rights to use these components in and I²C System, provided that the system

conforms to the I²C Standard Specification as defined by Philips.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

SL1935D/KG/NP4P [MICROSEMI]

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