SL2101C/KG/LH2N [MICROSEMI]
Telecom IC, Bipolar, PQCC28,;
| 型号： | SL2101C/KG/LH2N |
| 厂家： | 
Microsemi |
| 描述： | Telecom IC, Bipolar, PQCC28, |
| 文件： | 总27页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL2101
Synthesized Broadband Converter with
Programmable Power
Data Sheet
April 2005
Features
Ordering Information
•
•
Single chip synthesized broadband solution
Configurable as both up converter and
downconverter requirements in double
conversion tuner applications
SL2101C/KG/NP1P SSOP
SL2101C/KG/NP1Q SSOP
Tubes
Tape & Reel
SL2101C/KG/NP2P SSOP* Tubes
•
•
Incorporates 8 programmable mixer power
SL2101C/KG/NP2Q SSOP* Tape & Reel
settings
SL2101C/KG/LH2N MLP*
SL2101C/KG/LH2Q MLP*
Trays
Compatible with digital and analogue system
requirements
CSO -65 dBc, CTB -68 dBc (typical)
Extremely low phase noise balanced local
oscillator, with very low fundamental and
harmonic radiation
Tape& Reel
* Pb free
All codes baked and drypacked
-40°C to +85°C
•
•
Description
•
•
•
PLL frequency synthesizer designed for high
comparison frequencies and low phase noise
The SL2101 is a fully integrated single chip broadband
mixer oscillator with low phase noise PLL frequency
synthesizer. It is intended for use in double conversion
tuners as both the up and down converter and is
compatible with HIIF frequencies up to 1.4 GHz and all
standard tuner IF output frequencies. It also contains a
programmable power facility for use in systems where
power consumption is important.
Buffered crystal output for pipelining system
reference frequency
I2C Controlled
Applications
•
•
•
•
•
Double conversion tuners
Digital Terrestrial tuners
Cable telephony
Cable Modems
The device contains all elements necessary, with the
exception of local oscillator tuning network, loop filter
and crystal reference to produce
a
complete
synthesized block converter, compatible with digital
and analogue requirements.
MATV
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
SL2101
Data Sheet
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
XTAL CAP
XTAL
SDA
PUMP
DRIVE
PORT P0
Vee
SCL
BUFREF
Vccd
ADD
6
7
8
9
Vee
Vee
VccLO
LOB
Vee
RF
LO
RFB
VccLO
Vee
10
Vee
11
12
13
14
VccRF
Vee
VccLO
Vee
IFOUTPUTB
IFOUTPUT
NP 28
Figure 2 - Pin Diagram SSOP Package
24 23
25
22
21
20
19
28 27 26
Vccd
nc
ADD
nc
1
2
Pin 1 Ident
nc
VccLO
LOB
LO
3
4
RF
18
17
16
15
RFB
nc
5
6
7
VccLO
nc
VccRF
9
13
14
8
10 11 12
Vee to pad
under package
Figure 3 - Pin Diagram MLP Package
2
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Quick Reference Data
All data applies at maximum power setting with the following conditions unless otherwise stated;
a) nominal loads as follows;
1220 MHz output load as in Figure 4
44 MHz output load as in Figure 5
b) input signal per carrier of 63 dBµV
Characteristic
RF input operating range
Units
50-1400
MHz
Input noise figure, SSB,
50-860 MHz
6.5 - 8.5
8.5 - 12
dB
dB
860-1400
Conversion gain
12
-68
-65
110
dB
dBc
CTB (fully loaded matrix)
CSO (fully loaded matrix)
P1 dB input referred
dBc
dBµV
Local oscillator phase noise as upconverter
SSB @ 10 kHz offset
-90
-112
dBc/Hz
dBc/Hz
SSB @ 100 kHz offset
Local oscillator phase noise as downconverter
SSB @ 10 kHz offset
-93
-115
dBc/Hz
dBc/Hz
SSB @ 100 kHz offset
Local oscillator phase noise floor
-136
<-70
4
dBc/Hz
dBc
PLL spurs on converted output with input @ 60 dBµV
PLL maximum comparison frequency
MHz
PLL phase noise at phase detector
-152
dBc/Hz
*dBm assumes a 75 Ω characteristic impedance, and 0 dBm = 109 dBµV
Functional Description
The SL2101 is a broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency
synthesizer, optimized for application in double conversion tuner systems as both the up and down converter. It
also has application in any system where a wide dynamic range broadband synthesized frequency converter is
required.
The SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in Figures 2
and 3 for the SSOP and MLP packages and the block diagram in Figure 1.
The device also contains a programmable facility to adjust the power in the lna/mixer so allowing power to be
traded against intermodulation performance for power critical applications, such as telephony modems.
3
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Converter Section
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to
the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region
of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite
distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the
mixer section and back isolation from the local oscillator section.
The lna/mixer current and hence signal handling and device power consumption are programmable through the I2C
bus as tabulated in Figure 7.
The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and
9 respectively and for narrow band downconversion in Figures 10 and 11 respectively. The input referred two tone
intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and
gain versus frequency and NF specification limits, over selectable power settings are contained in Figures 13, 14
and 15 respectively.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator
application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The
typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure
19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator.
Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of
an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner
output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example
with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is
shown in Figure 4, which will typically be terminated with a differential 200 load. When used as a narrowband
downconverter the output should be differentially loaded with a discrete differential to single ended converter as in
Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in
which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is
contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20.
The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22
respectively.
In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation
performance.
The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference
Data'.
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
4
Zarlink Semiconductor Inc.
SL2101
Data Sheet
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in figure
23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when
driving a second SL2101 as a downconverter.
The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop
filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the
oscillator.
The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to
port P0 by programming the device into test mode. The test modes are described in Figure 26.
The crystal reference frequency can be switched to BUFREF output by bit RE as described in Figure 27. The
BUFREF output is not available on the MLP package.
Programming
The SL2101 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. Tables 1 and 2 in Figure 28 illustrate the format of the data. The
device can be programmed to respond to several addresses, which enables the use of more than one device in an
I2C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write Mode
With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 214 -20 inclusive.
Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29.
Byte 5 controls the test modes, see Figure 26, the buffered crystal reference output select RE, see Figure 27, the
power setting, see Figure 7 and the output port P0.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows
the same procedure, without re-addressing the device. This procedure continues until a STOP condition is
received. The STOP condition can be generated after any data byte, if however it occurs during a byte
transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP
condition.
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped
below 3V (at 25° C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is
terminated by a STOP command. When POR is set high this indicates that the programmed information may have
been corrupted and the device reset to the power up condition.
Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
5
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Programmable Features
Synthesizer programmable divider
Function as described above
Function as described above.
Reference programmable divider
Charge pump current
The charge pump current can be programmed by bits C1 & C0 within
data byte 4, as defined in Figure 29.
Power setting
The device power and hence signal handling can be programmed by
bits I2 - I0 within data byte 5, as defined in Figure 7.
In all power settings the synthesizer remains enabled to facilitate rapid
PLL lock reacquisition
Test mode
The test modes are defined by bits T2 - T0 as described in Figure 26.
The general purpose port can be programmed by bits P0;
Logic '1' = on
General purpose ports, P0
Logic '0' = off (high impedance) - this is the default state at device power
on
Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the
BUFREF output by bit RE as described in Figure 27. The BUFREF
output defaults to the 'ON' condition at device power up. This output is
only available on the SSOP package.
33 Ω
SAWF
33 Ω
Figure 4 - Nominal Output Load as Upconverter into Differential SAWF
6
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Vcc
15 pF
15
820 nH
OUTPUT
10 uH
SL2101
10 nF
14
15 pF
820 nH
Figure 5 - Nominal Output Load as Downconverter, 44 MHz IF
10 nF
Vcc
680 nH
100 nF
680 nH
10 nF
OUTPUTB
Figure 6 - Output Load as Downconverter to a Differential Amplifier
Supply Current in mA
I2
I1
I0
Typ.
Max.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
90*
120
89
67
56
75
51
68
82
109
78
59
48
43
64
57
Figure 7 - Supply Current
* default setting on SL2101
7
Zarlink Semiconductor Inc.
SL2101
Data Sheet
27 Jul 2001 11:24:54
-99.426 1.6007 pF
CH1
S
1 U FS
DB1 4.7V
1_: 4.3164
11
1 000.000 000 MHz
PRm
Cor
2_: 3.7266
-80.117
1.15 GHz
Z
0
3_: 4.1328
Avg
16
Smo
-70.223
50
1.25 GHz
4_: 4.7617
-58.166
1.4 GHz
1
2
3
4
START 1 000.000 000 MHz
STOP 1 400.000 000 MHz
Figure 8 - Typical RF Input Impedance as Broadband Upconverter (Maximum Power Setting)
RFIN
75 Ω
Figure 9 - RF Input Impedance Matching Network as 50 - 860 MHz Upconverter
8
Zarlink Semiconductor Inc.
SL2101
Data Sheet
27 Jul 2001 09:05:31
-46.965 3.3888 pF
CH1
S
1 U FS
UA6 4.7V
1_: 20.07
11
1 000.000 000 MHz
PRm
Cor
2_: 19.795
-34.527
1.15 GHz
Z
0
3_: 20.666
Avg
16
Smo
-26.233
75
1.25 GHz
4_: 25.772
-15.155
1.4 GHz
4
3
1
2
START 1 000.000 000 MHz
STOP 1 400.000 000 MHz
Figure 10 - Typical RF Input Impedance as Narrow Band Downconverter (maximum power
setting)
RFIN
200 Ω
Figure 11 - RF Input Impedance Matching Network as 1.22 GHz Downconverter
9
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Figure 12 - Two Tone Intermodulation Test Condition Spectrum, Input Referred
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
600
700
800
900
Input frequency (MHz)
Figure 13 - Input NF, Typical (Maximum Power Setting)
10
Zarlink Semiconductor Inc.
SL2101
Data Sheet
11
10
9
8
7
6
Gain
5
4
3
2
1
0
0
100
200
300
400
500
600
700
800
900
Input frequency(in MHz)
Figure 14 - Conversion Gain as Upconverter (Maximum Power Setting)
typ
CSO*
(dBc)
typ
CTB*
(dBc)
typ
IPIP2
(dBµV)
typ
IPIP3
(dBµV)
Typ NF
(dB)
Gain
(dB)
I2
I1
I0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.8
6.0
5.8
6.5
8.7
6.2
5.9
6.4
10.1
9.1
-65
-60
-56
-49
-63
-64
-58
-50
-65
-54
-42
-35
-60
-56
-42
-34
144
141
132
129
146
142
133
126
121
114
108
106
117
113
106
103
7.6
5.4
10.4
10.0
8.3
5.8
Figure 15 - Upconverter Gain, NF and Intermodulation with Recommended Load Versus Power
Setting
* Measured with 128 channels at +7 dBmV.
3x2.75 mm
3x0.5 mm
3x1.5 mm
(centre)
Figure 16 - Upconverter Oscillator Application
11
Zarlink Semiconductor Inc.
SL2101
Data Sheet
-85
-87
-89
-91
-93
-95
PN
0
100
200
300
400
500
600
700
800
900
Figure 17 - Oscillator Typical Phase Noise Performance at 10 kHz Offset
2.5 pF
20
21
Ω
1 k
Varactor
line
BB555
Figure 18 - Downconverter Oscillator Application
Figure 19 - Typical Phase Noise Performance as Downconverter at 10 kHz Offset
12
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Typ NF
(dB)
typ IPIP3
(dBµV)
I2
I1
I0
Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10.3
9.3
8.8
8.7
11.6
9.0
8.3
8.0
15.6
15.1
14.0
12.1
15.4
15.1
13.9
11.9
124
119
112
106
121.3
119.7
112.6
106.3
Figure 20 - Downconverter Gain, NF and IP3 with Recommended (Fig. 4) Load Versus Power
Setting
27 Jul 2001 11:24:54
CH1
S
1 U FS
DB1 4.7V
1_: 4.3164
-99.426
1.6007 pF
11
1 000.000 000 MHz
PRm
Cor
2_: 3.7266
-80.117
1.15 GHz
Z
0
3_: 4.1328
-70.223
Avg
16
Smo
50
1.25 GHz
4_: 4.7617
-58.166
1.4 GHz
1
2
3
STOP 1 400.000 000 MHz
4
START 1 000.000 000 MHz
Figure 21 - Typical IF Output Impedance as Upconverter, Single-Ended
13
Zarlink Semiconductor Inc.
SL2101
Data Sheet
27 Jul 2001 09:48:39
-1.1071 k 7.1882 pF
CH1
S
1 U FS
UA6 4.7V
1_: 1.3588 k
11
20.000 000 MHz
PRm
Cor
2_: 606.87
-695.97
40 MHz
Z
0
3_: 305.72
-549.5
Avg
16
Smo
50
70 MHz
4_: 213.55
-449.58
100 MHz
1
2
3
4
START 10.000 000 MHz
STOP 100.000 000 MHz
Figure 22 - Typical IF Output Impedance as Downconverter, Single-Ended
R4
R3
R2
R1
R0
Ratio
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
Illegal state
5
10
20
40
80
160
320
14
Zarlink Semiconductor Inc.
SL2101
Data Sheet
R4
R3
R2
R1
R0
Ratio
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Illegal state
6
12
24
48
96
192
384
Illegal state
7
14
28
56
112
224
448
Figure 23 - Reference Division Ratios
2
4
Figure 24 - Standard Application
15
Zarlink Semiconductor Inc.
SL2101
Data Sheet
1
XTALCAP
SL2101
DOWNCONVE RTER
47pF
2
47pF
XTAL
1
2
4MHz
XTALCAP
SL2101
UPCONVE RTER
820nH
10pF
10k
XTAL
Figure 25 - Application When Driving Two SL2101 from One Crystal
T2
T1
T0
Test Mode Description
Normal operation
0
0
0
0
0
1
Charge pump sink *
Status byte FL set to logic ‘0’
0
0
1
1
0
1
Charge pump source *
Status byte FL set to logic ‘0’
Charge pump disabled *
Status byte FL set to logic ‘1’
1
1
0
0
0
1
Normal operation and Port P0 = Fpd/2
Charge pump sink *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1
1
1
1
0
1
Charge pump source *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
Charge pump disabled *
Status byte FL set to logic ‘1’
Port P0 = Fcomp
Figure 26 - Test Modes
* clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle
status byte bit FL.
RE
BUFREF output
0
1
disabled, high impedance
enabled
Note:The BUFREF output is only available on the SSOP package
Figure 27 - Buffered Crystal Reference Output Select
16
Zarlink Semiconductor Inc.
SL2101
Data Sheet
MSB
LSB
Address
1
0
1
0
0
0
MA1
210
MA0
29
0
A
A
Byte 1
Byte 2
214
213
212
211
28
Programmable
divider
27
26
25
24
23
22
21
20
Programmable
divider
A
Byte 3
Control data
Control data
1
C1
T1
C0
T0
R4
I2
R3
I1
R2
I0
R1
RE
R0
P0
A
A
Byte 4
Byte 5
T2
Table 1 - Write Data Format (MSB is transmitted first)
MSB
LSB
Address
1
1
0
0
0
0
0
0
MA1
0
MA0
0
1
0
A
Byte 1
Byte 2
Programmable
divider
POR
FL
A
Table 2 - Read Data Format (MSB is transmitted first)
A
:
:
Acknowledge bit
Variable address bits (see Table 3)
MA1,MA0
214-20
I2-I0
C1-C0
R4-R0
T2-T0
RE
:
:
:
:
:
:
:
:
:
Programmable division ratio control bits
lna/mixer power select (see Figure 7)
Charge pump current select (see Figure 29)
Reference division ratio select (see Figure 23)
Test mode control bits (see Figure 26)
Buffered crystal reference output enable (see Figure 27
P0 port output state
P0
POR
FL
Power on reset indicator
Phase lock flag
MA1
MA0
Address input voltage level
0-0.1Vcc
0
0
1
1
0
1
0
1
Open circuit
0.4Vcc – 0.6 Vcc #
0.9 Vcc - Vcc
Table 3 - Address Selection
Figure 28 - Read/Write Data Formats
17
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Current in mA
Typ.
C1
C0
Min.
Max.
0
0
1
1
0
1
0
1
+-98
+-210
+-450
+-975
+-130
+-280
+-600
+-1300
+-162
+-350
+-750
+-1625
Figure 29 - Charge Pump Current
Electrical Characteristics - Test conditions (unless otherwise stated). Tamb = -40o to 85oC, Vee= 0V, Vcc=5 V+-5%. These
characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage at
maximum power setting unless otherwise stated.
Characteristic
Supply current
Pin
Min.
Typ.
Max.
Units
Conditions
6,
12,17,
19, 22
90
120
mA
IF outputs will be connected to
Vcc through the differential load
as in Figures 4, 5 & 6.
See Figure 7 for programmable
settings.
Input frequency range
Output frequency range
9, 10
14, 15
9, 10
50
30
1400
1400
MHz
MHz
Operating condition only.
Operating condition only.
Operating condition only.
Composite peak input
signal
97
dBµV
All synthesizer related
spurs on IF Output
14, 15
-60
dBc
Within channel bandwidth of
8 MHz and with input power of
60 dBµV.
Upconverter
application
Input frequency range
Input impedance
Input return loss
9, 10
50
6
860
9.5
MHz
Ω
75
See Figure 8.
dB
With input matching network as in
Figure 9.
°
Input Noise Figure
dB
dB
Tamb=27 C, see Figure 13, with
input matching network as in
Figure 9.
See Figure 15 for programmable
settings.
Conversion gain
9
Differential voltage gain to 200 Ω
load on output of SAWF as in
Figure 4, see Figure 14.
See Figure 15 for programmable
settings.
18
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Characteristic
Pin
Min.
Typ.
Max.
Units
Conditions
50-860 MHz
Gain variation across
operation range
-1
+1
dB
Gain variation within
channel
0.5
-20
dB
Channel bandwidth 8 MHz within
operating frequency range.
Through gain
CSO
dB
45-1400 MHz
-65
-68
dBc
Measured with 128 channels at 62
dBµV. See Figure 15 for
programmable settings.
CTB
dBc
Measured with 128 channels at 62
dBµV. See Figure 15 for
programmable settings.
IPIP22T
IPIP32T
141
117
dBuV
dBuV
See Note 2.
See Figure 15 for programmable
settings.
See Note 2.
See Figure 15 for programmable
settings.
IPIM22T
-47
-46
2.3
dBc
dBc
GHz
See Note 2. See Figure 12.
See Note 2. See Figure 12.
IPIM32T
LO operating range
1
1
Maximum tuning range 0.9 GHz
determined by application.
LO phase noise, SSB
@ 10 kHz offset
Application as in Figure 16. See
Figure 17.
-86
-106
dBc/Hz
dBc/Hz
@ 100 kHz offset
LO phase noise floor
-136
1.4
dBc/Hz Application as in Figure 16.
GHz
IF output frequency
range
14, 15
9, 10
IF output impedance
See Figure 21.
Downconverter
application
Input frequency range
Input impedance
Input return loss
1000
12
1400
14
MHz
75
Ω
See Figure 10.
dB
With input matching network as in
Figure 11.
°
Input Noise Figure
dB
Tamb=27 C, with input matching
network as in Figure 11. See
Figure 20 for programmable
settings.
19
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Characteristic
Pin
Min.
Typ.
Max.
Units
Conditions
Conversion gain
12
dB
Differential voltage gain to 50 Ω
load on output of impedance
transformer as in Figure 6. See
Figure 20 for programmable
settings.
Gain variation within
channel
0.5
-20
dB
Channel bandwidth 8 MHz within
operating frequency range.
Through gain
IPIP32T
dB
dBµV
dBc
45-1400 MHz
117
1
See Note 2.
IPIM32T
-46
2.3
See Note 2. See Figure 12.
LO operating range
GHz
Maximum tuning range
determined by application, see
Note 4.
LO phase noise, SSB
@ 10 kHz offset
Application as in Figure 18. See
Figure 19.
-92
-112
dBc/Hz
dBc/Hz
@ 100 kHz offset
LO phase noise floor
-136
100
dBc/Hz Application as in Figure 18.
MHz
IF output frequency
range
14, 15
3, 4
IF output impedance
Synthesizer
See Figure 22.
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
Hysterysis
3
0
5.5
1.5
10
V
I2C ‘Fast mode’ compliant
V
µA
µA
µA
Input voltage = Vcc
Input voltage = Vee
Vcc=Vee
-10
10
0.4
+-3
SDA output voltage
3
0.4
0.6
V
V
Isink = 3 mA
Isink = 6 mA
SCL clock rate
4
400
kHz
Charge pump output
current
28
See Figure 29.
Vpin = 2 V
Charge pump output
leakage
28
+-10
nA
Vpin = 2 V
20
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Characteristic
Pin
Min.
Typ.
Max.
Units
Conditions
Vpin = 0.7 V
Charge pump drive
output current
27
0.5
mA
Crystal frequency
1,2
2
10
2
20
200
20
MHz
Ω
See Figure24 and Figure 25 for
application.
Recommended crystal
series resistance
4 MHz parallel resonant crystal
External reference input
frequency
2
2
MHz
Vpp
MHz
Sinewave coupled through 10 nF
blocking capacitor
External reference drive
level
0.2
0.5
4
Compatible with BUFREF output.
(SSOP package only)
Phase detector
comparison frequency
Equivalent phase noise
at phase detector
SSB, within loop bandwidth
-148
-152
-158
dBc/Hz
Fcomp = 1 MHz
dBc/Hz Fcomp = 250 kHz
dBc/Hz Fcomp = 62.5 kHz
Local oscillator
240
2
32767
programmable divider
division ratio
Reference division ratio
See Figure 23.
See Note 3.
Output port
26
5
sink current
Vport = 0.7 V
Vport =Vcc
mA
µA
leakage current
10
BUFREF output
output amplitude
AC coupled. Note 5.
Enabled by bit RE=1 and default
state on power-up. BUFREF
output only available on SSOP
package
0.35
250
Vpp
output impedance
Ω
Address select
See Figure 28, Table 3
Vin=Vcc
Input high current
Input low current
1
-0.5
mA
mA
Vin=Vee
Note 1: All power levels are referred to 75 Ω and 0 dBm = 109 dBµV
Note 2: Any two tones within RF operating range at 94 dBµV beating within band, with output load as in Figure 4
Note 3: Port powers up in high impedance state
Note 4: To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in Figure
18 has a tuning range of 200 MHz.
Note 5: If the BUFREF output is not used it should be left open circuit or connected to Vccd and disabled by setting RE = '0'.
21
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Absolute Maximum Ratings - All voltages are referred to Vee at 0 V (pins 7, 8, 11, 13, 16, 18, 23, 25).
Characteristic
Supply voltage, Vcc
Pin
Min.
Max.
Units
Conditions
6, 12,
17, 19,
22
-0.3
6
V
RF input voltage
9, 10
117
dBuV
Differential, AC coupled
inputs
All I/O port DC offsets
SDA, SCL DC offsets
Storage temperature
Junction temperature
-0.3
-0.3
-55
Vcc+0.3
6
V
V
3, 4
Vcc = Vee to 5.25 V
Power applied.
°
150
125
20
C
°
C
°
Package thermal resistance, chip
to case (SSOP)
C/W
°
Package thermal resistance, chip
to ambient (SSOP)
85
C/W
Power consumption at 5.25 V
ESD protection (pins 3-28)
630
mW
kV
Maximum power setting.
1
Mil-std 883B method 3015
cat1
ESD protections (pins 1, 2)
0.75
kV
22
Zarlink Semiconductor Inc.
SL2101
Data Sheet
RF inputs
Oscillator inputs
IF outputs
Figure 30 - Input and Output Interface Circuits (RF section)
23
Zarlink Semiconductor Inc.
SL2101
Data Sheet
V
ccd
1
200µA
Reference oscillator
Loop amplifier
V
ccd
120K
*
* On SDA only
SDA/SCL (pins 3 and 4)
ADD input
V
ccd
P0
1mA
Output port
BUFREF output
Figure 31 - Input and Output Interface Circuits (PLL section)
24
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明