SP5511/NA/DP [MICROSEMI]
PLL/Frequency Synthesis Circuit, BIPolar, PDIP18;
| 型号： | SP5511/NA/DP |
| 厂家： | 
Microsemi |
| 描述： | PLL/Frequency Synthesis Circuit, BIPolar, PDIP18 光电二极管 |
| 文件： | 总12页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5511
Bidirectional I2C Bus 4-Address Synthesiser
DS3090 - 4.0 January 1997
TheSP5511isasingle-chipfrequencysynthesiserdesigned
for TV tuning systems. Control data is entered in the standard
I2C BUS format. In 18-lead plastic DIL package, the SP5511
hasthreeaddressablecurrent-limitedoutputports(P0-P3)and
four bi-directional output ports (P0-P2) and four addressable
bi-directional open-collector ports (P4-P7) of which P6 is also
a 3-bit 5-level ADC input. The information on these ports can
be read via the I2C BUS. The SP5511S is a variant in a 16-lead
miniature plastic package, without P0-P2 but functionally
identical in other respects to the SP5511.
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
The device has four programmable I2C BUS addresses,
allowing two or more synthesisers to be used in a system.
SP5511
SCL
V
CC
†
*
I/O PORT P7
I/O PORT P6
I/O PORT P5
I/O PORT P4
P0 OUTPUT PORT
P1 OUTPUT PORT
P2 OUTPUT PORT
P3 ADD SELECT PORT
FEATURES
■ Complete 1·3GHz Single Chip System
■ Programmable via the I2C BUS
■ Low Power Consumption (240mW Typ.)
†
†
DP18
■
Low Radiation
■ Phase Lock Detector
■ Varactor Drive Amp Disable
1
16
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
■ 7 Controllable Outputs, 4 Bi-directional (SP5511)
■ 4 Bi-directional Controllable Outputs (SP5511S)
■ 5-Level ADC
SP5511S
SCL
V
CC
NC
P3 ADD SELECT PORT
I/O PORT P4
†
*
†
I/O PORT P7
I/O PORT P6
I/O PORT P5
■ Variable I2C BUS Address for Picture in Picture TV
■ ESD Protection *
8
9
†
MP16
† = Logic level I/O port
= 3-bit ADC input
* Normal ESD handling precautions should be observed.
*
APPLICATIONS
Fig. 1 Pin connections – top view
■ Cable Tuning Systems
■ VCRs
ORDERING INFORMATION
SP5511 NA DP (18-lead plastic package)
SP5511S NA MP (16-lead miniature plastic package)
SP5511
ELECTRICAL CHARACTERISTICS
TAMB = 210°C to 180°C, VCC = 14·5V to 15·5V. All pin references are to the SP5511 (DP18 package).
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Value
Characteristic
Pin
Units
Conditions
Typ.
Min.
Max.
Supply current
14
48
60
mA
V
CC = 5V
Prescaler input voltage
15,16
12·5
30
300 mVrms 80MHz to 1GHz
300 mVrms 1·3GHz, see Fig. 5
Prescaler input impedance
Prescaler input capacitance
15,16
50
2
Ω
pF
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
4,5
4,5
4,5
4,5
4,5
3
0
5·5
1·5
10
210
10
V
V
µA
µA
µA
Input voltage = VCC
Input voltage = 0V
When VCC = 0V
SDA
Output voltage
4
0·4
V
Sink current = 3mA
Charge pump current low
Charge pump current high
1
1
1
650
6170
µA
µA
nA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 18 = 0·7V
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
65
18
500
10
6400
40
200
Ω
mV p-p
Ω
Parallel resonant crystal (note 2)
Crystal oscillator negative resistance
2
750
Output Ports
mA
µA
mA
µA
P0-P2 sink current (see note 1)
P0-P2 leakage current (see note 1)
P4-P7 sink current
11-13
11-13
6-9
0·7
10
1
1·5
10
V
V
V
V
OUT = 12V
OUT = 13·2V
OUT = 0·7V
OUT = 13·2V
P4-P7 leakage current
6-9
10
Input Ports
mA
mA
V
V
µA
µA
P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low
10
10
6,8,9
6,8,9
7
1
20·5
0·8
V pin 10 = 13·2V
V pin 10 = 0V
2·7
110
210
See Table 3 for ADC levels
7
NOTES
1. Ports P0-P2 not present on the SP5511S
2. The maximum resistance quoted refers to all conditions, including start-up.
2
SP5511
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE and pin 3 at 0V
Value
Pin
Units
Parameter
Conditions
SP5511 SP5511S
Min.
Max.
Supply voltage
RF input voltage
Port voltage
14
12
20·3
7
V
15,16
2·5
V p-p
13,14
6-9,11-13
6-9
11-13
10
6-9
6-9
-
20·3
20·3
20·3
20·3
14
6
14
V
V
V
V
Port in off state
Port in on state
Port in on state
10
V
CC10·3
6-9,11-13
50
mA
V
Total port output current
RF input DC offset
6-9
13-14
1
15-16
1
20·3
20·3
20·3
20·3
V
V
V
V
V
CC10·3
CC10·3
CC10·3
CC10·3
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
V
18
V
16
2
2
V
4,5
4,5
20·3
20·3
CC10·3
5·5
V
V
With VCC applied
V
CC not applied
Storage temperature
Junction temperature
255
1150
1150
°C
°C
DP18 thermal resistance, chip-to-ambient
DP18 thermal resistance, chip-to-case
78
24
°C/W
°C/W
MP16 thermal resistance, chip-to-ambient
MP16 thermal resistance, chip-to-case
111
41
°C/W
°C/W
363
mW
Power consumption at 5·5V
V
CC
RF IN
15 BIT
PROGRAMMABLE
DIVIDER
F
DIV
F
COMP
PHASE
Q1
Q2
PRE
AMP
48
DIVIDER
4512
OSC
4MHz
CRYSTAL
COMP
PRESCALER
F
RF IN
POWER ON
DETECTOR
LOCK
DETECTOR
CHARGE
PUMP
15 BIT DIVIDER
RATIO LATCH
CHARGE
PUMP
DRIVE
OUTPUT
SCL
SDA
2
I C BUS
T0 CP
TRANSCEIVER
8-BIT LATCH
CONTROL
OS
LOGIC
PORT
DATA
INFORMATION
LATCH
3 TTL
LEVEL
COMP
T1
ADDRESS
SELECT
3-BIT
ADC
V
EE
P3
P0 P1 P2
P4 P5 P6 P7
Fig. 2 Block diagram. (Ports P0-P2 not present on SP5511S)
3
SP5511
FUNCTIONAL DESCRIPTION
The SP5511 is programmed from an I2C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I2C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I2C BUS
system. Table 4 shows how the address is selected by
applying a voltage to P3. The address input circuit is shown
in Fig.6.The LSB of the address Byte (R/W) sets the device
into read mode if it is high and write mode if it is low. When
the SP5511 receives a correct address Byte it pulls the SDA
line low during the acknowledge period and during following
acknowledgeperiodsafterfurtherdataBytesareprogrammed.
When the SP5511 is programmed into the read mode the
controlling device accepting the data must pull down the SDA
line during the following acknowledge period to read another
status Byte.
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 6170µA and
a logic 0 for 650µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a logic
1 connects FCOMP to P6 and FDIV to P7.
Byte5programstheoutputportsP0-P7, alogic0forahigh
impedance output, logic 1 for low impedance (on).
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 213 select the
synthesised frequency while Bytes 415 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to re-
address the device until an I2C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
READ MODE
When the device is in the read mode the status data read
from the device on the SDA line takes the form shown in Table
2.
Bit 1 (POR) is the power on reset indicator and is set to a
logic 1 if the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when
the device is initially turned on). The POR is set to 0 when the
readsequenceisterminatedbyastopcommand. Theoutputs
are all set to high impedance when the device is initially
powered up. Bit 2 (FL) indicates whether the device is phase
locked, a logic 1 is present if the device is locked and a logic
0 if the device is unlocked.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in
Figs. 7 and 8.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5 and P4 respectively. A logic 0 indicates a low level and
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic1).
These inputs will then respond to data complying with stand-
ard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to
give the output of the 5-level ADC.
The 5-level ADC can be used to feed AFC information to
the microprocessor from the IF section of the television, as
illustrated in Fig. 4.
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency FCOMP
.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
4
SP5511
MSB
LSB
0
Address
1
1
0
0
0
MA1 MA0
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
0
214 213 212 211 210
29
21
1
28
20
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
26
25
24
23
22
27
1
CP T1 T0
1
1
OS
P7 P6 P5 P4 P3 P2* P1* P0*
Table 1 Write data format (MSB transmitted first)
Address
1
1
0
0
0
MA1 MA0
A2 A1
1
A
A
Byte 1
Byte 2
Status byte
FL
I2
I1
I0
POR
A0
Table 2 Read data format
A2 A1 A0
Voltage input to P6
1
0
0
0
0
0
1
1
0
0
MA1 MA0
0
1
0
1
0
0·6VCC to 13·2V
0·45VCC to 0·6VCC
0·3VCC to 0·45VCC
0·15VCC to 0·3VCC
0V to 0·15VCC
Voltage input to P3
0V to 0·1VCC
0
0
1
1
0
1
0
1
Open circuit
0·4VCC to 0·6VCC
†
0·9VCC to VCC
Table 4 Address selection
Table 3 ADC levels
A
:
Acknowledge bit
MA1, MA0
CP
T1
T0
:
:
:
:
:
:
Variable address bits (see Table 4)
Charge Pump current select
Test mode selection
Charge pump disable
Varactor drive Output disable Switch
Control output port states
OS
P7, P6, P5, P4,
P3, P2*, P1*, P0*
POR
FL
I2, I1, I0
:
:
:
:
Power On Reset indicator
Phase lock detect flag
Digital information from ports P7, P5 and P4 respectively
5-level ADC data from P6 (see Table 3)
A2, A1, A0
NOTE
† Programmed by connecting a 15kΩ resistor between pin 10 and VCC
Don’t care condition on SP5511S.
*
Fig. 3 Data formats
5
SP5511
APPLICATION
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6.
130V
112V
15V
22k
39n
22k
180n
0·1µ
10k
47k
10n
V
T
VARACTOR DRIVE
2N3904
18
17
16
15
1
2
3
4
15V
18p
1n
1n
4MHz
SDA
SCL
OSCILLATOR OUTPUT
TUNER
CONTROL
MICRO
2
I C BUS
SP5511 14
22k
22k
22k
5
6
7
8
9
P0
P7
P6
P5
P4
13
12
11
10
P1
P2
2N3906
BAND INPUTS
2N3906
2N3906
112V
P3
AFC OUT
IF SECTION
IF SIGNAL
Fig. 4 Typical application
300
37·5
25
OPERATING
WINDOW
12·5
80
500
1000
1300
1500
FREQUENCY (MHz)
Fig. 5 Typical input sensitivity
6
SP5511
V
CC
V
REF
CHARGE
PUMP
550
550
RF INPUTS
170
DRIVE
OUTPUT
Loop amplifier
RF input
V
V
CC
CC
30k
10k
3k
P3
SCL/SDA
ACK
*
*
ON SDA ONLY
Address programming port
SCL and SDA inputs
NOT ON
P0-P2
PORT
12k*
CRYSTAL Q1
*
NO RESISTOR
ON P4-P7
CRYSTAL Q2
Reference oscillator
Ports P0-P2 and P4-P7 (SP5511).
P4- P7 only on SP5511S
Fig. 6 SP5511 input/output interface circuits
7
SP5511
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
1·25GHz
2j5
2j0.2
2j2
S11:ZO = 50Ω
2j0.5
NORMALISED TO 50Ω
FREQUENCY MARKER STEP = 250MHz
2j1
Fig. 7 Typical input impedance, SP5511
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
2j5
2j0.2
1·25GHz
2j2
S11:ZO = 50Ω
2j0.5
NORMALISED TO 50Ω
FREQUENCY MARKER STEP = 250MHz
2j1
Fig. 8 Typical input impedance, SP5511S
8
SP5511
PACKAGE DETAILS
Dimensions are shown thus: mm (in).
1
PIN 1 REF
NOTCH
7·62 (0·3)
NOM CTRS
7·11 (0·28)
MAX
18
1·14/1·65
(0·045/0·107)
0·23/0·41
(0·009/0·016)
25·40 (1·000)
MAX
0·51 (0·02) 3·05 (0·120)
MIN
MIN
5·08/(0·20)
MAX
This package outline diagram is for
guidance only. Please contact your
GPS Customer Service Centre for
further information.
0·38/0·61
(0·015/0·24)
18 LEADS AT 2·54 (0·10)
NOM. SPACING
18-LEAD PLASTIC DIL – DP18
9·80/10·01
(0·386/0·394)
0·19/0·25
(0·007/0·010)
16
0·37
(0·015)
345°
SPOT REF.
5·80/6·20
(0·228/0·244)
3·80/4·00
(0·150/0·157)
CHAMFER
REF.
PIN 1
0-8°
0·35/0·49
(0·014/0·019)
0·41/1·27
(0·016/0·050)
0·69 (0·027)
MAX
0·10/0·25
(0·004/0·010) (0·053/0·069)
1·35/1·75
This package outline diagram is for
guidance only. Please contact your
GPS Customer Service Centre for
further information.
16 LEADS AT
1·27 (0·050)
NOM SPACING
16-LEAD MINIATURE PLASTIC DIL - MP16
9
SP5511
NOTES
10
SP5511
NOTES
11
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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