SP8782/B/MP2Q [MICROSEMI]
Prescaler, PDSO8;
| 型号： | SP8782/B/MP2Q |
| 厂家： | 
Microsemi |
| 描述： | Prescaler, PDSO8 光电二极管 逻辑集成电路 |
| 文件： | 总5页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP8782A & B
1GHz 16/17, 32/33 Multi-Modulus Divider
April 2008
Features
Ordering Information
•
Advanced Resynchronisation techniques to negate
loop delay effects
SP8782/B/MP2Q
8 Pin SOP/SOIC**
Tape & Reel
•
•
•
CMOS compatible output capability
Multi-Modulus division
Available as DESC SMD 5962-9208901MPA
**Pb Free Tin/Silver/Copper
Description
Absolute Maximum Ratings
Supply Voltage
6V
Clock input level
2.5V p-p
+175 C
The SP8782 is a multi-modulus divider which divides by 16/
17 when the Ratio Select input is low and by 32/33 when
theRatio Select input is high. When high, the modulus Control
input selects the lower division ratio (16 or 32) and the higher
ratio (17 or 33) when it is low.
Junction temperature
Storage temperature range:
SP8782A
-55 C to +150 C
-55 C to +125 C
SP8782B
The device uses resynchronisation techniques to reduce the
effects of propagation delays in frequency synthesis.
The SP8782A (ceramic DIL package) is characterised over
the full military temperature range of -55 C to +125 C, the
SP8782B (miniature plastic DIL package) over the industrial
range of -40 C to+85 C.
RATIO
SELECT
VCC
2
1
2
CLOCK INPUT
7
16/17
32/33
OUTPUT
3
CLOCK INPUT
4
5
VEE
MODULUS
CONTROL
INPUT
Figure 1 Functional Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2008, Zarlink Semiconductor Inc. All Rights Reserved.
SP8782A & B
1
2
3
4
8
7
6
5
VCC
RATIO SELECT
CLOCK INPUT
CLOCK INPUT
VEE
OUTPUT
NC
MODULUS CONTROL
DG 8
VCC
8
7
6
5
1
2
3
4
RATIO SELECT
OUTPUT
NC
CLOCK INPUT
CLOCK INPUT
VEE
MODULUS CONTROL
MP 8
Figure 2 Typical Pin Connections
Electrical Characteristics
Unless otherwise stated, the Electrical Characteristics are guaranteed over the specified supply, frequency and
temperature range.
Supply Voltage, VCC = +4V to +5.5V, VEE = 0V
Temperature T
= -55°C to +125°C, (SP8782A), -40°C to +85° C (SP8782B)
amb
Characteristic
Pin
Value
Conditions
Min
Max Units
Maximum frequency
(sinewave input)
2, 3
1
GHz
Input = 200-1200mVp-p
Input = 400-1200mVp-p
Minimum frequency
2, 3
2, 3
8
50
100
60
MHz
V/µs
mA
V
Min Slew rate for low frequency operation
Power Supply current, ICC
Output low voltage
Output unloaded, VCC=5.5V
7
0
VCC-1.4
0.7VCC
0
1.7
Output high voltage
7
VCC
VCC
0.3VCC
1.2
V
Modulus control input high voltage
Modulus control input low voltage
Modulus control input high current
Modulus control input low current
Ratio select input high voltage
Ratio selected input low voltage
Ratio select input current
Clock to output propagation Delay
Set-up time, ts
5
V
At driver end of 3kΩ resistor
At driver end of 3kΩ resistor
Via 3kΩ resistor to VCC
5
V
5
0.6
mA
mA
V
5
-0.6
0.6VCC
0
-1.2
VCC
0.4VCC
10
Via 3kΩ resistor to VCC
1
1
V
1
-10
µA
ns
ns
ns
2,3,7
5,7
5,7
3
3
3
See note 1 and Fig. 3a
See note 2 and Fig. 3b
Release time,tr
Notes: 1. The set-up time ts is defined as the minimum time that can elapse between L→H transition of the
modulus control input and the next L→H output transition to ensure that the ÷ 16 (32) mode is obtained.
2. The release time tr is defined as the minimum time that can elapse between H→L transition of the modulus
control input and the next L→H output transition to ensure that the ÷ 17 (33) mode is obtained.
2
SP8782A & B
Modulus control
input
Ratio select input
0
1
0
1
÷17
÷16
÷33
÷32
Table 1 Truth table for control inputs
CLOCK INPUT
t
s
t
s
MODULUS
CONTROL INPUT
DON’T CARE
DON’T CARE
9 (17)
8 (16)
OUTPUT
8 (16)
8 (16)
DIVIDE-BY-16 (32) MODE
ESTABLISHED
e
Figure 3a Setting divide - by - 16 (32 mode)
CLOCK INPUT
t
r
t
r
MODULUS
CONTROL INPUT
DON’T CARE
DON’T CARE
8 (16)
9 (17)
8 (16)
OUTPUT
8 (16)
EXTRA
PULSE
DIVIDE-BY-17 (33) MODE
ESTABLISHED
Figure 3b Setting divide - by - 17 (33 mode)
Figure 3 Timing diagrams
3
SP8782A & B
1600
1400
1200
1000
800
600
400
200
0
* Tested as specified
in table of Electrical
GUARANTEED
OPERATING
WINDOW
*
Characteristics
0
200
400
600
800
1000
INPUT FREQUENCY (MHz)
Figure 4 Typical input characteristics
RATIO SELECT
1
V
CC
6
8
10n
3k
5
2
MODULUS
CONTROL
INPUT
7
OUTPUT
1n
CLOCK
INPUT
DIVIDE BY
16/17 OR32/33
NOTES
1n
4 V
EE
3
1.
Pin 6 is grounded to improve
isolation between the output and
the modulus control input
2.
The 3kΩ resistor on pin 5 reduces
the amplitude of the modulus control
signal to minimise radiation
Figure 5 Typical application showing interfacing
4
SP8782A & B
j
1
j
0.5
j
2
j
0.2
1100
j
5
0.5
1000
5
0.2
1
2
0
2
j5
200
800
2j0.2
400
600
2
j2
2j0.5
2j1
Figure 6 Typical input impedance. Test conditions: supply voltage =5V, ambient temperature =25°C,
frequencies in MHz, impedances normalised to 50Ω
5
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