UF1660GD [MICROSEMI]
16.0 Ampere Insulated Dual Series Connection Ultra Fast Recovery Rectifiers;
| 型号： | UF1660GD |
| 厂家： | 
Microsemi |
| 描述： | 16.0 Ampere Insulated Dual Series Connection Ultra Fast Recovery Rectifiers |
| 文件： | 总13页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W7NCF-H-M1 Series
White Electronic Designs
Medical Series CompactFlash® Card
FEATURES
Storage Capacities:
•
128MB, 256MB, 512MB,1GB, 2GB, 4GB and
8GB
Environment conditions:
•
Operating temperature: -40°C to 85°C
•
Storage temperature: -55°C to 125°C
CompactFlash® Compatibility
•
•
•
CFA standard 2.1 compliant
3.3V or 5.0V single power supply
50 pin connector with Type-I form factor (3.3mm
thickness)
Dimensions:
•
Type I card : 36.4mm(L) x 42.8mm(W) x
3.3mm(H)
•
256 Bytes of attribute memory
Power consumption
Highly resistant to data corruption due to power loss
or card removal
•
5V operation
Active mode:
DESCRIPTION
Write operation: 28 mA (Typ.), 30 mA (Max.)
Read operation: 23 mA (Typ.), 30 mA (Max.)
Sleep mode: 2.0mA (max.)
3.3V operation
The W7NCF-H-M1 series CompactFlash® family is
designed for high reliability and robust operation. This
product not only offers a strictly controlled and locked bill
of materials but also the robust operation which is desired
in many medical applications. The product’s reliability
backbone is established by using a 32 bit RISC based
controller along with the best SLC (single level cell) NAND
flash memory devices. Utilizing proprietary techniques, our
card offers both firmware and hardware features which
mitigate problems relating to power disturbances and
interruptions. Implemented is the industry leading ECC
protection which is capable of correcting 6 bytes in every
512 byte sector. This leading ECC protection combined
with patented static wear leveling technology provides the
highest read/write endurance possible.
•
Active mode:
Write operation: 28 mA (Typ.), 30 mA (Max.)
Read operation: 23 mA (Typ.), 30 mA (Max.)
Sleep mode: 2.0mA (max.
RoHS compliant
Interface modes
•
•
•
PC card memory mode
PC card I/O mode
True IDE mode
Less than 1 Error in 1014 bits read
CompactFlash® is a trademark of SanDisk Corporation and is licensed royalty-free to the
CFA, which in turn will license it royalty-free to CFA members.
CFA: CompactFlash® Association.
MTBF > 4,000,000 hours
High shock & vibration tolerance
W/E Endurance: 4,000,000 write/erase cycles
High performance
•
Interface Transfer speed in PIO mode 4 or Multi
Word DMA mode 2 cycle timing; up to 16.7
MB/second (PIO mode 3 & 4 are available in
IDE mode only).
sector
•
•
•
Typical write: 5.0 MBytes/s in ATA PIO mode 4
Typical read: 7.0 MBytes/s in ATA PIO mode 4
On card ECC up to 6 Bytes per 512 Byte data
March 2007
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
ENVIRONMENTAL CHARACTERIZATION
Item
Performance
Temperature Cycle
Humidity
JEDEC - JESD STD A104 Temp condition N (-40°C to 85 °C) and soak mode 3; 200 cycles
MIL-STD 810F, Method 507.4, Paragraph 4.5.2 - 10 day test per figure 507.4-1, 10 day test
MIL-STD 810F, Method 514.5, procedure 1, category 24, 1 hour per axis
Vibration
MIL-STD 810F, Method 516.5, procedure1, non-operational, 40g, SRS functional shock for ground equipment, three (3)
shock per axis (positive or negative).
Shock
JEDEC- JESD22-B, 104-A, test condition B,1500 g pulse, 0.5 msec
Altitude
MIL-STD 810F, Method 500.4, procedure II, modified to 80,000 ft and non operation 1 hr test duration at altitude
PRODUCT RELIABILITY
Item
Value
MTBF (@ 25°C)
Data reliability
Endurance
> 4,000,000 Hours
< 1 Non-Recoverable Error in 1014 Bits Read
> 4,000,000 write/erase cycles
PRODUCT PERFORMANCE
Item
Performance (PIO mode 4 true IDE)
Read Transfer Rate (Typical)
Write Transfer Rate (Typical)
Burst Transfer Rate
7MB/s
5MB/s
up to 16.7MB/s
Controller Overhead
(Command to DRQ)
1ms typical, 5ms (max)
March 2007
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
DC ELECTRICAL CHARACTERISTICS
Symbol
VIL
Parameter
Min
-0.3
2.0
Max
+0.8
Units
Notes
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Operating Current, VCC_R=5.0V
Sleep Mode
V
V
V
V
VIH
VCC+0.3
0.45
VOL
at 4mA
at 4mA
VOH
ICC
2.4
0.2
30
mA
mA
Operating, 20 MHz
Operating Current, VCC_R=3.3V
Sleep Mode
ICC
0.2
30
mA
mA
μA
μA
Operating, 20 MHz
Input Leakage Current
Output Leakage Current
ILI
±10
±10
ILO
Attribute Memory Read and Write AC Characteristics
VCC = 5V ± 0.5V, 3.3 V ±0.3V
Symbol
tcR
Parameter
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
250
ta(A)
Address Access Time
250
250
125
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Card Enable Access Time
Output Enable Access Time
Output Disable time from CE
Output Disable time from OE
Output Enable time from CE
Output Enable time from OE
Data valid time from address change
Address Setup Time
5
5
0
tsu(A)
th(A)
30
20
2
Address Hold Time
tsu(CE)
th(CE)
tcW
Card Enable Setup Time
Card Enable Hold Time
Write Cycle Time
20
250
tw(WE)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
Write Pulse TIme
150
180
180
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time for WE
Card Enable setup time for WE
Data setup time for WE
Data hold time
30
tdis(WE)
Output disable time from WE
Output enable time from WE
Output Enable setup time for WE
Output Enable hold time from WE
ten(WE)
5
100
tsu(OE-WE)
th(OE-WE)
10
10
March 2007
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
Common Memory Read and Write AC Charateristics
Symbol
tcR
Parameter
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
150
ta(A)
Address Access Time
150
150
75
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Card Enable Access Time
Output Enable Access Time
Output Disable time from CE
Output Disable time from OE
Output Enable time from CE
Output Enable time from OE
Data valid time from address change
Address Setup Time
75
75
5
5
0
tsu(A)
th(A)
20
20
0
Address Hold Time
tsu(CE)
th(CE)
tcW
Card Enable Setup Time
Card Enable Hold Time
Write Cycle Time
20
150
tw(WE)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
Write Pulse TIme
80
100
100
50
ns
ns
ns
ns
ns
Address setup time for WE
Card Enable setup time for WE
Data setup time for WE
Data hold time
20
trec(WE)
20
tdis(WE)
Output disable time from WE
Output enable time from WE
Output Enable setup time for WE
Output Enable hold time from WE
ns
ns
ns
ns
ten(WE)
5
75
tsu(OE-WE)
th(OE-WE)
10
10
March 2007
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
I/O Access Read and Write AC Characteristic
Symbol
td(IORD)
Parameter
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay after IORD
100
th(IORD)
Data Hold following IORD
IORD pulse width
0
165
70
20
5
tw(IORD)
tsuA(IORD)
thA(IORD)
Address setup time for IORD
Address hold time for IORD
Card Enable setup time for IORD
Card Enable hold time from IORD
REG setup time for IORD
REG Hold time from IORD
INPACK delay falling from IORD
INPACK delay rising from IORD
IOIS16 delay falling from address
IOIS16 delay rising from address
Data setup time for IOWR
Data hold time from IOWR
IOWR pulse width
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdflNP(IORD)
tdrlNP(IORD)
tdflO16(IORD)
tdrlO16(IORD)
tsu(IOWR)
20
5
0
0
45
45
35
35
60
30
th(IOWR)
tw(IOWR)
165
70
tsuA(IOWR)
Address setup time for IOWR
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
Address hold time from IOWR
Card Enable setup time fro IOWR
Card Enable hold time from IOWR
20
5
ns
ns
ns
ns
ns
20
5
tsuREG(IOWR) REG setup time for IOWR
thREG(IOWR)
REG hold tme from IOWR
0
True-IDE Mode I/O Access Read and Write AC Characteristics
Symbol
tcR
Parameter
Min
120
25
10
70
25
20
5
Max
Units
ns
Cycle time
tsuA
Address setup time for IORD/IOWR
Address hold time from IORD/IOWR
IORD/IORW pulse width
IORD/IORW recovery time
Data setup time for IORD
Data hold time for IORD
Output disable time from IORD
ns
thA
ns
tw
ns
trec
ns
tsuD(IORD)
thD(IORD)
tdis(IORD)
ns
ns
30
ns
tsuD(IOWR)
thD(IOWR)
Data setup time for IOWR
Data hold following IOWR
20
10
ns
ns
March 2007
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
Pin Assignments & Pin Type
PC Card Memory Mode
Pin Number Signal Name Pin Type In, Out Type
PC Card I/O Mode
True IDE Mode
Pin Number Signal Name Pin Type In, Out Type
Pin Number Signal Name Pin Type In, Out Type
1
2
3
4
5
6
7
8
GND
D03
D04
D05
D06
D07
-CE1
A10
-OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
WP
-CD2
-CD1
D111
D121
D131
D141
D151
-CE21
-VS1
-IORD
-IOWR
-WE
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
IZ1
IU3
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
OT3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
Ground
I3U
I3U
I3U
OT1
Power
I2Z
OPEN
I2Z
OT1
OT1
I3U
OT1
OT1
1
2
3
4
5
6
7
8
GND
D03
D04
D05
D06
D07
-CE1
A10
-OE
A09
A08
A07
VCC
A06
A05
A04
A03
A02
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
IZ1
IU3
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
OT3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
Ground
I3U
I3U
I3U
OT1
Power
I2Z
OPEN
I2Z
OT1
OT1
I3U
OT1
OT1
1
2
3
4
5
6
7
8
GND
D03
D04
D05
D06
D07
-CS0
A102
-ATA SEL
A092
A082
A072
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3U
IZ1
IU3
I1Z
I1Z
I1Z
Power
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
ON3
Ground
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
I3Z
Ground
I3Z
I3Z
I3U
OZ1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
9
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
I
I
I
I
I
I
I
I
I
I
A062
I
I
I
I
I
A052
A042
A032
A02
A01
A00
D00
D01
D02
I
I
A01
A00
D00
D01
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
D02
-IOIS16
-CD2
-CD1
D111
D121
D131
D141
D151
-CE21
-VS1
-IORD
-IOWR
-WE
-IOIS16
-CD2
-CD1
D111
D121
D131
D141
D151
-CS11
-VS1
-IORD
-IOWR
-WE3
IREQ
VCC
RDY
VCC
IREQ
VCC
Power
I2U
OPEN
I2Z
ON1
OZ1
-CSEL4
-VS2
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
DO81
DO91
D101
GND
I
O
I
O
O
I
O
O
I/O
I/O
I/O
-CSEL4
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
DO81
DO91
D101
GND
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
-CSEL
-VS2
RESET
-IORDY
DMARQ
-DMACK5
-DASP
PDIAG
DO81
DO91
D101
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
I3U
I1U, ON1
I1U, ON1
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
I1Z, OZ3
I1Z, OZ3
I1Z, OZ3
Ground
GND
4: The -CSEL signal is ignored by the card in PC Card moudes. However,
because it is not pulled up on the card in thses modes, it should not be left
floating by the host in PC card modes. In these modes, the pin should be
connected by th host to PC card A25 or grounded by the host.
Note: These signals are required only for 16-bit access and are not required when
installed in 8-bit systems. Devices should allow for 3-state signals not to
consume current.
2: Should be grounded by the host system.
5: If DMA operations are not used, the signal should be held high or tied to VCC
by the host. For proper operation in older hosts: while DMA operations are not
active, the card shall ignore the signal, including a floating condition.
3: Should be tied to VCC by the host system.
March 2007
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
Signal Description
Signal Name
Dir.
Pin
Description
These address lines along with the -REG signal are used to select the following: The I/O
port address registers within the CompactFlash® Storage Card or CF+ Card, the memory
mapped port address registers within the CompactFlash® Storage Card or CF+ Card, a byte
in the card's information structure and its configuration control and status registers.
A10-A0
(PC Card Memory Mode)
8, 10, 11, 12, 14, 15,
16, 17, 18, 19, 20
I
A10-A0
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
A2 - A0
(True IDE Mode)
In True IDE Mode, only A[2:0] are used to select the one of eight registers in the Task File,
the remaining address lines should be grounded by the host.
18, 19, 20
BVD1
This signal is asserted high, as BVD1 is not supported.
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mde)
Status Changed
This signal is asserted low to alert the host to changes in the READY and Write Protect
states , while the I/O interface is configured. Its use is controlled by the Card Config and
Status Register.
I/O
I/O
O
46
-PDIAG
(True IDE Mode)
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the Master / Slave
handshake protocol.
BVD2
This signal is asserted high, as BVD2 is not supported.
(PC Card Memory Mode)
-SPKR
(PC Card I/O Mode)
This line is the Binary Audio out put from the card. If the Card does not support the Binary
Audio function, this line should be held negated.
45
-DASP
(True IDE Mode)
In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/
Slave handshake protocol.
These Card Detect pins are connected to ground on the CompactFlash® Storage Card or
CF+ Card. They are used by the host to determine that the CompactFlash® Storage Card or
CF+ Card is fully inserted into its socket.
-CD1, -CD2
(PC Card Memory Mode)
-CD1, CD2
(PC Card I/O Mode)
26, 25
This signal is the same for all modes.
This signal is the same for all modes.
-CD1, CD2
(True IDE Mode)
These input signals are used both to select the card and to indicate to the card whether
a byte or a word operation is being performed. -CE2 always accesses the odd byte of the
word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2.
A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on
D0-D7.
-CE1, -CE2
(PC Card Memory Mode)
Card Enable
-CE1, -CE2
(PC Card I/O Mode)
Card Enable
I
7, 32
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, -CS0 is the chip select for the task file registers while -CS1 is used
to select the Alternate Status Register and the Device Control Register. While –DMACK is
asserted, -CS0 and –CS1 shall be held negated and the width of the transfers shall be 16
bits.
-CS0, CS1
(True IDE Mode)
-CSEL
(PC Card Memory Mode)
This signal is not used for this mode, but should be connected by the host to PC Card A25
or grounded by the host.
-CSEL
(PC Card I/O Mode)
This signal is not used for this mode, but should be connected by the host to PC Card A25
or grounded by the host.
I
39
This internally pulled up signal is used to configure this device as a Master or a Slave when
configured in the True IDE Mode. When this pin is grounded, this device is configured as a
Master. When the pin is open, this device is configured as a Slave.
-CSEL
(True IDE Mode)
March 2007
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NCF-H-M1 Series
White Electronic Designs
Signal Description (con'd)
Signal Name
D15 - D00
Dir.
Pin
Description
These lines carry the Data, Commands and Status information between the host and the
controller . D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of
the Word.
(PC Card Memory Mode)
31, 30, 29, 28, 27, 49,
48, 47, 6, 5, 4, 3, 2,
23, 22, 21
D15 - D00
(PC Card I/O Mode)
I/O
This signal is the same as the PC Card Memory Mode signal.
D15 - D00
(True IDE Mode)
In True IDE Mode, all Task File operations occur in byte mode on the low order bus D[7:0]
while all data transfers are 16 bit using D[15:0].
GND
Ground
(PC Card Memory Mode)
GND
-
1, 50
This signal is the same for all modes.
This signal is the same for all modes.
This signal is the same for all modes.
(PC Card I/O Mode)
GND
(True IDE Mode)
-INPACK
(PC Card Memory Mode)
The Input Acknowledge signal is asserted by the CompactFlash® Storage Card or CF+
Card when the card is selected and responding to an I/O read cycle at the address that is
on the address bus. This signal is used by the host to control the enable of any input data
buffers between the CompactFlash® Storage Card or CF+ Card and the CPU.
-INPACK
(PC Card I/O Mode)
Input Acknowledge
This signal is a DMA Request that is used for DMA data transfers between host and device.
It shall be asserted by the device when it is ready to transfer data to or from the host. For
Multiword DMA transfers, the direction of data transfer is controlled by DIOR- and DIOW-.
This signal is used in a handshake manner with DMACK-, i.e., the device shall wait until the
host asserts DMACK- before negating DMARQ, and re asserting DMARQ if there is more
data to transfer.
O
43
While a DMA operation is in progress, -CS0 and –CS1 shall be held negated and the width
of the transfers shall be 16 bits.
DMARQ
(True IDE Mode)
If there is no hardware support for DMA mode in the host, this output signal is not used and
should not be connected at the host. In this case, the BIOS must report that DMA mode is
not supported by the host so that device drivers will not attempt DMA mode.
A host that does not support DMA mode and implements both PCMCIA and True-IDE modes
of operation need not alter the PCMCIA mode connections while in True-IDE mode as long
as this does not prevent proper operation in any mode.
-IORD
(PC Card Memory Mode)
This signal is not used in this mode.
This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus
from the CompactFlash® Storage Card or CF+ Card when the card is configured to use the
I/O interface.
-IORD
(PC Card I/O Mode)
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34
-IORD
(Tru IDE Mode)
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
March 2007
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Signal Description (con'd)
Signal Name
Dir.
Pin
Description
-IOWR
(PC Card Memory Mode)
This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the
CompactFlash® Storage Card or CF+ Card controller registers when the CompactFlash®
Storage Card or CF+ Card is configured to use the I/O interface.
-IOWR
(PC Card I/O Mode)
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35
The clocking shall occur on the negative to positive edge of the signal (trailing edge).
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
-IOWR
(True IDE Mode)
This is an Output Enable strobe generated by the host interface. It is used to read data from
the CompactFlash® Storage Card or CF+ Card in Memory Mode and to read the CIS and
configuration registers.
-OE
(PC Card Memory Mode)
-OE
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9
In PC Card I/O Mode, this signal is used to read the CIS and configuration registers.
(PC Card I/O Mode)
-ATA SEL
(True IDE Mode)
To enable True IDE Mode this input should be grounded by the host.
In Memory Mode, this signal is set high when the CompactFlash® Storage Card or CF+
Card is ready to accept a new data transfer operation and is held low when the card is busy.
At power up and at Reset, the READY signal is held low (busy) until the CompactFlash®
Storage Card or CF+ Card has completed its power up or reset function. No access of any
type should be made to the CompactFlash® Storage Card or CF+ Card during this time.
READY
(PC Card Memory Mode)
Note, however, that when a card is powered up and used with RESET continuously
disconnected or asserted, the Reset function of the RESET pin is disabled. Consequently,
the continuous assertion of RESET from the application of power shall not cause the
READY signal to remain continuously in the busy state.
O
37
I/O Operation – After the CompactFlash® Storage Card or CF+ Card has been configured
for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to
generate a pulse mode interrupt or held low for a level mode interrupt.
-IREQ
(PC Card I/O Mode)
INTRQ
In True IDE Mode signal is the active high Interrupt Request to the host.
Signal Name
Dir.
Pin
Description
-REG
This signal is used during Memory Cycles to distinguish between Common Memory and
Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory.
(PC Card Memory Mode)
Attribute Memory Select
-REG
(PC Card I/O Mode)
The signal shall also be active (low) during I/O Cycles when the I/O address is on the Bus.
This is a DMA Acknowledge signal that is asserted by the host in response to DMARQ to
initiate DMA transfers.
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44
While DMA operations are not active, the card shall ignore the -DMACK signal, including a
floating condition.
-DMACK
(True IDE Mode)
If DMA operation is not supported by a True IDE Mode only host, this signal should be
driven high or connected to VCC by the host.
A host that does not support DMA mode and implements both PCMCIA and True-IDE modes
of operation need not alter the PCMCIA mode connections while in True-IDE mode as long
as this does not prevent proper operation all modes.
March 2007
Rev. 2
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W7NCF-H-M1 Series
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Signal Description (con'd)
Signal Name
Dir.
Pin
Description
The CompactFlash® Storage Card or CF+ Card is Reset when the RESET pin is high with
the following important exception:
The host may leave the RESET pin open or keep it continually high from the application of
power without causing a continuous Reset of the card. Under either of these conditions, the
card shall emerge from power-up having completed an initial Reset.
RESET
(PC Card Memory Mode)
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41
The CompactFlash® Storage Card or CF+ Card is also Reset when the Soft Reset bit in the
Card Configuration Option Register is set.
RESET
(Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, this input pin is the active low hardware reset from the host.
+5 V, +3.3 V power.
-RESET
(True IDE Mode)
VCC
(PC Card Memory Mode)
VCC
-
13, 38
This signal is the same for all modes.
(Pc Card I/O Mode)
VCC
(True IDE Mode)
This signal is the same for all modes.
-VS1
-VS2
Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so that
the CompactFlash® Storage Card or CF+ Card CIS can be read at 3.3 volts and -VS2 is
reserved by PCMCIA for a secondary voltage and is not connected on the Card.
(PC Card Memory Mode)
-VS1
-VS2
(PC Card I/O Mode)
O
33, 40
This signal is the same for all modes.
This signal is the same for all modes.
-VS1
-VS2
(True IDE Mode)
-WAIT
(PC Card Memory Mode)
The -WAIT signal is driven low by the CompactFlash® Storage Card or CF+ Card to signal
the host to delay completion of a memory or I/O cycle that is in progress.
-WAIT
(PC Card I/O Mode)
O
42
36
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, this output signal may be used as IORDY.
IORDY
(True IDE Mode)
This is a signal driven by the host and used for strobing memory write data to the registers
of the CompactFlash® Storage Card or CF+ Card when the card is configured in the
memory interface mode. It is also used for writing the configuration registers.
-WE
(PC Card Memory Moce)
-WE
I
In PC Card I/O Mode, this signal is used for writing the configuration registers.
(PC Card I/O Mode)
-WE
(True IDE Mode)
In True IDE Mode, this input signal is not used and should be connected to VCC by the host.
Memory Mode – The CompactFlash® Storage Card or CF+ Card does not have a write
protect switch. This signal is held low after the completion of the reset initialization
sequence.
WP
(PC Card Memory Mode)
I/O Operation – When the CompactFlash® Storage Card or CF+ Card is configured for I/O
Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal
indicates that a 16 bit or odd byte only operation can be performed at the addressed port.
-IOIS16
(PC Card I/O Model)
O
24
-IOCS16
(True IDE Mode)
In True IDE Mode this output signal is asserted low when this device is expecting a word
data transfer cycle.
March 2007
Rev. 2
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PACKAGE DIMENSIONS
1.60mm .05
(.063 in .002)
.99mm .05
(.039 in .002)
50
26
1
25
1.01mm .07
(0.040 in. .003)
1.01mm .07
(0.040 in. .003)
3.30mm .10
(.130 in .004)
2.44mm .07
(.096 in. .003)
.01mm .07(.039 in .003)
Optional Configuration
(See note.)
2.15mm .07
(.085 in x .003)
1.65mm
(.130 in.)
0.76mm .07(0.30 in .003)
41.66mm .13(1.640 in . 005)
42.80mm .10(1.685 in .004)
0.63mm .07(.025 in .003)
4xR 0.5mm .1
(4xR.020 in .004)
Note: The optional notched configuration was shown in the CF Specification Rev. 1.0
in specification Rev. 1.2, the notch was removed for ease of tooling. This optional
configuration can be used but it is not recommended.
ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2007
Rev. 2
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W7NCF-H-M1 Series
White Electronic Designs
Part Numbering Guide
W 7N CF xxx H x 0 x x x x x M1 x
WEDC:
Flash Card, SLC - NAND:
CompactFlash®:
Memory Capacity:
128 = 128M Byte
256 = 256M Byte
512 = 512M Byte
01G = 1G Byte
02G = 2G Byte
04G = 4G Byte
08G = 8G Byte
Controller manufacturer
H = H-Series
Controller/Firmware Revision
Number:
1, 2, 3...
Labels or Custom Labeling:
0 = labels front and back
1 = label on back only
Temperature:
C = Commercial (0°C - 70°C)
I = Industrial (-40°C - +85°C)
Memory Mfg.:
S = Samsung
Memory Vendor Revsison:
Blank = Initial release
A = Susequent release etc.
Memory Device Information:
2 = 512Mbit single die package
3 = 1Gb single die package
4 = 2Gb single die package
5 = 4Gb dual die package
6 = 4Gb single die package
7 = 8Gb dual die package
8 = 8Gb single die package
9 = 16Gb quad die package
A = 16Gb dual die package
B = 16Gb single die package
Option:
B = Standard CF card configuration
A = Standard CF with conformal coating
C = Standard card with DMA disabled
D = Standard card with DMA disabled and conformal coating
E = Fixed disk option (for compatibility with some embedded software)
F = Fixed disk with conformal coating
H = Fixed with DMA disable
J = Fixed disk with DMA disable and conformal coating
Market Series:
M1 = Medical Series 1
G = for RoHS:
* For help selecting the proper and most current part number for your application please contact your local sales representative.
March 2007
Rev. 2
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W7NCF-H-M1 Series
White Electronic Designs
Document Title
128MB to 8GB Medical Series CompactFlash®
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
February 2007
Concept
Rev 1
Rev 2
1.0 Reviewed by enginerieng
March 2007
Advanced
1.1 Moved from concept to advanced
2.0 Added 1GB density to storage capacites
March 2007
Advanced
March 2007
Rev. 2
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