VS-702-ECE-KECA-324M000000 [MICROSEMI]

SAW Oscillator, 324MHz Nom, LCC-6;


型号：	VS-702-ECE-KECA-324M000000
厂家：	Microsemi
描述：	SAW Oscillator, 324MHz Nom, LCC-6
文件：	总7页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VS-702

Voltage Controlled SAW Oscillator

Previous Vectron Model VS-720

VS-702

Description

The VS-702 is a SAW Based Voltage Controlled Oscillator that achieves low phase noise and very low jitter performance. The VS-

702 is housed in an industry standard hermetically sealed LCC package and available in tape and reel.

Features

Applications

Ideal for PLL circuits for clock smoothing and frequency

translation

•

Industry Standard Package, 5.0 x 7.5 x 2.0 mm

ASIC Technology for Ultra Low Jitter

•

SONET, SDH

0.100 ps-rms typical across 12 kHz to 20 MHz BW

0.120 ps-rms typical across 50 kHz to 80 MHz BW

Output Frequencies from 150 MHz to 1 GHz

3.3 V Operation

Synchronous Ethernet

Fiber Channel

•

LAN / WAN

Test and Measurement

LV-PECL or LVDS Conﬁguration with Fast Transition Times

Improved Temperature Stability over Standard VCSO ( 20 ppmꢀ

Output Disable Feature

0/70°C or -40/85°C operating temperature

Product is free of lead and compliant to EC RoHS Directive

Block Diagram

Complementary

Output

V_DD

BAW

SAW

V_C

E/D

Gnd

Page1

Performance Speciﬁcations

Table 1. Electrical Performance

Parameter

Symbol

Min

Typical

Maximum

Units

Supply

Voltage¹

V_DD

I_DD

2.97

3.3

3.63

Current (No Loadꢀ

Frequency

150

Nominal Frequency²

Absolute Pull Range ^3,6

Linearity³

f_N

1000

MHz

ppm

APR

Lin

K_V

±±5

Gain Transfer Positive³(See pg ±)

Temperature Stability³

+155

±ꢀ5

ppm/V

ppm

f_STAB

Outputs

Mid Level³

V_DD-1.±

V_DD-1.3

7±5

V_DD-1.ꢀ

Single Ended Swing³

Double Ended Swing³

Current

mV-pp

V-pp

1.±

I_OUT

ꢀ5

Rise Time⁴

Fall Time⁴

t_R

t_F

±55

Symmetry³

SYM

фJ

4±

±5

5.1

5.1ꢀ

ꢀ.±

±±

5.ꢀ±5

5.355

3.5

ps-rms

Jitter (1ꢀ kHz - ꢀ5 MHz BW)6ꢀꢀ.58MHz^±

Jitter (±5 kHz - 85 MHz BW)1±±.±ꢀMHz^±

Period Jitter, RMS (6ꢀꢀ.58MHz)⁷

Period Jitter, Peak - Peak (6ꢀꢀ.58MHz)⁷

Spurious Suppression^ꢀ

фJ

ꢀ4

-65

-±5

dBc

Control Voltage

Control Voltage Range for APR

Control Voltage Input Impedance

Control Voltage Modulation BW

V_C

Z_IN

5.3

3.5

7±

±5

KΩ

kHz

Enable/Disable

5.7*V_DD

Output Enabled, Option A

Output Disabled, Option A

V_IH

V_IL

5.3*V_DD

5.ꢀ*V_DD

Output Enabled, Option C

Output Disabled, Option C

V_IL

V_IH

5.7*V_DD

Operating Temperature

Package Size

T_OP

5/75 or -45/8±

±.5 x 7.± x ꢀ.5

°C

1] The VS-75ꢀ power supply should be ﬁltered, eg, 5.1 and 5.51uF to ground

ꢀ] See Standard Frequencies and Ordering Information tables for more speciﬁc information

3] Parameters are tested with production test circuit below (Fig 1).

4] Measured from ꢀ5% to 85% of a full output swing (Fig ꢀ).

±] Integrated across stated bandwidth.

6] Tested with Vc = 5.3V to 3.5V unless otherwise stated in part description

7] Broadband Period Jitter measured using Lecroy Wavemaster 8655A 6 GHz Oscilloscope, ꢀ±K samples taken. See application note.

Fig 1: Test Circuit

Fig 2: LVPECL Waveform

SYM = 100 x t_A/ t_R

t_R

t_F

Vc (-1.0V to +1.7V)

OD (-1.3V), OE (Open)

Vee (-1.3V)

Vcc (+2V)

COutput

Output

50Ω

t_A

Test Circuit Notes:

1) To Permit 50Ω Measurement of Outputs, all DC Inputs are Biased Down 1.3V.

2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise.

3) 50Ω Terminations are Within Test Equipment.

t_R

Pageꢀ

Outline Drawing & Pad Layout

XVXSX7.X0X2XXYWW

CCC-CCCC

XXX.XX

XXXMXXX

Dimensions in inches (mmꢀ

Table 2. Pin Out

Symbol

V_C

Function

VCXO Control Voltage

Enable/Disable

**See Ordering Options**

GND

Output

COutput

V_DD

Case and Electrical Ground

Output

Complementary Output

Power Supply Voltage (3.3V 10ꢁꢀ

Typical Phase Noise

Typical Gain

VS-702 @ 622.08 MHz

200

150

100

120

110

100

Series1

Series2

0.5

1.5

2.5

-50

-100

-150

-200

Vc (volts)

Page3

Suggested Output Load Conﬁgurations

The VS-702 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes on

terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as

shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.

Figure 4 Single Resistor Termination Scheme

Figure 5 Pull-Up Pull-Down Termination

Figure 3 Standard PECL Output Conﬁguration

Resistor values are typically 120 to 240 ohms

Reliability

VI qualiﬁcation includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reﬂow

simulation. The VS-75ꢀ family is capable of meeting the following qualiﬁcation tests:

Table 3. Environmental Compliance

Parameter

Conditions

Mechanical Shock

MIL-STD-883, Method ꢀ55ꢀ

MIL-STD-883, Method ꢀ557

MIL-STD-883, Method ꢀ553

MIL-STD-883, Method 1514

MIL-STD-883, Method ꢀ51±

MSL 1

Typical Characteristics - Phase Noise

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solvents

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not

implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.

Exposure to absolute maximum ratings for extended periods may adversely aﬀect device reliability. Permanent damage is

also possible if OD or Vc is applied before Vcc.

Table 4. Absolute Maximum Ratings

Parameter

Power Supply

Symbol

V_DD

Ratings

5 to 6

Unit

Output Current

I_OUT

ꢀ±

Voltage Control Range

Storage Temperature

Soldering Temp/Time

V_C

5 to V_DD

-±± to 1ꢀ±

260 / 40

°C

T_LS

°C / sec

Although ESD protection circuitry has been designed into the VS-702 proper precautions should be taken when handling

and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing

and design protection evaluation.

Table 5. ESD Ratings

Model

Minimum

500V

Conditions

MIL-STD-883, Method 3015

JESD22-C101

Human Body Model

Charged Device Model

500V

Page4

IR Reﬂow

Table 6. Reﬂow Proﬁle (IPC/JEDEC J-STD-020C)

Parameter

Symbol

Value

PreHeat Time

Ts-min

Ts-max

t_S

60 sec Min, 180 sec Max

150°C

200°C

Ramp Up

Time Above 217 °C

Time To Peak Temperature

Time at 260 °C

R_UP

t_L

3 °C/sec Max

60 sec Min, 150 sec Max

480 sec Max

T_{25C to peak}

t_P

20 sec Min, 40 sec Max

6 °C/sec Max

Ramp Down

R_DN

The device is qualiﬁed to meet the JEDEC

standard for Pb-Free assembly. The

temperatures and time intervals listed

are based on the Pb-Free small body

requirements. The VS-702 device is

hermetically sealed so an aqueous wash is

not an issue.

Termination Plating:

Electroless Gold Plate over Nickel Plate

Tape & Reel (EIA-481-2-A)

Table 7. Tape and Reel Information

Tape Dimensions (mm)

Reel Dimensions (mm)

Dimension

Tolerance

VS-702

Typ

1.5

Typ

Min

Typ

16.4

Max

22.4

# Per

Reel

Typ

7.5

Typ

178

Min

1.5

Typ

Min

20.2

200

Page5

Table 8. Standard Output Frequencies (MHz)

155M520000

240M000000

320M000000

491M520000

635M040000

690M569200

800M000000

156M250000

245M760000

324M000000

500M000000

637M500000

693M483000

901M120000

160M000000

250M000000

350M000000

531M250000

640M000000

704M380600

1000M00000

162M000000

260M000000

375M000000

532M000000

644M531300

707M352700

175M000000 187M500000 200M000000 212M500000

268M800000 300M000000 311M040000 312M500000

384M000000 389M600000 400M000000 480M000000

533M000000 537M600000 622M080000 625M000000

657M421900 666M514300 669M326600 672M162700

720M000000 742M434700 768M000000 796M875000

Ordering Information

VS-702- E C E - K X A N - xxxMxxxxxx

Frequency in MHz

Product Family

VS: VCSO

Performance Options

N: Standard

A: Improved Phase Noise

Package

702: 5 x 7.5 x 2.0 mm

Enable/Disable

A: Enable High

C: Enable Low

Input

E: 3.3 Vdc ±±0ꢀ

Stability

X: Standard

E: 20ppm Temperature Stability

Output

C: LVPECL (45/55% Symmetry)

D: LVDS (45/55% Symmetry)

Absolute Pull Range

K: ±50ppm

Operating Temperature

T: 0/70°C

E: -40/85°C

*Note: not all combination of options are available.

Other speciﬁcations may be available upon request.

Example: VS-702-ECE-KXAN-622M080000

For Additional Information, Please Contact

* Add _SNPBDIP for tin lead solder dip

Example: VS-702-ECE-KXAN-622M080000_SNPBDIP

Page6

Revision History

Revision Date

Feb 12, 2014

July 7, 2015

Approved

Change Summary

Updated VI Asia address.

Change current speciﬁcaꢀon in Table 1 to reﬂect 70 ma typical and 90mA maximum.

Update logo and contact informaꢀon, add “SNPBDIP” ordering informaꢀon.

Aug 10, 2018

Page7

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