VSC8223RV [MICROSEMI]
ATM/SONET/SDH Clock Recovery Circuit, CMOS, PQFP48,;
| 型号： | VSC8223RV |
| 厂家： | 
Microsemi |
| 描述： | ATM/SONET/SDH Clock Recovery Circuit, CMOS, PQFP48, ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总26页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VSC8223
Datasheet
Extended Multirate STS-12/STM-4, STS-3/STM-1 and FEC Clock and Data Recovery IC
● On-die input and output termination
FEATURES
● Selectable high-speed clock output
● Extended multirate clock and data recovery
support for STS-12/STM-4, STS-3/STM-1, and
FEC data rates
● Selectable LVPECL reference frequencies:
19.44 MHz, 77.76 MHz, or 155.52 MHz (or FEC)
● Internal phase-locked loop maintains clock
● Complies with Bellcore and ITU-T specifications
output in the absence of data
for jitter tolerance, transfer, and generation
● Low power CMOS technology
● 2.5 V supply operation
● Status indication signals (LVTTL) for:
Loss of signal (LOS)
Loss of lock (LOL)
No reference (NOREF)
● 0.4 W typical power dissipation
● 48-pin LQFP package
● Automatic and manual lock-to-reference modes
GENERAL DESCRIPTION
The VSC8223 device is a high-performance, extended multirate clock and data recovery (CDR) IC that supports
SONET/SDH systems operating at STS-12/STM-4, STS-3/STM-1, and forward error correction (FEC) data rates.
The VSC8223 generates a differential bit clock and differential retimed data.
High-speed input and output signals are terminated on-chip to maintain the highest degree of signal integrity possible.
Two selectable, externally supplied reference clock (REFCLK[1:0]) inputs support the phase-locked loop (PLL)
operation and are used to maintain a lock condition when the high-speed data is missing at the input. A reference
clock selector (RCLK_SEL) input allows the user to select between either of the two REFCLK inputs. The reference
clock frequency (155.52 MHz, 77.76 MHz, 19.44 MHz or FEC) to the VSC8223 is selected using the
RCLK_FSEL[1:0] control signals.
The loss of lock (LOL) status signal indicates the loss of lock of the PLL. The loss of signal (LOS) status signal
indicates the occurrence of an all zeros or all ones pattern. During a LOS condition, an all zeros data pattern is output
along with a SONET/SDH-quality clock (for SONET/SDH rates only).
During LOS conditions, the PLL automatically switches to the REFCLK. The PLL automatically switches back to the
high-speed input when the LOS signal is de-asserted. The PLL can also be manually forced into the lock to REFCLK
mode using the LREF control pin. In addition, the automatic lock to REFCLK mode can be disabled.
The VSC8223 device is available in a plastic, low-profile quad flat package (LQFP) with an exposed pad and a
7 mm × 7 mm body. The device is also available in a lead(Pb)-free package, VSC8223XRV.
G52417 Revision 4.0
July 2007
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: webmaster@vitesse.com
Internet: www.vitesse.com
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VSC8223
Datasheet
Block Diagram
STS12/3
LOS LOL
SDI
SDO
SDO
Data
Output
V
Input
TT
SDI
CRU
SCO
SCO
Clock
Output
MUX
REFCLK1
REFCLK1
REFCLK
Frequency
Select
Lock to Reference
MUX
REFCLK0
REFCLK0
RCLK_SEL RCLK_FSEL[1:0]
LREF_DIS
LREF
SCO_EN
System-Level Block Diagram
VSC7971
VSC8223
VSC3138
VSC3139
VSC3140
2
VSC7216
VSC7226
TIA/PA
CDR
Optics
Backplane
Drivers
Asynchronous
Crosspoint
Switch Matrix
2
VSC8223
VSC7939
CDR
LD
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Datasheet
REVISION HISTORY
This section describes the changes that were implemented in this document. The changes are listed by revision,
starting with the most current publication.
Revision 4.0
Revision 4.0 of this datasheet was published in July 2007. The following is a summary of the changes implemented in
the datasheet:
● The device is now available in a lead(Pb)-free package.
● ESD and moisture sensitivity specifications were added. For more information,
see “Stress Ratings,” page 19 and “Moisture Sensitivity,” page 25.
● The thermal specifications were updated. For more information, see “Thermal Specifications,” page 25.
● The system-level block diagram was updated to reference new products. The LVPECL input terminations diagram
was also updated. For more information, see “System-Level Block Diagram,” page 2 and “LVPECL Input
Terminations,” page 7.
● For the supported upper and lower data ranges, the lower data range for HIGH (1) was changed from 150 Mbps to
155 Mbps and the lower data range for LOW (0) was changed from 600 Mbps to 622 Mbps.
● The recommended REFCLK input frequencies for STS-12/-3 FEC were updated. For more information,
see Table 6, page 10.
● The conditions for the jitter tolerance and jitter transfer bandwidth parameters were updated to include
LBW [1:0] = 0, 0.
● The maximum values for the CRU lock time (synchronous and asynchronous switch) parameters were changed to
typical values.
● The operating temperature parameter was clarified as ambient to case and the minimum value was changed from
–40 °C to –20 °C.
● The minimum values for the power supply current parameters were updated and the power supply requirements
table (formerly table 17) was integrated with the recommended operating conditions. For more information, see
“Recommended Operating Conditions,” page 19.
● In the electrical specifications section, the voltage input swing (single-ended drive), input high voltage, REFCLK
input duty cycle, input HIGH current, input LOW current, and case temperature parameters were removed.
● Errata information was also removed.
Revision 2.0
Revision 2.0 of this datasheet was published in October 2002. This was the first publication of the document.
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Datasheet
FUNCTIONAL DESCRIPTION
The VSC8223 extended multirate CDR consists of the following functional blocks:
●
●
●
●
●
●
●
●
High-speed data inputs
High-speed clock and data outputs
Low-speed REFCLK LVPECL inputs
Static LVTTL control inputs
Static LVTTL status outputs
Clock and data recovery unit (CRU)
LOCK to REFCLK unit
Power and ground
High-Speed Data Inputs (SDI/SDI)
The VSC8223 high-speed data input stage provides the following features:
● On-die 100 Ω termination resistance using two series 50 Ω resistors, with the internal junction of the two resistors
accessible on an external pin V
TT
● AC-coupled operation
● DC-coupled operation (input common-mode voltages must be taken into account)
● Single-ended input operation
● Differential input operation
The high-speed input receivers are terminated on-chip to 50 Ω and are internally biased to accommodate CML or
PECL levels. AC-coupling or DC-coupling to the device can be used. However, with DC-coupling, the input
common-mode voltage levels must be within the allowable limits. See the following illustrations for different
high-speed input termination schemes.
Limiting Amplifier
VSC8223
VDD
CAC
ZO = 50 Ω
50 Ω
50 Ω
VTT
VSS
Output
Driver
Input
Driver
C
VDD
ZO = 50 Ω
CAC
VSS
Figure 1. Differential AC-Coupled Input Termination
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Datasheet
Limiting Amplifier
VSC8223
VDD
ZO = 50 Ω
50 Ω
50 Ω
VTT
VSS
Output
Driver
Input
Driver
C
VDD
ZO = 50 Ω
VSS
Figure 2. Differential DC-Coupled Input Termination
Single-Ended Driver
VSC8223
VDD
CAC
ZO = 50 Ω
Output
Driver
50 Ω
50 Ω
VSS
VTT
Input
Driver
C
VDD
C
VSS
Figure 3. Single-Ended AC-Coupled Input Termination
Single-Ended Driver
VSC8223
VDD
ZO = 50 Ω
Output
Driver
50 Ω
50 Ω
VTT
VSS
VDD
Input
Driver
C
VCM
V
CM = Common-Mode Voltage of the Output Buffer
VSS
NOTE: For best performance, it is strongly recommended differential input
configurations be used. Vitesse does not guarantee device performance
will meet datasheet specifications for single-ended termination schemes.
Figure 4. Single-Ended DC-Coupled Input Termination
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Datasheet
High-Speed Data and Clock Outputs (SDO/SDO and SCO/SCO)
The VSC8223 high-speed data output stage provides the following features:
● On-die 50 Ω termination resistance to V
DD
● AC-coupled and DC-coupled operation
● Differential output operation
● Single-ended output operation
The high-speed data and clock output drivers are CML and consist of a differential pair designed to drive a 50 Ω
transmission line. See the following illustrations for differential termination schemes.
Receiving Device
VSC8223
CAC
ZO = 50 Ω
ZO = 50 Ω
50 Ω
Input
Driver
Output
Driver
100 Ω
VDD
CAC
50 Ω
VDD
Receiving Device
VSC8223
CAC
ZO = 50 Ω
50 Ω
Output
Driver
50 Ω
Input
Driver
CAC
ZO = 50 Ω
VDD
VDD
50 Ω
50 Ω
VDD
VDD
NOTE: The 50 Ω and 100 Ω termination resistors can be internal or external to the receiving device.
Figure 5. High-Speed Output—AC-Coupled Terminations
Receiving Device
VSC8223
ZO = 50 Ω
ZO = 50 Ω
50 Ω
Input
Driver
Output
Driver
100 Ω
VDD
50 Ω
VDD
VSC8223
Receiving Device
ZO = 50 Ω
ZO = 50 Ω
50 Ω
Output
Driver
50 Ω
VDD
Input
Driver
VDD
50 Ω
50 Ω
VDD
VDD
NOTE: The 50 Ω and 100 Ω termination resistors can be internal or external to the receiving device.
Figure 6. High-Speed Output—DC-Coupled Terminations
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Datasheet
Low-Speed REFCLK LVPECL Inputs
The LVPECL REFCLK[1:0] inputs are driven differentially, single-ended, DC-coupled or AC-coupled. For more
information, see Table 21, page 18. The REFCLK inputs are internally biased; however, external input terminations
must be provided.
AC-Coupled
Transmitting Device
VSC8223
CIN
CIN
ZO = 50 Ω
Output
Driver
Input
Receiver
R
100 Ω
T
ZO = 50 Ω
V
SS
R
T
CIN typ = 100 nF
V
SS
NOTE: Consult the transmitting device's application for R value.
T
DC-Coupled
Transmitting Device
VSC8223
ZO = 50 Ω
R
50 Ω
VDD - 2.0 V
1
Output
Driver
Input
Receiver
ZO = 50 Ω
R
50 Ω
2
VDD - 2.0 V
NOTE: Termination schemes must meet the stated LVPECL levels and swings.
Figure 7. LVPECL Input Terminations
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Datasheet
Reference Clock Input Selection
In the following table, the RCLK_SEL signal selects either the REFCLK1 and REFCLK0 inputs.
Table 1: RCLK_SEL Truth Table
RCLK_SEL
Floating or not connected
LOW (0)
REFCLK Input Selected
REFCLK0
REFCLK0
HIGH (1)
REFCLK1
Reference Clock Frequency Selection
In the following table, the RCLK_FSEL[1:0] control signals are used to select the REFCLK input frequency.
Table 2: RCLK_FSEL[1:0] Truth Table
SONET REFCLK
RCLK_FSEL1
LOW (0)
RCLK_FSEL0
LOW (0)
Frequency (or FEC)
19.44 MHz(1)
Not allowed
LOW (0)
HIGH (1)
LOW (0)
HIGH (1)
HIGH (1)
77.76 MHz
HIGH (1)
155.52 MHz
1. Does not meet SONET jitter specifications in lock-to-reference mode; however, it is valid in the normal mode of operation.
An example application for SONET/SDH systems can be as follows: The regular frequency SONET/SDH reference
clock can be connected to the REFCLK0/REFCLK0 inputs, and the FEC version of the same clock can be connected
to REFCLK1/REFCLK1. Up to 15/14 FEC is supported.
Static LVTTL Control Inputs
LVTTL inputs are used for the following signals: RCLK_SEL, RCLK_FSEL[1:0], FC_SEL, STS12/3, LREF,
SCO_EN, and LREF_DIS. The LVTTL input signal levels are specified in Table 15, page 14.
Static LVTTL Control Outputs
LVTTL outputs are used for the following signals: LOS, LOL, and NOREF. The LVTTL output signal levels are
specified in Table 16, page 14.
LOS Assertion
The LOS pin indicates inactivity on the SDI, SDI lines. LOS is defined in Telcordia GR-253-CORE, Section 6.2.1.1.
LOS is interpreted as described in the following sections. If all-zeros or all-ones pattern exists at the input high-speed
input receiver for 2.3 µs or less, LOS must not be asserted. If inactivity lasts 100 µs or greater, LOS must be asserted.
If inactivity lasts between 2.3 µs and 100 µs, LOS assertion is left to the choice of the designer. The VSC8223
supports LOS assertion according to the specifications in Table 3, page 9.
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Datasheet
LOS Termination
LOS may be terminated after 125 µs of time during which an LOS defect does not exist. LOS must be terminated
after 250 µs of time during which an LOS defect does not exist.
NOREF Operation
The NOREF output will go HIGH to indicate that there is no signal on the REFCLK input or that the REFCLK is
more than approximately 25% above or below the expected value.
Table 3: LOS Parameters
Symbol
Parameter
Minimum Maximum
Unit
μs
Condition
tLOS_SET
tLOS_CLEAR
LOS set time
LOS clear time
2.3
100
250
From data interruption
From data restoration
125
μs
LOL
The LOL pin indicates loss of PLL lock. Loss of PLL lock is defined as the condition in which the absolute value of
the difference between the frequency of the VCO and the frequency of the incoming serial data is greater than
400 ppm. The LOL specifications are summarized in the following table.
Table 4: LOL Parameters
Symbol
Parameter
Typical
1
Unit
ms
μs
Condition
tLOL_SET
tLOL_CLEAR
LOL set time
LOL clear time
From data interruption
From data restoration
500
Clock and Data Recovery Unit
This circuit meets or exceeds SONET jitter generation, jitter tolerance, and jitter transfer requirements.
The CRU accepts high-speed NRZ data (on SDI/SDI inputs) and recovers the clock for down-stream devices. The
on-chip PLL consists of a phase detector, loop filter, VCO, and prescaler. If there is a phase error between the
incoming data and the on-chip VCO, the loop filter raises or lowers the control voltage to the VCO to null the phase
difference.
The CRU supports STS-12, STS-3, and FEC data rates. The VSC8223 device supports the data rates through the
STS12/3 pin, which is LVTTL. If no connections are made to the STS12/3 pin, the default data rate supported is
STS-12 and STS-12 (FEC). The following table shows the typical upper and lower data rate ranges.
Table 5: Supported Upper and Lower Data Ranges
STS12/3
Floating or not connected
LOW (0)
Lower Data Rate
600 Mbps
Upper Data Rate
675 Mbps
Service Type
STS-12, STS-12 (FEC)
STS-12, STS-12 (FEC)
STS-3, STS-3 (FEC)
622 Mbps
675 Mbps
HIGH (1)
155 Mbps
168 Mbps
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Datasheet
Two reference clock inputs (REFCLK0 and REFCLK1) are provided as clocking inputs to the device. The REFCLK
to the CRU is selected by an external TTL control pin (RCLK_SEL). For more information about the REFCLK
operation, see Table 1, page 8.
For SONET/SDH operation, the frequency of the REFCLK input to the CRU is 19.44 MHz, 77.76 MHz, or 155 MHz.
For detailed information for selecting one of the above reference clocks, see Table 2, page 8.
Table 6: Recommended REFCLK Input Frequencies
STS-12/-3
77.76 MHz
155.52 MHz
STS-12/-3 FEC
83.314 MHz
166.629 MHz
The CRU outputs a high-speed output clock that is the same frequency as the serial bit clock that generated the
incoming data stream. The accuracy of this clock is 20 ppm or better.
Loop Filter
The PLL on the VSC8223 employs one external capacitor and must be connected between FILT0 and GND. The
recommended capacitor is a low-inductance 1.0 µF (0603 or 0805) ceramic SMT X7R device, 6.3 WVDC or greater.
VCO
The internal VCO is capable of tuning through the STS-3, STS-12, and FEC frequency ranges.
Prescaler
The prescaler selection is detailed in Table 5, page 9.
Decision Circuit
The decision circuit is a D-FF. The retimed serial data is sent out on SDO and SDO. The clock used to retime the
serial data is also sent out on SCO and SCO output pins.
DATA OUTPUT
tPD
CLOCK OUTPUT
Figure 8. Clock to Data Propagation Delay
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VSC8223
Datasheet
Clock Output Enable
The high-speed clock output (SCO/SCO) can be disabled by using the SCO_EN pin. The operation of this control
signal is detailed in the following table.
Table 7: SCO_EN Truth Table
SCO_EN
Floating or not connected
LOW (0)
Operating Mode
High-speed clock output enabled
High-speed clock output disabled
High-speed clock output enabled
HIGH (1)
Lock to Reference
The VSC8223 provides an automatic lock-to-reference mode (LOCK to REFCLK) during LOS occurrences. This
mode can also be manually forced using the LREF signal. During a LOCK to REFCLK condition, the high-speed
clock output is the same frequency prior to the LOCK to REFCLK condition and the high-speed data output is forced
to a logic 0 level.
For diagnostic purposes or for applications that do not require the automatic LOCK to REFCLK operation, this mode
of operation can be disabled using the LREF_DIS control signal.
Table 8: LREF_DIS Truth Table
RCLK_SEL
Operating Mode
Normal—CRU locks to incoming data (if present and valid) and automatic LOCK to REFCLK
operation is enabled. LREF operates normally.
Floating or not connected
Normal—CRU locks to incoming data (if present and valid) and automatic LOCK to REFCLK
operation is enabled. LREF operates normally.
LOW (0)
HIGH (1)
Disabled—Automatic LOCK to REFCLK operation is disabled and high-speed clock and data
outputs are derived from the incoming data stream. LREF operates normally.
The LOCK to REFCLK mode of operation is entered when either event listed below occurs:
● Manually forced with LREF control signal—The LREF signal is used to manually force the VSC8223 into the
LOCK to REFCLK mode of operation.
● Clean LOS occurrence—A clean LOS occurs when the incoming optical receiver stops receiving the incoming
signal (such as due to a fiber cut) and the optical receiver electronics goes to either a static logic 1 or logic 0 state.
For more information, see “LOS Assertion,” page 8, “LOS Termination,” page 9, and Table 3, page 9.
Table 9: LREF Truth Table
LREF
Operating Mode
Floating or not connected
Normal—CRU locks to incoming data (if present and valid) and automatic LOCK to REFCLK
operation is enabled.
LOW (0)
HIGH (1)
Normal—CRU locks to incoming data (if present and valid) and automatic LOCK to REFCLK
operation is enabled.
Forced—CRU locks to previously selected REFCLK input and outputs a high-speed clock (with
same tolerance as REFCLK signal) and high-speed data outputs are forced to a logic 0 level.
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Datasheet
● LOL occurrence—An LOL can occur due to unlockable input data such as if the incoming data was random, if the
incoming data exceeded the input jitter tolerance of the VSC8223, or if the incoming data rate was out of the
tuning range of the internal VCO. In this case, the high-speed clock outputs, SCO/SCO, are within 400 ppm of
the incoming clock.
● Dirty LOS occurrence—A dirty LOS operation can occur due to the same condition as a clean LOS occurrence
except the optical receiver does not go to a static logic 1 or 0, but instead oscillates and outputs random, unlockable
data to the downstream CDR. This occurrence is seen as a LOL condition by the CRU. In this case, the high-speed
clock outputs, SCO/SCO is within 400 ppm of the incoming clock.
Automatic LOCK to REFCLK Detailed Operation
The automatic LOCK to REFCLK detailed operation is described through the use of four states as outlined in the
Table 10, page 12. This description assumes that either LREF or LREF_DIS is not asserted.
Power Supplies
The following table lists the automatic LOCK to REFCLK states for the VSC8223 device.
Table 10: Automatic LOCK to REFCLK States
Description
LOS
N/A
0
LOL
N/A
0
SCO/SCO
N/A
SDO/SDO
N/A
Device powered off
Normal Operation—Device is powered on and
Phase-locked to input data
Retimed output data
lockable input data is present
Clean LOS Operation—Device is powered on
and static 1 or 0 input data is present
1
0
0
1
Phase-locked to REFCLK
Static logic 0
Static logic 0
LOL or Dirty LOS Operation—Device is powered
on and unlockable input data, other than static 1
or 0, is present
400 ppm of N × REFCLK
The VSC8223 has a number of internally isolated power and ground busses. The V
and V
busses are used for
SSA
DDA
the internal analog sections. For optimum performance, the V
filtered from the other busses.
and V
busses should be isolated and separately
SSA
DDA
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Datasheet
ELECTRICAL SPECIFICATIONS
Specifications listed in the following tables are guaranteed over the recommended operating conditions listed in
Table 22, page 19, unless otherwise noted.
DC Characteristics
The following tables show the DC characteristics for the VSC8223 device.
Table 11: High-Speed Inputs (SDI, SDI)
Symbol Parameter
Minimum
Typical
Maximum
Unit
Condition
VSDI_DE Voltage input swing (differential drive)
50
1000
mVp–p
Input signal on both
true and complement
inputs.
VICM
RSDI
Input common-mode voltage
1.2
80
VDD – 0.1
120
V
VIH < VDD.
Input termination resistance (differential)
100
Ω
Table 12: High-Speed Data Outputs (SDO, SDO)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
VSDO
Output data voltage swing
400
500
800
mVp–p
Vp–p swing on true and
complement
outputs. With 50 Ω to
VDD
.
VOCM
RSDO
Output common-mode voltage
VDD – 0.7
40
VDD – 0.1
60
V
With 50 Ω to VDD.
Back-terminated output resistance
50
Ω
Table 13: High-Speed Clock Outputs (SCO/SCO)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
VSCO
Output clock voltage swing
300
500
800
mVp–p
Vp–p swing on true
and complement
output.
VOCM
RSCO
Output common-mode voltage
VDD – 0.7
40
VDD – 0.1
60
V
With 50 Ω to VDD.
Back-terminated output resistance
50
Ω
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Table 14: LVPECL Inputs
Symbol
Parameter
Minimum
Maximum
Unit
Condition
VDE_REFCLK REFCLK input voltage swing
155
650
mVp–p
Input signal on both true and
complement inputs.
(differential). Normal CRU operation.
VSE_REFCLK REFCLK input voltage swing
(single-ended). Normal CRU
operation.
310
1300
mVp–p
Input signal on either true or
complement input with other
input terminated.
VIH_REFCLK
VIL_REFCLK
REFCLK input HIGH voltage
REFCLK input LOW voltage
VDD – 1.165
VDD – 2.0
VDD – 0.70
V
V
VDD – 1.475
Table 15: LVTTL Inputs
Symbol
VIH
Parameter
Minimum
Maximum
3.3
Unit
V
Condition
Input HIGH voltage
Input LOW voltage
2.0
0
IIH = 100 mA
ILL = –100 μA
VIL
0.8
V
Table 16: LVTTL Outputs
Symbol
VOH
Parameter
Minimum
Maximum
VDD
Unit
V
Condition
IOH = 1 mA
IOL = –1 mA
Output HIGH voltage
Output LOW voltage
2.2
0
VOL
0.4
V
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Datasheet
AC Characteristics
The following tables show the AC characteristics for the VSC8223 device.
Table 17: High-Speed Inputs (SDI, SDI)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
DRSDI_NORM
Input data rate, normal CRU
operation
0.125
670
Mbps
STS-12 FEC rate.
t
SDI_R, tSDI_F
Serial data input rise time and
fall time
150
ps
20% to 80%
STS-12/STM-4 (FEC).
See Figure 11, page 18.
Table 18: High-Speed Data Outputs (SDO,SDO)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
DRSDO_NORM
Output data rate, normal CRU
operation
0.125
670
Mbps
STS-12/STM-4 FEC rate
t
SDO_R, tSDO_F Output data rise time and fall
150
ps
%
20% to 80%,
STS-12/STM-4 (FEC).
See Figure 5, page 6.
time
With 50 Ω to VDD
.
DCSDO
Data output duty cycle
45
50
55
Only relevant with 101010
input data patterns. With
50 Ω to VDD
.
Table 19: High-Speed Clock Outputs (SCO/SCO)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
DRSCO_NORM
Output clock rate, normal CRU
operation
0.125
670
MHz
Depends on signal.
t
SCO_R, tSCO_F Output clock rise time and fall
150
ps
%
20% to 80%,
STS-12/STM-4 (FEC).
See Figure 5, page 6.
time
With 50 Ω to VDD
.
DCSCO
Clock output duty cycle
45
50
55
Measured at 50%
crossing of peak-to-peak
voltage. With 50 Ω to VDD
.
Table 20: Clock and Data Recovery
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
JGEN1_CLOCK
Jitter generation
(clock output)(1)
8.5
mUIrms
High-speed clock output
jitter in the appropriate
frequency band. Assumes
1.2 ps rms input data
jitter. With 50 Ω to VDD
.
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Table 20: Clock and Data Recovery (Continued)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
JGEN1_DATA
Jitter generation
(data output)(1)
8.5
mUIrms
High-speed data output
jitter in the appropriate
frequency band. Assume
1.2 ps rms input data
jitter. With 50 Ω to VDD
.
JTOL_12
JTOL_3
JTBW
Jitter tolerance, STS-12(1)
Jitter tolerance, STS-3(1)
Jitter transfer bandwidth(1)
0.15
1.5
15
UI
UI
UI
250 kHz < f < 5 MHz
300 Hz < f < 25 kHz
10 Hz < f < 30 Hz
LBW [1:0] = 0,0.
0.15
1.5
15
UI
UI
UI
65 kHz < f < 1.3 MHz
300 Hz < f < 6.5 kHz
10 Hz < f < 30 Hz
LBW [1:0] = 0,0.
500
kHz
Meets STS-12/STM-4.
Scales linearly for lower
data rates. Bandwidth not
specified in
lock-to-reference modes.
With 50 Ω to
VDD. LBW [1:0] = 0,0.
JTPEAK
tPD
Jitter transfer peaking(1)
0.1
dB
ps
With 50 Ω to VDD.
See Figure 10, page 17.
Data to clock propagation
delay
0
150
Center of output data eye
from rising edge of SCO.
With 50 Ω to VDD
.
tPWR_UP
tSYNC
CRU lock time (on power-up)
50
ms
With 50 Ω to VDD.
CRU lock time
2500
bit times
When input is switched to
a source with the same
data rate. With 50 Ω to
(synchronous switch)
VDD
.
tASYNC
CRU lock time
50
ms
When input is switched to
a source with a different
data rate. With 50 Ω to
(asynchronous switch)
VDD
.
tLREF
LOCK-to-REFCLK switch time
100
100
µs
Time after assertion of
LOS for clock output to be
valid. With 50 Ω to VDD
.
tLREF_REC
Recover from
LOCK-to-REF-CLK switch
time
μs
Time after deassertion of
LOS for valid clock and
data. With 50 Ω to VDD
.
1. Jitter generation, tolerance, transfer, and peaking specifications measured using SONET methodologies.
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Slope = –20 dB/decade
15 UIpp
1.5 UIpp
0.15 UIpp
10 Hz
30 Hz
300 Hz
25 kHz
250 kHz
Figure 9. STS-12 SONET Jitter Tolerance Mask
fC
STS-n/STS-n
Slope = –20 dB/decade
Level
(kHz)
0.1
3
130
500
12
Acceptable
Range
fC
Frequency (kHz)
Figure 10. SONET Jitter Transfer Mask
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Table 21: LVPECL Inputs
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Condition
fREFCLK
REFCLK input frequency,
normal CRU operation
14.8
169
MHz
Maximum is STS-12 FEC
rate.
tREFCLK_R,
tREFCLK_F
REFCLK rise time and fall
times, normal CRU operation
250
100
ps
20% to 80%. See Figure 11.
REFCLK = 155 MHz.
fREFCLK_TOL
REFCLK frequency tolerance,
normal CRU operation
–100
40
ppm
20 ppm required to meet
SONET/SDH specifications
when in LOCK to REFCLK
mode.
DCREFCLK
JREFCLK
REFCLK input duty cycle
REFCLK input jitter
50
60
%
Measured at 50% crossing of
peak-to-peak voltage.
1.2
ps rms
tR
tF
VSC8223
80%
80%
VICMmax
VICMmin
a
20%
20%
Unit Interval (UI)
CML
Input
Receiver
tR
tF
80%
80%
V
ICMmax
b
VICMmin
20%
20%
Unit Interval (UI)
If used differentially (true and complement), each signal should meet the requirements for a = b = VA_DE
If used single-ended (true only), the value required is a = 2 x VA_DE
.
.
Figure 11. Input Parametric Symbol Definitions
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Operating Conditions
The following table shows the recommended operating conditions for the VSC8223 device.
Table 22. Recommended Operating Conditions
Symbol
VDD
Parameter
Minimum
Typical
Maximum
2.625
181
Unit
V
Condition
Power supply voltage
Power supply current
Power supply current
Power dissipation
2.375
2.5
5% tolerance
IDD_SDO
IDD
mA
mA
mW
mW
°C
217
PTOT_SDO
315
400
475
Clock disabled
Clock enabled
PTOT
Total power dissipation
Operating temperature(1)
570
T
–20
85
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
Stress Ratings
This section contains the stress ratings for the VSC8223 device.
Stresses listed in the following table may be applied to devices one at a time without causing permanent damage.
Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may
affect device reliability.
Table 23. Stress Ratings
Symbol
Parameter
Minimum
–0.5
Maximum
3.8
Unit
V
VDD
Power supply voltage
DC input voltage (differential)
DC input voltage (TTL)
–0.5
VCC + 0.5
5.5
V
–0.5
V
DC output voltage (TTL)
–0.5
VCC + 0.5
50
V
Output current (differential and TTL)
Electrostatic discharge voltage, charged device model
Electrostatic discharge voltage, human body model
–50
mA
V
VESD_CDM
VESD_HBM
–500
–250
500
250
V
ELECTROSTATIC DISCHARGE
This device can be damaged by ESD. Vitesse recommends that all integrated circuits
be handled with appropriate precautions. Failure to observe proper handling and
installation procedures may adversely affect reliability of the device.
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PIN DESCRIPTIONS
This sections contains the pin diagram and pin descriptions for the VSC8223 device.
Pin Diagram
The VSC8223 device has 48 pins as shown in the following diagram.
NC(1)
VSS
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VDD
SDO
SDO
VDD
VSS
VSS
VDD
SCO
SCO
VDD
VSS
VDD
3
SDI
4
VTT
5
SDI
6
VSC8223
VDD
7
Top View
VSS
8
RCLK_FSEL0
RCLK_FSEL1
RCLK_SEL
NC(1)
9
10
11
12
(1) No Connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either
the positive or negative supply rails or a logic level driver may cause improper operation or failure of the device;
or in extreme cases, may cause permanent damage to the device.
Figure 12. Pin Diagram
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Pin Identifications
This section contains detailed pin descriptions for the VSC8223 device.
Table 24: Pin Identification for 48-Pin LQFP
Pin Number
Signal Name
NC
I/O
Level
LVTTL
Power
Power
CML
Description
No connect(1)
Ground.
1
2
3
4
5
I
.
VSS
VDD
2.5 V power supply
SDI
I
I
High-speed serial input, true.
VTT
Analog/
Power
High-speed input data termination voltage. One option is to
bypass to VDD with a capacitor. Direct connection to a supply
V
SS <= VTERM <= VDD is also allowed as long as input
common-mode levels are maintained within limits specified in
Table 11, page 13.
6
7
SDI
VDD
CML
High-speed serial input, complement.
2.5 V power supply.
Power
Power
LVTTL
LVTTL
LVTTL
8
VSS
Ground.
9
RCLK_FSEL0
RCLK_FSEL1
RCLK_SEL
I
I
I
Reference clock rate select pin. Default: LOW (0).
Reference clock rate select pin. Default: LOW (0).
10
11
Reference clock select pin. Default: LOW (0). When LOW (0),
select REFCLK0/REFCLK0; when HIGH (1), select REFCLK1/
REFCLK1.
12
13
14
15
16
17
18
19
NC
Not connected(1)
.
REFCLK0
REFCLK0
REFCLK1
REFCLK1
VDD
I
I
I
I
LVPECL
LVPECL
LVPECL
LVPECL
Power
Reference clock 0, true.
Reference clock 0, complement.
Reference clock 1, true.
Reference clock 1, complement.
2.5 V power supply.
VSS
Power
Ground.
LOS
O
LVTTL
When HIGH, indicates no serial data input signals. It may trigger
the automatic lock-to-reference clock based on LREF_DIS.
20
21
22
23
24
25
26
27
28
29
30
31
LOL
NOREF
NC
O
O
LVTTL
LVTTL
When HIGH, indicates the device lost lock-to-reference clock.
When HIGH, indicates no reference clock is provided.
No connect(1)
No connect(1)
No connect(1)
Ground.
.
.
.
NC
NC
VSS
VDD
SCO
SCO
VDD
VSS
VSS
Power
Power
2.5 V power supply.
O
O
High-speed clock serial clock output, complement.
High-speed clock serial clock output, true.
Power
Power
Power
2.5 V power supply.
Ground.
Ground.
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Table 24: Pin Identification for 48-Pin LQFP(Continued)
Pin Number
Signal Name
I/O
Level
Description
32
VDD
Power
2.5 V power supply.
33
34
35
36
37
SDO
SDO
O
O
CML
CML
High-speed serial data output, complement.
High-speed serial data output, true.
2.5 V power supply.
VDD
Power
Power
LVTTL
VSS
Ground.
LREF_DIS
I
I
Default: LOW (0). When HIGH (1), disables the automatic lock to
reference clock function. Manual lock-to-reference clock function
using LREF is still enabled.
38
39
40
LREF
LBW0
LBW1
LVTTL
Default: LOW (0). When HIGH (1), enables the force
lock-to-reference clock function.
Default: Leave unconnected. Optional: Connect to VDD for loop
bandwidth control.
Default: Leave unconnected. Optional: Connect to VDD for loop
bandwidth control.
41
42
43
44
45
FILT
SCO_EN
VSSA
Analog
LVTTL
Power
Power
LVTTL
Connected to an external PLL 1 µF capacitor.
Default: HIGH (1). When LOW (0), clock output is disabled.
Ground for VCO.
I
I
VDDA
Power supply for VCO.
FC_SEL
Default: LOW (0). When HIGH (1), PLL/VCO runs at 2.125 GHz
(Fibre Channel rate). When LOW (0), runs at 2.488 GHz.
46
VDD
Power
2.5 V power supply.
47
48
STS12/3
TEST
I
I
LVTTL
LVTTL
Input data rate select pin. Default: LOW(0). Selects between the
STS-12 and STS-3 data rates.
Default: LOW (0), normal operation. When HIGH (1), enter test
mode.
1. No connect (NC) pins must be left unconnected or floating. Connecting any of these pins to either the positive or negative power
supply rails or a logic level driver may cause improper operation or failure of the device, or in extreme cases, cause permanent
damage to the device.
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PACKAGE INFORMATION
The VSC8223 is available in two package types. VSC8223RV is a 48-pin, plastic low-profile quad flat package
(LQFP) with an exposed pad, 7 mm × 7 mm body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.60 mm
maximum height. The device is also available in a lead(Pb)-free package, VSC8223XRV.
Lead(Pb)-free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and JEDEC
standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the VSC8223
device.
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Package Drawing
Notes:
1.
2.
3.
All dimensions and tolerances are in
millimeters (mm).
Dimensions shown are normal with
tolerances as indicated.
Foot length “L” is measured at gage plane,
at 0.25 above the seating plane.
Figure 13. Package Drawing
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Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using
a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information,
see the JEDEC standard.
Table 25. Thermal Resistances
θJA (°C/W) vs. Airflow (ft/min)
Part Order Number
VSC8223RV
θJC
3.6
3.6
θJB
28
0
100
43.5
43.5
200
46.5
46.5
40.2
40.2
VSC8223XRV
28
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described
in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the
following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment
Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
Moisture Sensitivity
Moisture sensitivity level ratings for Vitesse products comply with the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020.
VSC8223RV is rated moisture sensitivity level 3 or better.
VSC8223XRV is rated moisture sensitivity level 4.
For more information, see the IPC and JEDEC standard.
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ORDERING INFORMATION
The VSC8223 is available in two package types. VSC8223RV is a 48-pin, plastic low-profile quad flat package
(LQFP) with an exposed pad, 7 mm × 7 mm body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.60 mm
maximum height. The device is also available in a lead(Pb)-free package, VSC8223XRV.
Lead(Pb)-free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and JEDEC
standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
The following table lists the ordering information for the VSC8223 device.
VSC8223 Extended Multirate STS-12, STS-3, and FEC Clock and Data Recovery IC
Part Number
Description
VSC8223RV
48-pin, plastic LQFP with an exposed pad, 7 mm × 7 mm body size, 1.4 mm body thickness, 0.5 mm pin
pitch and 1.60 mm maximum height
VSC8223XRV
Lead(Pb)-free, 48-pin, plastic LQFP with an exposed pad, 7 mm × 7 mm body size, 1.4 mm body thickness,
0.5 mm pin pitch, and 1.60 mm maximum height
CORPORATE HEADQUARTERS
Vitesse Semiconductor Corporation
741 Calle Plano
Camarillo, CA 93012
Tel: 1-800-VITESSE
·
FAX:1-(805) 987-5896
For application support, latest technical literature, and locations of sales offices,
please visit our web site at
www.vitesse.com
Copyright © 2002, 2007 by Vitesse Semiconductor Corporation
PRINTED IN THE U.S.A
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or manufactura-
bility. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without
notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore,
the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer.
Vitesse products are not intended for use in life support products where failure of a Vitesse product could reasonably be expected to result in death or personal
injury. Anyone using a Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully
indemnify Vitesse for any damages that may result from such use or sale.
Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and
may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their
respective holders.
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相关型号：
VSC8238
10.3125 Gbps Advanced Electronic Equalization with Limiting Amplifier, and Clock and Data Recovery
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