VSC8658HJ [MICROSEMI]
Octal 10/100/1000BASE-T PHY and 100BASEFX/1000BASE-X SerDes;
| 型号： | VSC8658HJ |
| 厂家： | 
Microsemi |
| 描述： | Octal 10/100/1000BASE-T PHY and 100BASEFX/1000BASE-X SerDes 局域网（LAN）标准 |
| 文件： | 总95页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VSC8658 Datasheet
Octal 10/100/1000BASE-T PHY and 100BASE-
FX/1000BASE-X SerDes
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
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About Microsemi
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subsidiary of Microchip Technology Inc. All
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and service marks are the property of their
respective owners.
Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of
semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and
ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's
standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and
midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.
VMDS-10242. 4.1 11/18
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1
4.1.2
4.1.3
SerDes MAC-to-Cat5 Mode MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SGMII MAC-to-Cat5 Mode MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
All Modes Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SGMII MAC-to-100BASE-FX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Media-Sense (AMS) Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Cat5 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Manual MDI/MDI-X Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transformerless Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12.2 Link Partner Wake-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.12.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13
4.14
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13.2 SMI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.2 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.3 Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15
4.16
GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.1 Ethernet Packet Generator (EPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16.6 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.16.7 IEEE 1149.1 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.16.8 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.16.9 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VMDS-10242 VSC8658 Datasheet Revision 4.1
iii
4.17
IEEE 1149.6 AC-JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.1
5.1.2
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reserved Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
IEEE Standard and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Auto-Negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Link Partner Auto-Negotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auto-Negotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Transmit Auto-Negotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Auto-Negotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.11 Main Registers Reserved Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.12 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.13 100BASE-TX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.14 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.15 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.16 Reserved Main Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.17 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.18 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2.19 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.20 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.21 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.22 MAC Interface Auto-Negotiation Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.23 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.24 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.25 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3
Extended Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SerDes MAC/Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SIGDET Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
EEPROM Interface Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
EEPROM Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.10 VeriPHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.11 VeriPHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.12 VeriPHY Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.13 Reserved Extended Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.14 Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.15 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4
5.5
General-Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
Reserved GPIO Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SIGDET vs GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
100BASE-FX Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.1
5.5.2
CMODE Pins and Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Functions and Related CMODE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VMDS-10242 VSC8658 Datasheet Revision 4.1
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5.5.3
CMODE Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.6
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6.1
5.6.2
EEPROM Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Read/Write Access to the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
VDDIO at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VDDIO at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VDDIO at 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VDD at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MAC and SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MAC and SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2
6.3
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4
6.5
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.1
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.2
Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.1
8.2
8.3
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.1
9.2
9.3
9.4
9.5
PHY Address ID (Register 23E, Bits 15 to 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
JTAG Input High Voltage at 2.1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
First SMI Write Fails After Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LED3 Port 7 Coupling Issue into XTAL Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
100BASE-FX Clock Data Recovery Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
High-level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MDINT_n Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MDINT_n Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Test Access Port and Boundary Scan Architecture Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EEPROM Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SMI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Pin Diagram, Left Side, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin Diagram, Right Side, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Mode vs. Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LED Serial Stream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JTAG Device Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
JTAG Interface Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IEEE 802.3 Standard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Device Auto-Negotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Auto-Negotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auto-Negotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auto-Negotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Auto-Negotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
100BASE-TX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MAC Auto-Negotiation Control and Status, Address 27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Available LED Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Extended Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Extended Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SerDes Media Auto-Negotiation Control/Status, Address 16E (0x10) . . . . . . . . . . . . . . . . . . . . . . 46
SerDes MAC Control, Address 17E (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CRC Good Counter, Address 18E (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SIGDET Polarity Control, Address 19E (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Extended PHY Control 3, Address 20E (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
EEPROM Interface Status and Control, Address 21E (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
EEPROM Read or Write, Address 22E (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended PHY Control 4, Address 23E (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VeriPHY Control Register 1, Address 24E (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
VeriPHY Control Register 2, Address 25E (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
VeriPHY Control Register 3, Address 26E (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VeriPHY Control Register 3 Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EPG Control Register 1, Address 29E (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EPG Control Register 2, Address 30E (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
General-Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SIGDET vs GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
100BASE-FX Control, Address 18G (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CMODE Configuration Pins and Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Device Functions and Associated CMODE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CMODE Resistor Values and Resultant Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EEPROM Configuration Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC Characteristics for Pins Referenced to VDDIO at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DC Characteristics for Pins Referenced to VDDIO at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DC Characteristics for Pins Referenced to VDDIO at 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DC Characteristics for Pins Referenced to VDD33 at 3.30 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . 63
DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DC Characteristics for LED[3:0]_n Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DC Characteristics for JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Current Consumption in SerDes/SGMII to 1000BASE-X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Consumption in SerDes/SGMII to 100BASE-FX or SerDes Pass-Through Mode . . . . . . . . . . . . . 65
AC Characteristics for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Characteristics for REFCLK Input with 25 MHz Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Characteristics for the CLKOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Characteristics for the JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AC Characteristics for the SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AC Characteristics for Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Characteristics for Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
GPIO and SIGDET Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power Supply and Associated Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VMDS-10242 VSC8658 Datasheet Revision 4.1
viii
Revision History
1
Revision History
This section describes the changes that were implemented in this document. The changes are listed by
revision, starting with the most current publication.
1.1
1.2
Revision 4.1
Revision 4.1 of this datasheet was published in June 2007. In revision 4.1, design consideration issues
were added. For more information, see LED3 Port 7 Coupling Issue into XTAL Clock Pin, page 85 and
100BASE-FX Clock Data Recovery Improvement, page 85.
Revision 4.0
Revision 4.0 of this datasheet was published in March 2007. The following is a summary of the changes
implemented in the datasheet:
•
•
•
•
In register 0, the definitions for bits 13 and 6 (forced speed selection) were combined, because they
are correlated.
Throughout the electrical specifications, all references to VDD33A were corrected to VDD33 and all
references to VDDIG were corrected to VDD12
.
In the DC characteristics for VDDIO at 1.8 V, the condition for the output low voltage parameter
(VOL) was corrected from a negative value (IOL = –0.5 mA) to a positive value (IOL = 0.5 mA).
In the DC characteristics for VDD33 at 3.30 V, the output leakage (IOLEAK) was changed to match
the same values as the input leakage (IILEAK) with the same condition (internal resistor included).
Specifically, the values were changed from –10 µA minimum and 10 µA maximum to –42 µA
minimum and 42 µA maximum.
•
•
•
In the DC characteristics for MAC_RDP/N_n and SER_DOP/N_n pins, the total jitter parameter (TJ)
was updated from 160 ps typical to 185 ps typical and from 180 ps maximum to 260 ps maximum.
In the DC characteristics for MAC_TDP/N_n and SER_DIP/N_n pins, the input differential voltage
parameter (VIDIFF) was updated from 1400 mV maximum to 2400 mV maximum.
For better organization, the total receive jitter tolerance parameter (JRXTotal) was moved from the
MAC_RDP/N_n and SER_DOP/N_n pin characteristics to the MAC_TDP/N_n and SER_DIP/N_n
pin characteristics. The values were also updated to account for differences between 1000BASE-X
and 100BASE-FX modes.
•
In the DC characteristics for LED pins, a qualifier in the introductory paragraph was removed stating
that these specifications are valid only when a voltage range of 1.3 V to 2.3 V is applied to the LED
pins. For the low voltage parameter (VOL), the condition was corrected from a negative value (IOL
–4.0 mA) to a positive value (IOL = 4.0 mA). The output low current drive strength parameter (IOL
=
)
was updated from 4.0 mA maximum to 8.0 mA maximum. The maximum value for the output high
current drive strength parameter (IOH) was removed.
•
•
•
The current consumption specifications previously named 1000BASE-X/100BASE-FX mode are
now named 1000BASE-X mode. The current consumption specifications previously named
1000BASE-X mode are now named 100BASE-FX or SerDes pass-through mode.
The current consumption specifications were updated for 100BASE-FX or SerDes pass-through
mode (previously named 1000BASE-X mode). All of the parameters were updated, except for the
IVDDIO parameters, which remain the same.
In the stress ratings, for the DC input voltage on both the VDD12 and VDD12A supply pins, the
maximum was updated from 1.5 V to 1.4 V. The electrostatic discharge voltage values were added.
For charged device model, it was specified ±250 V. For human body model, it was specified as
meeting a Class 2 rating.
•
•
•
For the serial management interface (SMI) pins, it was clarified that EECLK and EEDAT are
referenced to VDD33, not VDDIO.
The moisture sensitivity was specified as level 3 for the VSC8658HJ package. For the lead(Pb)-free
package, VSC8658XHJ, it was specified as level 4.
Design consideration issues were added.
VMDS-10242 VSC8658 Datasheet Revision 4.1
1
Revision History
1.3
Revision 2.0
Revision 2.0 of this datasheet was published in November 2006. This was the first publication of the
document.
VMDS-10242 VSC8658 Datasheet Revision 4.1
2
Introduction
2
Introduction
This document consists of descriptions and specifications for both functional and physical aspects of the
Octal 10/100/1000BASE-T PHY and 100BASE-FX/1000BASE-X SerDes.
In addition to datasheets, the Microsemi website offers an extensive library of documentation, support
files, and application materials specific to each device. The address of the Microsemi website is
www.microsemi.com.
2.1
Register and Bit Conventions
This document refers to registers by their address and bit number in decimal notation. A range of bits is
indicated with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14.
Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least
significant bit.
VMDS-10242 VSC8658 Datasheet Revision 4.1
3
Product Overview
3
Product Overview
The VSC8658 device is a low-power, octal Gigabit Ethernet transceiver with dual, fully integrated
1.25 Gbps SerDes interfaces. It is designed for use in applications, such as multiport switches and
routers, where its compact ball grid array (BGA) packaging, low electromagnetic interference (EMI) line
driver, and integrated line side termination resistors conserve both power and PC board space. Using the
VSC8658 device in your design makes it possible to lower the component count of your PC board, sub-
assembly, or device without sacrificing chip-centric capabilities or utility. This feature can make it less
expensive to produce and more cost-effective to deploy.
Microsemi’s mixed signal and digital signal processing (DSP) architecture—a key operational feature of
the VSC8658 device—assures robust performance even under less-than-favorable environmental
conditions. It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T
communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater
than 140 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient
environment and system electronic noise. This device also supports 100BASE-FX and 1000BASE-X to
connect to fiber modules, such as GBICs and SFPs.
The following illustration shows a high-level, generic view of a VSC8658 application.
Figure 1 • Typical Application
SGMII, SerDes
1.2 V
3.3 V
SerDes
SerDes
Optics / SFP
RJ-45 and Magnetics
Optics / SFP
10/100/1000 Mbps Ethernet MAC
10/100/1000 Mbps Ethernet MAC
VSC8658
Octal
10/100/1000BASE-T
100BASE-FX/1000BASE-X
Gigabit Ethernet
RJ-45 and Magnetics
Transceiver PHY
SerDes
Optics / SFP
10/100/1000 Mbps Ethernet MAC
RJ-45 and Magnetics
3.1
Features and Benefits
This section lists key aspects of the VSC8658 device functionality and design that distinguish it from
similar products.
Table 1 •
Features and Benefits
Feature
Benefit
650 mW per port power consumption (when configured
for 1000BASE-T operation)
Lowers system cost by eliminating the need for extra
heat-dissipating and power-processing components;
simplifies system design
27 mm x 27 mm, 444-pin BGA packaging
Facilitates single row, high port density switch designs
Patented, low EMI line driver with integrated line side
termination resistors
Eliminates the need for as many as 384 passive
components in 48-port switch applications
Auto-Media Sense™ capability configurable per-port
Detects and automatically configures a port for operation
with copper or fiber media; auto-enables
10/100/1000BASE-T fixed media ports, 100BASE-FX
SFPs, 1000BASE-X SFPs, 1000BASE-T SFPs, triple-
speed SFPs, or backplanes
VMDS-10242 VSC8658 Datasheet Revision 4.1
4
Product Overview
Table 1 •
Features and Benefits (continued)
Feature
Benefit
Dual, high-performance, 1.25 Gbps SerDes
Maximizes receive jitter tolerance and minimizes transmit
jitter (in comparison to single SerDes architectures)
Compliance with IEEE standard 802.3 (10BASE-T,
Ensures seamless deployment in devices throughout
100BASE-TX, 1000BASE-T, 1000BASE-X, 100BASE-FX) existing copper networks while maintaining excellent
tolerance to ambient electronic noise and any
substandard cabling
Support for frame sizes greater than 16 kilobytes at all
device throughput settings and programmable
synchronization FIFO buffers
Provides for maximum Jumbo frame sizes on custom
SANs and LANs
Four integrated and programmable LED direct drivers per Eliminates the need for external components, lowers EMI
port, on-chip filtering and support for bi-color LEDs generation, and lowers design cost
Multiple built-in testing facilities, including near-end, far- Lowers system or device development, lowers
end, and connector loopback; Ethernet packet generator deployment costs, and decreases time-to-market
with CRC error counter
Serial LED interface option
Enables design flexibility
Support for the CISCO specification for serial gigabit
media-independent interface version 1.7 (SGMII (v1.7),
for 1000BASE-X MACs, for IEEE standard 1149.1-1999
JTAG boundary scan, and for IEEE standard 1149.6
AC-JTAG scan.
Saves manufacturing and quality assurance costs
VeriPHY™ cable diagnostics
Enables system managers to simplify deployment and
improve Gigabit Ethernet network performance
3.2
Block Diagram
The following illustration shows the primary functional blocks of the VSC8658 device.
VMDS-10242 VSC8658 Datasheet Revision 4.1
5
Product Overview
Figure 2 • High-level Block Diagram
TX VP_A _n
TX VN _A_ n
TX VP_B _ n
TX VN _B _n
TX VP_C _n
TX VN _C _n
TX VP_D _n
TX VN _D _n
10 /100 /
1000 BA SE -T
P C S
10 /100 /
1000 BA SE -T
P M A
M D I
Tw isted P a ir
In terfa ce
M A C_ T DP_ n
M A C_TD N _ n
10 00BASE -X
PC S
1000BASE -X
PM A
SER _D O P _ n
SER _D O N _n
M A C_ R DP_ n
M A C_R D N _ n
M D I
SerD es
In terfa ce
SER _D IP _n
SER _D IN _n
100BASE -FX
PC S
100BASE -FX
PM A
SIG DET_n /
G P IO[7 :0]
1 0/100/100 0BASE -T SFP D ata Path
CM O D E [7 :0]
N R ESET
M DC
M DIO
M D IN T _n
EEDAT
EEC LK
G PIO [15 :8]
X T A L1/R E FC LK
X T A L2
R EF_FILT _A
R E F_R E X T _A
R EF_FILT _B
R E F_R E X T _B
C LK O U T
M a n a g em en t
a n d
P LL
JTA G
Co n tro l In terfa ce
(M IIM )
LED In terfa ce
LED[3 :0]_n
VMDS-10242 VSC8658 Datasheet Revision 4.1
6
Functional Descriptions
4
Functional Descriptions
This section provides detailed information about how the VSC8658 device works, what configurations
and operational features are available, and how to test its function. It includes descriptions of the various
device interfaces and how to set them up.
With the information in this section, you can better determine which device setup parameters you must
access to configure the VSC8658 device to work in your application. There are three ways to configure
the VSC8658 device. You can access and set its internal memory registers, use a combination of the
device CMODE pins and its registers, or configure and connect an external EEPROM to execute a
configuration sequence upon system startup.
For information about VSC8658 device registers, see Configuration, page 26.
For information about the device CMODE pins, see CMODE, page 55.
For information about using an EEPROM with the VSC8658 device, see EEPROM, page 58.
4.1
Operating Modes
With respect to its function in your design, the VSC8658 device can act as the interface between a media
access controller (MAC) and either Category 5 (Cat5) media, 100BASE-FX fiber media, or 1000BASE-X
fiber media. Or, the VSC8658 device can act as a MAC-to-MAC pass-through device to take advantage
of the auto-negotiation feature.
Depending upon the speed of data throughput required in your application, the MAC may be either a
SerDes or an SGMII device, and can also be configured to support twisted pair Cat5 cabling, 100BASE-
FX/1000BASE-X fiber optic cabling, or copper small form factor pluggable (SFP) devices.
As shown in the following table, the operating mode you choose when setting up the VSC8658 device is
a function of which type of MAC is to be connected, which data throughput speeds are required in the
application, and the type of Cat5 media support required.
Table 2 •
Operating Mode vs. Speed
10/100/
1000BASE-X
1000BASE-T
10/100/1000BAS Fiber Optic
100BASE-FX Copper SFP
VSC8658 Mode
E-T Support
Support
Support
Support
SerDes MAC-to-Cat5 Link Partner
1000BASE-T
only
SGMII MAC-to-Cat5 Link Partner
Yes
SerDes MAC-to-SerDes with Auto-Negotiation
Yes
1000BASE-T
only
SGMII MAC-to-SerDes with Auto-Negotiation
SerDes MAC-to-SerDes with Pass-Through
Yes
1000BASE-T
only
Yes(1)
Yes(1)
1000BASE-T
only(1)
SGMII MAC-to-SGMII with Pass-Through
SGMII MAC-to-100BASE-FX
Yes(1)
Yes
Yes
SerDes MAC with Automatic Media Sensing
(AMS) and Auto Negotiation
1000BASE-T
Only
Yes
Yes
SGMII MAC with AMS
Yes
VMDS-10242 VSC8658 Datasheet Revision 4.1
7
Functional Descriptions
Table 2 •
Operating Mode vs. Speed (continued)
10/100/
1000BASE-T
1000BASE-X
10/100/1000BAS Fiber Optic
100BASE-FX Copper SFP
VSC8658 Mode
E-T Support
Support
Support
Support
SerDes MAC with AMS and Pass-Through
1000BASE-T
Only
Yes(1)
1000BASE-T
only(1)
SGMII MAC with AMS and Pass-Through
Yes
Yes(1)
Yes(1)
1. The MAC used must be capable of supporting this media.
4.1.1
SerDes MAC-to-Cat5 Mode MAC Interface
When connected to a SerDes MAC, the VSC8658 device provides data throughput at a rate of
1000 Mbps only; 10 Mbps and 100 Mbps rates are not supported. To configure the device for operation in
this mode, select the 1000BASE-T-only setting in the registers, using the CMODE pin, or in the external
EEPROM startup sequence.
For information about using the device registers to configure the VSC8658 device for operation in
SerDes MAC-to-Cat5 mode, see Mode Control, page 28.
For information about the device CMODE pins, see CMODE, page 55.
For information about using an EEPROM with the VSC8658 device, see EEPROM, page 58.
The following illustration shows a typical connection of the VSC8658 device to a SerDes MAC.
Figure 3 • SerDes MAC Interface
TDP
MAC_TDP
100 Ω
or
150 Ω
TDN
MAC_TDN
VSC8658
PHY Port_n
SerDes MAC
0.1 µF
0.1 µF
RDP
MAC_RDP
100 Ω
or
150 Ω
100 Ω
or
150 Ω
RDN
MAC_RDN
4.1.2
SGMII MAC-to-Cat5 Mode MAC Interface
When configured to detect and switch between 10BASE-T, 100BASE-T, and 1000BASE-T data rates, the
VSC8658 device can be connected to an SGMII-compatible MAC.
For information about using the device registers to configure the VSC8658 device for operation in
SerDes MAC-to-Cat5 Mode, see Mode Control, page 28.
For information about the device CMODE pins, see CMODE, page 55.
For information about using an EEPROM with the VSC8658 device, see EEPROM, page 58.
The following illustration shows a typical connection of the VSC8658 device to an SGMII-compatible
MAC.
VMDS-10242 VSC8658 Datasheet Revision 4.1
8
Functional Descriptions
Figure 4 • SGMII MAC Interface
TDP
MAC_TDP
100 Ω
or
150 Ω
TDN
MAC_TDN
TCP
TCN
VSC8658
PHY Port_n
SGMII MAC
0.1 µF
0.1 µF
RDP
RDN
MAC_RDP
100 Ω
100 Ω
or
150 Ω
or
150 Ω
MAC_RDN
4.1.3
All Modes Cat5 Media Interface
The VSC8658 device twisted pair interface is compliant with the IEEE standard 802.3-2000. Unlike many
other gigabit PHYs, the VSC8658 device uses fully integrated, passive components (required to connect
the PHY’s Cat5 interface to an external 1:1 transformer). The following illustration shows the
connections.
Figure 5 • Cat5 Media Interface
TXVP_A_n
1
2
A+
A–
0.1 µF
0.1 µF
TXVN_A_n
B+
B–
3
6
TXVP_B_n
Transformer
TXVN_B_n
VSC8658
RJ-45
PHY Port_n
4
5
C+
C–
TXVP_C_n
0.1 µF
0.1 µF
TXVN_C_n
7
8
D+
D–
TXVP_D_n
TXVN_D_n
75 Ω
75 Ω
75 Ω
75 Ω
1000 pF, 2 kV
VMDS-10242 VSC8658 Datasheet Revision 4.1
9
Functional Descriptions
4.2
SerDes Media Interface
The VSC8658 device SerDes Media Interface performs data serialization and deserialization functions
using an integrated SerDes block. The interface operates at 1.25 Gbps speed, providing full-duplex and
half-duplex 1000 Mbps bandwidth that can connect directly to 100BASE-FX/1000BASE-X-compliant
optical devices as well as to 10/100/1000BASE-T copper SFP devices. The interface can be operated in
two SerDes modes:
•
•
SerDes with Media Interface PCS Auto-Negotiation mode
SerDes with Pass-Through mode
The SerDes with Media Interface PCS Auto-Negotiation mode supports IEEE standard 802.3, clauses 36
and 37, which describe fiber auto-negotiation. In this mode, control and status of the SerDes media is
displayed in the VSC8658 device registers 0 through 15 in a manner similar to what is described in the
IEEE standard 802.3, clause 28. In this mode, connected copper SFPs can only operate at 1000BASE-T
speed. A link in this mode is established using auto-negotiation (enabled or disabled) between the PHY
and the link partner.
For information about how the VSC8658 LEDs operate in this mode, see LED Behavior, page 19.
SerDes with Pass-Through mode is a feature that links a fiber module or copper SFP directly to the
SerDes interface of the MAC through the VSC8658 device. For example, to support 10/100/1000 copper
SFPs, the MAC must be able to operate in SGMII mode. Because the MAC controls the establishment of
the link, PHY registers 0 through 15 and the PHY LEDs do not indicate link information when in SerDes
Pass-Through Mode. In this case, the only supported LED operation is the force on and force off modes.
A pass-through link is established when the SIGDET pin is asserted.
4.3
4.4
SGMII MAC-to-100BASE-FX Mode
The VSC8658 can support the 100BASE-FX communication speed to connect to fiber modules, such as
GBICs and SFPs.
This capability is facilitated by using the connections on the SerDes pins when connected to a MAC
through SGMII. Ethernet Package Generator (EPG), cyclical redundancy checking (CRC) counters, and
loopback modes are supported in the 100BASE-FX over SerDes mode. For information about how the
VSC8658 LEDs operate in this mode, see LED Behavior, page 19.
For information about how to configure the VSC8658 in 100BASE-FX mode using the twisted pair
interface, see 100BASE-FX Control, page 54.
Automatic Media-Sense (AMS) Interface Mode
This mode can automatically set the media interface to Cat5 or to SerDes interface modes automatically.
The active media mode chosen is based on the automatic media-sense (AMS) preferences set in the
device register 23, bit 11.
The following illustration shows a block diagram of the AMS functionality in the VSC8658 device.
VMDS-10242 VSC8658 Datasheet Revision 4.1
10
Functional Descriptions
Figure 6 • Automatic Media Sense Block Diagram
VSC8658 port_n
Cat5
MAC
SGMII /
Serial MAC
Auto Sense
Logic
TD
RD
SerDes
SIGDET
Fiber Optic
Module
When both SerDes and Cat5 media interfaces attempt to establish a link, the preferred media interface
overrides a link-up of the non-preferred media interface. For example, if the preference is set for SerDes
mode and Cat5 media establishes a link, then Cat5 becomes the active media interface. However, after
the SerDes media interface establishes a link, the Cat5 interface drops its link because the preference
was set for SerDes mode. In this scenario, the SerDes preference determines the active media source
until the SerDes link is lost. Also, Cat5 media cannot link up unless there is no SerDes media link
established.
The following table lists the available AMS preferences.
Table 3 •
AMS Media Preferences
Cat5 Linked,
SerDes Linked,
Both Cat5 and
Preference Cat5 Linked,
SerDes Linked,
SerDes Attempts Cat5 Attempts to SerDes Attempt
Setting
SerDes
Cat5
Fiber Not Linked Cat5 Not Linked to Link
Link
to Link
SerDes
Cat5
Cat5
Cat5
SerDes
SerDes
SerDes
Cat5
SerDes
Cat5
The status of the media mode selected by the AMS can be read from device register 20E, bits 7:6. It
indicates whether copper media, SerDes media, or no media is selected.
Each PHY has two auto-media sense modes. The difference between the modes is based on the SerDes
media modes:
•
•
SerDes with Auto-Negotiation
SerDes with Pass-Through
For more information about SerDes media mode functionality with AMS enabled, see SerDes Media
Interface, page 10.
For AMS with SerDes auto-negotiation, the status and control of both the Cat5 and the SerDes media
can be made using registers 0 through 15. For AMS with SerDes pass-through, only the Cat5 interface
can have its interface control and status monitored. The SerDes media must then be controlled and
monitored within the MAC.
4.5
Cat5 Auto-Negotiation
The VSC8658 device supports twisted pair auto-negotiation as defined by clause 28 of the IEEE
standard 802.3-2000.
The auto-negotiation process consists of the evaluation of the advertised capabilities of the PHY and its
link partner to determine the best possible operating mode, throughput speed, duplex configuration, and
master or slave operating modes in the case of 1000BASE-T setups. Auto-negotiation also allows a
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Functional Descriptions
connected MAC to communicate with its link partner MAC through the VSC8658 device using optional
“next pages,” which set attributes that may not otherwise be defined by the IEEE standard.
In installations where the Cat5 link partner does not support auto-negotiation, the VSC8658 automatically
switches to use parallel detection to select the appropriate link speed.
Clearing VSC8658 device register 0, bit 12 disables clause 28 twisted-pair auto-negotiation. If auto-
negotiation is disabled, the state of register bits 0.6, 0.13, and 0.8 determine the device operating speed
and duplex mode. For more information about configuring auto-negotiation, see IEEE Standard and Main
Registers, page 27.
4.6
Manual MDI/MDI-X Setting
As an alternative to Auto MDI/MDI-X detection, you can force the PHY to be MDI or MDI-X using the
following scripts.
Format:
Phywrite ( register(dec), data(hex) )
Phywritemask ( register(dec), data(hex), mask(hex) )
To force MDI:
Phywrite ( 31, 0x2A30 )
Phywritemask ( 5, 0x0010, 0x0018 )
Phywrite ( 31, 0x0000 )
To force MDI-X:
Phywrite ( 31, 0x2A30 )
Phywritemask ( 5, 0x0018, 0x0018 )
Phywrite ( 31, 0x0000 )
To resume MDI/MDI-X setting based on register 18, bits 7 and 5:
Phywrite ( 31, 0x2A30 )
Phywritemask ( 5, 0x0000, 0x0018 )
Phywrite ( 31, 0x0000 )
4.7
Automatic Crossover and Polarity Detection
For trouble-free configuration and management of Ethernet links, the VSC8658 device includes a robust,
automatic, media-dependent and crossed media-dependent detection feature, Auto MDI/MDI-X, in all of
its three available speeds (10BASE-T, 100BASE-T, and 1000BASE-T). The function is fully compliant
with clause 40 of the IEEE standard 802.3-2002.
Additionally, the device detects and corrects polarity errors on all MDI pairs—a useful capability that
exceeds the requirements of the standard.
Both auto MDI/MDI-X detection and polarity correction are enabled in the device by default. You can
change the default settings using device register bits 18.5:4. Status bits for each of these functions are
located in register 28.
The VSC8658 device’s automatic MDI/MDI-X algorithm successfully detects, corrects, and operates with
any of the MDI wiring pair combinations listed in the following table.
Table 4 •
Supported MDI Pair Combinations
RJ-45 Pin Pairings
1, 2
A
3, 6
B
4, 5
C
7, 8
D
Mode
Normal MDI
B
A
D
C
Normal MDI-X
A
B
D
C
Normal MDI with pair swap on C and D pair
Normal MDI-X with pair swap on C and D pair
B
A
C
D
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Functional Descriptions
Note: The VSC8658 device can be configured to perform Auto MDI/MDI-X even when its Auto-negotiation
feature is disabled (setting register 0.12 to 0) and the link is forced into 10/100 speeds. To enable this
feature, set register 18.7 to 0.
4.8
Link Speed Downshift
For operation in cabling environments that are incompatible with 1000BASE-T, the VSC8658 device
provides an automatic link speed “downshift” option. When enabled, the device automatically changes its
1000BASE-T auto-negotiation advertisement to the next slower speed after a set number of failed
attempts at 1000BASE-T.
This is useful in setting up in networks using older cable installations that may include only pairs A and B
and not pairs C and D.
You can configure and monitor link speed downshifting using register bits 20E.4:1. For more information,
see Extended PHY Control Set 1, page 37.
4.9
Transformerless Ethernet
The Cat5 media interface supports 10/100/1000BT Ethernet for backplane applications such as those
specified by the PICMG™ 2.16 and ATCA™ 3.0 specifications for eight-pin channels. With proper AC
coupling, the typical Cat5 transformer can be removed and replaced with capacitors.
4.10 Ethernet Inline Powered Devices
The VSC8658 device can detect legacy inline powered devices in Ethernet network applications. Its
inline powered detection capability can be part of a system that allows for IP-phone and other devices
such as wireless access points to receive power directly from their Ethernet cable, similar to office digital
phones receiving power from a Private Branch Exchange (PBX) office switch over the telephone cabling.
This can eliminate the need for an IP-phone to have an external power supply. It also enables the inline
powered device to remain active during a power outage (assuming the Ethernet switch is connected to
an uninterrupted power supply, battery, back-up power generator, or some other uninterruptable power
source).
For more information about legacy inline powered device detection, visit the Cisco Web site at
www.cisco.com.
The following illustration shows an example of this type of application.
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Functional Descriptions
Figure 7 • Inline Powered Ethernet Switch Diagram
Gigabit Switch
Processor
Control
SMI
SGMII
Interface
Inline,
Power-Over-Ethernet
(PoE)
VSC8658_0
VSC8658_1
VSC8658_n
Power Supply
Transformer
Transformer
Transformer
RJ-45
I/F
RJ-45
I/F
RJ-45
I/F
Cat5
Link
Partner
Link
Partner
Link
Partner
The following procedure describes the process that an Ethernet switch must perform in order to process
inline power requests made by a link partner (LP) that is, in turn, capable of receiving inline power.
1. Enable the inline powered device detection mode on each VSC8658 PHY using its serial
management interface. Set register bit 23E.10 to 1.
2. Ensure that the VSC8658 device Auto-Negotiation Enable bit (register 0.12) is also set to 1. In the
application, the device sends a special Fast Link Pulse (FLP) signal to the LP. Reading register bit
23E.9:8 returns 00 during the search for devices that require Power-over-Ethernet (PoE).
3. The VSC8658 PHY monitors its inputs for the FLP signal looped back by the LP. An LP capable of
receiving PoE loops back the FLP pulses when the LP is in a powered-down state. This is reported
when VSC8658 device register bit 23E.9:8 reads back 01. It can also be verified as an inline power
detection interrupt by reading VSC8658 device register bit 26.9, which should be a 1, and which is
subsequently cleared and the interrupt de-asserted after the read. If an LP device does not loop
back the FLP after a specific time, VSC8658 device register bit 23E.9:8 automatically resets to 10.
4. If the VSC8658 PHY reports that the LP needs PoE, the Ethernet switch must enable inline power
on this port, externally of the PHY.
5. The PHY automatically disables inline powered device detection if the VSC8658 device register bit
23E.9:8 automatically resets to 10, and then automatically changes to its normal auto-negotiation
process. A link is then auto-negotiated and established when the link status bit is set (register bit 1.2
is set to 1).
6. In the event of a link failure (indicated when VSC8658 device register bit 1.2 reads 0), the inline
power should be disabled to the inline powered device external to the PHY. The VSC8658 PHY
disables its normal auto-negotiation process and re-enables its inline powered device detection
mode.
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Functional Descriptions
4.11
IEEE 802.3af PoE Support
The VSC8658 device is also compatible with switch designs that are intended for use in systems that
supply power to Data Terminal Equipment (DTE) by means of the MDI or twisted pair cable, as described
in clause 33 of the IEEE standard 802.3af.
4.12 ActiPHY Power Management
In addition to the IEEE-specified power-down control bit (device register bit 0.11), the device also
includes an ActiPHY™ power management mode for each PHY. This mode enables support for power-
sensitive applications such as laptop computers with Wake-on-LAN™ capability. It utilizes a signal-detect
function that monitors the media interface for the presence of a link to determine when to automatically
power-down the PHY. The PHY “wakes up” at a programmable interval and attempts to “wake-up” the
link partner PHY by sending a burst of FLP over copper media.
The ActiPHY™ power management mode in the VSC8658 device is enabled on a per-port basis during
normal operation at any time by setting register bit 28.6 to 1.
There are three operating states possible when ActiPHY™ mode is enabled:
•
•
•
Low power state
LP wake-up state
Normal operating state (link up state)
The VSC8658 device switches between the low power state and LP wake-up state at a programmable
rate (the default is two seconds) until signal energy has been detected on the media interface pins. When
signal energy is detected, the PHY enters the normal operating state. If the PHY is in its normal operating
state and the link fails, the PHY returns to the low power state after the expiration of the link status time-
out timer. After reset, the PHY enters the low power state.
When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as described. If auto-
negotiation is disabled and the link is forced to use 10BT or 100BTX modes while the PHY is in its low
power state, the PHY continues to transition between the low power and LP wake-up states until signal
energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and
stays in that state even when the link is dropped. If auto-negotiation is disabled while the PHY is in the
normal operation state, the PHY stays in that state when the link is dropped and does not transition back
to the low power state.
The following illustration shows the relationship between ActiPHY states and timers.
Figure 8 • ActiPHY State Diagram
Low Power State
Signal Energy
Detected on the
Connected Media
Sleep Timer
Expires
FLP Burst or
Clause 37 Restart
Signal Sent
Timeout Timer Expires;
Auto-negotiation Enabled
Link Partner
Wake-up State
Normal
Operation
4.12.1 Low Power State
In the low power state, all major digital blocks are powered down. However, the following functionality is
provided:
•
SMI interface (MDC, MDIO, MDINT_n)
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Functional Descriptions
•
CLKOUT
In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low
power state and transitions to the normal operating state when signal energy is detected on the media.
This happens when the PHY is connected to one of the following:
•
•
Auto-negotiation capable link partner
Another PHY in enhanced ActiPHY LP wake-up state
In the absence of signal energy on the media pins, the PHY transitions from the low power state to the
LP wake-up state periodically based on the programmable sleep timer (register bits 20E.14:13). The
actual sleep time duration is randomized from –80 milliseconds (ms) to +60 ms to avoid two linked PHYs
in ActiPHY mode entering a lock-up state during operation.
4.12.2 Link Partner Wake-up State
In this state, the PHY attempts to wake up the link partner. Up to three complete FLP bursts are sent on
alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer, which is set using
register bits 20E.12:11.
In this state, the following functionality is provided:
•
•
SMI interface (MDC, MDIO, MDINT_n)
CLKOUT
After sending signal energy on the relevant media, the PHY returns to the low power state.
4.12.3 Normal Operating State
In this state, the PHY establishes a link with a link partner. When the media is unplugged or the link
partner is powered down, the PHY waits for the duration of the programmable link status time-out timer,
which is set using register bit 28.7 and bit 28.2. It then enters the low power state.
4.13 Serial Management Interface
The VSC8658 device includes an IEEE 802.3-compliant serial management interface (SMI) that is
affected by use of its MDC and MDIO pins. The SMI provides access to device control and status
registers. The register set that controls the SMI consists of 32 16-bit registers, including all required
IEEE-specified registers. Also, there are additional pages of registers accessible using device register
31.
For more information, see Extended Page Registers, page 45.
The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is clocked on the
rising edge of the MDC pin. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending
on the total load on MDIO. An external, 2 kΩ pull-up resistor is required on the MDIO pin.
4.13.1 SMI Frames
Data is transferred over the SMI using 32-bit frames with an optional and arbitrary length preamble. The
following illustrations show the SMI frame format for the read operation and write operation.
Figure 9 • SMI Read Frame
Station Manager Drives MDIO
PHY Drives MDIO
MDC
MDIO
Z
Z
1
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Z
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Data from PHY
Z
Z
Idle Preamble SFD
(optional)
Read
PHY Address
Register Address
to PHY
TA
Idle
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Functional Descriptions
Figure 10 • SMI Write Frame
Station Manager Drives MDIO (PHY tristates MDIO during entire sequence)
MDC
MDIO
Z
Z
1
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Data from PHY
Z
Z
Preamble
(optional )
Idle
SFD
Write
PHY Address
Register Address
to PHY
TA
Idle
The following provides additional information about the terms used in Figure 9 and Figure 10.
Idle During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up resistor
to pull the MDIO node up to a logical 1 state. Because the idle mode should not contain any transitions
on MDIO, the number of bits is undefined during idle.
Preamble By default, preambles are not expected or required. The preamble is a string of ones. If it
exists, the preamble must be at least one bit; otherwise, it may be of an arbitrary length.
Start of Frame (SFD) A pattern of 01 indicates the start of frame. If the pattern is not 01, all following
bits are ignored until the next preamble pattern is detected.
Read or Write Opcode A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits are
not either 01 or 10, all following bits are ignored until the next preamble pattern is detected.
PHY Address The particular VSC8658 responds to a message frame only when the received PHY
address matches its physical address. The physical address is five bits long (4:0). Bits 4:3 are set by the
CMODE pins. Bits 2:0 represent the PHY of the device being addressed.
Register Address The next five bits are the register address.
Turnaround The two bits used to avoid signal contention when a read operation is performed on the
MDIO are called the turnaround (TA) bits. During read operations, the VSC8658 device drives the
second TA bit, a logical 0.
Data The 16-bits read from or written to the device are considered the data or data stream. When data
is read from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge of MDC.
When data is written to the PHY, it must be valid around the rising edge of MDC.
Idle The sequence is repeated.
4.13.2 SMI Interrupts
The SMI also includes an output interrupt signal, MDINT_n, for signaling the station manager when
certain events occur in the PHY. A separate MDINT_n pin is included for each VSC8658 device PHY.
Each MDINT_n pin can be configured for open-drain (active-low) by tying the pin to a pull-up resistor and
to VDDIO. The following illustration shows this configuration.
Figure 11 • MDINT_n Configured as an Open-Drain (Active-Low) Pin
External Pull-up
Resistor at the
VDDIO
Station Managerfor
Open-drain
(Active-low Mode)
PHY_n
Interrupt Pin Enable
(Register 25.15)
MDINT_n
(to the Station
Manager)
MDINT_n
Interrupt Pin Status
(Register 26.15)
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Functional Descriptions
Alternatively, each MDINT_n pin can be configured for open-source (active-high) by tying the pin to a
pull-down resistor and to VSS. The following illustration shows this configuration.
Figure 12 • MDINT_n Configured as an Open-Source (Active-High) Pin
VDDIO
Interrupt Pin Enable
(Register 25.15)
MDINT_n
(to the Station
Manager)
MDINT_n
Interrupt Pin Status
External Pull-down at
the Station Manager
For Open-source
(Register 26.15)
PHY_n
(Active-high Mode)
If only one interrupt pin is required, each MDINT_n pin can be tied together to a single pull-up or pull-
down resistor in a wired-OR configuration.
When a PHY generates an interrupt, the MDINT_n pin is asserted (driven high or low, depending on
resistor connection) if the interrupt pin enable bit (MII register 25.15) is set.
4.14 LED Interface
The VSC8658 device drives up to four LEDs directly for each PHY port. All LED outputs are active-low
and are driven using 3.3 V from the VDD33 power supply. The pins, mainly used to sink the current of the
cathode side of an LED when active, can also supply power to the anode portion of LEDs when not in the
active state. This allows for two LED pins to be used to drive a multi-status, bi-colored LED.
4.14.1 LED Modes
Each LED pin can be configured to display different status information. Set the LED mode either by using
register 29 or the CMODE pin setting. For additional operating flexibility, LED output functions can be set
on a per-port basis.
The modes in the following table are equivalent to the setting used in register 29 to configure each LED
pin. For all LED states, 1 = pin held high (de-asserted), 0 = pin held low (asserted), and the blink/pulse-
stretch is dependent on the LED behavior setting in register 30.
Table 5 •
LED Mode and Function Summary
Mode
Function Name
LED State and Description
0
Link/Activity(1)
1 = No link in any speed on any media interface.
0 = Valid link at any speed on any media interface.
Blink or pulse-stretch = Valid link at any speed on any media interface with
activity present.
1
2
3
Link1000/Activity
Link100/Activity
Link10/Activity
1 = No link in 1000BASE-T.
0 = Valid 1000BASE-T link.
Blink or pulse-stretch = Valid 1000BASE-T link with activity present.
1 = No link in 100BASE-TX.
0 = Valid 100BASE-TX link.
Blink or pulse-stretch = Valid 100BASE-TX link with activity present.
1 = No link in 10BASE-T.
0 = Valid 10BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T link with activity present.
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Functional Descriptions
Table 5 •
LED Mode and Function Summary (continued)
Mode
Function Name
LED State and Description
4
Link100/1000/Activity
1 = No link in 100BASE-TX or 1000BASE-T.
0 = Valid 100BASE-TX or 1000BASE-T link.
Blink or pulse-stretch = Valid 100BASE-TX or 1000BASE-T link with activity
present.
5
6
7
8
Link10/1000/Activity
Link10/100/Activity
1 = No link in 10BASE-T or 1000BASE-T.
0 = Valid 10BASE-T or 1000BASET-T link.
Blink or pulse-stretch = Valid 10BASE-T or 1000BASE-T link with activity
present.
1 = No link in 10BASE-T or 100BASE-TX.
0 = Valid 10BASE-T or 100BASE-TX link.
Blink or pulse-stretch = Valid 10BASE-T or 100BASE-TX link with activity
present.
Link100BASE-FX/
1000BASE-X/Activity
1 = No link in 100BASE-FX or 1000BASE-X.
0 = Valid 100BASE-FX or 1000BASE-X link.
Blink or pulse-stretch = Valid 100BASE-FX or 1000BASE-X link with activity
present.
Duplex/Collision
1 = Link established in half-duplex mode, or no link established.
0 = Link established in full-duplex mode.
Blink or pulse-stretch = Link established in half-duplex mode but collisions are
present.
9
Collision
Activity
1 = No collision detected.
Blink or pulse-stretch = Collision detected.
10
1 = No activity present.
Blink or pulse-stretch = Activity present (becomes TX activity present if register
bit 30.14 is set to 1).
11
100BASE-FX/
1000BASE-X Fiber
Activity
1 = No 100BASE-FX or 1000BASE-X activity present.
Blink or pulse-stretch = 100BASE-FX or 1000BASE-X activity present (becomes
RX activity present if register bit 30.14 is set to 1).
12
13
Auto-Negotiation Fault 1 = No auto-negotiation fault present.
0 = Auto-negotiation fault occurred.
Serial Mode
Serial stream = See Serial LED Mode, page 20. Only relevant on PHY port 0 and
reserved in others.
14
15
Force LED Off
Force LED On
1 = De-asserts the LED.
0 = Asserts the LED.
1. Link/Activity can be configured to only display copper link and disable fiber link status by setting register bits 30.15 to 1.
4.14.2 LED Behavior
Several LED behaviors can be programmed into the VSC8658 device. Use the settings in register 30 to
program LED behavior, which includes the following:
LED Combine Enables an LED to display the status for a combination of primary and secondary
modes. This can be enabled or disabled for each LED pin. For example, a copper link running in
1000BASE-T mode and activity present can be displayed with one LED by configuring an LED pin to
Link1000/Activity mode. The LED asserts when linked to a 1000BASE-T partner and also blinks or
performs pulse-stretch when activity is either transmitted by the PHY or received by the Link Partner.
When disabled, the combine feature only provides status of the selected primary function. In this
example, only Link1000 asserts the LED, and the secondary mode, activity, does not display if the
combine feature is disabled.
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Functional Descriptions
LED Blink or Pulse-Stretch This behavior is used for activity and collision indication. This can be
uniquely configured for each LED pin. Activity and collision events can occur randomly and intermittently
throughout the link-up period. Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED
pin. Pulse-stretch guarantees that an LED is asserted and de-asserted for a specific period of time when
activity is either present or not present. These rates can also be configured using a register setting.
Rate of LED Blink or Pulse-Stretch This behavior controls the LED blink rate or pulse-stretch length
when blink/pulse-stretch is enabled on an LED pin. The blink rate, which alternates between a high and
low voltage level at a 50% duty cycle, can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the
rate can be set to 50 ms, 100 ms, 200 ms, or 400 ms.
LED Pulsing Enable To provide additional power savings, the LEDs (when asserted) can be pulsed at
5 kHz, 20% duty cycle.
Fiber LED Disable This bit controls whether the LEDs indicate the Fiber and Copper status (default) or
the Copper status only.
4.14.3 Serial LED Mode
Optionally, the VSC8658 device can be configured so that access to all its LED signals is available
through two pins. This option is enabled by setting LED0 on PHY0 to Serial LED mode. When the mode
is enabled on PHY0, the device LED[0] pin becomes the serial data pin and the LED[1] pin becomes the
serial clock pin. All other LED pins can still be configured normally. The Serial LED mode clocks the 96
LED status bits on the rising edge of the serial clock.
The LED behavior settings (in device register 30) can also be used in Serial LED Mode. The controls are
used on a per-PHY basis, where the LED combine and LED blink or pulse-stretch setting of LED0_n for
each PHY is used to control the behavior of each bit of the serial LED stream for each corresponding
PHY.
The serial bitstream outputs, 1 through 96, of each LED signal are shown in the following table beginning
with PHY port 0 and ending with PHY port 7. The individual signals can be clocked in the order shown.
Table 6 •
LED Serial Stream Order
PHY0
PHY1
PHY2
PHY3
PHY4
PHY5
PHY6
PHY7
Bit 1.
Bit 13.
Bit 25.
Bit 37.
Bit 49.
Bit 61.
Bit 73.
Bit 85.
Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity Link/Activity
Bit 2.
Bit 14.
Bit 26.
Bit 38.
Bit 50.
Bit 62.
Bit 74.
Bit 86.
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Link1000/
Activity
Bit 3.
Bit 15.
Bit 27.
Bit 39.
Bit 51.
Bit 63.
Bit 75.
Bit 87.
Link100/
Activity
Link100/
Activity
Link100/
Activity
Link100/
Activity
Link100/
Activity
Link100/
Activity
Link100/
Activity
Link100/
Activity
Bit 4. Link10/ Bit 16.
Bit 28.
Link10/
Activity
Bit 40.
Link10/
Activity
Bit 52.
Link10/
Activity
Bit 64.
Link10/
Activity
Bit 76.
Link10/
Activity
Bit 88.
Link10/
Activity
Activity
Link10/
Activity
Bit 5.
Bit 17.
Bit 29.
Bit 41.
Bit 53.
Bit 65.
Bit 77.
Bit 89.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6. Duplex/ Bit 18.
Bit 30.
Bit 42.
Bit 54.
Bit 66.
Bit 78.
Bit 90.
Collision
Duplex/
Collision
Duplex/
Collision
Duplex/
Collision
Duplex/
Collision
Duplex/
Collision
Duplex/
Collision
Duplex/
Collision
Bit 7.
Bit 19.
Bit 31.
Bit 43.
Bit 55.
Bit 67.
Bit 79.
Bit 91.
Collision
Collision
Collision
Collision
Collision
Collision
Collision
Collision
Bit 8. Activity Bit 20.
Activity
Bit 32.
Activity
Bit 44.
Activity
Bit 56.
Activity
Bit 68.
Activity
Bit 80.
Activity
Bit 92.
Activity
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Functional Descriptions
Table 6 •
LED Serial Stream Order (continued)
PHY0
PHY1
PHY2
PHY3
PHY4
PHY5
PHY6
PHY7
Bit 9.
Bit 21.
Bit 33.
Bit 45.
Bit 57.
Bit 69.
Bit 81.
Bit 93.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 10. TX
Activity
Bit 22. TX
Activity
Bit 34. TX
Activity
Bit 46. TX
Activity
Bit 58. TX
Activity
Bit 70. TX
Activity
Bit 82. TX
Activity
Bit 94. TX
Activity
Bit 11. RX
Activity
Bit 23. RX
Activity
Bit 35. RX
Activity
Bit 47. RX
Activity
Bit 59. RX
Activity
Bit 71. RX
Activity
Bit 83. RX
Activity
Bit 95. RX
Activity
Bit 12. Auto- Bit 24. Auto- Bit 36. Auto- Bit 48. Auto- Bit 60. Auto- Bit 72. Auto- Bit 84. Auto- Bit 96. Auto-
Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation Negotiation
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
4.15 GPIO Pins
The VSC8658 provides up to 8 dedicated general-purpose input/output (GPIO) pins. In addition, the
eight device SIGDET pins can also be configured as eight GPIO pins, resulting in a total of 16 GPIO pins.
All device GPIO pins and their behavior are controlled using registers. For more information, see
General-Purpose I/O Registers, page 52.
4.16 Testing Features
The VSC8658 device includes several testing features designed to make it easier to perform system-
level debugging and in-system production testing. This section describes the available features.
4.16.1 Ethernet Packet Generator (EPG)
The device EPG can be used at each of the 10/100/1000BASE-T speed settings for Copper Cat5 media
to isolate problems between the MAC and the VSC8658 device, or between a locally connected PHY
and its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins
and selects the EPG as the source for all data transmitted onto the twisted pair interface.
Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use
the EPG testing feature when the VSC8658 device is connected to a live network.
To enable the VSC8658 device EPG feature, set the device register bit 29E.15 to 1.
When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY.
However, the PHY receive output pins to the MAC are still active when the EPG is enabled. If it is
necessary to disable the MAC receive pins as well, set the register bit 0.10 to 1.
When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet packets based on
the settings in registers 29E and 30E. These registers set:
•
•
•
•
•
•
Source and destination addresses for each packet
Packet size
Inter-packet gap
FCS state
Transmit duration
Payload pattern
If register bit 29E.13 is set to 0, register bit 29E.14 is cleared automatically after 30,000,000 packets are
transmitted.
4.16.2 CRC Counters
Two separate cyclical redundancy checking (CRC) counters are available on all PHYs in the VSC8658
device. There is a 14-bit good CRC counter available in register bits 18E.13:0 and a separate 8-bit
counter available in register bits 23E.7:0.
The device CRC counters operate in the 100BASE-FX/1000BASE-X over SerDes mode as well as in the
10/100/1000BASE-T mode testing as follows:
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Functional Descriptions
•
•
After receiving a packet on the media interface, register bit 18E.15 is set and cleared after being
read. The packet then is counted by either the good CRC counter or the bad CRC counter. Both
CRC counters are also automatically cleared when read.
The good CRC counter’s highest value is 10,000 packets. After it reaches this value, the counter
clears and continues to count additional packets beyond that value. The bad CRC counter stops
counting when it reaches its maximum counter limit of 255 packets.
4.16.3 Far-End Loopback
The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces
incoming data from a link partner on the current media interface to be retransmitted back to the link
partner on the media interface as shown in the following illustration. In addition, the incoming data also
appears on the receive data pins of the MAC interface. Data present on the transmit data pins of the
MAC interface is ignored when using this testing feature.
Figure 13 • Far-End Loopback Diagram
Link Partner
PHY_Port_n
MAC
RX
RXD
TXD
TX
Cat5
4.16.4 Near-End Loopback
When the near-end loopback testing feature is enabled (by setting the device register bit 0.14 to 1), data
on the transmit data pins (TXD) is looped back onto the device receive data pins (RXD), as shown in the
following figure. When using this testing feature, no data is transmitted over the network.
Figure 14 • Near-End Loopback Diagram
Link Partner
PHY Port_n
MAC
RX
RXD
TXD
TX
Cat5
4.16.5 Connector Loopback
The connector loopback testing feature allows the twisted pair interface to be looped back externally.
When using this feature, the PHY must be connected to a loopback connector or a loopback cable. Pair
A should be connected to pair B, and pair C to pair D, as shown in the following figure. The connector
loopback feature functions at all available interface speeds.
Figure 15 • Connector Loopback Diagram
A
RXD
TXD
B
C
Cat5
PHY Port_n
MAC
D
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Functional Descriptions
When using the connector loopback testing feature, the device auto-negotiation, speed, and duplex
configuration is set using device registers 0, 4, and 9. For 1000BASE-T connector loopback, only the
following additional writes are required. Execute the additional writes in the following order:
1. Enable the 1000BASE-T connector loopback. Set register bit 24.0 to 1.
2. Disable pair swap correction. Set register bit 18.5 to 1.
4.16.6 VeriPHY Cable Diagnostics
The VSC8658 device includes a comprehensive suite of cable diagnostic functions that are available
using SMI reads and writes. These functions enable a variety of cable operating conditions and status to
be accessed and checked. The VeriPHY® suite has the ability to identify the cable length and operating
conditions and to isolate a variety of common faults that can occur on the Cat5 twisted pair cabling.
Note: If a link is established on the twisted pair interface in the 1000BASE-T mode, VeriPHY can run without
disrupting the link or disrupting any data transfer. However, if a link is established in 100BASE-TX or
10BASE-T, VeriPHY causes the link to drop while the diagnostics are running. After the diagnostics are
finished, the link is re-established.
The following diagnostic functions are part of the VeriPHY suite:
•
•
•
Detecting coupling between cable pairs
Detecting cable pair termination
Determining cable length
Coupling Between Cable Pairs Shorted wires, improper termination, or high crosstalk resulting from
an incorrect wire map can cause error conditions, such as anomalous coupling between cable pairs. All
these conditions can prevent the device from establishing a link in any speed.
Cable Pair Termination Proper termination of Cat5 cable requires a 100 Ω differential impedance
between the positive and negative cable terminals. The IEEE standard 802.3 allows for a termination of
as high as 115 Ω or as low as 85 Ω. If the termination falls outside of this range, it is reported by the
VeriPHY diagnostics as an anomalous termination. The diagnostics can also determine the presence of
an open or shorted cable pair.
Cable Length When the Cat5 cable in an installation is properly terminated, VeriPHY reports the
approximate cable length in meters.
4.16.7 IEEE 1149.1 JTAG Boundary Scan
The VSC8658 device supports the Test Access Port (TAP) and Boundary Scan Architecture described in
the IEEE standard 1149.1. The device includes an IEEE 1149.1-compliant test interface, often referred to
as a “JTAG TAP Interface.”
The JTAG boundary scan logic on the VSC8658 device, accessed using its TAP interface, consists of a
boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required
signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal NTRST.
The following illustration shows the TAP and Boundary Scan Architecture.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Functional Descriptions
Figure 16 • Test Access Port and Boundary Scan Architecture Diagram
Boundary-Scan Register
Device Identification
Register
Bypass Register
TDO
Mux,
DFF
Control
Instruction Register,
Instruction Decode,
Control
TDI
Control
TMS
Select
Test Access Port
Controller
NTRST
TDO Enable
TCK
After a TAP reset, the device identification register is serially connected between TDI and TDO by
default. The TAP instruction register is loaded either from a shift register (when a new instruction is
shifted in) or, if there is no new instruction in the shift register, a default value of 0110 (IDCODE) is
loaded. Using this method, there is always a valid code in the instruction register, and the problem of
toggling instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
4.16.8 JTAG Instruction Codes
The VSC8658 device supports the following instruction codes:
EXTEST Allows tests of the off-chip circuitry and board-level interconnections by sampling input pins
and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which
have to be updated with valid values (with the PRELOAD instruction) prior to the EXTEST instruction.
SAMPLE/PRELOAD Allows a snapshot of inputs and outputs during normal system operation to be
taken and examined. It also allows data values to be loaded into the boundary-scan cells prior to the
selection of other boundary-scan test instructions.
IDCODE Provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer
identity (bits 11:1) to be serially read from the device.
The following table provides information about the meaning of IDCODE binary values stored in the
device JTAG registers.
Table 7 •
JTAG Device Identification Register Description
Device Version
Manufacturing
Identity
Description
Bit field
Number
31 through 28
0000
Model Number
LSB
27 through 12
11 through 1
0
1
Binary value
1000 0110 0101 1000 001 1001 1000
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Functional Descriptions
CLAMP Allows the state of the signals driven from the component pins to be determined from the
boundary scan register while the bypass register is selected as the serial path between TDI and TDO.
While the CLAMP instruction is selected, the signals driven from the component pins do not change.
HIGHZ Places the component in a state in which all of its system logic outputs are placed in a high-
impedance state. In this state, an in-circuit test system may drive signals onto the connections normally
driven by a component output without incurring a risk of damage to the component. This makes it
possible to use a board where not all of the components are compatible with the IEEE 1149.1 standard.
BYPASS The bypass register contains a single shift-register stage and is used to provide a minimum-
length serial path (one TCK clock period) between TDI and TDO to bypass the device when no test
operation is required.
The following table provides more information about the location and IEEE compliance of the JTAG
instruction codes used in the VSC8658. For more information about these IEEE specifications, visit the
IEEE Web site at www.IEEE.org.
Table 8 •
JTAG Interface Instruction Codes
Register IEEE 1149.1
IEEE 1149.6
Instruction
Code
Selected Register
Boundary-Scan
Boundary-Scan
Width
Specification
Specification
EXTEST
0000
244
Mandatory
SAMPLE/PRELOA 0001
D
244
Mandatory
IDCODE
0110
0010
0011
1111
0100
0101
Device Identification
Bypass Register
32
1
Optional
Optional
Optional
Mandatory
CLAMP
HIGHZ
Bypass Register
1
BYPASS
Bypass Register
1
EXTEST_PULSE
EXTEST_TRAIN
RESERVED
Boundary-Scan Register
Boundary-Scan Register
244
244
Mandatory
Mandatory
0111,
1000 through
1110
4.16.9 Boundary Scan Register Cell Order
All inputs and outputs are observed in the boundary scan register cells. All outputs are additionally driven
by the contents of boundary scan register cells. Bidirectional pins have all three related boundary scan
register cells: input, output, and control.
The complete boundary scan cell order is available as a BSDL file format on the Microsemi Web site at
www.microsemi.com.
4.17 IEEE 1149.6 AC-JTAG Boundary Scan Interface
The IEEE 1149.6 AC-JTAG solution integrated on all SerDes ports of the VSC8658 device extends the
capability of IEEE 1149.1 boundary scan for robust board-level testing. This interface is backward-
compatible to the IEEE 1149.1 standard.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
5
Configuration
The VSC8658 device can be configured using three different methods:
•
•
•
Setting internal memory registers using the management interface
Setting a combination of CMODE pins and registers
Loading a configuration into an external EEPROM and connecting that device so that it writes
configuration information at system startup
5.1
Registers
This section provides information about how to configure the VSC8658 device using its internal memory
registers and the management interface. For information about configuring the device using the CMODE
pins, see CMODE, page 55. For information about setting up an external EEPROM to perform startup
configuration, see EEPROM, page 58.
The VSC8658 device uses three types of registers:
•
•
•
IEEE standard and main device registers with addresses from 0 to 31
Extended registers with addresses from 16E through 30E
General-purpose input and output (GPIO) registers with addresses from 0G to 30G
The following illustration shows the relationship between the device registers and their address spaces.
Figure 17 • Register Space Diagram
0
1
2
3
.
0G
1G
2G
3G
.
.
.
.
.
.
.
.
.
IEEE 802.3
.
Standard Registers
.
.
.
.
.
15
15G
16G
.
.
.
.
.
.
.
.
.
.
.
16
17
18
19
.
.
.
.
.
.
.
.
16E
17E
18E
19E
.
.
.
.
.
.
.
.
GPIO Registers
Main Registers
Extended Registers
30
30E
30G
0x0000
0x0001
0x0010
31
5.1.1
Reserved Registers
For main registers 16 through 31, extended registers 16E through 30E, and GPIO registers 0G through
30G, any bits marked as “Reserved” should be processed as read only and their states as undefined.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
5.1.2
Reserved Bits
In writing to registers with reserved bits, use a “read-modify-then-write” technique, where the entire
register is read but only the intended bits to be changed are modified. Reserved bits cannot be changed
and their read state cannot be considered static or unchanging.
5.2
IEEE Standard and Main Registers
In the VSC8658 device, the page space of the standard registers consists of the IEEE standard registers
and the Microsemi standard registers. The following table lists the names of the registers associated with
the addresses as dictated by the IEEE standard.
Table 9 •
IEEE 802.3 Standard Registers
Register Address Register Name
0
Mode control
1
Mode status
2
PHY identifier 1
3
PHY identifier 2
4
Auto-negotiation advertisement
Auto-negotiation link partner ability
Auto-negotiation expansion
Auto-negotiation next-page transmit
Auto-negotiation link partner next-page receive
1000BASE-T control
1000BASE-T status
Reserved
5
6
7
8
9
10
11
12
13
14
15
Reserved
Reserved
Reserved
1000BASE-T status extension 1
The following table lists the names of the registers in the main page space of the device. These registers
are accessible only when register address 31 is set to 0x0000.
Table 10 • Main Registers
Register Address Register Name
16
17
18
19
20
21
22
23
24
100BASE-TX status extension
1000BASE-T status extension 2
Bypass control
Reserved
Reserved
Reserved
Extended control and status
Extended PHY control 1
Extended PHY control 2
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Configuration
Table 10 • Main Registers (continued)
Register Address Register Name
25
26
27
28
29
30
31
Interrupt mask
Interrupt status
MAC interface auto-negotiation control and status
Auxiliary control and status
LED mode select
LED behavior
Extended register page access
5.2.1
Mode Control
The device register at memory address 0 controls several aspects of VSC8658 functionality. The
following table shows the available bit settings in this register and what they control.
Table 11 • Mode Control, Address 0 (0x00)
Bit
Name
Access Description
R/W This is a self-clearing bit that restores all
Default
15
Software reset
0
serial management interface (SMI) registers
to their default state, except for sticky and
super sticky bits.
1 = Reset asserted.
0 = Reset de-asserted.
You must wait 4 µs after setting this bit to
initiate another SMI register access.
14
Loopback
R/W
1 = Loopback enabled.
0
0 = Loopback disabled.
When loop back is enabled, the device
functions at the current speed setting and
with the current duplex mode setting (bit 8 of
this register).
13
12
LSB for speed
selection
R/W
R/W
See bit 6 below.
0
1
0
Auto-negotiation
enable
1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
11
10
Power-down
Isolate
R/W
R/W
1 = Power-down enabled.
1 = Disable MAC interface outputs and ignore 0
MAC interface inputs.
9
8
Restart auto-
negotiation
R/W
R/W
This is a self-clearing bit.
1 = Restart auto-negotiation on media
interface.
0
Duplex
1 = Full-duplex.
0 = Half-duplex.
0
7
Collision test enable R/W
1 = Collision test enabled.
0
6, 13
Forced speed
selection
R/W
MSB = bit 6, LSB = bit 13.
00 = 10 Mbps.
10
01 = 100 Mbps.
10 = 1000 Mbps.
11 = Reserved.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
Table 11 • Mode Control, Address 0 (0x00) (continued)
Bit
Name
Access Description
Default
5:0
Reserved
000000
5.2.2
Mode Status
The register at address 1 in the device main registers space allows you to read the currently enabled
mode setting. The following table shows possible readouts of this register.
Table 12 • Mode Status, Address 1 (0x01)
Bit
Name
Access Description
Default
15
100BASE-T4
capability
RO
RO
RO
RO
RO
RO
RO
RO
1 = 100BASE-T4 capable.
0
14
13
12
11
10
9
100BASE-TX FDX
capability
1 = 100BASE-TX FDX capable.
1 = 100BASE-TX HDX capable.
1 = 10BASE-T FDX capable.
1 = 10BASE-T HDX capable.
1 = 100BASE-T2 FDX capable.
1 = 100BASE-T2 HDX capable.
1
1
1
1
0
0
1
100BASE-TX HDX
capability
10BASE-T FDX
capability
10BASE-T HDX
capability
100BASE-T2 FDX
capability
100BASE-T2 HDX
capability
8
Extended status
enable
1 = Extended status information present in
register 15.
7
6
Reserved
RO
RO
0
1
Preamble
suppression
capability
1 = MF preamble may be suppressed.
0 = MF always required.
5
4
3
2
1
0
Auto-negotiation
complete
RO
RO
RO
RO
RO
RO
1 = Auto-negotiation complete.
0
0
1
0
0
1
Remote fault
This bit latches high.
1 = Far-end fault detected.
Auto-negotiation
capability
1 = Auto-negotiation capable.
Link status
This bit latches low.
1 = Link is up.
Jabber detect
Extended capability
This bit latches high.
1 = Jabber condition detected.
1 = Extended register capable.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
5.2.3
Device Identification
All 16 bits in both register 2 and register 3 in the VSC8658 device are used to provide information
associated with aspects of the device identification. The following tables list the readouts you can expect.
Table 13 • Identifier 1, Address 2 (0x02)
Bit
Name
Access Description
Default
15:0
Organizationally unique RO
identifier (OUI)
OUI most significant bits (3:18)
0x0007
Table 14 • Identifier 2, Address 3 (0x03)
Bit
Name
Access Description
Default
0x0001
110101
15:10 OUI
RO
RO
OUI least significant bits (19:24)
VSC8658
9:4
3:0
Microsemi model
number
Device revision number RO
0000
5.2.4
Auto-Negotiation Advertisement
The bits in address 4 in the main registers space control the VSC8658 device ability to notify other
devices of the status of its auto-negotiation feature. The following table shows the available settings and
readouts.
Table 15 • Device Auto-Negotiation Advertisement, Address 4 (0x04)
Bit
Name
Access Description
Default
15
Next page transmission
request
R/W
1 = Request enabled
0
14
13
12
11
Reserved
RO
0
Transmit remote fault
Reserved technologies
R/W
R/W
R/W
1 = Enabled
0
0
Advertise asymmetric
pause
1 = Advertises asymmetric pause
1 = Advertises symmetric pause
1 = Advertises 100BASE-T4
CMODE
10
9
Advertise symmetric
pause
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CMODE
0
Advertise
100BASE-T4
8
Advertise
100BASE-TX FDX
1 = Advertise 100BASE-TX FDX
1 = Advertises 100BASE-TX HDX
1 = Advertises 10BASE-T FDX
1 = Advertises 10BASE-T HDX
CMODE
CMODE
CMODE
CMODE
00001
7
Advertise
100BASE-TX HDX
6
Advertise
10BASE-T FDX
5
Advertise
10BASE-T HDX
4:0
Advertise selector
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Configuration
5.2.5
Link Partner Auto-Negotiation Capability
The bits in main register 5 enable you to determine if the Cat5 link partner (LP) used with the VSC8658
device is compatible with the auto-negotiation functionality.
Table 16 • Auto-Negotiation Link Partner Ability, Address 5 (0x05)
Bit
Name
Access Description
Default
15
LP next page
RO
1 = Requested
0
transmission request
14
13
12
11
LP acknowledge
LP remote fault
Reserved
RO
RO
RO
RO
1 = Acknowledge
1 = Remote fault
0
0
0
0
LP advertise
asymmetric pause
1 = Capable of asymmetric pause
1 = Capable of symmetric pause
1 = Capable of 100BASE-T4
10
9
LP advertise
symmetric pause
RO
RO
RO
RO
RO
RO
0
LP advertise
100BASE-T4
0
8
LP advertise
100BASE-TX FDX
1 = Capable of 100BASE-TX FDX
1 = Capable of 100BASE-TX HDX
1 = Capable of 10BASE-T FDX
1 = Capable of 10BASE-T HDX
0
7
LP advertise
100BASE-TX HDX
0
6
LP advertise
10BASE-T FDX
0
5
LP advertise
0
10BASE-T HDX
4:0
LP advertise selector RO
00000
5.2.6
Auto-Negotiation Expansion
The bits in main register 6 work together with those in register 5 to indicate the status of the LP auto-
negotiation functioning. The following table shows the available settings and readouts.
Table 17 • Auto-Negotiation Expansion, Address 6 (0x06)
Bit
Name
Access Description
Default
15:5 Reserved
RO
00000000000
0
4
Parallel detection
fault
RO
This bit latches high.
1 = Parallel detection fault.
3
2
LP next page capable RO
1 = LP is next page capable.
1 = Local PHY is next page capable.
0
1
Local PHY next page RO
capable
1
0
Page received
RO
This bit latches low.
1 = New page is received.
0
0
LP is auto-negotiation RO
capable
1 = LP is capable of auto-negotiation.
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Configuration
5.2.7
Transmit Auto-Negotiation Next Page
The settings in register 7 in the main registers space provide information about the number of pages in
an auto-negotiation sequence. The following table shows the settings available.
Table 18 • Auto-Negotiation Next Page Transmit, Address 7 (0x07)
Bit
15
14
13
Name
Access Description
Default
Next page
Reserved
Message page
R/W
RO
1 = More pages follow
0
0
1
R/W
1 = Message page
0 = Unformatted page
12
11
Acknowledge 2
Toggle
R/W
RO
1 = Complies with request
0 = Cannot comply with request
0
0
1 = Previous transmitted LCW = 0
0 = Previous transmitted LCW = 1
10:0 Message
/unformatted code
R/W
00000000
001
5.2.8
Auto-Negotiation Link Partner Next Page Receive
The bits in register 8 of the main register space work together with register 7 to determine certain aspects
of the LP auto-negotiation. The following table shows the possible readouts.
Table 19 • Auto-Negotiation LP Next Page Receive, Address 8 (0x08)
Bit
15
14
13
Name
Access Description
Default
LP next page
Acknowledge
LP message page
RO
RO
RO
1 = More pages follow
0
0
0
1 = LP acknowledge
1 = Message page
0 = Unformatted page
12
11
LP Acknowledge 2
LP toggle
RO
RO
1 = LP complies with request
0
0
1 = Previous transmitted LCW = 0
0 = Previous transmitted LCW = 1
10:0 LP message
/unformatted code
RO
00000000000
5.2.9
1000BASE-T Control
The VSC8658 device’s 1000BASE-T functionality is controlled by the bits in register 9 of the main
register space. The following table shows the settings and readouts available.
Table 20 • 1000BASE-T Control, Address 9 (0x09)
Bit
Name
Access Description
Default
15:13 Transmitter test R/W
mode
000 = Normal.
000
001 = Mode 1: Transmit waveform test.
010 = Mode 2: Transmit jitter test as master.
011 = Mode 3: Transmit jitter test as slave.
100 = Mode 4: Transmitter distortion test.
101 to 111 = Reserved: Operation not defined.
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Configuration
Table 20 • 1000BASE-T Control, Address 9 (0x09) (continued)
Bit
Name
Access Description
Default
12
Master/slave
manual
configuration
R/W
R/W
1 = Master/slave manual configuration enabled.
0
11
Master/slave
value
This register is only valid when bit 9.12 is set to 1.
1 = Configure PHY as master during negotiation.
0 = Configure PHY as slave during negotiation.
0
10
9
Port type
R/W
R/W
R/W
R/W
1 = Multi-port device.
0 = Single-port device.
1
1000BASE-T
FDX capability
1 = PHY is 1000BASE-T FDX capable.
CMODE
CMODE
0x00
8
1000BASE-T
HDX capability
1 = PHY is 1000BASE-T HDX capable.
7:0
Reserved
Note Transmitter Test mode (bits 15:13) operates in the manner described in IEEE standard 802.3,
section 40.6.1.1.2. When using any of the Transmitter Test modes, the Auto-Media Sense functionality
must be disabled. For more information, see Extended PHY Control Set 1, page 37.
5.2.10 1000BASE-T Status
The bits in register 10 of the main register space allow you to read the status of the 1000BASE-T
communications enabled in the device. The following table shows the readouts.
Table 21 • 1000BASE-T Status, Address 10 (0x0A)
Bit
Name
Access Description
Default
15
Master/slave
RO
This bit latches high.
0
configuration fault
1 = Master/slave configuration fault detected.
0 = No master/slave configuration fault
detected.
14
Master/slave
configuration
resolution
RO
1 = Local PHY configuration resolved to
master.
0 = Local PHY configuration resolved to slave.
1
13
12
Local receiver status RO
1 = Local receiver is operating normally.
1 = Remote receiver OK.
0
0
Remote receiver
status
RO
11
10
LP 1000BASE-T FDX RO
capability
1 = LP 1000BASE-T FDX capable.
1 = LP 1000BASE-T HDX capable.
0
0
LP 1000BASE-T HDX RO
capability
9:8
7:0
Reserved
RO
RO
00
Idle error count
This is a self-clearing bit.
0x00
5.2.11 Main Registers Reserved Addresses
In the VSC8658 device main registers page space, registers 11 through 15 (0x0B through 0x0E) are
reserved.
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Configuration
5.2.12 1000BASE-T Status Extension 1
Register 15 provides additional information about the operation of the device 1000BASE-T
communications. The following table shows the readouts available.
Table 22 • 1000BASE-T Status Extension 1, Address 15 (0x0F)
Bit
Name
Access Description
Default
15
1000BASE-X FDX
capability
RO
RO
RO
RO
RO
1 = PHY is 1000BASE-X FDX capable
0
14
13
12
1000BASE-X HDX
capability
1 = PHY is 1000BASE-X HDX capable
1 = PHY is 1000BASE-T FDX capable
1 = PHY is 1000BASE-T HDX capable
0
1000BASE-T FDX
capability
1
1000BASE-T HDX
capability
1
11:0 Reserved
0x000
5.2.13 100BASE-TX Status Extension
Register 16 in the main registers page space of the VSC8658 device provides additional information
about the status of the device’s 100BASE-TX operation.
Table 23 • 100BASE-TX Status Extension, Address 16 (0x10)
Bit
Name
Access Description
Default
15
100BASE-TX
Descrambler
RO
RO
RO
1 = Descrambler locked.
0
14
13
100BASE-TX lock
error
This is a self-clearing bit.
1 = Lock error detected.
0
0
100BASE-TX
disconnect state
This is a self-clearing bit.
1 = PHY 100BASE-TX link disconnect
detected.
12
11
10
9
100BASE-TX current RO
link status
1 = PHY 100BASE-TX link active.
0
0
0
0
0
100BASE-TX receive RO
error
This is a self-clearing bit.
1 = Receive error detected.
100BASE-TX
transmit error
RO
RO
RO
RO
This is a self-clearing bit.
1 = Transmit error detected.
100BASE-TX SSD
error
This is a self-clearing bit.
1 = Start-of-stream delimiter error detected.
8
100BASE-TX ESD
error
This is a self-clearing bit.
1 = End-of-stream delimiter error detected.
7:0
Reserved
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Configuration
5.2.14 1000BASE-T Status Extension 2
The second status extension register is at address 17 in the device main registers space. It provides
information about another set of parameters associated with 1000BASE-T communications. For
information about the first status extension register, see Table 23, page 34.
Table 24 • 1000BASE-T Status Extension 2, Address 17 (0x11)
Bit
Name
Access Description
Default
15
1000BASE-T
descrambler
RO
RO
RO
1 = Descrambler locked.
0
14
13
1000BASE-T lock
error
This is a self-clearing bit.
1 = Lock error detected.
0
0
1000BASE-T
disconnect state
This is a self-clearing bit.
1 = PHY 1000BASE-T link disconnect
detected.
12
11
10
9
1000BASE-T current RO
link status
1 = PHY 1000BASE-T link active.
0
0
0
0
0
0
1000BASE-T receive RO
error
This is a self-clearing bit.
1 = Receive error detected.
1000BASE-Ttransmit RO
error
This is a self-clearing bit.
1 = Transmit error detected.
1000BASE-T SSD
error
RO
This is a self-clearing bit.
1 = Start-of-stream delimiter error detected.
8
1000BASE-T ESD
error
RO
This is a self-clearing bit.
1 = End-of-stream delimiter error detected.
7
1000BASE-T carrier RO
extension error
This is a self-clearing bit.
1 = Carrier extension error detected.
6:0
Reserved
RO
5.2.15 Bypass Control
The bits in the Bypass Control register in the VSC8658 device control aspects of functionality in effect
when the device is disabled so that traffic can bypass it in your design. The following table shows the
settings available.
Table 25 • Bypass Control, Address 18 (0x12)
Bit
Name
Access Description
Default
15
Transmit disable
R/W
RO
1 = PHY transmitter disabled.
0
14:9 Reserved
8
1000BASE-T
transmitter test clock
R/W
1 = Enabled.
0
1
7
Auto MDI-X at forced R/W
10/100
This is a sticky bit.
1 = Disable Auto MDI-X at forced 10/100
speeds.
6
5
Reserved
RO
Disable pair swap
correction
R/W
This is a sticky bit.
1 = Disable the automatic pair swap correction.
0
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Table 25 • Bypass Control, Address 18 (0x12) (continued)
Bit
Name
Access Description
R/W This is a sticky bit.
Default
4
Disable polarity
correction
0
1 = Disable polarity inversion correction on
each subchannel.
3
Parallel detect control R/W
This is a sticky bit.
1
1 = Do not ignore advertised ability.
0 = Ignore advertised ability.
2
1
Reserved
RO
Disable automatic
1000BASE-T next
page exchange
R/W
This is a sticky bit.
1 = Disable automatic 1000BASE-T next page
exchanges.
0
0
CLKOUT output
enable
R/W
This is a sticky bit.
1 = Enable clock output pin.
CMODE
Note If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is
returned to the user through the SMI after the base page is exchanged. The user then must send the
correct sequence of next pages to the link partner, determine the common capabilities, and force the
device into the correct configuration following the successful exchange of pages.
5.2.16 Reserved Main Address Space
The bits in register 19, register 20, and register 21 (0x13, 0x14, and 0x15, respectively) are reserved.
5.2.17 Extended Control and Status
The bits in register 22 provide additional device control and readouts. The following table shows the
settings available.
Table 26 • Extended Control and Status, Address 22 (0x16)
Bit
Name
Access Description
Default
15
Force 10BASE-T
link high
R/W
R/W
This is a sticky bit.
1 = Bypass link integrity test.
0 = Enable link integrity test.
0
14
13
Jabber detect
disable
This is a sticky bit.
1 = Disable jabber detect.
0
1
Disable 10BASE-T R/W
echo
This is a sticky bit.
1 = Disable 10BASE-T echo.
12
Reserved
RO
11:10
10BASE-T squelch R/W
control
This is a sticky bit.
00 = Normal squelch.
01 = Low squelch.
10 = High squelch.
11 = Reserved.
00
9
8
7
Sticky reset enable R/W
This is a super-sticky bit.
1 = Enabled.
1
0
0
EOF Error
RO
RO
This bit is self-clearing.
1 = EOF error detected.
10BASE-T
This bit is self-clearing.
disconnect state
1 = 10BASE-T link disconnect detected.
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Configuration
Table 26 • Extended Control and Status, Address 22 (0x16) (continued)
Bit
Name
Access Description
Default
6
10BASE-T link
status
RO
1 = 10BASE-T link active.
0
5:1
0
Reserved
RO
SMI broadcast
write
R/W
This is a sticky bit.
1 = Enabled.
0
The following information applies to the extended control and status bits:
•
•
When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link
pass status.
When bits 22.11:0 are set to 00, the squelch threshold levels are based on the IEEE standard for
10BASE-T. When set to 01, the squelch level is decreased, which may improve the bit error rate
performance on long loops. When set to 10, the squelch level is increased and may improve the bit
error rate in high-noise environments.
•
•
When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this
bit causes all sticky register bits to change to their default values upon software reset. Super-sticky
bits retain their values upon software reset regardless of the setting of bit 22.9.
When bit 22.0 is set, if a write to any PHY register (registers 0 through 31, including extended
registers), the same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to
PHY_0 is executed (register 0 is set to 0x1040), all PHYs’ register 0s are set to 0x1040. Disabling
this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the
value that is read corresponds only to the particular PHY being addressed.
5.2.18 Extended PHY Control Set 1
The bits in the extended control set control the MAC auto-negotiation function, the 100BASE-FX SerDes
function, and report SGMII alignment errors and EEPROM status. The following table shows the settings
available.
Table 27 • Extended PHY Control 1, Address 23 (0x17)
Bit
Name
Access Description
Default
15:14 Reserved
RO
13
12
MAC interface
auto-negotiation
R/W
This is a super-sticky bit.
1 = Enabled.
CMODE
0
MAC interface mode R/W
This is a super-sticky bit.
1 = 1000BASE-X.
0 = SGMII.
11
AMS preference
R/W
This is a super-sticky bit.
0
1 = Cat5 copper preferred.
0 = SerDes fiber/SFP preferred.
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Table 27 • Extended PHY Control 1, Address 23 (0x17) (continued)
Bit
Name
Access Description
R/W This is a super-sticky bit.
Default
10:8
Media operating
mode
CMODE
000 = Cat5 copper only.
001 = SerDes fiber/SFP pass-through mode
only. No auto-negotiation performed in the
PHY.
010 = 1000BASE-X fiber/SFP media only with
auto-negotiation performed by the PHY.
011 = 100BASE-X fiber/SFP on the fiber
media pins only
101 = Auto-Media Sense with Cat5 media or
SerDes fiber/SFP pass-through mode.
110 = Auto-Media Sense with Cat5 media or
1000BASE-X fiber/SFP media with auto-
negotiation performed by PHY.
111 = Auto-Media Sense with Cat5 media or
100BASE-FX fiber/SFP media.
100 = Reserved.
7:6
Force AMS override R/W
00 = Normal auto-media selection (AMS).
01 = Force AMS to select SerDes media only.
10 = Force AMS to select copper media only.
11 = Reserved.
00
5:4
3
Reserved
RO
Far-end loopback
mode
R/W
1 = Enabled.
0
0
2
1
Reserved
RO
RO
SGMII alignment
error status
This is a self-clearing bit.
1 = Alignment error detected since last read.
0
EEPROM status
RO
1 = EEPROM present on EECLK and EEDAT 0
pins.
Note After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0,
bit 15) must be written to change the device operating mode.
5.2.19 Extended PHY Control Set 2
The second set of extended controls is located in register 24 in the main register space for the device.
The following table shows the settings and readouts available.
Table 28 • Extended PHY Control 2, Address 24 (0x18)
Bit
Name
Access Description
R/W This is a sticky bit.
Default
15:13
100BASE-TX edge
rate control
110
011 = +5 Edge rate (slowest).
010 = +4 Edge rate.
001 = +3 Edge rate.
000 = +2 Edge rate.
111 = +1 Edge rate.
110 = Default edge rate.
101 = –1 Edge rate.
100 = –2 Edge rate (fastest).
12
PICMG 2.16 reduced R/W
power mode
This is a sticky bit.
1 = Enabled.
0
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Table 28 • Extended PHY Control 2, Address 24 (0x18) (continued)
Bit
Name
Access Description
Default
11:9
8:7
Reserved
RO
SGMII input preamble R/W
This is a sticky bit.
00
00 = No SGMII preamble required.
01 = One-byte SGMII preamble required.
10 = Two-byte SGMII preamble required.
11 = Reserved.
6
SGMII output
preamble
R/W
This is a sticky bit.
0 = No SGMII preamble.
1 = Two-byte SGMII preamble.
1
5:4
Jumbo packet mode R/W
This is a sticky bit.
00
00 = Normal IEEE 1.5 kB packet length.
01 = 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock).
10 = 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock).
11 = Reserved.
3:1
100BASE-TX
transmitter amplitude
control
R/W
011 = +3 Amplitude setting (largest).
010 = +2 Amplitude setting.
001 = +1 Amplitude setting.
000 = Default amplitude.
000
111 = –1 Amplitude setting.
110 = –2 Amplitude setting.
101 = –3 Amplitude setting.
100 = –4 Amplitude setting (smallest).
0
1000BASE-T
R/W
1 = Enabled.
0
connector loopback
Note When bits 5:4 are set to Jumbo Packet mode, the default maximum packet values are based on
100 ppm driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY
as specified in the bit description results in a higher Jumbo packet length.
5.2.20 Interrupt Mask
The bits in register 25 control the device interrupt mask. The following table shows the settings available.
Table 29 • Interrupt Mask, Address 25 (0x19)
Bit
Name
Access Description
Default
15
MDINT interrupt status enable
R/W
R/W
R/W
R/W
This is a sticky bit.
1 = Enabled.
0
14
13
12
Speed state change mask
Link state change mask
FDX state change mask
This is a sticky bit.
1 = Enabled.
0
0
0
This is a sticky bit.
1 = Enabled.
This is a sticky bit.
1 = Enabled.
11
10
Auto-negotiation error mask
R/W
R/W
1 = Enabled.
0
0
Auto-negotiation complete mask
This is a sticky bit.
1 = Enabled.
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Configuration
Table 29 • Interrupt Mask, Address 25 (0x19) (continued)
Bit
Name
Access Description
Default
9
Inline powered device (PoE) detect mask
R/W
This is a sticky bit.
0
1 = Enabled.
8:5
4
Reserved
RO
AMS media changed mask
R/W
This is a sticky bit.
1 = Enabled.
0
3
2
Reserved
RO
Link speed downshift detect mask
R/W
This is a sticky bit.
1 = Enabled.
0
0
1
0
Master/Slave resolution error mask
Reserved
R/W
RO
This is a sticky bit.
1 = Enabled.
Note When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the
state of bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted.
5.2.21 Interrupt Status
The status of interrupts already written to the device are available for reading from register 26 in the main
registers space. The following table shows the readouts you can expect.
Table 30 • Interrupt Status, Address 26 (0x1A)
Bit
Name
Access Description
Default
15
Interrupt status
RO
RO
RO
RO
RO
RO
RO
This is a self-clearing bit.
1 = Interrupt pending.
0
14
13
12
11
10
9
Speed state change status
Link state change status
This is a self-clearing bit.
1 = Interrupt pending.
0
0
0
This is a self-clearing bit.
1 = Interrupt pending.
FDX state change status
This is a self-clearing bit.
1 = Interrupt pending.
Auto-negotiation error status
Auto-negotiation complete status
Inline powered device detect status
This is a self-clearing bit.
1 = Interrupt pending.
This is a self-clearing bit.
1 = Interrupt pending.
0
0
This is a self-clearing bit.
1 = Interrupt pending.
8:5
4
Reserved
RO
RO
AMS media changed status
This is a self-clearing bit.
1 = Interrupt pending.
0
3
2
Reserved
RO
RO
Link speed downshift detect status
This is a self-clearing bit.
1 = Interrupt pending.
0
0
1
0
Master/Slave resolution error status RO
Reserved RO
This is a self-clearing bit.
1 = Interrupt pending.
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Configuration
The following information applies to the interrupt status bits:
•
All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of
the interrupt can be read by reading bits 26.14:0.
•
•
For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.
For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.
5.2.22 MAC Interface Auto-Negotiation Control and Status
Device auto-negotiation for the MAC interface is controlled in register 27. The same register is used to
check the status of those parameters. The following table shows the settings available.
Table 31 • MAC Auto-Negotiation Control and Status, Address 27 (0x1B)
Bit
Name
Access Description
Default
15
MAC or media
interlock
R/W
R/W
R/W
This is a sticky bit.
1 = MAC interface disabled when media link
down.
0 = MAC interface not suppressed by media
link status.
0
14
13
MAC or media
restart
auto-negotiation
interlock
This is a sticky bit.
1 = MAC interface restarts its auto-negotiation
if the media link changes.
0 = MAC interface does not automatically
change if media link changes.
0
0
MAC interface
auto-negotiation
auto-sense
This is a sticky bit.
1 = If MAC auto-negotiation is enabled, this
allows the MAC interface to be able to link to
MACs with auto-negotiation enabled and
disabled.
0 = Normal MAC auto-negotiation behavior.
12
MAC interface
auto-negotiation
restart
R/W
This is a self-clearing bit.
1 = Restart auto-negotiation.
0
11:10 Reserved
RO
RO
9:8
Remote fault
Corresponds to the remote fault bits sent by
the MAC during auto-negotiation.
00
detected from MAC
7
Asymmetric pause RO
advertised by the
MAC
Corresponds to the asymmetric pause bit sent 0
by the MAC during auto-negotiation.
6
5
4
3
2
Symmetric pause
advertised by the
MAC
RO
RO
RO
RO
Corresponds to the symmetric pause bit sent
by the MAC during auto-negotiation.
0
0
Full-duplex
advertised by the
MAC
Corresponds to the full-duplex bit sent by the
MAC during auto-negotiation.
Half-duplex
advertised by the
MAC
Corresponds to the half-duplex bit sent by the 0
MAC during auto-negotiation.
MAC
auto-negotiation
capable
1 = MAC is auto-negotiation capable.
1 = The MAC interface is actively linked.
0
0
MAC interface link RO
status
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Configuration
Table 31 • MAC Auto-Negotiation Control and Status, Address 27 (0x1B) (continued)
Bit
Name
Access Description
Default
1
MAC interface
auto-negotiation
complete
RO
1 = The MAC interface auto-negotiation is
complete.
0
0
Reserved
RO
5.2.23 Device Auxiliary Control and Status
Register 28 provides control and status information for several device functions not controlled or
monitored by other device registers. The following table shows the settings available and the readouts
you can expect.
Table 32 • Auxiliary Control and Status, Address 28 (0x1C)
Bit
Name
Access Description
Default
15
Auto-negotiation
complete
RO
Duplicate of bit 1.5.
0
14
13
Auto-negotiation
disabled
RO
Inverted duplicate of bit 0.12.
0
0
MDI/MDI-X crossover RO
indication
1 = MDI/MDI-X crossover performed
internally.
12
11
10
9
CD pair swap
RO
RO
RO
RO
RO
R/W
1 = CD pairs are swapped.
1 = Polarity swap on pair A.
1 = Polarity swap on pair B.
1 = Polarity swap on pair C.
1 = Polarity swap on pair D.
0
A polarity inversion
B polarity inversion
C polarity inversion
D polarity inversion
0
0
0
8
0
7
ActiPHY link status
time-out control [1]
This is a sticky bit.
Bits 7 and 2 are part of the ActiPHY Link
Status time-out control.
Bit 7 is the MSB.
CMODE
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
6
ActiPHY mode enable R/W
This is a sticky bit.
1 = Enabled.
0
5
FDX status
RO
RO
1 = Full-duplex.
0 = Half-duplex.
00
0
4:3
Speed status
00 = Speed is 10BASE-T.
01 = Speed is 100BASE-TX or 100BASE-FX.
10 = Speed is 1000BASE-T or 1000BASE-X.
11 = Reserved.
2
ActiPHY link status
time-out control [0]
R/W
This is a sticky bit.
Bits 7 and 2 are part of the ActiPHY Link
Status time-out control.
Bit 7 is the MSB.
0
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
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Configuration
Table 32 • Auxiliary Control and Status, Address 28 (0x1C) (continued)
Bit
Name
Access Description
Default
1:0
Reserved
RO
5.2.24 LED Mode Select
The device LED outputs are controlled using the bits in register 29 of the main register space. The
following table shows the information you need to access the functionality of each of the outputs. For
information about the LED modes referenced in the table, see Table 34, page 43.
Table 33 • LED Mode Select, Address 29 (0x1D)
Bit
Name
Access Description
Default
15:12 LED3 mode select
R/W
R/W
R/W
R/W
This is a sticky bit.
Select from LED modes 0 through 15.
CMODE
11:8
7:4
LED2 mode select
LED1 mode select
LED0 mode select
This is a sticky bit.
Select from LED modes 0 through 15.
CMODE
CMODE
CMODE
This is a sticky bit.
Select from LED modes 0 through 15.
3:0
This is a sticky bit.
Select from LED modes 0 through 15.
The following table shows the LED functional modes that can be programmed into any of the device’s
LED outputs. For more information about accessing or reading the status of the outputs, see Table 33,
page 43.
Table 34 • Available LED Mode Settings
Bit Setting
0000
0001
0010
0011
0100
0101
0110
0111
LED Indicates
Link/activity, Mode 0
Link1000/activity, Mode 1
Link100/activity, Mode 2
Link10/activity, Mode 3
Link100/1000/activity, Mode 4
Link10/1000/activity, Mode 5
Link10/100/activity, Mode 6
Link100BASE-FX/1000BASE-X/activity, Mode 7
Duplex/collision, Mode 8
1000
1001
1010
1011
1100
1101
1110
Collision, Mode 9
Activity, Mode 10
100BASE-FX/1000BASE-X/fiber activity, Mode 11
Auto-negotiation fault, Mode 12
Serial mode (on LED0 and LED1 on PHY0 only), Mode 13
Force LED off, Mode 14
1111
Force LED on, Mode 15
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Configuration
5.2.25 LED Behavior
The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device
LEDs. The following table shows the settings you can write to the register or read from the register.
Table 35 • LED Behavior, Address 30 (0x1E)
Bit
Name
Access Description
Default
15
Copper and fiber LED R/W
combine disable
This is a sticky bit.
0 = Combine enabled
(Copper/Fiber on
0
Link/LinkXXXX/Activity LED).
1 = Disable combination
(Link/LinkXXXX/Activity LED
indicates copper only).
14
Activity output select R/W
This is a sticky bit.
0
1 = Activity LED becomes
TX_Activity and fiber activity LED
becomes RX_Activity.
0 = TX and RX activity both
displayed on activity LEDs.
13
12
Reserved
RO
LED pulsing enable
R/W
This is a sticky bit.
0
0 = Normal operation.
1 = LEDs pulse with a 5-kHz, 20%
duty cycle when active.
11:10
LED blink/
R/W
This is a sticky bit.
CMODE
pulse-stretch rate
00 = 2.5-Hz blink rate / 400 ms
pulse-stretch.
01 = 5-Hz blink rate / 200 ms pulse-
stretch.
10 = 10-Hz blink rate / 100 ms
pulse-stretch.
11 = 20-Hz blink rate / 50 ms pulse-
stretch.
9
8
Reserved
RO
LED3 pulse-stretch/ R/W
blink select
This is a sticky bit.
1 = Pulse-stretch.
0 = Blink.
CMODE
CMODE
CMODE
CMODE
7
6
5
4
LED2 pulse-stretch/ R/W
blink select
This is a sticky bit.
1 = Pulse-stretch.
0 = Blink.
LED1 pulse-stretch/ R/W
blink select
This is a sticky bit.
1 = Pulse-stretch.
0 = Blink.
LED0 pulse-stretch/ R/W
blink select
This is a sticky bit.
1 = Pulse-stretch.
0 = Blink.
Reserved
RO
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Configuration
Table 35 • LED Behavior, Address 30 (0x1E) (continued)
Bit
Name
Access Description
Default
3
LED3 combine
feature disable
R/W
R/W
R/W
R/W
This is a sticky bit.
0 = Combine enabled (link/activity,
duplex/collision).
1 = Disable combination (link only,
duplex only).
CMODE
2
1
0
LED2 combine
feature disable
This is a sticky bit.
0 = Combine enabled (link/activity,
duplex/collision).
1 = Disable combination (link only,
duplex only).
CMODE
CMODE
CMODE
LED1 combine
feature disable
This is a sticky bit.
0 = Combine enabled (link/activity,
duplex/collision).
1 = Disable combination (link only,
duplex only).
LED0 combine
feature disable
This is a sticky bit.
0 = Combine enabled (link/activity,
duplex/collision).
1 = Disable combination (link only,
duplex only).
Note: Bits 29.11:10 are controlled only by port 0 and affect the behavior of all ports.
5.3
Extended Page Registers
To provide functionality beyond the IEEE802.3-specified 32 registers and main device registers, the
VSC8658 device includes an extended set of registers that provide an additional 15 register spaces.
To access the extended page registers (16E through 30E), enable extended register access by writing
0x0001 to register 31. For more information, see Table 37, page 46.
When extended page register access is enabled, reads and writes to registers 16 through 30 affect the
extended registers 16E through 30E instead of those same registers in the IEEE-specified register
space. Registers 0 through 15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page space. These
registers are accessible only when the device register 31 is set to 0x0001.
Table 36 • Extended Registers Page Space
Register Address Register Name
16E
17E
18E
19E
20E
21E
22E
23E
24E
SerDes Media control
SerDes MAC/Media control
CRC good counter
SIGDET polarity control
Extended PHY control 3 (ActiPHY)
EEPROM interface status and control
EEPROM data read or write
Extended PHY control 4 (PoE and CRC error counter)
VeriPHY 1
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Configuration
Table 36 • Extended Registers Page Space (continued)
Register Address Register Name
25E
26E
27E
28E
29E
30E
VeriPHY 2
VeriPHY 3
Reserved
Reserved
Ethernet packet generator (EPG) 1
EPG 2
5.3.1
Extended Page Access
The register at address 31 controls the access to both the extended and GPIO registers for the VSC8658
device. Accessing the GPIO page register space is similar to accessing the extended page registers. The
following table shows the settings available.
Table 37 • Extended Page Access, Address 31 (0x1F)
Bit Name Access Description
Default
15:0 Extended/GPIO page R/W
register access
0x0000 = Register 16 through 30 accesses
main register space
0x0000
0x0001 = Register 16 through 30 accesses
extended register space
0x0010 = Register 0 through 30 accesses
GPIO register space
5.3.2
SerDes Media Control
Register 16E, which is accessible only when extended register access is enabled, controls the SerDes
media interface. The following table shows the settings available.
Table 38 • SerDes Media Auto-Negotiation Control/Status, Address 16E (0x10)
Bit
Name
Access Description
Default
15:14 Transmit remote fault R/W
Remote fault indication sent to link partner
(LP).
00
13:12 Link partner (LP)
remote fault
RO
Remote fault bits sent by LP during auto-
negotiation.
00
0
11
Parallel detect
R/W
1 = Enables parallel detect of auto-
negotiation enabled and disabled devices.
10
9:0
SerDes media signal RO
detect
Signal detect indication on media interface.
0
Reserved
RO
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Configuration
5.3.3
SerDes MAC/Media Control
Register 17E, which is accessible only when extended register access is enabled, controls the
transmitter and receiver of the VSC8658 device SerDes MAC/Media. The following table shows the
settings available.
Table 39 • SerDes MAC Control, Address 17E (0x11)
Bit
Name
Access Description
Default
15:8
7:5
Reserved
RO
SerDes media output R/W
swing control
This is a sticky bit.
100
000 = 400 mV (peak-to-peak).
001 = 600 mV (peak-to-peak).
010 = 800 mV (peak-to-peak).
011 = 1000 mV (peak-to-peak).
100 = 1200 mV (peak-to-peak).
101 = 1400 mV (peak-to-peak).
110 and 111 = Reserved.
4:2
SerDes MAC output R/W
swing control
This is a sticky bit.
100
000 = 400 mV (peak-to-peak).
001 = 600 mV (peak-to-peak).
010 = 800 mV (peak-to-peak).
011 = 1000 mV (peak-to-peak).
100 = 1200 mV (peak-to-peak).
101 = 1400 mV (peak-to-peak).
110 and 111 = Reserved.
1:0
Reserved
RO
5.3.4
CRC Good Counter
Register 18E makes it possible to read the contents of the CRC good counter; the number of CRC
routines that have executed successfully. The following table shows the readouts you can expect.
Table 40 • CRC Good Counter, Address 18E (0x12)
Bit
Name
Access Description
Default
15
Packet since last read RO
This is a self-clearing bit.
0
1 = Packet received since last read.
14
Reserved
RO
RO
13:0 CRC good counter
contents
This is a self-clearing bit.
0x000
Counter containing the number of packets
with valid CRCs; this counter does not
saturate and will roll over.
5.3.5
SIGDET Polarity Control
Register 19E controls the SIGDET pin polarity. The following table shows the settings available.
Table 41 • SIGDET Polarity Control, Address 19E (0x13)
Bit
15:1
0
Name
Access Description
Default
Reserved
RO
SIGDET pin polarity R/W
1 = Active low.
0 = Active high.
CMODE
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Configuration
5.3.6
ActiPHY Control
Register 20E controls the device ActiPHY sleep timer, its wake-up timer, the frequency of the CLKOUT
signal, and its link speed downshifting feature. The following table shows the settings available.
Table 42 • Extended PHY Control 3, Address 20E (0x14)
Bit
Name
Access Description
Default
15
Disable carrier
extension
R/W
1 = Disable.
0
14:13 ActiPHY sleep timer
R/W
This is a sticky bit.
00 = 1 second.
01 = 2 seconds.
10 = 3 seconds.
11 = 4 seconds.
01
12:11 ActiPHY wake-up timer R/W
This is a sticky bit.
00 = 160 ms.
11
01 = 400 ms.
10 = 800 ms.
11 = 2 seconds.
10:9
8
Reserved
RO
CLKOUT frequency (1) R/W
This is a sticky bit.
1 = 156.25 MHz.
0 = 125 MHz.
CMODE
00
7:6
Media mode status
Reserved
RO
RO
00 = No media selected.
01 = Copper media selected.
10 = SerDes media selected.
11 = Reserved.
5
4
Enable link speed auto- R/W
downshift feature
This is a sticky bit.
1 = Enable auto link speed downshift from
1000BASE-T.
CMODE
01
3:2
Link speed
R/W
This is a sticky bit.
auto-downshift control
00 = Downshift after 2 failed 1000BASE-T
auto-negotiation attempts.
01 = Downshift after 3 failed 1000BASE-T
auto-negotiation attempts.
10 = Downshift after 4 failed 1000BASE-T
auto-negotiation attempts.
11 = Downshift after 5 failed 1000BASE-T
auto-negotiation attempts.
1
0
Link speed
auto-downshift status
RO
RO
0 = No downshift.
1 = Downshift is required or has occurred.
0
Reserved
1. Bit 8 is valid only on PHY_0.
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Configuration
5.3.7
EEPROM Interface Status and Control
Register 21E is used to affect control over device function when you have incorporated a startup
EEPROM into your design.
Table 43 • EEPROM Interface Status and Control, Address 21E (0x15)
Bit
15
14
Name
Access Description
Default
Reserved
RO
Re-read EEPROM
after software reset
R/W
R/W
This is a super-sticky bit.
1 = Contents of EEPROM to be re-read
after software reset.
0
13
Enable EEPROM
access
This is a self-clearing bit.
1 = Execute read or write EEPROM
based on the settings of register bit
21E.12.
0
1
12
11
EEPROM read or
write
R/W
1 = Read from EEPROM.
0 = Write to EEPROM.
EEPROM ready
RO
1 = EEPROM is ready for read or write. 1
10:0 EEPROM address
R/W
Sets the address of the EEPROM to
00000000000
which the read or write is to be directed.
5.3.8
5.3.9
EEPROM Data Read/Write
Register 22E in the extended register space enables access to the contents of the external EEPROM in
your design. The following table shows the writes needed to obtain the data from the external device.
Table 44 • EEPROM Read or Write, Address 22E (0x16)
Bit
Name
Access Description
Default
15:8 EEPROM read data RO
Eight-bit data read from EEPROM;
requires setting register 21E, bit 13.
0x00
7:0
EEPROM write data R/W
Eight-bit data to be written to EEPROM. 0x00
PoE and Miscellaneous Functionality
The register at address 23E controls various aspects of inline powering and the CRC error counter in the
VSC8658.
Table 45 • Extended PHY Control 4, Address 23E (0x17)
Bit
Name
Access Description
RO PHY address; latched on reset.
Default
CMODE
0
15:11
10
PHY address
Inline powered device R/W
detection
This is a sticky bit.
1 = Enabled.
9:8
Inline powered device RO
detection status
00 = Searching for devices.
01 = Device found; requires inline power.
10 = Device found; does not require inline
power.
00
11 = Reserved.
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Configuration
Table 45 • Extended PHY Control 4, Address 23E (0x17) (continued)
Bit
Name
Access Description
RO This is a self-clearing bit.
Default
7:0
CRC error counter
0x00
CRC error counter for the Ethernet packet
generator. The value saturates at 0xFF and
subsequently clears when read and restarts
count.
Note: Bits 9:8 are only valid if bit 10 is set.
5.3.10 VeriPHY Control 1
Register 24E in the extended register space provides control over the device VeriPHY diagnostics
features. There are three separate VeriPHY control registers. The following table shows the settings
available and describes the readouts you can expect.
Table 46 • VeriPHY Control Register 1, Address 24E (0x18)
Bit
Name
Access Description
Default
15
VeriPHY trigger
R/W
RO
This is a self-clearing bit.
0
1 = Triggers the VeriPHY algorithm and clears
when VeriPHY has completed. Settings in
registers 24E through 26E become valid after
this bit clears.
14
VeriPHY valid
1 = VeriPHY results in registers 24E through
26E are valid.
0
13:8 Pair A (1-2) distance RO
Loop length or distance to anomaly for pair A 0x00
(1-2).
7:6
5:0
Reserved
RO
Pair B (3-6) distance RO
Loop length or distance to anomaly for pair B 0x00
(3-6).
Note: The resolution of the 6-bit length field is 3 meters.
5.3.11 VeriPHY Control 2
The register at address 25E consists of the second of the three device registers that provide control over
VeriPHY diagnostics features. The following table shows the readouts you can expect.
Table 47 • VeriPHY Control Register 2, Address 25E (0x19)
Bit
Name
Access Description
Default
15:14 Reserved
RO
13:8
Pair C (4-5) distance RO
Loop length or distance to anomaly for
0x00
pair C (4 and 5)
7:6
5:0
Reserved
RO
Pair D (7-8) distance RO
Loop length or distance to anomaly for
pair D (7 and 8)
0x00
Note: The resolution of the 6-bit length field is 3 meters.
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Configuration
5.3.12 VeriPHY Control 3
The register at address 26E consists of the third of the three device registers that provide control over
VeriPHY diagnostics features. Specifically, this register provides information about the termination status
(fault condition) for all four link partner pairs. The following table shows the readouts you can expect.
Table 48 • VeriPHY Control Register 3, Address 26E (0x1A)
Bit
Name
Access Description
Default
15:12
Pair A (1 and 2)
termination status
RO
RO
RO
RO
Termination fault for pair A (1 and 2)
0x00
11:8
7:4
Pair B (3 and 6)
termination status
Termination fault for pair B (3 and 4)
Termination fault for pair C (4 and 5)
Termination fault for pair D (7 and 8)
0x00
0x00
0x00
Pair C (4 and 5)
termination status
3:0
Pair D (7 and 8)
termination status
The following table shows the meanings for the various fault codes.
Table 49 • VeriPHY Control Register 3 Fault Codes
Code
0000
0001
0010
0100
1000
1001
1010
1011
1100
1101
1110
1111
Denotes
Correctly terminated pair
Open pair
Shorted pair
Abnormal termination
Cross-pair short to pair A
Cross-pair short to pair B
Cross-pair short to pair C
Cross-pair short to pair D
Abnormal cross-pair coupling with pair A
Abnormal cross-pair coupling with pair B
Abnormal cross-pair coupling with pair C
Abnormal cross-pair coupling with pair D
5.3.13 Reserved Extended Address Space
The bits in the extended register page space at address 27E (0x1B) and 28E (0x1C) are reserved.
5.3.14 Ethernet Packet Generator Control 1
The EPG control register provides access to and control of various aspects of the EPG testing feature.
There are two, separate EPG control registers. The following table shows the setting available in the first
register.
Table 50 • EPG Control Register 1, Address 29E (0x1D)
Bit
15
14
Name
Access Description
Default
EPG enable
EPG run or stop
R/W
R/W
1 = Enable EPG
1 = Run EPG
0
0
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Configuration
Table 50 • EPG Control Register 1, Address 29E (0x1D) (continued)
Bit
Name
Access Description
Default
13
Transmission
duration
R/W
R/W
1 = Continuous (sends in 10,000-packet
increments)
0 = Send 30,000,000 packets and stop
0
12:11
Packet length
00 = 125 bytes
0
01 = 64 bytes
10 = 1518 bytes
11 = 10,000 bytes (Jumbo packet)
10
9:6
5:2
1
Inter-packet gap
R/W
1 = 8,192 ns
0 = 96 ns
0
Destination address R/W
Lowest nibble of the 6-byte destination
address
0001
0000
0
Source address
Payload type
R/W
R/W
R/W
Lowest nibble of the 6-byte destination
address
1 = Randomly generated payload pattern
0 = Fixed based on payload pattern
0
Bad frame check
sequence (FCS)
generation
1 = Generate packets with bad FCS
0 = Generate packets with good FCS
0
The following information applies to the EPG control number 1:
•
•
Do not run the EPG when the VSC8658 device is connected to a live network.
Bit 29E.13 (Continuous EPG mode control): When enabled, this mode causes the device to send
continuous packets. When disabled, the device continues to send packets only until it reaches the
next 10,000-packet increment mark. It then ceases to send packets.
•
•
•
The six-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF
FF FF FF F0 through 0xFF FF FF FF FF FF.
The six-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF
FF FF F0 through 0xFF FF FF FF FF FF.
If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared
and then set back to 1 for the change to take effect and to restart the EPG.
5.3.15 Ethernet Packet Generator Control 2
The register at address 30E consists of the second of bits that provide access to and control over various
aspects of the EPG testing feature. For information about the first set of EPG control bits, see Table 50,
page 51. The following table shows the settings available.
Table 51 • EPG Control Register 2, Address 30E (0x1E)
Bit
Name
Access Description
Default
15:0 EPG packet payload R/W
Data pattern repeated in the payload of
packets generated by the EPG
0x00
Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E is set to 1),
that bit (29E.14) must first be cleared and then set back to 1 for the change to take effect and to restart
the EPG.
5.4
General-Purpose I/O Registers
Accessing the GPIO page register space is similar to accessing the extended page registers. Set register
31 to 0x0010. This sets all 32 registers to the GPIO page register space.
To restore main register page access, write 0x0000 to register 31.
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Configuration
The following table lists the addresses and register names in the GPIO register page space. These
registers are accessible only when the device register 31 is set to 0x0010.
Table 52 • General-Purpose Registers Page Space
Register Address Register Name
0G through 12G
Reserved
13G
SIGDET vs GPIO control
Reserved
14G
15G
GPIO input
16G
GPIO output
17G
GPIO output enable
100BASE-FX control
Reserved
18G
19G through 30G
5.4.1
5.4.2
Reserved GPIO Address Space
The bits in registers 0G to 12G, and 14G of the GPIO register page space are reserved.
SIGDET vs GPIO Control
The SIGDET control register configures GPIO pins 7:0 to be either SIGDET pins for each port or to be
GPIO pins. The following table shows the values that can be written.
Table 53 • SIGDET vs GPIO Control, Address 13G (0x0D)
Bit
Name
Access Description
00 = Normal SIGDET operation
Default
15:14 SIGDET7 control
13:12 SIGDET6 control
11:10 SIGDET5 control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
0x00
0x00
0x00
0x00
0x00
0x00
0x00
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
9:8
7:6
5:4
3:2
1:0
SIGDET4 control
SIGDET3 control
SIGDET2 control
SIGDET1 control
SIGDET0 control
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
00 = Normal SIGDET operation
01, 10 = Reserved
11 = Controlled by MII registers 15G to 17G
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Configuration
5.4.3
GPIO Input
The input register contains information about the input to the device GPIO pins. Read from this register to
access the data on the device GPIO pins. The following table shows the readout you can expect.
Table 54 • GPIO Input, Address 15G (0x0F)
Bit
Name
Access Description
RO Data read from the GPIO pins
Default
15:0 GPIO [15:0] input
0x00
5.4.4
5.4.5
GPIO Output
The output register allows you to access and control the output from the device GPIO pins. The following
table shows the values you can write.
Table 55 • GPIO Output, Address 16G (0x10)
Bit
Name
Access Description
R/W Data written to the GPIO pins
Default
15:0 GPIO [15:0] output
0x00
GPIO Pin Configuration
Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or
an output. The following table shows the settings available.
Table 56 • GPIO Input/Output Configuration, Address 17G (0x11)
Bit
Name
Access Description
Default
15:0 GPIO [15:0] input or R/W
output enable
1 = Pin is configured as an output.
0 = Pin is configured as an input.
0x00
5.4.6
100BASE-FX Control
The 100BASE-FX control register can configure each PHY within the device to be in 100BASE-FX mode.
The following table shows the values that can be written.
Table 57 • 100BASE-FX Control, Address 18G (0x12)
Bit
Name
Access Description
Default
15
Activate 100BASE-FX R/W
0 = No action
0
1 = Activate 100BASE-FX based on bits
11:0
14:12 Reserved
RO
000
0
11
100BASE-FX on all
PHYs
R/W
0 = No 100BASE-FX on all PHYs
1 = Configure 100BASE-FX on all PHYs
10:8
7:0
Individual 100BASE-FX R/W
setting
PHY number to be configured for
100BASE-FX mode
000
100BASE-FX mode
R/W
0x00 = No 100BASE-FX
0x01 = 100BASE-FX mode
0x02 to 0xFF = Reserved
0x00
Example 1 To configure all PHYs to 100BASE-FX mode, first ensure bit 15 = 0, then set bit 11 = 1 and
bits 7:0 = 0x01, and then reset bit 15 = 1.
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Configuration
Example 2 To configure an individual PHY to 100BASE-FX mode, first ensure that bit 15 = 0, then set
bits 10:8 to the correct PHY number to be configured for 100BASE-FX, then set bits 7:0 = 0x01, and
finally reset bit 15 = 1. Repeat these steps for each individual PHY.
5.5
CMODE
The information in this section provides a detailed description of the methods you can use to configure
the VSC8658 device using its CMODE pins. It includes descriptions of the registers that work together
with the CMODE pins to control the device function.
There are eight configuration mode (CMODE) pins on the VSC8658 device. For more information about
the physical location of the CMODE pins, see Pin Descriptions, page 72. Each of the CMODE pins maps
to four configuration bits, which means that each pin controls 16 possible settings for the device.
5.5.1
CMODE Pins and Related Functions
The following table lists the pin numbers and device functionality that are controlled by each
configuration bit.
Table 58 • CMODE Configuration Pins and Device Functions
CMODE Pin Bit 3 (MSB) Control
Bit 2 Controls
Bit 1 Controls
Bit 0 (LSB) Controls
7
6
5
4
3
2
1
0
Reserved
Always set to logic 0
Link speed downshift
Speed and duplex [1]
Speed and duplex [0]
MAC auto-negotiation ActiPHY
Advertise asymmetric
pause
Advertise symmetric
pause
Media interface [2]
Media interface [1]
Media interface [0]
SIGDET polarity
Clock speed 125 MHz CLKOUT enable
or 156 MHz selection
LED fiber/copper
combine
LED blink or pulse
stretch [1]
LED blink or pulse
stretch [0]
LED3 combine or
separate
LED3 [1]
LED2 [1]
LED1 [1]
LED0 [1]
LED3 [0]
LED2 [0]
LED1 [0]
LED0 [0]
PHY address reversal LED2 combine or
separate
PHY address [4]
LED1 combine or
separate
PHY address [3]
LED0 combine or
separate
5.5.2
Functions and Related CMODE Pins
The following table lists the pin and bit settings according to the device function and CMODE pin used to
configure them.
Table 59 • Device Functions and Associated CMODE Pins
Sets MII
Register
CMODE
Pin
Function
Bit
Description
Link speed
downshift
Register 20E, 7
bit 4
2
0 = Link only according to the auto-negotiation resolution.
1 = Enable link speed downshift feature.
Speed and duplex
Register 4,
bits 8:5 and
register 9,
bits 9:8
7
1 and 0 00 = 10/100/1000BASE-T FDX/HDX. 1000BASE-X
FDX/HDX.
01 = 10/100/1000BASE-T FDX; 10/100BASE-T HDX.
1000BASE-X FDX.
10 = 1000BASE-T FDX only.
11 = 10/100BASE-T FDX/HDX.
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Configuration
Table 59 • Device Functions and Associated CMODE Pins (continued)
Sets MII
Register
CMODE
Pin
Function
Bit
Description
MAC
auto-negotiation
Register 23,
bit 13
6
3
0 = Disabled.
1 = Enabled.
ActiPHY
Register 28,
bit 6
6
2
1
0
3
0 = Disabled.
1 = Enabled.
Advertise
asymmetric pause bit 11
Register 4,
6
0 = Not advertised.
1 = Advertised.
Advertise symmetric Register 4,
pause
6
0 = Not advertised.
1 = Advertised.
bit 10
Media interface [2:0] Register 23,
bits 10:8
5, 4, 3
000 = Cat5 copper only.
001 = SerDes Fiber/SFP Pass-Through mode only. No
auto-negotiation performed in the PHY.
010 = 1000BASE-X Fiber/SFP mode only with auto-
negotiation performed by the PHY.
011 = 100BASE-X Fiber/SFP mode on the fiber media pins
only.
101 = Auto-media sense with Cat5 media or SerDes
Fiber/SFP Pass-Through mode.
110 = Auto-media sense with Cat5 media or 1000BASE-X
Fiber/SFP mode with auto-negotiation performed by PHY.
111 = Auto-media sense with Cat5 media or 100BASE-FX
Fiber/SFP mode.
100 = Reserved.
SIGDET polarity
Clock speed
Register 19E, 5
bit 0
2
1
0
2
0 = Active high.
1 = Active low.
Register 20E, 5
bit 8
0 = 125 MHz.
1 = 156.2 MHz.
CLKOUT enable
Register 18,
bit 0
5
0 = Disabled.
1 = Enabled.
LED fiber/copper
combine
Register 30,
bit 15
4
0 = Combine enabled (Copper/Fiber on
Link/LinkXXXX/Activity LED).
1 = Disable combination (Link/LinkXXXX/Activity LED
indicates copper only).
LED blink/pulse
stretch rate
Register 30,
bits 11:10
4
1 and 0 00 = 2.5 Hz blink rate, 400 ms pulse stretch.
01 = 5.0 Hz blink rate, 200 ms pulse stretch.
10 = 10.0 Hz blink rate, 100 ms pulse stretch.
11 = 20.0 Hz blink rate, 50 ms pulse stretch.
LED_3, LED_2,
LED_1, and LED_0 bits 3:0
combine or separate
Register 30,
3, 2, 1,
and 0
2
0 = Link, Link10, Link100, Link1000, Link10/100,
Link10/1000, Link100/1000.
LEDs blink or flash when activity is present.
Also, a duplex LED blinks or flashes when collision is
present.
1 = Link, Link10, Link100, Link1000, Link10/100,
Link10/1000, Link100/1000.
LEDs indicate status only.
Also, a duplex LED indicates a duplex status only.
LED_3 indication
function
Register 29,
bits 15:12
3
1 and 0 00 = Duplex or collision.
01 = Link100 or activity.
10 = Activity.
11 = Fiber_Link/Fiber_Activity.
VMDS-10242 VSC8658 Datasheet Revision 4.1
56
Configuration
Table 59 • Device Functions and Associated CMODE Pins (continued)
Sets MII
Register
CMODE
Pin
Function
Bit
Description
Address reversal
2
2
3
0 = Normal functioning.
PHY address 0:7 = Port 0:7.
1 = Reversed functioning.
PHY address 7:0 = Port 0:7.
LED_2 indication
function
Register 29,
bits 11:8
1 and 0 00 = Link or activity.
01 = Duplex or collision.
10 = Fiber_Activity.
11 = Link10 or activity.
PHY address [4:3]
1 and 0
1
3
Sets the two MSBs of the PHY address.
LED_1 indication
function
Register 29,
bits 7:4
1 and 0 00 = Link100 or activity.
01 = Link100/1000 or activity.
10 = Link 10/100 or activity.
11 = Fiber_Link/Fiber_Activity.
LED_0 indication
function
Register 29,
bits 3:0
0
1 and 0 00 = Link1000 or activity.
01 = Link100/1000 or activity.
10 = Activity.
11 = Link or activity.
Note: The MAC auto-negotiation, LED_0, LED_1, LED_2, and LED_3 settings available using the CMODE
pins and configuration bits is limited. For full functionality, use the registers. For more information about
using the registers for these and other functions, see Registers, page 26.
5.5.3
CMODE Resistor Values
To affect an aspect of the VSC8658 device configuration, find the parameter in Table 58, page 55 or in
Table 59, page 55, and connect the associated pin to the resistor specified in the following table. This
sets the bits as shown.
Table 60 • CMODE Resistor Values and Resultant Bit Settings
With CMODE
Pin Tied To
With 1%
Set
Set
Set
Bit 1 to:
Set
Resistor Value Bit 3 (MSB) to: Bit 2 to:
Bit 0 (LSB) to:
VSS
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VSS
2.26 kΩ
4.02 kΩ
5.90 kΩ
8.25 kΩ
12.1 kΩ
16.9 kΩ
22.6 kΩ
0
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
2.26 kΩ
4.02 kΩ
5.90 kΩ
8.25 kΩ
12.1 kΩ
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
Table 60 • CMODE Resistor Values and Resultant Bit Settings (continued)
With CMODE
With 1%
Set
Set
Set
Set
Pin Tied To
Resistor Value Bit 3 (MSB) to: Bit 2 to:
Bit 1 to:
Bit 0 (LSB) to:
VDD33
16.9 kΩ
22.6 kΩ
1
1
1
1
1
1
0
1
VDD33
Using resistors with the CMODE pins can be optional in designs that access the device’s MDC/MDIO
pins. In designs that do this, all configurations otherwise affected on the device by using the CMODE
pins can be changed using the regular device register settings, and all the CMODE pins can be pulled to
VSS (ground). However, in this case, the PHYADDR [4:3] and the PHYADD_REVERSAL settings still
require CMODE configuration. This configuration can be set by connecting these pins to either the
VDD33 or VSS pins.
5.6
EEPROM
The VSC8658 device EEPROM interface makes it possible for you to set up the device to self-configure
its internal registers based on the information programmed into and stored in an external device. To
accomplish this, the EEPROM is read on power-up or de-assertion of the NRESET bit. For field
configurability, the EEPROM can also be accessed using VSC8658 device registers 21E and 22E.
The EEPROM you use to interface to the VSC8658 device must have a two-wire interface. A device such
as the Atmel part AT24CXXX is suggested.
As defined by the interface, data is clocked from the VSC8658 device on the falling edge of EECLK. The
device determines that an external EEPROM is present if EEDAT is connected to a 4.7-kΩ external pull-
up resistor. The EEDAT pin can be left floating or grounded to indicate that no EEPROM is present.
5.6.1
EEPROM Contents Description
When an EEPROM is present, the VSC8658 device looks for the command header, 0xBDBD at address
0 and 1 of the EEPROM. The address is incremented by 256 until the header is found. If the header is
not found or no EEPROM is connected, the VSC8658 device bypasses the EEPROM read step.
When an EEPROM is present, the VSC8658 device waits for an acknowledgement for approximately
three seconds (in accordance with the ATMEL EEPROM protocol). If there is no acknowledgement for
three seconds, the VSC8658 device aborts its attempt to connect to the EEPROM and reverts to its
otherwise normal operating mode.
After the header value is found, the two-byte address value shown in the following table indicates the
EEPROM word address where the configuration contents for the device are located. At the base address
location, the next set of bytes indicates where the configuration data contents to be programmed into the
VSC8658 device are located. The first address points to the data common to all PHYs. Each subsequent
address location points to each individual PHY’s configuration contents. At each programming location,
the two bytes represent the total number of bytes (11 bits, with MSB first) where the
Total_Number_Bytes[10:0] is equal to the number of SMI writes multiplied by 3 (one byte for SMI port
and register address and two bytes for data). Data is read from the EEPROM sequentially until all SMI
write commands are completed.
Table 61 • EEPROM Configuration Contents
10-bit Address
Content (Bits 7:0)
0
1
2
3
0xBD
0xBD
PHY_ADDR[4:2], 00, Base_Address_Location[10:8]
Base_Address_Location[7:0] (K)
Address length not specified
00000, Common_Config_Base_Address[10:8]
K
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Configuration
Table 61 • EEPROM Configuration Contents (continued)
10-bit Address
Content (Bits 7:0)
K+1
K+2
K+3
K+4
K+5
K+6
K+7
Common_Config_Base_Address[7:0] (X)
00000, PHY0_Specific_Config_Base_Address[10:8]
PHY0_Specific_Config_Base_Address[7:0] (Y)
00000, PHY1_Specific_Config_Base_Address[10:8]
PHY1_Specific_Config_Base_Address[7:0]
00000, PHY2_Specific_Config_Base_Address[10:8]
PHY2_Specific_Config_Base_Address[7:0]
Address length not specified
K+16
K+17
00000, PHY7_Specific_Config_Base_Address[10:8]
PHY7_Specific_Config_Base_Address[7:0]
Address length not specified
X
00000, Total_Number_Bytes[10:8]
Total_Number_Bytes [7:0] (M)
X+1
X+2
X+3
X+4
X+5
X+6
X+7
Register address a
Data[15:8] to be written to register address a
Data[7:0] to be written to register address a
Register address b
Data[15:8] to be written to register Address b
Data[7:0] to be written to register address b
Address length not specified
X+(M-2)
X+(M-1)
X+M
Register address x
Data[15:8] to be written to register address x
Data[7:0] to be written to register address x
Address length not specified
Y
00000, Total_Number_Bytes[10:8]
Total_Number_Bytes [7:0] (N)
Y+1
Y+2
Y+3
Y+4
Register address a
Data[15:8] to be written to register address a
Data[7:0] to be written to register address a
Address length not specified
Y+(N-2)
Y+(N-1)
Y+N
Register address x
Data[15:8] to be written to register address x
Data[7:0] to be written to register address x
Address length not specified
Max Address
5.6.2
Read/Write Access to the EEPROM
The VSC8658 device also has the ability to read from and write to an EEPROM such as an ATMEL
AT24CXXX that is directly connected to its EECLK and EEDAT pins. If it is required to be able to write to
VMDS-10242 VSC8658 Datasheet Revision 4.1
59
Configuration
the EEPROM, refer to the EEPROM’s specific datasheet to ensure that write protection on the EEPROM
is not set.
The following illustration shows the interaction of the VSC8658 device and the EEPROM.
Figure 18 • EEPROM Read and Write Register Flow
Start
21E.11 = 0
Wait for Ready
Read Data = 22E.15:8
21E.11 = 1
21E.11 = 1
Write EEPROM
Data
Read or Write
21E.13 = 1
Wait for Ready
21E.13 = 1
Read EEPROM
Data
21E.11 = 0
21E.10:0 = Write Address
21E.12 = 0
22E.7:0 = Data to Write
21E.10:0 = Address to Read
21E.12 = 1
To read a value from a specific address of the EEPROM:
1. Read the VSC8658 device register bit 21E.11, and ensure that it is set.
2. Write the EEPROM address to be read to register bits 21E.10:0.
3. Set both register bits 21E.12 and 21E.13 to 1.
4. When register bit 21E.11 changes to 1, read the 8-bit data value found at register bits 22E.15:8. This
is the contents of the address just read by the PHY.
To write a value to a specific address of the EEPROM:
1. Read the VSC8658 device register bit 21E.11 and ensure that it is set.
2. Write the address to be written to register bits 21E.10:0.
3. Set register bit 21E.12 to 0.
4. Set register bits 22E.7:0 with the 8-bit value to be written to the EEPROM.
5. Set register bit 21E.13 to 1.
To avoid collisions during read and write transactions, always wait until register bit 21E.11 changes to 1
before performing another EEPROM read or write operation.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Electrical Specifications
6
Electrical Specifications
This section provides the DC characteristics, AC characteristics, recommended operating conditions,
and stress ratings for the VSC8658 device. It includes information on the various timing functions of the
device.
6.1
DC Characteristics
In addition to any parameter-specific conditions, the specifications listed in the following tables may be
considered valid only in the environment characterized by the specifications listed as recommended
operating conditions for the VSC8658 device. For more information about the recommended operating
conditions, see Operating Conditions, page 70.
6.1.1
VDDIO at 3.3 V
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 3.3 V
VDD33 is 3.3 V
VDD12 is 1.2 V
VDD12A is 1.2 V
Table 62 • DC Characteristics for Pins Referenced to VDDIO at 3.3 V
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage VOH
2.4
0
3.6
0.5
3.6
0.9
42
V
IOH = –4 mA
IOL = 4 mA
Output low voltage
Input high voltage
Input low voltage
VOL
VIH
VIL
V
2.1
–0.3
–42
–42
V
V
Input leakage current IILEAK
µA
µA
Internal resistor included
Internal resistor included
Output leakage
current
IOLEAK
42
Output low current
drive strength
IOL
8
mA
mA
Output high current
drive strength
IOH
–8
6.1.2
VDDIO at 2.5 V
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 2.5 V
VDD33 is 3.3 V
VDD12 is 1.2 V
VDD12A is 1.2 V
Table 63 • DC Characteristics for Pins Referenced to VDDIO at 2.5 V
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage
Output low voltage
VOH
VOL
2.0
2.8
0.4
V
V
IOH = –1.0 mA
IOL = 1.0 mA
–0.3
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Electrical Specifications
Table 63 • DC Characteristics for Pins Referenced to VDDIO at 2.5 V (continued)
Parameter
Symbol Minimum Maximum Unit Condition
Input high voltage
Input low voltage
VIH
VIL
1.7
3.0
0.7
32
32
6
V
–0.3
–32
–32
V
Input leakage current IILEAK
Output leakage current IOLEAK
µA
µA
mA
Internal resistor included
Internal resistor included
Output low current
drive strength
IOL
Output high current
drive strength
IOH
–6
mA
6.1.3
VDDIO at 1.8 V
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 1.8 V
VDD33 is 3.3 V
VDD12 is 1.2 V
VDD12A is 1.2 V
Table 64 • DC Characteristics for Pins Referenced to VDDIO at 1.8 V
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage
Output low voltage
Input high voltage
Input low voltage
VOH
VOL
VIH
VIL
1.4
2.1
0.3
2.1
0.6
23
V
IOH = –0.5 mA
IOL = 0.5 mA
V
1.2
V
V
Input leakage current IILEAK
–23
–23
µA
µA
Internal resistor included
Internal resistor included
Output leakage
current
IOLEAK
23
Output low current
drive strength
IOL
4.0
mA
mA
Output high current
drive strength
IOH
–4.0
6.1.4
VDD at 3.3 V
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 3.3 V
VDD33 is 3.3 V
VDD12 is 1.2 V
VDD12A is 1.2 V
Table 65 • DC Characteristics for Pins Referenced to VDD33 at 3.30 V
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage
Output low voltage
VOH
VOL
2.4
0
3.6
0.5
V
V
IOH = –4 mA
IOL = 4 mA
VMDS-10242 VSC8658 Datasheet Revision 4.1
62
Electrical Specifications
Table 65 • DC Characteristics for Pins Referenced to VDD33 at 3.30 V (continued)
Parameter
Symbol Minimum Maximum Unit Condition
Input high voltage
Input low voltage
VIH
VIL
2.1
3.6
0.9
42
42
8
V
–0.3
–42
–42
V
Input leakage current IILEAK
Output leakage current IOLEAK
µA
µA
mA
Internal resistor included
Internal resistor included
Output low current
drive strength
IOL
Output high current
drive strength
IOH
–8
mA
6.1.5
MAC and SerDes Outputs
For more information about the number and physical location of the MAC and SerDes output pins on the
VSC8658 device, see Pin Descriptions, page 72.
Table 66 • DC Characteristics for MAC_RDP/N_n and SER_DOP/N_n Pins
Parameter
Symbol Minimum Typical Maximum Unit Condition
Frequency lock time TLOCK
500
µs
Output differential
voltage
VODIFF
700
480
1000
1200
mV
Measured peak-to-
peak. Based on
100 Ω differential
load.
Output common-
mode voltage
VOCM
540
185
610
300
mV
ps
VDD12A = 1.20 V.
Output rise time and tr , f
fall time (20% to
80%)
t
Total jitter
TJ
260
8
ps
Measured peak-to-
peak. Uses K28.5
test pattern. Bit error
rate (BER) = 10–12
.
Output low current
drive strength
IOL
mA
mA
Ω
Output high current IOH
drive strength
–8
Output driver
impedance per pin
ZO
50
6.1.6
MAC and SerDes Inputs
For more information about the number and physical location of the MAC and SerDes input pins on the
VSC8658 device, see Pin Descriptions, page 72.
Table 67 • DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins
Parameter
Symbol Minimum Maximum Unit
120 2400 mV
Condition
Input differential voltage VIDIFF
Measured peak-to-peak.
Based on 100 Ω
differential load.
VMDS-10242 VSC8658 Datasheet Revision 4.1
63
Electrical Specifications
Table 67 • DC Characteristics for MAC_TDP/N_n and SER_DIP/N_n Pins (continued)
Parameter
Symbol Minimum Maximum Unit
Condition
Input common mode
voltage
VICM
0.4
1.3
V
VDD12A = 1.20 V.
Total receive jitter
tolerance
JRXTotal 450
JRXTotal 5870
550
6500
ps
ps
Measured peak-to-peak.
1000BASE-X mode.
Measured peak-to-peak.
100BASE-FX mode.
6.1.7
LED Pins
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 3.30 V
VDD33 is 3.30 V
VDD12 is 1.20 V
VDD12A is 1.20 V
Table 68 • DC Characteristics for LED[3:0]_n Pins
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage
VOH
VOL
IOLEAK
IOL
2.4
0
3.6
0.5
10
V
IOH = –4.0 mA
IOL = 4.0 mA
Output low voltage
V
Output leakage current
Output low current drive strength
Output high current drive strength
–10
µA
mA
mA
8.0
IOH
–8.0
6.1.8
JTAG Pins
In addition to any parameter-specific conditions, the specifications listed in the following table may be
considered valid only when:
•
•
•
•
VDDIO is 3.30 V
VDD33 is 3.30 V
VDD12 is 1.20 V
VDD12A is 1.20 V
Table 69 • DC Characteristics for JTAG Pins
Parameter
Symbol Minimum Maximum Unit
Condition
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
VOH
VOL
VIH
2.4
0
3.6
0.5
3.6
0.9
42
42
8
V
IOH = –1.5 mA
IOL = 1.5 mA
V
2.1
–0.3
–42
–42
V
VIL
V
IILEAK
µA
µA
mA
Internal resistor included
Internal resistor included
Output leakage current IOLEAK
Output low current drive IOL
strength
Output high current
drive strength
IOH
–8
mA
VMDS-10242 VSC8658 Datasheet Revision 4.1
64
Electrical Specifications
6.2
Current Consumption
There are three sets of current consumption values:
•
•
•
Typical current consumption
Current consumption in SerDes/SGMII to 1000BASE-X mode
Current consumption in SerDes/SGMII to 100BASE-FX mode or SerDes pass-through mode
The typical current consumption values are based on nominal voltages with all ports operating at
1000BASE-T speeds with full-duplex enabled and a 64-bit random data pattern at 100% utilization.
Table 70 • Typical Current Consumption
Parameter
Symbol Typical
Maximum Unit
Worst-case power consumption
Current with VDDIO at 1.8 V
Current with VDDIO at 2.5 V
Current with VDDIO at 3.3 V
Current with VDD33 at 3.3 V
Current with VDD12 at 1.2 V
Current with VDD12A at 1.2 V
PD
5.91
W
IVDDIO
IVDDIO
IVDDIO
IVDD33
IVDD12
1
mA
mA
mA
mA
mA
mA
1
1
852
1488
IVDD12A 490
If all eight ports are running in SerDes/SGMII to 1000BASE-X mode, the current consumption values are
shown in the following table.
Table 71 • Current Consumption in SerDes/SGMII to 1000BASE-X Mode
Parameter
Symbol Typical
Maximum Unit
Worst-case power consumption
Current with VDDIO at 1.8 V
Current with VDDIO at 2.5 V
Current with VDDIO at 3.3 V
Current with VDD33 at 3.3 V
Current with VDD12 at 1.2 V
Current with VDD12A at 1.2V
PD
1.05
W
IVDDIO
IVDDIO
IVDDIO
IVDD33
IVDD12
1
mA
mA
mA
mA
mA
mA
1
1
68.6
134.2
IVDD12A 448.6
If all eight ports are running in SerDes/SGMII to 100BASE-FX mode or SerDes pass-through mode, the
current consumption values are as shown in the following table.
Table 72 • Consumption in SerDes/SGMII to 100BASE-FX or SerDes Pass-Through Mode
Parameter
Symbol Typical
Maximum
Unit
W
Worst-case power consumption
Current with VDDIO at 1.8 V
Current with VDDIO at 2.5 V
Current with VDDIO at 3.3 V
Current with VDD33
PD
1.09
IVDDIO
IVDDIO
IVDDIO
IVDD33
IVDD12
1
mA
mA
mA
mA
mA
mA
1
1
64
146
Current with VDD12
Current with VDD12A
IVDD12A 444
VMDS-10242 VSC8658 Datasheet Revision 4.1
65
Electrical Specifications
6.3
AC Characteristics
The AC specifications are grouped according to specific device pins and associated timing
characteristics.
6.3.1
Reference Clock Input
The following table shows the specifications for the reference clock input frequency including various
frequencies, duty cycle, and accuracy.
Table 73 • AC Characteristics for REFCLK Input
Parameter
Symbol Minimum Typical Maximum Unit
Frequency with 25 MHz input
Frequency with 125 MHz input
Frequency accuracy
fCLK25
fCLK125
fTOL
25
MHz
MHz
ppm
%
125
100
60
4
Duty cycle
%
40
DUTY
Rise time with 25 MHz input (20% to 80%)
tR25
ns
Rise time with 125 MHz input (20% to 80%) tR125
Fall time with 25 MHz input (20% to 80%) tR25
Fall time with 125 MHz input (20% to 80%) tF125
1
ns
4
ns
1
ns
If using the 25 MHz crystal clock input option, the additional specifications in the following table are
required.
Table 74 • AC Characteristics for REFCLK Input with 25 MHz Clock Input
Parameter
Minimum Typical
Maximum Unit
Crystal parallel load capacitance
Crystal equivalent series resistance
Crystal accuracy
18
20
30
50
pF
10
Ω
ppm
6.3.2
Clock Output
The specifications in the following table show the AC characteristics for the clock output of the VSC8658
device when used in your design.
Table 75 • AC Characteristics for the CLKOUT Pin
Parameter
Symbol
Minimum
Typical
Maximum
Unit Condition
CLKOUT frequency
fCLK125
125.00
156.25
MHz 125 MHz output clock
156.25 MHz output clock
CLKOUT cycle time
tCYC
8.0
6.4
ns
125 MHz output clock
156.25 MHz output clock
Frequency stability
Duty cycle
fSTABILITY
100
60
1
ppm
%
%
40
50
DUTY
Clock rise and fall times tR and tF
(20% to 80%)
ns
Total jitter
JCLK
217
491
ps
Measured peak-to-peak
VMDS-10242 VSC8658 Datasheet Revision 4.1
66
Electrical Specifications
6.3.3
JTAG Interface
The following table lists the characteristics for the JTAG testing feature. The illustration provides a
diagram of the timing.
Table 76 • AC Characteristics for the JTAG Interface
Parameter
Symbol Minimum Maximum Unit
TCK frequency
fCLK
tCYC
tWH
tWL
tSU
tH
10
MHz
ns
TCK cycle time
100
45
45
10
10
TCK time high
ns
TCK time low
ns
Setup time to TCK rising
Hold time from TCK rising
TCK to TDO valid
ns
ns
tCO
15
ns
Figure 19 • JTAG Interface Timing
tCYC
TCK
tWL
tWH
tSU
tH
TDI
TMS
TDO
tCO
6.3.4
SMI Interface
Use the information in the following table when incorporating the VSC8658 device SMI interface into your
own design. The illustration provides information about SMI interface timing.
Table 77 • AC Characteristics for the SMI Interface
Parameter
Symbol Minimum
Typical
2.5
Maximum Unit Condition
MDC frequency(1)
MDC cycle time
MDC time high
MDC time low
fCLK
12.5
MHz
ns
tCYC
tWH
tWL
80
20
20
10
10
400
50
ns
50
ns
Setup to MDC rising tSU
ns
Hold from MDC
rising
tH
ns
MDC rise time
tR
100
ns
For MDC = 0 – 1 MHz
For MDC = 1 MHz – fCLK(MAX)
tCYC × 10%(1)
VMDS-10242 VSC8658 Datasheet Revision 4.1
67
Electrical Specifications
Table 77 • AC Characteristics for the SMI Interface (continued)
Parameter
Symbol Minimum
tF 100
CYC × 10%(1)
Typical
Maximum Unit Condition
MDC fall time
t
MDC to MDIO valid tCO
10
300
ns
Time-dependant on the value of
the external pull-up resistor on
the MDIO pin
1. For fCLK above 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC clock period. For example,
if fCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns.
Figure 20 • SMI Interface Timing
tWH
tWL
MDC
tCYC
tSU
tH
MDIO
(write)
Data
tCO
MDIO
(read)
Data
6.3.5
Device Reset
The following specifications apply to the device reset functionality. The illustration shows the reset timing.
Table 78 • AC Characteristics for Device Reset
Parameter
Symbol
tRESET
tWAIT
Minimum Maximum Unit Condition
NRESET assertion time
100
ns
Wait time between
NRESET de-assert and
access of the SMI
interface
20
220
ms
ms
Register 21E.14 = 0
Register 21E.14 = 1
Soft reset (pin) assertion tSRESET_ASSERT
4
4
ms
ms
Soft reset (pin) de-
assertion
tSRESET_DEASSERT
Wait time between soft
reset pin de-assert and
access of the SMI
interface
tSWAIT
4
µs
µs
ms
ms
Registers 22.9 = 1, 21E.14 = 0
Registers 22.9 = 0, 21E.14 = 0
Registers 22.9 = 0, 21E.14 = 1
Registers 22.9 = 1, 21E.14 = 1
300
200
200
Soft reset MII register 0.15 tSREG_RESET
assertion
100
ns
VMDS-10242 VSC8658 Datasheet Revision 4.1
68
Electrical Specifications
Table 78 • AC Characteristics for Device Reset (continued)
Parameter
Symbol
Minimum Maximum Unit Condition
Wait time between Soft
Reset (MII Register 0.15)
de-assert and access to
the SMI interface
tSREG_WAIT
4
µs
µs
ms
ms
Registers 22.9 = 1, 21E.14 = 0
Registers 22.9 = 0, 21E.14 = 0
Registers 22.9 = 0, 21E.14 = 1
Registers 22.9 = 1, 21E.14 = 1
300
200
200
Figure 21 • Reset Timing
REFCLK
tWAIT
tRESET
NRESET
tSWAIT
tSRESET_ASSERT
tSRESET_DEASSERT
NSRESET
tSREG_WAIT
tSREG_RESET
Soft Reset
(MII Register 0.15)
Undefined State
MDC
MDIO
6.3.6
Serial LEDs
The following table provides specifications for the device serial LEDs. The illustration shows the LED
timing.
Table 79 • AC Characteristics for Serial LEDs
Parameter
Symbol Minimum Maximum Unit
LED_CLK cycle time
tCYC
tPAUSE
tCO
1
µs
ms
ns
Pause between LED bit sequences
LED_CLK to LED_DATA
25
1
VMDS-10242 VSC8658 Datasheet Revision 4.1
69
Electrical Specifications
Figure 22 • Serial LED Timing
tCYC
tPAUSE
LED_CLK
tCO
Bit 1
Bit 2
Bit 96
LED_DATA
Bit 1
6.4
Operating Conditions
The following table shows the recommended operating conditions for the VSC8658 device.
Table 80 • Recommended Operating Conditions
Parameter
Symbol Minimum Typical
Maximum Unit
Power supply voltage for VDDIO at 1.8 V VDDIO
Power supply voltage for VDDIO at 2.5 V VDDIO
Power supply voltage for VDDIO at 3.3 V VDDIO
1.70
2.37
3.13
3.13
1.14
1.80
2.50
3.30
3.30
1.20
1.20
1.90
2.63
3.47
3.47
1.26
1.26
90
V
V
V
V
V
V
°C
Power supply voltage for VDD33
Power supply voltage for VDD12
Power supply voltage for VDD12A
Operating temperature(1)
VDD33
VDD12
VDD12A 1.14
T
0
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
6.5
Stress Ratings
This section contains the stress ratings for the VSC8658 device.
Warning Stresses listed in the following table may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these
values for extended periods may affect device reliability.
Table 81 • Stress Ratings
Parameter
Symbol
VDDIO
Minimum
–0.5
Maximum Unit
DC input voltage on VDDIO supply pin
DC input voltage on VDD33 supply pin
DC input voltage on VDD12 supply pin
DC input voltage on VDD12A supply pin
DC input voltage on JTAG 5 V-tolerant pins
DC input voltage on any non-supply pin
Storage temperature
4.0
V
V
V
V
V
V
oC
V
VDD33
–0.5
4.0
VDD12
–0.5
1.4
VDD12A
–0.5
1.4
V
DD(5 V)
–0.5
5.5
VDD(PIN)
TS
–0.5
VDD + 0.5
150
250
–65
Electrostatic discharge voltage, charged device
model
VESD_CDM –250
Electrostatic discharge voltage, human body model VESD_HBM See note(1)
VMDS-10242 VSC8658 Datasheet Revision 4.1
V
70
Electrical Specifications
1. This device has completed all required testing as specified in the JEDEC standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a Class 2
rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an ESD pulse of
4000 V.
Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures may adversely affect reliability of the device.
VMDS-10242 VSC8658 Datasheet Revision 4.1
71
Pin Descriptions
7
Pin Descriptions
The VSC8658 device has 444 pins, which are described in this section.
7.1
Pin Diagram
The following illustrations show the pin diagram for the VSC8658 device. For clarity, the device is shown
in two halves in Figure 23, page 72 and Figure 24, page 73.
Figure 23 • Pin Diagram, Left Side, Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VSS
TXVPB_6 TXVPC_6 TXVPD_6 TXVPA_5 TXVPB_5 TXVPC_5 TXVPD_5 TXVPA_4 TXVPB_4 TXVPC_4 TXVPD_4
TXVNB_6 TXVNC_6 TXVND_6 TXVNA_5 TXVNB_5 TXVNC_5 TXVND_5 TXVNA_4 TXVNB_4 TXVNC_4 TXVND_4
A
B
VSS
TXVPA_6 TXVNA_6 VDD33
TXVPD_7 TXVND_7 VDD33
TXVPC_7 TXVNC_7 VDD12A
VDD33
VDD33
VDD12A
VSS
VSS
NC
VDD12A
VDD12A
VSS
VSS
VSS
VSS
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD12A
VDD12 A
C
VDD12A
D
E
TXVPB_7 TXVNB_7
TXVPA_7 TXVNA_7
VSS
NC
F
REF_REXT_B
REF_FILT_B
VSS
G
VSS
XTAL1/REFCLK
VSS
VSS
XTAL2
VSS
VSS
H
LED3_7
LED1_7
LED3_5
LED1_5
VDD33
LED3_4
LED1_4
NTRST
M DC
LED2_7
LED0_7
LED2_5
LED0_5
VDD33
LED2_4
LED0_4
TDO
J
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
LED3_6
LED1_6
VDD33
EECLK
LED2_6
LED0_6
VDD33
EEDAT
L
VSS
VSS
VSS
VSS
VSS
M
VSS
VSS
VSS
VSS
VSS
N
VSS
VSS
VSS
VSS
VSS
P
PLLM ODE OSCEN
VSS
VSS
VSS
VSS
VSS
R
TM S
TDI
TCK
VSS
VSS
VSS
VSS
VSS
T
VDDIO
VDDIO
VDD33
VSS
VDD12
VDD12
VDD12
VDD12
VDD12
U
CLKOUT
M DIO
V
M DINT_0 M DINT_1 MDINT_2 M DINT_3
M DINT_4 M DINT_5 MDINT_6 M DINT_7
W
Y
NRESET
VSS
VSS
VDDIO
VDD12A
VSS
AA
AB
AC
AD
AE
AF
SER_DON_7 SER_DOP_7
SER_DIN_7 SER_DIP_7
MAC_RDN_7 MAC_RDP_7
MAC_TDN_7 MAC_TDP_7
VSS
VSS
VDD12A
VDD33
VSS
VSS
VDD12A
VDD33
VDD12A
VDD12A
VSS
VSS
VSS
VSS
VDD12A
VDD33
VDD12A
VDD33
VDD12A
VSS
VDD33
SER_DoP_6 SER_DIP_6 MAC_RDP_6 MAC_TDP_6 SER_DoP_5 SER_DiP_5 MAC_RDP_5 MAC_TDP_5 SER_DoP_4 SER_DiP_4 MAC_RDP_4 MAC_TDP_4
SER_DoN_6 SER_DIN_6 MAC_RDN_6 MAC_TDN_6 SER_DoN_5 SER_DiN_5 MAC_RDN_5 MAC_TDN_5 SER_ DoN_4 SER_DiN_4 MAC_RDN_4 MAC_TDN_4
1
2
3
4
5
6
7
8
9
10
11
12
13
VMDS-10242 VSC8658 Datasheet Revision 4.1
72
Pin Descriptions
Figure 24 • Pin Diagram, Right Side, Top View
14
15
16
17
18
19
2 0
2 1
2 2
2 3
2 4
2 5
2 6
TXVPA_3 TXVPB_3 TXVPC_3 TXVPD_3 TXVPA_2 TXVPB_2 TXVPC_2 TXVPD_2 TXVPA_1 TXVPB_1 TXVPC_1 TXVPD_1
TXVNA_3 TXVNB_3 TXVNC_3 TXVND_3 TXVNA_2 TXVNB_2 TXVNC_2 TXVND_2 TXVNA_1 TXVNB_1 TXVNC_1 TXVND_1
A
B
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VDD33
VDD33
VSS
VSS
VDD12A
VDD12A
VDD12A
VDD12A
VDD33
VDD33
NC
VDD33
VSS
VSS
VDD33
C
VDD33
VDD12A
TXVNA_0 TXVPA_0
D
VDD12A TXVNB_0 TXVPB_0
E
REF_FILT_A
REF_REXT_A
VDD33
VDD33
VDD33
VSS
VDD33
NC
TXVNC_0 TXVPC_0
TXVND_0 TXVPD_0
F
G
VDD33
CM ODE7
VSS
H
CM ODE6 CM ODE5 CM ODE4
CM ODE3 CM ODE2 CM ODE1
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
K
VSS
CM ODE0
VDD33
LED0_2
LED2_2
LED0_3
LED2_3
GPIO11
LED1_0
LED3_0
LED1_1
LED3_1
VDD33
GPIO14
GPIO12
GPIO8
LED0_0
LED2_0
LED0_1
LED2_1
VDD33
GPIO15
GPIO13
GPIO9
L
VSS
VSS
VSS
VSS
VSS
VDD33
LED1_2
LED3_2
LED1_3
LED3_3
GPIO10
M
VSS
VSS
VSS
VSS
VSS
N
VSS
VSS
VSS
VSS
VSS
P
VSS
VSS
VSS
VSS
VSS
R
VSS
VSS
VSS
VSS
VSS
T
VDD12
VDD12
VDD12
VDD12
VDD12
U
GPIO6
GPIO2
GPIO0
/
/
/
SIGDET_6 GPIO7
/
/
/
SIGDET_7
SIGDET_3
SIGDET_1
V
SIGDET_2
SIGDET_0
GPIO3
GPIO1
GPIO4
/
SIGDET_4
GPIO5 / SIGDET_5
W
Y
VSS
VSS
VDD33
VDD33
VSS
VSS
AA
AB
AC
AD
AE
AF
MAC_TDP _0 MAC_TDN_0
MAC_RDP_0 MAC_RDN_0
VDD12A
VSS
VDD12A
VSS
VDD12A
VSS
VSS
VDD12A
VSS
VDD12A
VDD12A
VDD12A
VDD33
VSS
VSS
VSS
VDD12A SER_DIP_0
VSS
SER_DIN_0
VDD33
VDD33
VDD33
VSS
SER_DOP_0 SER_DON_0
VSS
SER_DOP_3 SER_DIP_3 MAC_RDP_3 MAC_TDP_3 SER_DOP_2 SER_DIP_2 MAC_RDP_2 MAC_TDP_2 SER_DOP_1 SER_DIP_1 MAC_RDP_1 MAC_TDP_1
SER_DON_3 SER_DIN_3 MAC_RDN_3 MAC_TDN_3 SER_DON_2 SER_DIN_2 MAC_RDN_2 MAC_TDN_2 SER_DON_1 SER_DIN_1 MAC_RDN_1 MAC_TDN_1
14
15
16
17
18
19
2 0
2 1
2 2
2 3
2 4
2 5
2 6
7.2
Pin Identifications
This section contains the functional pin descriptions for the VSC8658 device.
VMDS-10242 VSC8658 Datasheet Revision 4.1
73
Pin Descriptions
7.2.1
SerDes MAC Interface
The following table shows the pins associated with the device SerDes MAC interface.
Table 82 • SerDes MAC Interface Pins
Pin
Name
Type
Description
AD2
AE5
AE9
AE13
AE17
AE21
AE25
AA25
AD1
MAC_TDP_7
MAC_TDP_6
MAC_TDP_5
MAC_TDP_4
MAC_TDP_3
MAC_TDP_2
MAC_TDP_1
MAC_TDP_0
MAC_TDN_7
MAC_TDN_6
MAC_TDN_5
MAC_TDN_4
MAC_TDN_3
MAC_TDN_2
MAC_TDN_1
MAC_TDN_0
IDIFF
SerDes MAC transmitter input pair.
AF5
AF9
AF13
AF17
AF21
AF25
AA26
AC2
AE4
AE8
AE12
AE16
AE20
AE24
AB25
AC1
MAC_RDP_7
MAC_RDP_6
MAC_RDP_5
MAC_RDP_4
MAC_RDP_3
MAC_RDP_2
MAC_RDP_1
MAC_RDP_0
MAC_RDN_7
MAC_RDN_6
MAC_RDN_5
MAC_RDN_4
MAC_RDN_3
MAC_RDN_2
MAC_RDN_1
MAC_RDN_0
ODIFF
SerDes MAC receiver output pair.
AF4
AF8
AF12
AF16
AF20
AF24
AB26
7.2.2
SerDes Media Interface
The following table shows the pins associated with the device SerDes media interface.
Table 83 • SerDes Media Interface Pins
Pin
Signal Name
Type
Description
VMDS-10242 VSC8658 Datasheet Revision 4.1
74
Pin Descriptions
Table 83 • SerDes Media Interface Pins (continued)
AA2
AE2
AE6
AE10
AE14
AE18
AE22
AD25
AA1
SER_DOP_7
SER_DOP_6
SER_DOP_5
SER_DOP_4
SER_DOP_3
SER_DOP_2
SER_DOP_1
SER_DOP_0
SER_DON_7
SER_DON_6
SER_DON_5
SER_DON_4
SER_DON_3
SER_DON_2
SER_DON_1
SER_DON_0
ODIFF
SerDes media transmitter output pair.
AF2
AF6
AF10
AF14
AF18
AF22
AD26
AB2
AE3
AE7
AE11
AE15
AE19
AE23
AC25
AB1
SER_DIP_7
SER_DIP_6
SER_DIP_5
SER_DIP_4
SER_DIP_3
SER_DIP_2
SER_DIP_1
SER_DIP_0
SER_DIN_7
SER_DIN_6
SER_DIN_5
SER_DIN_4
SER_DIN_3
SER_DIN_2
SER_DIN_1
SER_DIN_0
IDIFF
SerDes media receiver input pair.
AF3
AF7
AF11
AF15
AF19
AF23
AC26
7.2.3
GPIO and SIGDET
The following table shows the pins associated with the device GPIO and SIGDET.
Table 84 • GPIO and SIGDET Pins
Pin
Name
Type
Description
T26
T25
U26
U25
U24
U23
V26
V25
V24
V23
W26
W25
W24
W23
Y24
Y23
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7 / SIGDET_7
GPIO6 / SIGDET_6
GPIO5 / SIGDET_5
GPIO4 / SIGDET_4
GPIO3 / SIGDET_3
GPIO2 / SIGDET_2
GPIO1 / SIGDET_1
GPIO0 / SIGDET_0
IPD/O
General purpose input/output (GPIO). Eight
dedicated GPIO pins are provided. Additionally, the
eight SIGDET pins can be configured to become
GPIO pins if not used.
VMDS-10242 VSC8658 Datasheet Revision 4.1
75
Pin Descriptions
7.2.4
Twisted Pair Interface
The following table lists the device pins associated with the device two-wire, twisted pair interface.
Table 85 • Twisted Pair Interface Pins
Pin
Name
Type
Description
G1
C1
A6
A10
A14
A18
A22
D26
TXVPA_7
TXVPA_6
TXVPA_5
TXVPA_4
TXVPA_3
TXVPA_2
TXVPA_1
TXVPA_0
ADIFF
TX/RX channel A positive signal
G2
C2
B6
B10
B14
B18
B22
D25
TXVNA_7
TXVNA_6
TXVNA_5
TXVNA_4
TXVNA_3
TXVNA_2
TXVNA_1
TXVNA_0
ADIFF
ADIFF
ADIFF
ADIFF
ADIFF
TX/RX channel A negative signal
TX/RX channel B positive signal
TX/RX channel B negative signal
TX/RX channel C positive signal
TX/RX channel C negative signal
F1
A3
A7
A11
A15
A19
A23
E26
TXVPB_7
TXVPB_6
TXVPB_5
TXVPB_4
TXVPB_3
TXVPB_2
TXVPB_1
TXVPB_0
F2
B3
B7
B11
B15
B19
B23
E25
TXVNB_7
TXVNB_6
TXVNB_5
TXVNB_4
TXVNB_3
TXVNB_2
TXVNB_1
TXVNB_0
E1
A4
A8
A12
A16
A20
A24
F26
TXVPC_7
TXVPC_6
TXVPC_5
TXVPC_4
TXVPC_3
TXVPC_2
TXVPC_1
TXVPC_0
E2
B4
B8
B12
B16
B20
B24
F25
TXVNC_7
TXVNC_6
TXVNC_5
TXVNC_4
TXVNC_3
TXVNC_2
TXVNC_1
TXVNC_0
VMDS-10242 VSC8658 Datasheet Revision 4.1
76
Pin Descriptions
Table 85 • Twisted Pair Interface Pins (continued)
Pin
Name
Type
Description
D1
A5
A9
A13
A17
A21
A25
G26
TXVPD_7
TXVPD_6
TXVPD_5
TXVPD_4
TXVPD_3
TXVPD_2
TXVPD_1
TXVPD_0
ADIFF
TX/RX channel D positive signal
D2
B5
B9
B13
B17
B21
B25
G25
TXVND_7
TXVND_6
TXVND_5
TXVND_4
TXVND_3
TXVND_2
TXVND_1
TXVND_0
ADIFF
TX/RX channel D negative signal
7.2.5
Serial Management Interface
The following table lists the device pins associated with the device serial management interface (SMI).
Note that the pins in this table, except for EECLK and EEDAT, are referenced to VDDIO and can be set to
a 1.8 V, 2.5 V, or 3.3 V power supply. The EECLK and EEDAT pins are instead referenced to VDD33.
Table 86 • SMI Pins
Pin
Name
Type
Description
U3
MDC
I
Management data clock. A 0 MHz to 12.5 MHz reference
input is used to clock serial MDIO data into and out of the
PHY.
V3
MDIO
OD
Management data input/output pin. Serial data is written
or read from this pin bidirectionally between the PHY and
Station Manager, synchronously on the positive edge of
MDC. One external pull-up resistor is required at the
Station Manager, and its value depends on the MDC clock
frequency and the total sum of the capacitive loads from
the MDIO pins.
Y4
Y3
Y2
Y1
W4
W3
W2
W1
MDINT_7
MDINT_6
MDINT_5
MDINT_4
MDINT_3
MDINT_2
MDINT_1
MDINT_0
OS/OD Management interrupt signal. Upon reset the device will
configure these pins as active-low (open drain) or active-
high (open source) based on the polarity of an external
10 kΩ resistor connection. These pins can be tied
together in a wired-OR configuration with only a single
pull-up or pull-down resistor.
VMDS-10242 VSC8658 Datasheet Revision 4.1
77
Pin Descriptions
Table 86 • SMI Pins (continued)
Pin
Name
Type
Description
P2
EEDAT
IPD/O
(Optional) EEPROM serial I/O data. Used to configure
PHYs in a system without a Station Manager. Connect to
the SDA pin of the ATMEL “AT24CXXX” serial EEPROM
device family.
The VSC8658 device determines that an external
EEPROM is present by monitoring the EEDAT pin at
power-up or when NRESET is de-asserted. If EEDAT has
a 4.7 kΩ external pull-up resistor, the VSC8658 assumes
an EEPROM is present. The EEDAT pin can be left
floating or grounded to indicate no EEPROM.
P1
EECLK
O
(Optional) EEPROM serial output clock. Used to configure
PHYs in a system without a station manager. Connect to
the SCL pin of the ATMEL “AT24CXXX” serial EEPROM
device family.
AA3
V1
NRESET
CLKOUT
IPU
O
Device reset. Active low input that powers down the
device and sets the register bits to their default state.
Clock output can be enabled or disabled and also output
a reference clock frequency of 125 MHz or 156.25 MHz
using CMODE or register setting. This pin is not active
when NRESET is asserted. When disabled, the pin is held
low.
7.2.6
JTAG
The following table lists the pins associated with the device JTAG testing facility.
Table 87 • JTAG Pins
Pin
U1
T4
T1
T2
T3
Name
TDI
Type
IPU5V
O
Description
JTAG test serial data input.
JTAG test serial data output.
JTAG test mode select.
JTAG test clock input.
TDO
TMS
TCK
IPU5V
IPU5V
IPU5V
NTRST
JTAG reset. If JTAG is not used, then tie this pin to VSS
(ground) with a pull-down resistor.
7.2.7
Power Supply
The following table lists the device power supply pins.
Table 88 • Power Supply Pins
Pin
Name
Type
Description
C3 C4 C10 C11 C12 C16 C17 C21 C23 VDD33
C25 D3 D4 D10 D11 D12 D16 D17 D21
D22 F24 G23 H23 H24 J23 M23 M24
N1 N2 N3 N4 R25 R26 U4 AA23 AB23
AD3 AD5 AD7 AD11 AD12 AD14 AD17
AD20 AD21
3.3 V
General 3.3 V power supply
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Pin Descriptions
Table 88 • Power Supply Pins (continued)
Pin
Name
Type
Description
U2 V2 AB4
VDDIO
3.3 V
2.5 V
1.8 V
I/O power supply
K8 K19 L8 L19 M8 M19 N8 N19 P8
P19 R8 R19 T8 T19 U8 U9 U10 U11
U12 U13 U14 U15 U16 U17 U18 U19
VDD12
1.2 V
Internal digital core voltage
C7 C13 C19 C20 D6 D7 D13 D19 D20 VDD12A
D23 E3 E4 E24 AB24 AC4 AC5 AC7
AC8 AC11 AC12 AC13 AC15 AC16
1.2 V
1.2 V analog power requiring additional PCB power
supply filtering
AC18 AC19 AC20 AC24 AD8 AD19
A2 B1 B2 B26 C5 C8 C9 C14 C15 C18 VSS
C24 C26 D5 D8 D9 D14 D15 D18 D24
F3 H1 H2 H3 H4 H26 K1 K2 K9 K10
K11 K12 K13 K14 K15 K16 K17 K18
K23 L9 L10 L11 L12 L13 L14 L15 L16
L17 L18 L23 M9 M10 M11 M12 M13
M14 M15 M16 M17 M18 N9 N10 N11
N12 N13 N14 N15 N16 N17 N18 P9
P10 P11 P12 P13 P14 P15 P16 P17
P18 R9 R10 R11 R12 R13 R14 R15
R16 R17 R18 T9 T10 T11 T12 T13 T14
T15 T16 T17 T18 V4 Y25 Y26 AA4
AA24 AB3 AC3 AC6 AC9 AC10 AC14
AC17 AC21 AC22 AC23 AD4 AD6 AD9
AD10 AD13 AD15 AD16 AD18 AD22
AD23 AD24 AE1 AE26
0 V
General device ground
Although certain function pins may not be used for a specific application, all power supply pins must be
connected to their respective voltage input.
Table 89 • Power Supply and Associated Function Pins
Nominal
Pin
Voltage
Associated Functional Pins
VDD33
3.3 V
LED[3:0]_n, GPIO[15:0], EECLK, EEDAT, JTAG (5), XTAL1,
XTAL2, CMODE, TXVP_n, TXVN_n, REF_FILT, REF_REXT
VDDIO
1.8 V, 2.5 V,
3.3 V
MDC, MDIO, MDINT_n, nRESET, CLKOUT
VDD12A
VDD12
1.2 V
1.2 V
MAC_RDP/N_n, MAC_TDP/N_n
N/A (Internal Core Voltage)
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Pin Descriptions
7.2.8
Miscellaneous
The following table lists pins not associated with a particular interface or facility on the device.
Table 90 • Miscellaneous Pins
Pin
Name
Type
Description
H25
J24
J25
J26
K24
K25
K26
L24
CMODE7
CMODE6
CMODE5
CMODE4
CMODE3
CMODE2
CMODE1
CMODE0
IA
Configuration mode (CMODE) pins. For more
information, see CMODE, page 55.
J1
XTAL1/REFCLK I
Crystal oscillator input. If OSCEN=high then a
25 MHz parallel resonant crystal with +/–50 ppm
frequency tolerance should be connected across
XTAL1 and XTAL2. A 33 pF capacitor should also
tie the XTAL1 pin to ground.
Reference clock input. If OSCEN=low, the clock
input frequency can either be 25 MHz
(PLLMODE=0) or 125 MHZ (PLLMODE is high).
J2
XTAL2
OCRYST Crystal oscillator output. The crystal should be
connected across XTAL1 and XTAL2. A 33 pF
capacitor should also tie the XTAL2 pin to ground.
If not using a crystal oscillator, this output pin can
be left floating if driving XTAL1/REFCLK with a
reference clock.
R2
R1
OSCEN
IPD
Oscillator enable. This pin is sampled on the rising
edge of NRESET. If HIGH, then the on-chip
oscillator circuit is enabled. If low (or left floating),
the oscillator circuit is disabled and the device
must be supplied with a 25 MHz or 125 MHz
reference clock to the REFCLK pin
PLLMODE
IPD
PLL mode input select. Sampled on power-up or
reset. If PLLMODE is low, then REFCLK must be
25 MHz. If PLLMODE is high, then REFCLK must
be 125 MHz.
J3 J4 K3 K4
L1 L2 M1 M2
L3 L4 M3 M4
P3 P4 R3 R4
T23 T24 R23 R24
P23 P24 N23 N24
P25 P26 N25 N26
M25 M26 L25 L26
LED[3:0]_7
LED[3:0]_6
LED[3:0]_5
LED[3:0]_4
LED[3:0]_3
LED[3:0]_2
LED[3:0]_1
LED[3:0]_0
O
LED direct-drive outputs. All LEDs pins are active-
low. A serial LED stream can also be
implemented. For more information about LED
operation, see LED Mode Select, page 43.
F23
E23
F4
REF_REXT_A ABIAS
REF_FILT_A ABIAS
REF_REXT_B ABIAS
Reference external connects to an external 2 KΩ
(1%) resistor to analog ground.
Reference filter connects to an external 1 µF
capacitor to analog ground.
Reference external connects to an external 2 KΩ
(1%) resistor to analog ground.
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Pin Descriptions
Table 90 • Miscellaneous Pins (continued)
Pin
Name
Type
Description
G4
REF_FILT_B
ABIAS
Reference filter connects to an external 1 µF
capacitor to analog ground.
G3 C6 C22 G24
NC
NC
These pins are no connects. Do not connect them
together or to ground. Leave these pins
unconnected (floating).
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Package Information
8
Package Information
The VSC8658 device is available in two package types. VSC8658HJ is a 444-pin, thermally enhanced,
plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum
height. The device is also available in a lead(Pb)-free package, VSC8658XHJ.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the
VSC8658 device.
8.1
Package Drawing
The following illustration shows the package drawing for the VSC8658 device. The drawing contains the
top view, bottom view, side view, dimensions, tolerances, and notes.
VMDS-10242 VSC8658 Datasheet Revision 4.1
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Package Information
Figure 25 • Package Drawing
Top View
Bottom View
0.10 M
0.25 M
C
C
A
B
Pin #1 corner
0.50~ 0.70 ( 44 )
2
4
6
8
10 12 14 16 18 20 22 24 26
9 11 13 15 17 19 21 23 25
26 24 22 20 18 16 14 12 10
25 23 21 19 17 15 13 11
8
6
4
2
1
3
5
7
9
7
5
3
1
A
C
A
C
B
D
F
B
D
F
E
E
G
J
G
J
H
K
M
P
H
K
M
P
L
L
N
R
N
R
T
T
U
W
AA
AB
AC
AD
AE
AF
U
V
Y
V
Y
W
AA
AB
AC
AD
AE
AF
E
1.00
4.00 * 45 (4 )
24.00 Ref.
B
Heat slug
19.0~20.0
25.00
D
A
27.00 +/-0.20
0.06
0.30 S C A S B S
0.50 S C D S E S
0.20 (4 )
Side View
30 Typ.
C
Seating plane
Note:
All dimensions are in millimeters (mm).
8.2
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
PCB). For more information, see the JEDEC standard.
Table 91 • Thermal Resistances
θJA (°C/W) vs. Airflow (ft/min)
Part Order Number
VSC8658HJ
θJC
4.1
4.1
θJB
7.3
7.3
0
100
200
13
13.4
13.4
13.2
13.2
VSC8658XHJ
13
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Package Information
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board
design described in the JEDEC standard EIA/JESD51 series must be applied. For information about
specific applications, see the following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal
Attachment Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
8.3
Moisture Sensitivity
Moisture sensitivity level ratings for Microsemi products comply with the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020.
VSC8658HJ is rated moisture sensitivity level 3 or better.
VSC8658XHJ is rated moisture sensitivity level 4.
For more information, see the IPC and JEDEC standard.
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Design Considerations
9
Design Considerations
This section provides information about design issues for the VSC8658 device.
9.1
PHY Address ID (Register 23E, Bits 15 to 11)
Issue: The PHY Address ID in Register 23E does not function as intended. It can only indicate the
physical PHY port numbers 0 through 7 instead of those set through the CMODE pins.
Implications: A user needs to be aware that this address only represents the physical port number as
opposed to the actually PHY address on the MDC/MDIO bus.
Workaround: Software needing this feature must detect which specific device it is communicating to and
add a necessary offset to the address value to process the correct address.
9.2
9.3
JTAG Input High Voltage at 2.1 V
Issue: The JTAG pins do not meet the VIH(min) requirements of the CMOS and LVTTL standards. At
certain PVT corners, the minimum is 2.1 V.
Implications: None.
Workaround: None.
First SMI Write Fails After Software Reset
Issue: After applying software reset (using either register 0, bit 15 or the NSRESET pin), the first
subsequent SMI write operation into register 4 (auto-negotiation advertisement) or register 9
(1000BASE-T control) does not work. This issue only occurs if the first SMI write after software reset is
into register 4 or 9. This issue does not occur if any kind of SMI transaction (either read or write) is
applied to any register between the time of the software reset and the SMI write into register 4 or 9.
Implications: The PHY may operate unexpectedly, because settings for registers 4 and 9 remain at the
reset value. There are no such implications after either hardware reset or power-down events.
Workaround: Writing “0x0000” into register 31 after every software reset avoids this issue, and
subsequent SMI writes into register 4 or 9 succeed.
9.4
9.5
LED3 Port 7 Coupling Issue into XTAL Clock Pin
Issue: Whenever LED3 Port 7 blinks, the resulting noise couples into the XTAL clock input pin. This
causes additional noise on the transmit SerDes interface in the form of transmit jitter. In this case,
transmit jitter increases to a value in the range of 360 ps to 380 ps. This behavior is not seen with other
LED pins.
Implications: Using both the LED3 Port 7 and XTAL pins causes a higher level of transmit jitter on the
SerDes interface of the device.
Workaround: For better performance, avoid using the LED3 Port 7 pin as an LED indication.
100BASE-FX Clock Data Recovery Improvement
Issue: It is possible to improve the overall receive data performance in 100BASE-FX media by changing
the standard settings for the Clock Data Recovery (CDR) block.
Implications: While there is a low chance of seeing an issue in 100BASE-FX, it is recommended to
implement this script.
Workaround: There is a software workaround for this problem that can improve the 100BASE-FX CDR.
Change the CDR settings using the following script at PHY initialization time:
PhyWrite( PortNo, Register (dec), 16_bit_unsigned_data(hex) );
16_bit_unsigned_data = PhyRead( PortNo, Register (dec) );
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Design Considerations
PhyWrite( PortNo, 31, 0x52b5 ); // Switch to internal block
PhyWrite( PortNo, 16, 0xae0e ); // Read CDR internal register
Reg18 = PhyRead( PortNo, 18 );
Reg17 = PhyRead( PortNo, 17 );
Reg17 = Reg17 & 0xffef;
// Clear bit 4 of this register
PhyWrite( PortNo, 18, Reg18 );
PhyWrite( PortNo, 17, Reg17 );
PhyWrite( PortNo, 16, 0x8e0e ); // Write CDR internal register
PhyWrite( PortNo, 31, 0x0000 ); // Goto Normal Page
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Ordering Information
10 Ordering Information
The VSC8658 device is available in two package types. VSC8658HJ is a 444-pin, thermally enhanced,
plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum
height. The device is also available in a lead(Pb)-free package, VSC8658XHJ.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
The following table lists the ordering information for the VSC8658 device.
Table 92 • Ordering Information
Part Order Number Description
VSC8658HJ
444-pin, thermally enhanced, plastic BGA with a 27 mm × 27 mm body size,
1 mm pin pitch, and a 2.36 mm maximum height
VSC8658XHJ
Lead(Pb)-free, 444-pin, thermally enhanced, plastic BGA with a 27 mm ×
27 mm body size, 1 mm pin pitch, and a 2.36 mm maximum height
VMDS-10242 VSC8658 Datasheet Revision 4.1
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