W3E64M16S-250NBC [MICROSEMI]
DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, 1.50 MM HEIGHT, PLASTIC, BGA-60;
| 型号： | W3E64M16S-250NBC |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM, 64MX16, 0.8ns, CMOS, PBGA60, 10 X 12.50 MM, 1.50 MM HEIGHT, PLASTIC, BGA-60 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总17页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3E64M16S-XNBX
White Electronic Designs
64Mx16 DDR SDRAM
FEATURES
BENEFITS
DDR SDRAM rate = 200, 250, 266, 333**
53% SPACE SAVINGS vs. 1-1GbTSOP
Package:
• 50% Space Savings vs 2 - 512Mb FPBGA
Reduced part count
• 60 Plastic Ball Grid Array (PBGA),
10mm x 12.5mm x 1.5mm
50% I/O reduction vs FPBGA
• 9% I/O reduction vs TSOP
1Gb upgrade to 512Mb 60 FBGA SDRAM
2.5V ±0.2V core power supply
Reduced trace lengths for lower parasitic
capacitance
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Suitable for hi-reliability applications
Commands entered on each positive CK
edge
GENERAL DESCRIPTION
Internal pipelined double-data-rate (DDR)
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 2 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
The 128MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. Asingle read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Abi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 64M x 16
Weight: W3E64M16S-XSBX — 1.0 grams typical
The 128MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
* This product is subject to change without notice.
** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature
CL = 3.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
May 2008
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DENSITY COMPARISONS
TSOP Approach (mm)
11.9
Actual Size
W3E64M16S-XSBX
S
A
V
I
64Mx16
66
22.3
12.5
N
G
S
TSOP
10
Area
265mm2
66 pins
125mm2
60 Balls
53%
9%
I/O
Count
Actual Size
W3E64M16S-XSBX
CSP Approach (mm)
S
A
V
I
N
G
S
10.0
10.0
60
60
12.5
12.5
FBGA
FBGA
10
2
2
2
Area
2 x 125mm = 250mm
2 x 60 balls = 120 balls
125mm
50%
50%
I/O
60 Balls
Count
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with theACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
Prior to normal operation, the DDR SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
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BALL ASSIGNMENT (TOP VIEW) 60 BALL FBGA
x16 (Top View)
1
2
3
4
5
6
7
8
9
A
V
SSQ DQ15
V
CC
DQ0
V
SS
V
CC
Q
B
C
D
E
DQ14
DQ12
DQ10
DQ8
V
V
V
V
CC
Q
Q
Q
Q
DQ2
DQ4
DQ6
LDQS
LDM
WE#
RAS#
BA1
A0
V
SS
Q
Q
Q
Q
DQ13
DQ11
DQ9
UDQS
UDM
CK#
CKE
A9
A7
A5
DQ1
DQ3
DQ5
DQ7
DNU
SS
V
CC
CC
V
SS
SS
V
CC
V
SS
V
CC
V
REF
F
CK
CAS#
CS#
BA0
A10
A1
G
H
A12
A11
A8
A6
A4
J
K
L
A2
V
M
V
SS
A3
CC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
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FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
WE#
RAS#
CAS#
WE# RAS#
CAS#
DQ
V
REF
V
REF
A
0-12
A0-12
DQ0
0
BA0-1
CLK
BA0-1
=
=
Y
Y
CK
CK#
CKE
CS#
LDM
LDQS
=
=
Y
Y
CLK
CKE
CS
=
=
Y
Y
64Mx8
=
=
Y
Y
=
=
Y
Y
=
=
Y
Y
DQM
DQS
DQ
7
DQ
7
WE# RAS#
CAS#
DQ
V
REF
A
0-12
0
DQ
8
BA0-1
CLK
CLK#
=
=
Y
Y
=
=
Y
Y
=
=
Y
Y
64Mx8
CKE
CS#
DQM
DQS
=
=
Y
Y
=
=
Y
Y
=
DQ15
=
Y
Y
DQ
UDM
UDQS
7
INITIALIZATION
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
After CKE passes through VIH, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable command.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.)Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
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REGISTER DEFINITION
MODE REGISTER
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bitsA0-A6 set to the desired values.ADLL reset
is initiated by issuing a MODE REGISTER SET command
with bitsA7 andA9-A12 each set to zero, bitA8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; byA2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLLshould always
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be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz)
ACTIVE
SPEED
-200
CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputsA0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
≤ 75
≤ 100
≤ 100
≤ 100
≤ 100
≤ 100
≤ 125
≤ 133
≤ 166
≤ 133
—
—
-250
-266
—
-333 IND
-333 MIL
≤ 166
≤ 166
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputsA0-9 selects
the starting column location. The value on input A10
determines whether or notAUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLLis enabled automatically.)Any time the DLLis enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputsA0-9
selects the starting column location. The value on inputA10
determines whether or notAUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; ifAUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the D/Qs
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
LOAD MODE REGISTER
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FIGURE 3 MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Type = Sequential Type = Interleaved
A0
0
2
4
0-1
1-0
0-1
1-0
1
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by usingA10 to enableAUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
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FIGURE 4 – CAS LATENCY
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125μs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
theAUTO REFRESH period. TheAUTO REFRESH period
begins when theAUTO REFRESH command is registered
and ends tRFC later.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
SELF REFRESH*
The SELF REFRESH command can be used to retain
The addressing is generated by the internal refresh
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TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
H
L
RAS#
CAS#
WE#
X
ADDR
X
DESELECT (NOP) (9)
X
H
L
X
H
H
L
NO OPERATION (NOP) (9)
H
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
L
H
Bank/Row
Bank/Col
Bank/Col
X
L
H
H
H
L
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
Code
X
L
L
H
L
L
L
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
DM
L
DQs
WRITE ENABLE (10)
WRITE INHIBIT (10)
Valid
X
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH
and is automatically enabled upon exiting SELF REFRESH
(200 clock cycles must then occur before a READ
command can be issued). Input signals except CKE are
“Don’t Care” during SELF REFRESH. VREF voltage is also
required for the full duration of SELF REFRESH.
Reset and NOPs for 200 additional clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR
,
because time is required for the completion of any internal
refresh in progress.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for tXSNR time, then a DLL
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ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
V
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
-1 to 3.6
-1 to 3.6
-55 to +125
-40 to +85
-55 to +125
V
°C
°C
°C
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter
Symbol
CI1
Max
TBD
TBD
TBD
TBD
Unit
pF
Input Capacitance: CK/CK#
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
CA
pF
CI2
pF
CIO
pF
BGA THERMAL RESISTANCE
Description
Symbol
Theta JA
Theta JB
Theta JC
Max
TBD
TBD
TBD
Units
°C/W
°C/W
°C/W
Notes
Junction to Ambient (No Airflow)
Junction to Ball
1
1
1
Junction to Case (Top)
Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.whiteedc.com in the application notes section for modeling conditions.
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
VIH
Min
VREF +0.310
—
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
—
V
V
VIL
VREF -0.310
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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
VCC
VCCQ
II
Min
2.3
2.3
-2
Max
2.7
2.7
2
Units
V
Supply Voltage (36, 41)
I/O Supply Voltage (36, 41, 44)
V
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ
Output Levels: Full drive option (37, 39)
μA
μA
μA
II
-8
8
IOZ
-5
5
IOH
-12
-
mA
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT
)
IOL
VREF
VTT
12
-
mA
V
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT
)
I/O Reference Voltage (6,44)
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
I/O Termination Voltage (7, 44)
V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46)
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
MAX
333Mbs 250Mbs 200Mbs Units
266Mbs
Parameter/Condition
Symbol
260
320
10
260
320
10
230
290
10
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 47)
ICC0
mA
mA
mA
mA
mA
mA
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT
0mA; Address and control inputs changing once per clock cycle (22, 47)
=
ICC1
ICC2P
ICC2F
ICC3P
ICC3N
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE
= LOW; (23, 32, 49)
90
90
90
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50)
70
70
60
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE =
LOW (23, 32, 49)
100
100
90
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK
tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing
once per clock cycle (22)
=
330
390
330
320
290
270
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
ICC4R
ICC4W
mA
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
580
20
580
20
560
20
AUTO REFRESH CURRENT
tREFC = tRC (MIN) (49)
tREFC = 7.8125μs (27, 49)
Standard (11)
ICC5
ICC5A
ICC6
mA
mA
mA
mA
10
10
10
SELF REFRESH CURRENT: CKE 0.2V
810
800
700
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ or WRITE commands. (22, 48)
ICC7
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1-5, 14-17, 33, 54)
333 Mbs CL 3 (53) 266 Mbs CL 2.5
266 Mbs CL2.5 200 Mbs CL2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Min
Max
Min
Max
Min
Max
Min
Max
Units
Parameter
Symbol
tAC
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
-0.70
0.45
0.45
6
+0.70
0.55
0.55
13
-0.75
0.45
0.45
+0.75
0.55
-0.8
0.45
0.45
+0.8
0.55
0.55
-0.8
0.45
0.45
+0.8
0.55
0.55
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
μs
μs
μs
μs
ns
ns
tCK
tCH
tCL
0.55
CL = 3 (53)
tCK (3)
tCK (2.5)
tCK (2)
tDH
Clock cycle time
CL = 2.5 (45, 52)
CL = 2 (45, 52)
7.5
13
7.5
10
13
13
8
13
13
10
13
13
15
10
13
10
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
0.45
0.45
1.75
-0.6
0.35
0.35
0.5
0.6
0.6
2
0.6
0.6
2
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
+0.6
+0.75
-0.8
0.35
0.35
+0.8
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
0.45
1.25
0.5
0.6
0.6
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tDSH
tHP
0.2
0.2
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
tHZ
+0.70
+0.75
+0.8
+0.8
tLZ
-0.70
0.75
0.75
0.8
0.8
12
-0.75
0.90
0.90
1
-0.8
1.1
-0.8
1.1
tIH
F
tIS
1.1
1.1
F
tIH
1.1
1.1
S
tIS
1
1.1
1.1
S
tMRD
tQH
tQHS
tRAS
15
16
16
tHP-tQHS
0.55
42
tHP-tQHS
tHP-tQHS
tHP-tQHS
0.75
1
1
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
70,000
40
20
65
75
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
tRAP
15
tRC
60
tRFC
72
tRCD
tRP
15
PRECHARGE command period
15
DQS read preamble (42)
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
0.9
0.4
12
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
0.25
0
DQS write preamble setup time (20, 21)
DQS write postamble (19)
0.4
15
0.6
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
tWTR
NA
1
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
REFRESH to REFRESH command interval (23) (C, I Temp only)
Average periodic refresh interval (23) (C, I Temp only)
REFRESH to REFRESH command interval (23) (M Temp)
Average periodic refresh interval (23) (M Temp)
Terminating voltage delay to VDD
tREFC
tREFI
tREFC
tREFI
tVTD
70.3
7.8
17
70.3
7.8
17
70.3
7.8
17
70.3
7.8
17
1.8
1.8
1.8
1.8
0
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
75
80
80
200
200
200
200
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NOTES:
16. Inputs are not recognized as valid until VREF stabilizes once initialized, including
SELF REFRESH mode, VREF must be powered within specified range. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
1. All voltages referenced to VSS
.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
indicated in Note 3, is VTT
tHZ and tLZ transitions occur in the same access time windows as valid data
.
18.
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIHDC (MIN) then it must not transition low (below
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL (AC) and VIH (AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
VIHDC) prior to tDQSH (MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
6.
V
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in
progress, DQS could be HIGH during this time, depending on tDQSS.
the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for
DC error and an additional ±25mV for AC noise. This measurement is to be taken
at the nearest VREF by-pass capacitor.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute value
for tRAS
.
7.
8.
V
TT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF
ID is the magnitude of the difference between the input level on CK and the input
level on CK#.
23. The refresh period 64ms. This equates to an average refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be asserted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
.
V
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device
and must track variations in the DC level of the same.
25. The valid data window is derived by achieving other specifications - tHP (tCK/2),
10.
I
CC is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. CC specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8-
DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
I
13. This parameter is not tested but guaranteed by design. tA = 25°C, f = 1 MHz
14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate
is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per each
100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it
remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF
.
FIGURE A – PULL-DOWN CHARACTERISTICS
FIGURE B – PULL-UP CHARACTERISTICS
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28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure C.
level, VIL (AC) or VIH (AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
level, VIL (DC) or VIH (DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK input slew rate must be ≥ 1V/ns (≥ 2V/ns differentially).
31. DQ and DM# input slew rates must not deviate from DQS by more than 10%. If the
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure D.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
32.
V
CC must not vary more than 4% if CKE is not active while any bank is active.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 V, and at the same voltage and temperature.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
34.
t
HP min is the lesser of tCL minimum and tCH minimum actually applied to the device
CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
RAS (MIN) can be satisfied prior to the internal precharge command being issued.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from a minimum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
t
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive. The average cannot be below the 2.5V minimum.
40.
VIH overshoot: VIH (MAX) = VCCQ+1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate.
37. Normal Output Drive Curves:
41.
42.
V
t
CC and VCCQ must track each other.
HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
tRPST end point and tRPRE bigin point are not referenced to a specific voltage level
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.
43.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0
volts, provided a minimum of 42 ohms of series resistance is used between the VTT
supply and the input pin.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.
45. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. Random addressing changing 50% of data changing at every transfer.
48. Random addressing changing 100% of data changing at every transfer.
49. CKE must be active (high) during the entire time a refresh command is executed.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
FIGURE C – PULL-DOWN CHARACTERISTICS
FIGURE D – PULL-UP CHARACTERISTICS
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That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.
53. For 333Mbs operation of commercial and Industrial temperature CL = 2.5, at
Military temperature CL = 3.
50.
I
I
CC2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
CC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs to
remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles before any READ command.
54. Self refresh is available in commercial and industrial temperatures only.
PACKAGE DIMENSION: 60 PLASTIC BALL GRID ARRAY (PBGA)
6.40
0.80 (TYP)
.45
Ø
60X
SOLDER BALL DIAMETER REFERS TO
POST REFLOW CONDITION. THE
BALL A1
BALL A1 ID
1.80
CTR
PRE-REFLOW DIAMETER IS Ø 0.40mm.
1.00
TYP
BALL A9
BALL #1 ID
6.25 0.05
C
11.00
L
12.50 0.10
OPTIONAL
SOLDER BALLS
5.50 0.05
C
L
3.20 0.05
5.00 0.05
1.50 MAX
10.00 0.10
ALL LINEAR DIMENSIONS ARE MILLIMETERS
May 2008
Rev. 0
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3E64M16S-XNBX
White Electronic Designs
ORDERING INFORMATION
W 3E 64M 16 S - XXX NB X
WHITE ELECTRONIC DESIGNS CORP.
DDR SDRAM
CONFIGURATION, 64M x 16
2.5V Power Supply
DATA RATE (Mbs)
200 = 200Mbs
250 = 250Mbs
266 = 266Mbs
333 = 333Mbs
PACKAGE:
NB = 60 Thin Plastic Ball Grid Array (PBGA),10 mm x 12.5 mm x
1.5mm
DEVICE GRADE:
M = Military
= Industrial
-55°C to +125°C
-40°C to +85°C
I
C = Commercial 0°C to +70°C
May 2008
Rev. 0
16
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3E64M16S-XNBX
White Electronic Designs
Document Title
64M x 16 DDR SDRAM Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
May 2008
Preliminary
May 2008
Rev. 0
17
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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