W3EG72128S202BD4-M [MICROSEMI]
DDR DRAM Module, 128MX72, 0.75ns, CMOS, SO-DIMM-200;
| 型号： | W3EG72128S202BD4-M |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX72, 0.75ns, CMOS, SO-DIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总14页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY*
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
DESCRIPTION
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Double-data-rate architecture
The W3EG72128S is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. This module consists of eighteen 64Mx8 bit
DDR SDRAMs in 66 pin TSOP packages mounted on a
200 pin FR4 substrate.
DDR200, DDR266 and DDR333
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Serial presence detect
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Dual Rank
Power supply: 2.5V 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5 mm (1.38") and
BD4: 31.75 mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2.5-3-3
2-2-2
2.5-3-3
2-2-2
August 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0-A12
Address input (Multiplexed)
Bank Select Address
Data Input/Output
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
BA0-BA1
1
VREF
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A9
A8
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
VCC
DQ0-DQ63
DQS0-DQS8 Data Strobe Input/Output
CK0
CK0#
CKE0, CKE1 Clock Enable input
CS0#, CS1#
RAS#
CAS#
WE#
DQM0-DQM8 Data-In Mask
VCC
VSS
VREF
VCCSPD
2
3
DQ19
DQ23
DQ24
DQ28
VCC
VSS
Clock Input
Clock Input
4
VSS
VSS
5
DQ0
DQ4
DQ1
DQ5
VCC
A7
6
A6
VCC
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
7
A5
VCC
8
VCC
A4
NC
9
DQ25
DQ29
DQS3
DQM3
VSS
A3
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
A2
NC
DQS0
DQM0
DQ2
DQ6
VSS
A1
VSS
Power Supply (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
A0
VSS
VCC
DQ48
DQ52
DQ49
DQ53
VCC
VSS
VCC
DQ26
DQ30
DQ27
DQ31
VCC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
VSS
SDA
SCL
SA0-SA2
VCCID
NC
DQ3
DQ7
DQ8
DQ12
VCC
VCC
DQS6
DQM6
DQ50
DQ54
VSS
VCC
CB0
CB4
CB1
CB5
VSS
VCC
DQ9
DQ13
DQS1
DQM1
VSS
NC
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VCC
VSS
VSS
DQS8
DQM8
NC
DQ32
DQ36
DQ33
DQ37
VCC
VSS
DQ10
DQ14
DQ11
DQ15
VCC
CB6
VCC
VCC
VCC
DQ57
DQ61
DQS7
DQM7
VSS
VCC
CB3
CB7
NC
DQS4
DQM4
DQ34
DQ38
VSS
VCC
CK0
VCC
NC
VSS
CK0#
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VSS
VSS
VSS
VSS
NC
DQ35
DQ39
DQ40
DQ44
VCC
VSS
DQ16
DQ20
DQ17
DQ21
VCC
NC
VCC
VCC
SDA
SA0
SCL
SA1
VCCSPD
SA2
VCCID
NC
VCC
VCC
VCC
CKE1
CKE0
NC
DQ41
DQ45
DQS5
DQM5
VSS
VCC
DQS2
DQM2
DQ18
DQ22
NC
A12
A11
VSS
August 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQM0
DQS4
DQM4
CS#
CS#
DM
CS#
DQS
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DQM1
DQS5
DQM5
CS#
CS#
DM
CS#
CS#
CS#
DQS
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQM2
DQS6
DQM6
CS#
CS#
DM
CS#
DQS
DM
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQM7
DQS3
DQM3
CS#
CS#
DM
DQS
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQM8
CS#
DM
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VCC
120Ω
CLK0/CLK0#
CLK1/CLK1#
CLK2/CLK2#
CLK3/CLK3#
CK0
CK0A
PLL
CK0#
CK0A#
RAASS##
CAASS##
RAS: DDR SDRAMs
CAS: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE: DDR SDRAMs
FEEDBACK
BA00--BBAA11
WEE##
SERIAL PD
A00--AA1122
CKKEE00
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
SCL
SDA
A0
A1
A2
SA0 SA1 SA2
CKKEE11
VCC
GNNDD
DDDRR SSDDRRAAMM
DDDRR SSDDRRAAMM
Note: All datalines are terminated through a 22 ohms series resistor.
August 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
9
Units
V
V
°C
W
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V 0.2V
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Symbol
VCC
Min
2.3
2.3
Max
2.7
2.7
Unit
V
V
V
V
V
V
V
V
VCCQ
VREF
VTT
VCCQ/2 - 50mV
VREF - 0.04
VREF + 0.15
-0.3
VTT + 0.76
—
VCCQ/2 + 50mV
VREF + 0.04
VCCQ + 0.3
VREF - 0.15
—
VIH
VIL
VOH
VOL
VTT - 0.76
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF =1.4V 200mV
Parameter
Symbol
CIN1
Max
56
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
CIN2
56
CIN3
29
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
CIN4
5.5
29
CIN5
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
CIN6
13
CIN7
56
COUT
13
August 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2
Parameter
Symbol Conditions
One device bank; Active - Precharge;
Units
Max
Max
Max
Max
t
RC=tRC(MIN); tCK=tCK(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD0
2620
2620
2620
2620
mA
One device bank; Active-Read-
Precharge; Burst = 2; tRC=tRC(MIN)
Operating Current
IDD1 ;tCK=tCK(MIN); Iout = 0mA; Address
and control inputs changing once per
clock cycle.
2890
90
2890
90
2890
90
2890
90
mA
mA
mA
mA
Precharge Power-
Down Standby Current
All device banks idle; Power- down
IDD2P
mode; tCK=tCK(MIN); CKE=(low)
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address
IDD2F and other control inputs changing
once per clock cycle. Vin = Vref for
DQ, DQS and DM.
Idle Standby Current
1085
630
1085
630
1085
630
1085
630
Active Power-Down
Standby Current
One device bank active; Power-down
IDD3P
mode; tCK(MIN); CKE=(low)
CS# = High; CKE = High; One
device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ,
Active Standby Current IDD3N DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
1175
1175
1175
1175
mA
clock cycle.
Burst = 2; Reads; Continous burst;
One device bank active;Address
Operating Current
Operating Current
IDD4R and control inputs changing once
per clock cycle; tCK=tCK(MIN); Iout
= 0mA.
2935
3025
2935
2845
2935
2845
2935
2845
mA
mA
Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
IDD4W
clock cycle; tCK=tCK(MIN); DQ,DM
and DQS inputs changing twice per
clock cycle.
Auto Refresh Current
Self Refresh Current
IDD5 tRC=tRC(MIN)
4060
360
4060
365
4060
365
4060
365
mA
mA
IDD6 CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
Operating Current
IDD7A (MIN); tCK=tCK(MIN); Address and
control inputs change only during
5095
5050
5050
5050
mA
Active Read or Write commands.
August 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
August 2005
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
PARAMETER
SYMBOL
tAC
MIN
-0.70
0.45
0.45
6
MAX
+0.70
0.55
0.55
13
MIN
-0.75
0.45
0.45
7.5
MAX
+0.75
0.55
0.55
13
MIN
MAX
0.75
0.55
0.55
13
UNITS NOTES
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
-0.75
0.45
0.45
7.5
ns
tCH
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
26
tCL
26
Clock cycle time
CL = 2.5
CL = 2
tCK (2.5)
tCK (2)
tDH
39, 44
39, 44
23, 27
23, 27
27
7.5
13
7.5
13
7.5/10
0.5
13
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.45
0.45
1.75
-0.60
0.35
0.35
0.5
tDS
0.5
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
1.75
-0.75
0.35
0.35
1.75
-0.75
0.35
0.35
+0.60
+0.75
+0.75
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
0.4
0.5
0.5
22, 23
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25
0.75
0.2
1.25
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
0.2
tCH,tCL
tCH,tCL
tCH, tCL
+0.75
30
16, 36
16, 36
12
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
tHZ
+0.70
+0.75
tLZ
-0.70
0.75
0.75
0.8
-0.75
0.90
0.90
1
-0.75
0.90
0.90
1
tIHF
tISF
tIHS
12
12
August 2005
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
AC CHARACTERISTICS
335
262
265/202
PARAMETER
SYMBOL
tISS
MIN
0.8
2.2
12
MAX
MIN
1
MAX
MIN
MAX
UNITS NOTES
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
1
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
ns
ns
tCK
12
tIPW
2.2
15
tMRD
tQH
tQHS
tRAS
15
tHP - tQHS
tHP - tQHS
tHP - tQHS
22, 23
30, 47
0.50
0.75
0.75
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
42
15
60
72
15
15
0.9
0.4
12
0.25
0
70,000
40
15
60
75
15
15
0.9
0.4
15
0.25
0
120,000
40
20
65
78
20
20
0.9
0.4
15
0.25
0
120,000
tRAP
tRC
tRFC
42
tRCD
tRP
DQS read preamble
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
1.1
0.6
1.1
0.6
1.1
0.6
37
37
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
18, 19
17
DQS write postamble
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
NA
tQH - DQSQ
t
tQH - DQSQ
t
tQH - tDQSQ
22
21
21
REFRESH to REFRESH command interval
Average periodic refresh interval
tREFC
tREFI
tVTD
70.3
7.8
70.3
7.8
70.3
7.8
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
0
0
0
tXSNR
tXSRD
75
75
75
200
200
200
August 2005
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
Notes
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
.
16. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
17. The intent of the Don’t Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH
DC) prior to tDQSH (MIN).
V
TT
50Ω
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
RReeffeerreennccee
Output
Point
30pF
(VOUT
)
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS
.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maximum absolute value
for tRAS
.
21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
22. The valid data window is derived by achieving other specifications: tHP (tCK/2),
6.
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional
in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may
not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV
for DC error and an additional 25mV for AC noise. This measurement is to be
taken at the nearest VREF bypass capacitor.
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, beyon which functionality
is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty
cycles ranging between 50/50 and 45/55.
7.
8.
V
TT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF
DD is dependent on output loading and cycle rates. Specified values are obtained
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
.
I
with mini-mum cycle time at CL = 2 for 262, and 263, CL = 2.5 for 335 and 265 with
the outputs open.
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).Reach at least the target AC level.
9. Enables on-chip refresh and address counters.
10. DD specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
I
b. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
11. This parameter is sampled. VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V, VREF = VSS,
f = 100 MHz, TA = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input
is grouped with I/O pins, reflecting the fact that they are matched in loading.
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing
must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For 335, slew rates must be 0.5 V/ns.
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns
differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.
If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps
must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns.
28.
VCC must not vary more than 4 percent if CKE is not active while any bank is active.
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary
by the same amount. tHP min is the lesser of tCL minimum and tCH minimum actually
applied to the device CK and CK# inputs, collectively during bank active.
VREF
.
14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.
30. READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(MIN) can be satisfied prior to the internal precharge command being issued.
15. The output timing reference level, as measured at the timing reference point
31. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either -300mV or 2.2V, whichever is more positive.
indicated in Note 3, is VTT
.
August 2005
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
32. Normal Output Drive Curves:
37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
a. The full variation in driver pull-down current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 8, Pull-Down Characteristics.
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
38. During Initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are
0.0V, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
b. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, Pull-Down Characteristics.
c. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 9, Pull-Up Characteristics.
d. The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 9, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
39. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reflect this option.
40. Random addressing changing and 50 percent of data changing at every transfer.
41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
43.
I
I
DD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
DD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
f. The full variation in the ratio of the nominal pull-up to pull-down current should
be unity 10 percent, for device drain-to-source volt-ages from 0.1V to 1.0V.
33. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
44. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles.
45. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. The 335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
34.
VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) =
-1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the
cycle rate.
35.
36.
V
CC and VCCQ must track each other.
HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
t
August 2005
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
W3EG72128S335BD4-xG
W3EG72128S262BD4-xG
W3EG72128S265BD4-xG
W3EG72128S202BD4-xG
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2.5
2
31.75 (1.25")
31.75 (1.25")
31.75 (1.25")
31.75 (1.25")
2
2
2.5
2
3
3
2
2
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR BD4
6.35
(0.250) MAX.
67.56
(2.666) MAX
3.98 0.1
(0.157 0.004)
31.75
(1.25)
20
(0.787)
2.31
(0.091) REF.
3.99
4.19
(0.157) MIN.
(0.165)
47.40
(1.866)
1.80
(0.071)
11.40
(0.449)
0.99 0.10
(0.039 0.004)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
August 2005
Rev. 3
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR AD4
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
W3EG72128S335AD4-xG
W3EG72128S262AD4-xG
W3EG72128S265AD4-xG
W3EG72128S202AD4-xG
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2.5
2
35.05 (1.138")
35.05 (1.138")
35.05 (1.138")
35.05 (1.138")
2
2
2.5
2
3
3
2
2
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AD4
67.56
(2.666) MAX.
6.35
(0.250) MAX.
2.0
(0.079)
35.05
(1.138) MAX.
3.98 0.1
(0.157 0.004)
20
(0.787)
P1
2.31
(0.091) REF.
3.99
4.19
(0.157) MIN.
(0.165)
47.40
(1.866)
1.80
(0.071)
0.99 0.10
(0.039 0.004)
11.40
(0.449)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
August 2005
Rev. 3
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
PART NUMBERING GUIDE
W 3 E G 72 128 S xxx D4 x -x G
WEDC
MEMORY
DDR
GOLD
BUS WIDTH
DEPTH
2.5V
SPEED (MHz)
PACKAGE 200 PIN
I = INDUSTRIAL
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
August 2005
Rev. 3
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72128S-AD4
-BD4
White Electronic Designs
PRELIMINARY
Document Title
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Rev 2
Rev 3
Created
7-23-03
4-6-04
10-4-04
8-05
Advanced
Preliminary
Preliminary
Preliminary
Added AD4 and BD4 package height option
Added AC specs
3.1 Added part number matrix
August 2005
Rev. 3
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
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