W3EG7262S202JD3S [MICROSEMI]

DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184;


型号：	W3EG7262S202JD3S
厂家：	Microsemi
描述：	DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184 动态存储器双倍数据速率
文件：	总12页 (文件大小：218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY*

512MB – 2X32Mx72 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG7262S is a 2x32Mx72 Double Data Rate

SDRAM memory module based on 256Mb DDR SDRAM

components. The module consists of eighteen 32Mx8

DDR SDRAMs in 66 pin TSOP packages mounted on a

184 pin FR4 substrate.

ꢀ

DDR200 and DDR266

• JEDEC design speciﬁed

ꢀ

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Dual Rank

Power supply: 2.5V 0.2V

JEDEC184 pin DIMM package

• JD3 PCB height: 30.48mm (1.20")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

OPERATING FREQUENCIES

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2-2-2

2.5-3-3

2-2-2

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

PIN CONFIGURATION

A0-A12

Address input (Multiplexed)

Bank Select Address

Data Input/Output

Check bits

Data Strobe Input/Output

Clock Input

Clock Enable input

Chip Select Input

Row Address Strobe

Column Address Strobe

Write Enable

Data-in-mask

Power Supply

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

BA0-BA1

DQ0-DQ63

CB0-CB7

DQS0-DQS8

CK0, CK1, CK2

CK0#, CK1#, CK2#

CKE0, CKE1

CS0#, CS1#

RAS#

V_REF

DQ0

V_SS

DQS8

V_SS

DQ4

DQ5

V_CCQ

DQM0

DQ6

DQ7

V_SS

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

V_SS

DQM8

A10

CB2

DQ1

DQS0

DQ2

V_CC

DQ3

V_SS

CB6

CB3

BA1

V_CCQ

CB7

DQ32

V_CCQ

DQ33

DQS4

DQ34

V_SS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

DQ36

DQ37

V_CC

DQM4

DQ38

DQ39

V_SS

DQ44

RAS#

DQ45

V_CCQ

CS0#

CS1#

DQM5

V_SS

CAS#

WE#

V_SS

DQM0-DQM8

V_CC

DQ8

DQ9

DQS1

V_CCQ

CK1

CK1#

V_SS

DQ10

DQ11

CKE0

V_CCQ

DQ16

DQ17

DQS2

V_SS

DQ18

V_CCQ

DQ19

DQ24

V_SS

V_CCQ

DQ12

DQ13

DQM1

V_CC

BA0

V_CCQ

Power Supply for DQS

Ground

DQ35

DQ40

V_CCQ

WE#

DQ41

CAS#

V_SS

V_REF

Power Supply for Reference

Serial EEPROM Power Supply

Serial data I/O

V_CCSPD

DQ14

DQ15

CKE1

V_CCQ

DQ20

A12

V_SS

DQ21

A11

DQM2

V_CC

DQ22

SDA

SCL

Serial clock

SA0-SA2

V_CCID

Address in EEPROM

V_CCIndentiﬁcation Flag

No Connect

DQS5

DQ42

DQ43

V_CC

DQ46

DQ47

DQ48

DQ49

V_SS

V_CCQ

DQ52

DQ53

CK2#

CK2

V_CCQ

DQS6

DQ50

DQ51

V_SS

V_CCID

DQ56

DQ57

V_CC

DQS7

DQ58

DQ59

V_SS

SDA

SCL

V_CC

DQ23

V_SS

DQM6

DQ54

DQ55

V_CCQ

DQ60

DQ61

V_SS

DQ28

DQ29

V_CCQ

DQM3

DQ25

DQS3

V_CC

DQ26

DQ27

DQ30

V_SS

DQM7

DQ62

DQ63

V_CCQ

SA0

DQ31

CB4

CB5

V_CCQ

CK0

CK0#

V_SS

CB0

CB1

V_CC

SA1

SA2

V_CCSPD

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

CS1#

CS0#

DQS4

DQM4

DQS0

DQM0

DM CS# DQS

I/O 0

DM CS# DQS

I/O 7

DM CS# DQS

I/O 7

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS1

DQM1

DQS5

DQM5

DM CS# DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQM2

DQS6

DQM6

DM CS# DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DQM3

DQS7

DQM7

DM CS# DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS8

DQM8

DM CS# DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Serial PD

SCL

W P

Clock Input

SDRAMs

SDA

6 SDRAMs

CK0 / CKO#

CK1 / CK1#

CK2 / CK2#

SA0 SA1 SA2

BA0-BA1 : DDR SDRAMs

A0-A12 : DDR SDRAMs

RAS# : DDR SDRAMs

CAS# : DDR SDRAMs

CKE1 : DDR SDRAMs

CKE0 : DDR SDRAMs

BA0 - BA1

A0 - A12

RAS#

CCSPD

SPD

^CC/ V^CCQ

DDR SDRAMs

CAS#

REF

CKE1

VSS

DDR SDRAMs

CKE0

W E #

: DDR SDRAMs

WE#

Notes:

1. DQ to I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

NOTE: All resistor values are 22 ohms unless otherwise speciﬁed.

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Units

°C

Voltage on any pin relative to V_SS

Voltage on V_CCsupply relative to V_SS

Storage Temperature

V_IN, V_OUT

V_CC, V_CCQ

T_STG

-0.5 to 3.6

-1.0 to 3.6

-55 to +150

Power Dissipation

P_D

Short Circuit Current

I_OS

Note:

Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C ≤ T_A≤ 70°C, V_CC= 2.5V 0.2V

Parameter

Symbol

V_CC

Min

2.3

Max

2.7

Unit

Supply Voltage

V_CCQ

V_REF

V_TT

2.3

2.7

Reference Voltage

Termination Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

1.15

1.35

1.15

1.35

V_IH

V_REF+ 0.15

-0.3

V_CCQ+ 0.3

V_REF-0.15

—

V_IL

V_OH

V_TT+ 0.76

—

V_OL

V_TT-0.76

CAPACITANCE

T_A= 25°C. f = 1MHz, V_CC= 2.5V 0.2V

Parameter

Input Capacitance (A0-A12)

Input Capacitance (RAS#,CAS#,WE#)

Input Capacitance (CKE0)

Input Capacitance (CK0#,CK0)

Input Capacitance (CS0#)

Input Capacitance (DQM0-DQM8)

Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)

Data input/output capacitance (CB0-CB7)

Symbol

C_IN1

C_IN2

C_IN3

C_IN4

C_IN5

C_IN6

C_IN7

C_OUT

Max

Unit

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

I_DDSPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C ≤ T_A≤ 70°C, V_CCQ= 2.5V 0.2V, V_CC= 2.5V 0.2V

Includes DDR SDRAM component only

DDR266@CL=2.0

Max

DDR266@CL=2.5

Max

DDR200@CL=2

Max

Parameter

Symbol Conditions

I_DD0

Units

Operating Current

One device bank; Active - Precharge;

TBD

1845

2205

1845

t_RC=t_RC(MIN); t_CK=t_CK(MIN); DQ,DM

and DQS inputs changing once per

clock cycle; Address and control

inputs changing once every two

cycles.

Operating Current

I_DD1

One device bank; Active-Read-

Precharge Burst = 2; t_RC=t_RC(MIN);

t_CK=t_CK(MIN); l_OUT= 0mA; Address

and control inputs changing once per

clock cycle.

2205

Precharge Power-

Down Standby

Current

I_DD2P

All device banks idle; Power-down

mode; t_CK=t_CK(MIN); CKE=(low)

TBD

rnA

Idle Standby Current

I_DD2F

CS# = High; All device banks idle;

t_CK=t_CK(MIN); CKE = high; Address

and other control inputs changing

once per clock cycle. V_IN= V_REFfor

DQ, DQS and DM.

810

Active Power-Down

Standby Current

I_DD3P

I_DD3N

One device bank active; Power-Down

mode; t_CK(MIN); CKE=(low)

TBD

450

900

450

900

Active Standby

Current

CS# = High; CKE = High; One device

bank; Active-Precharge; t_RC=t_RAS

(MAX); t_CK=t_CK(MIN); DQ, DM and

DQS inputs changing twice per clock

cycle; Address and other control

inputs changing once per clock cycle.

Operating Current

I_DD4R

Burst = 2; Reads; Continuous burst;

One device bank active; Address

and control inputs changing once

per clock cycle; T_CK= T_CK(MIN); l_OUT

= 0mA.

TBD

2250

2115

2250

2115

rnA

I_DD4W

Burst = 2; Writes; Continuous burst;

One device bank active; Address

and control inputs changing once per

clock cycle; t_CK=t_CK(MIN); DQ,DM

and DQS inputs changing once per

clock cycle.

Auto Refresh

Current

I_DD5

t_RC= t_RC(MIN)

TBD

3015

Self Refresh Current

Operating Current

I_DD6

TBD

CKE ≤ 0.2V

I_DD7A

Four bank interleaving Reads (BL=4)

with auto precharge with t_RC=t_RC

(MIN); t_CK=t_CK(MIN); Address and

control inputs change only during

Active Read or Write commands.

4050

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

DETAILED TEST CONDITIONS FOR DDR SDRAM I_DD1& I_DD7A

I_DD1: OPERATING CURRENT : ONE BANK

I_DD7A: OPERATING CURRENT : FOUR BANKS

1. Typical Case : V_CC=2.5V, T=25°C

2. Worst Case : V_CC=2.7V, T=10°C

1. Typical Case : V_CC=2.5V, T=25°C

2. Worst Case : V_CC=2.7V, T=10°C

3. Only one bank is accessed with t_RC(min), Burst

Mode, Address and Control inputs on NOP edge

are changing once per clock cycle. I_OUT= 0mA

3. Four banks are being interleaved with t_RC(min),

Burst Mode, Address and Control inputs on NOP

edge are not changing. Iout=0mA

4. Timing Patterns :

•

DDR200 (100 MHz, CL=2) : t_CK=10ns, CL2,

BL=4, t_RCD=2*t_CK, t_RAS=5*t_CK

Read : A0 N R0 N N P0 N A0 N - repeat the

same timing with random address changing;

50% of data changing at every burst

•

DDR200 (100 MHz, CL=2) : t_CK=10ns, CL2,

BL=4, t_RRD=2*t_CK, t_RCD=3*t_CK, Read with

Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0

- repeat the same timing with random address

changing; 100% of data changing at every

burst

DDR266 (133MHz, CL=2.5) : t_CK=7.5ns,

CL=2.5, BL=4, t_RCD=3*t_CK, t_RC=9*t_CK, t_RAS=5*t_CK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

DDR266 (133MHz, CL=2.5) : t_CK=7.5ns,

CL=2.5, BL=4, t_RRD=3*t_CK, t_RCD=3*t_CK

Read with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t_CK=7.5ns, CL=2,

BL=4, t_RCD=3*t_CK, t_RC=9*t_CK, t_RAS=5*t_CK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

changing; 50% of data changing at every burst

DDR266 (133MHz, CL=2) : t_CK=7.5ns, CL2=2,

BL=4, t_RRD=2*t_CK, t_RCD=2*t_CK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3

R (0-3) = Read Bank 0-3

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C ≤ T_A≤ +70°C; V_CC= +2.5V 0.2V, V_CCQ= +2.5V 0.2V

AC Characteristics

262

265, 202

Parameter

Symbol

t_AC

Min

-0.75

0.45

7.5

Max

+0.75

0.55

Min

Max

+0.75

0.55

Units

Notes

Access window of DQs from CK, CK#

CK high-level width

CK low-level width

-0.75

0.45

7.5

t_CH

t_CK

t_CL

Clock cycle time

CL=2.5

CL=2

_CK(2.5)

t_CK(2)

t_DH

7.5

DQ and DM input hold time relative to DQS

DQ and DM input setup time relative to DQS

DQ and DM input pulse width (for each input)

Access window of DQS from CK, CK#

DQS input high pulse width

0.5

14,17

t_DS

0.5

t_DIPW

t_DQSCK

t_DQSH

t_DQSL

t_DQSQ

1.75

-0.75

0.35

1.75

-0.75

0.35

+0.75

t_CK

DQS input low pulse width

DQS-DQ skew, DQS to last DQ valid, per group,

per access

0.5

13,14

Write command to ﬁrst DQS latching transition

DQS falling edge to CK rising - setup time

t_DQSS

t_DSS

t_DSH

t_HP

0.75

0.2

1.25

0.75

0.2

1.25

t_CK

DQS falling edge from CK rising - hold time

Half clock period

0.2

t_CH, t_CL

8,19

8,20

Data-out high-impedance window from CK, CK#

Data-out low-impedance window from CK, CK#

Address and control input hold time (fast slew rate)

Address and control input set-up time (fast slew rate)

Address and control input hold time (slow slew rate)

Address and control input setup time (slow slew rate)

Address and control input pulse width (for each input)

LOAD MODE REGISTER command cycle time

t_HZ

+0.75

t_LZ

-0.75

0.90

-0.75

0.90

t_IHf

t_ISf

t_IHs

t_ISs

t_IPW

t_MRD

t_QH

2.2

DQ-DQS hold, DQS to ﬁrst DQ to go non-valid, per access

Data hold skew factor

t_HP-t_QHS

13,14

t_QHS

t_RAS

t_RAP

t_RC

0.75

ACTIVE to PRECHARGE command

120,000

ACTIVE to READ with Auto precharge command

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

t_RFC

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

0°C ≤ T_A≤ +70°C; V_CC= +2.5V 0.2V, V_CCQ= +2.5V 0.2V

AC Characteristics

262

265, 202

Parameter

Symbol

t_RCD

Min

Max

Min

Max

Units

Notes

ACTIVE to READ or WRITE delay

PRECHARGE command period

DQS read preamble

t_RP

t_RPRE

t_RPST

t_RRD

0.9

0.4

1.1

0.6

0.9

0.4

1.1

0.6

t_CK

DQS read postamble

ACTIVE bank a to ACTIVE bank b command

DQS write preamble

t_WPRE

t_WPRES

t_WPST

t_WR

0.25

t_CK

DQS write preamble setup time

DQS write postamble

10,11

0.4

0.6

0.4

0.6

t_CK

Write recovery time

Internal WRITE to READ command delay

Data valid output window

t_WTR

t_CK

t_QH-t_DQSQ

REFRESH to REFRESH command interval

Average periodic refresh interval

Terminating voltage delay to V_CC

Exit SELF REFRESH to non-READ command

Exit SELF REFRESH to READ command

t_REFC

t_REFI

70.3

7.8

70.3

7.8

μs

t_VTD

t_XSNR

t_XSRD

200

t_CK

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

Notes

12. The refresh period is 64ms. This equates to an average refresh

rate of 15.625µs. However, an AUTO REFRESH command must

be asserted at least once every 140.6µs; burst refreshing or

posting by the DRAM controller greater than eight refresh cycles is

not allowed.

All voltages referenced to V_SS

Tests for AC timing, I_DD, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but

the related speciﬁcations and device operations are guaranteed for

the full voltage range speciﬁed.

13. The valid data window is derived by achieving other speciﬁcations

- t_HP(t_CK/2), t_DQSQ, and t_QH(t_QH= t_HP- t_QHS). The data valid

window derates directly proportional with the clock duty cycle

and a practical data valid window can be derived. The clock is

allowed a maximum duty cycled variation of 45/55. Functionality

is uncertain when operating beyond a 45/55 ratio. The data valid

window derating curves are provided below for duty cycles ranging

between 50/50 and 45/55.

Outputs are measured with equivalent load:

VTT

50Ω

RReeffeerreennccee

Outputt

Point

(VOUT

)

30ppFF

14. Referenced to each output group: x8 = DQS with DQ0-DQ7.

15. READs and WRITEs with auto precharge are not allowed to be

issued until t_RAS(MIN) can be satisﬁed prior to the internal precharge

command being issued.

AC timing and I_DDtests may use a V_IL-to-V_IHswing of up to 1.5V

in the test environment, but input timing is still referenced to V_REF

(or to the crossing point for CK/CK#), and parameter speciﬁcations

are guaranteed for the speciﬁed AC input levels under normal use

conditions. The minimum slew rate for the input signals used to

test the device is 1V/ns in the range between V_IL(AC) and V_IH(AC).

16. JEDEC speciﬁes CK and CK# input slew rate must be > 1V/ns

(2V/ns differentially).

17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,

timing must be derated: 50ps must be added to t_DSand t_DHfor

each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,

functionality is uncertain.

The AC and DC input level speciﬁcations are deﬁned in the SSTL_

2 standard (i.e., the receiver will effectively switch as a result of the

signal crossing the AC input level, and will remain in that state as

long as the signal does not ring back above [below] the DC input

LOW [high] level).

18.

_HPmin is the lesser of t_CLmin and t_CHmin actually applied to the

device CK and CK# inputs, collectively during bank active.

Command/Address input slew rate = 0.5V/ns. For 262 with slew

rates 1V/ns and faster, t_ISand t_IHare reduced to 900ps. If the

slew rate is less than 0.5V/ns, timing must be derated: t_IShas an

additional 50ps per each 100mV/ns reduction in slew rate from the

500mV/ns. t_IHhas 0ps added, that is, it remains constant. If the

slew rate exceeds 4.5V/ns, functionality is uncertain.

19. This maximum value is derived from the referenced test load. In

practice, the values obtained in a typical terminated design may

reﬂect up to 310ps less for t_HZ(MAX) and last DVW. t_HZ(MAX) will

prevail over the t_DQSCK(MAX) + t_RPST(MAX) condition. t_LZ(MIN)

will prevail over t_DQSCK(MIN) + PRE (MAX) condition.

Inputs are not recognized as valid until V_REFstabilizes. Exception:

during the period before V_REFstabilizes, CKE ≤ 0.3 x V_CCQis

recognized as LOW.

20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.

21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH

command is registered, CKE must be active at each rising clock

edge, until t_REFlater.

t_HZand t_LZtransitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a

speciﬁc voltage level, but specify when the device output is no

longer driving (HZ) and begins driving (LZ).

22. Whenever the operating frequency is altered, not including jitter,

the DLL is required to be reset. This is followed by 200 clock cycles

(before READ commands).

The maximum limit for this parameter is not a device limit. The

device will operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus

turnaround.

11. It is recommended that DQS be valid (HIGH or LOW) on or before

the WRITE command. The case shown (DQS going from High-Z to

logic LOW) applies when no WRITEs were previously in progress

on the bus. If a previous WRITE was in progress, DQS could be

high during this time, depending on t_DQSS

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

ORDERING INFORMATION FOR JD3

Part Number

Speed

CAS Latency

t_RCD

t_RP

Height*

W3EG7262S262JD3

W3EG7262S265JD3

W3EG7262S202JD3

133MHz/266Mb/s

100MHz/200Mb/s

2.5

30.48 (1.20")

NOTES:

• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)

• Vendor speciﬁc part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to

be replaced with the respective vendors code. Consult factory for qualiﬁed sourcing options. (M = Micron, S = Samsung & consult factory for others)

• Consult factory for availability of industrial temperature (-40°C to 85°C) option

PACKAGE DIMENSIONS FOR JD3

133.48

(5.255" MAX.)

131.34

(5.171")

3.81

(0.150) MAX

128.95

(5.077")

3.99

(0.157 (2x))

30.48

(1.20)

MAX

3.99

(0.157)

(MIN)

17.78

(0.700)

2.31

(0.091)

(2x)

3.00

(0.118)

(4x)

1.27

10.01

(0.050 TYP.)

(0.394)

6.35

(0.250)

49.53

(1.950)

64.77

1.27 0.10

(2.550)

(0.050 0.004)

6.35

1.78

(0.070)

(0.250)

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

ORDERING INFORMATION FOR D3

Part Number

Speed

CAS Latency

t_RCD

t_RP

Height*

W3EG7262S262D3

W3EG7262S265D3

W3EG7262S202D3

133MHz/266Mb/s

100MHz/200Mb/s

2.5

30.48 (1.20")

NOTES:

• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)

• Vendor speciﬁc part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to

be replaced with the respective vendors code. Consult factory for qualiﬁed sourcing options. (M = Micron, S = Samsung & consult factory for others)

• Consult factory for availability of industrial temperature (-40°C to 85°C) option

PACKAGE DIMENSIONS FOR D3

133.48

(5.255" MAX.)

131.34

(5.171")

3.81

(0.150) MAX

128.95

(5.077")

3.99

(0.157 (2x))

30.48

(1.20)

MAX

3.99

(0.157)

(MIN)

17.78

(0.700)

2.31

(0.091)

(2x)

3.00

(0.118)

(4x)

1.27

10.01

(0.050 TYP.)

(0.394)

6.35

(0.250)

49.53

(1.950)

64.77

1.27 0.10

(2.550)

(0.050 0.004)

6.35

1.78

(0.070)

(0.250)

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S-D3

-JD3

White Electronic Designs

PRELIMINARY

Document Title

512MB - 64Mx72 DDR SDRAM UNBUFFERED

Revision History

Rev #

History

Release Date Status

Rev 0

Created Datasheet

5-22-02

Advanced

Rev 1

1.1 Added document title page

4-27-04

Preliminary

1.2 Removed "ED" for Part Marking

Rev 2

Rev 3

2.1 Corrected pin conﬁguration

2.2 Updated block diagram

1-05

5-05

Preliminary

2.3 Added lead-free and RoHS notes

2.4 Added source control notes

2.5 Added industrial temp notes

3.1 Added JEDEC standard PCB

3.2 D3 PCB option is "NOT RECOMMENDED FOR NEW

DESIGNS

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG7262S202JD3S [MICROSEMI]

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