W3HG264M64EEU534D6GG [MICROSEMI]
DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | W3HG264M64EEU534D6GG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总11页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED*
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED DIMM
DESCRIPTION
FEATURES
The W3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
240-pin, dual in-line memory module. Raw card "E"
Fast data transfer rates: PC2-6400*, PC2-5300,
PC2-4200 and PC2-3200
Utilizes 800*, 667, 533 and 400 MT/s DDR2
SDRAM components
V
V
CC = VCCQ = 1.8V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
CCSPD = +1.7V to +3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
July 2007
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No.
1
Symbol
VREF
VSS
Pin No.
Symbol
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
Pin Name
A0-A13
Function
61
A4
VSS
Address Inputs
Bank Address Inputs
Data Input/Output
Data Strobe
2
62
VCCQ
A2
DQ4
DQ5
VSS
BA0 - BA1
DQ0 - DQ63
DQS0 - DQS7
3
DQ0
DQ1
VSS
63
A1
4
64
VCC
VCC
5
65
VSS
DM0
NC
CK0
CK0#
VCC
6
DQS0#
DQS0
VSS
66
VSS
DQS0# - DQS7#
DM(0-7)
Data Strobe Negative
Data Masks
7
67
VCC
VSS
8
68
NC
DQ6
DQ7
VSS
A0
9
DQ2
DQ3
VSS
69
VCC
VCC
ODT0, ODT1
On Die Termination
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
A10
BA1
VCCQ
RAS#
CS0#
VCCQ
ODT0
A13
CK0,CK0# - CK2, Clock Inputs
CK2#
71
BA0
DQ12
DQ13
VSS
DQ8
DQ9
VSS
72
VCCQ
WE#
CAS#
VCCQ
CS1#
ODT1
VCCQ
VSS
73
CKE0, CKE1
CS0#, CS1#
RAS#
Clock enable inputs
74
DM1
NC
Chip Select Inputs
Row Address Strobe
Column Address Strobe
Write Enable
DQS1#
DQS1
VSS
75
76
VSS
77
CK1
CK1#
VSS
VCC
CAS#
NC
78
VSS
WE#
NC
79
DQ36
DQ37
VSS
VSS
80
DQ32
DQ33
VSS
DQ14
DQ15
VSS
V
CC, VCCQ
Voltage Supply
Ground
DQ10
DQ11
VSS
81
VSS
82
DM4
NC
SA0 ~ SA2
SDA
SPD Address
83
DQS4#
DQS4
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
84
VSS
Serial Data I/O
Serial clock
85
DQ38
DQ39
VSS
SCL
86
DQ34
DQ35
VSS
DM2
NC
VREF
I/O reference supply
Serial EEPROM
No Connect
DQS2#
DQS2
VSS
87
88
VSS
DQ44
DQ45
VSS
VCCSPD
NC
89
DQ40
DQ41
VSS
DQ22
DQ23
VSS
DQ18
DQ19
VSS
90
91
DM5
NC
92
DQS5#
DQS5
VSS
DQ28
DQ29
VSS
DQ24
DQ25
VSS
93
VSS
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
DM3
NC
DQS3#
DQS3
VSS
96
97
VSS
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ30
DQ31
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2#
VSS
SA2
NC
NC
NC
NC
NC
VSS
VSS
DM6
NC
VSS
DQS6#
DQS6
VSS
NC
NC
NC
VSS
NC
VSS
DQ54
DQ55
VSS
VSS
DQ50
DQ51
VSS
NC
NC
NC
NC
VSS
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VCCQ
CKE1
VCC
VCCQ
CKE0
VCC
DM7
NC
DQS7#
DQS7
VSS
NC
NC
NC
VSS
NC
VCCQ
A12
A9
DQ62
DQ63
VSS
VCCQ
A11
DQ58
DQ59
VSS
A7
VCC
VCCSPD
SA0
SA1
VCC
SDA
SCL
A8
A5
A6
July 2007
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ8
DQ9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
DM/
CS#
DQS DQS#
RDQS
RDQS
RDQS
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serial PD
SCL
WP
V
CCSPD
Serial PD
SDA
A0
A1
A2
V
CC/VCCQ
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SA0
SA1
SA2
V
REF
V
SS
*Clock Wiring
Clock
Input
DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
(See Notes)
BA0 - RBA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
BA0 - BA1
A0 - A13
RAS#
*Wire per Clock Loading
Table/Wiring Diagrams
CAS#
WE#
CKE0
CKE1
Notes:
ODT0
1. DQ, DM, DQS, DQS# resistors: 22 Ohms +/- 5%
2. BAx, Ax, RAS#, CAS#, WE# resistors: 10 Ohms +/- 5%
ODT1
July 2007
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
1.8
Max
1.9
Unit
V
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
3.6
V
VTT
V
VCCSPD
-
V
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
3. CCQ of all IC's are tied to VCC
V
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
- 0.5
- 0.5
-55
0
Max
2.3
2.3
100
85
Unit
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
°C
°C
uA
TCASE
IL
Device Operating Temperature
Input leakage current; Any input 0V<VIN<VCC
VREF input 0V<VIN<<0.95; Other pins not
under test = 0V
;
Command/Address, RAS#,
CAS#, WE#
-80
80
CS#, CKE
CK, CK#
-40
-30
-10
-10
40
30
10
10
uA
uA
uA
uA
DM
IOZ
Output leakage current; 0V<VOUT<VCCQ; DQs
and ODT are disable
DQ, DQS, DQS#
IVREF
VREF leakage current; VREF = Valid VREF level
-32
32
uA
July 2007
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature
TOPER
0ºC to 85ºC
ºC
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VREF + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667 & DDR2-800
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667 & DDR2-800
VREF+ 0.250
-
V
V
V
V
VREF+ 0.200
-
-
-
VREF - 0.250
VREF - 0.200
July 2007
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol Proposed Conditions
Operating one bank active-precharge current;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
806
665
534
403
Units
ICC0*
t
696
624
576
544
mA
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
ICC1*
816
736
656
616
mA
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
112
720
816
112
640
720
112
560
608
112
512
544
mA
mA
mA
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
624
144
528
144
448
144
384
144
mA
mA
All banks open; tCK = tCK(ICC); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
ICC3P**
ICC3N**
ICC4W*
ICC4R*
ICC5B*
ICC6**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
960
1,296
1,296
1,216
112
800
1,096
1,096
1,176
112
688
936
624
816
mA
mA
mA
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
=
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK
= tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
936
816
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
1,096
112
1,056
112
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
Normal
FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
=
ICC7*
1,336
1,272
1,216
1,184
mA
* Value calculated as one module rank in thes operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition
NOTES:
• ICC specifications were calculated using QIMONDA components. Other manufactures DRAMs may have different values.
July 2007
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
806
665
534
403
SYMBOL
UNIT
PARAMETER
MIN
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
MIN
MAX
MIN
MAX
MIN
MAX
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
ps
ps
ps
ps
3,000
3,750
5,000
8,000
8,000
8,000
3,750
3,750
5,000
8,000
8,000
8,000
5,000
5,000
5,000
8,000
8,000
8,000
Clock cycle time
CK high-level width
tCH
0.48
0.48
0.52
0.52
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
TBD
TBD
CK low-level width
Half clock period
tCL
tHP
tAC
tCK
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
MIN (tCH, tCL
)
MIN (tCH, tCL
)
MIN (tCH, tCL
)
DQ output access time from CK/CK#
-450
+450
-500
+500
-600
+600
Data-out high-impedance window from CK/
CK#
tHZ
tLZ
tAC MAX
tAC MAX
tAC MAX
ps
ps
TBD
TBD
TBD
TBD
Data-out low-impedance window from CK/
CK#
2x
tAC MIN
2x
AC MIN
2x
AC MIN
tAC MAX
tAC MAX
tAC MAX
t
t
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
tDS
tDH
tDIPW
tQHS
100
175
0.35
100
150
ps
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
225
275
0.35
0.35
340
400
450
DQ - DQS hold, DQS to first DQ to go
nonvalid, per access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
TBD
TBD
DQS input high pulse width
tDQSH
tDQSL
tDQSCK
tDSS
0.35
0.35
-400
0.2
0.35
0.35
-450
0.2
0.35
0.35
-500
0.2
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
+400
240
+450
300
+500
350
tCK
tCK
tDSH
0.2
0.2
0.2
DQS - DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
ps
TBD
TBD
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
tRPRE
tRPST
tWPRE
tWPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.35
0.4
0.25
0.4
0.25
0.4
0.6
0.6
0.6
WL +
0.25
WL +
0.25
WL +
0.25
Write command to first DQS latching transition
tDQSS
tIPW
WL - 0.25
0.6
WL - 0.25
0.6
WL - 0.25
0.6
tCK
tCK
TBD
TBD
TBD
TBD
Address and control input pulse width for
each input
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different.
Continued on next page
July 2007
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
806
665
534
403
SYMBOL
UNIT
PARAMETER
MIN
TBD
TBD
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
TBD
TBD
MIN
60
MAX
MIN
60
MAX
MIN
55
MAX
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRC
tRRD
tRCD
tRAS
tRTP
tWR
ns
ns
ns
ns
ns
ns
7.5
15
7.5
15
7.5
15
45
70,000
45
70,000
40
70,000
7.5
15
7.5
15
7.5
15
Auto precharge write recovery + precharge
time
tDAL
tWR + tRP
tWR + tRP
tWR + tRP
ns
TBD
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
tRP
tRPA
tMRD
tDELAY
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
tRP+tCK
tRP+tCK
tRP+tCK
2
2
2
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
CKE low to CK,CK# uncertainty
ns
ns
TBD
TBD
TBD
TBD
REFRESH to Active of Refresh to Refresh
command internal
tRFC
REFI
105
105
105
Average periodic refresh interval
t
7.8
2
7.8
2
7.8
2
μs
TBD
TBD
TBD
TBD
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
Exit self refresh to non-READ command
tXSNR
ns
Exit self refresh to READ command
ODT turn-on delay
tXSRD
tAOND
200
2
200
2
200
2
tCK
tCK
TBD
TBD
TBD
TBD
tAC (MAX)
+ 700
tAC (MAX)
+ 1000
tAC (MAX)
+ 700
ODT turn-on
tAON
tAC (MIN)
tAC (MIN)
tAC (MIN)
ps
TBD
TBD
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
TBD
TBD
TBD
TBD
tAC (MAX)
+ 600
tAC (MAX)
+ 600
tAC (MAX)
+ 600
tAC (MIN)
tAC (MIN)
tAC (MIN)
2 x tCK
+
2 x tCK
+
2 x tCK +
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
ps
ps
TBD
TBD
TBD
TBD
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7 - AL
6 - AL
6 - AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different.
July 2007
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D6
Part Number
Speed/Data Rate CAS Latency
tRCD
6
tRP
6
Height*
W3HG264M64EEU806D6xG**
W3HG264M64EEU665D6xG
W3HG264M64EEU534D6xG
W3HG264M64EEU403D6xG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
5
5
4
4
3
3
** Consult factory for availability
NOTES:
• For part numbering interpretation, please see"part numbering guide" on page 10.
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.35 (5.25)
TYP
3.00
(0.118)
(4x)
30.00 (1.181)
TYP
+
+
17.80 (0.700)
TYP
10.00 (0.394)
TYP
4.00
(0.158)
(4x)
0.80 0.2
(0.032 0.2) TYP
4.00 (0.158)
PIN 120
PIN 1
2.50 0.20
(0.098 0.007)
1.50 0.10
(0.059 0.004)
1.00 (0.039) TYP
4.00 (0.158)
MAX
5.00
(0.196)
BACK VIEW
63.00 (2.48) TYP
55.00 (2.165) TYP
PIN 240
PIN 121
1.27 0.1
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
July 2007
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
W 3 H G 2 64M 64 E E U xxx D6 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 240 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank" for industrial add "I")
(Industrial Temp: -40°C to +85°C)
COMPONENT VENDOR NAME
(G = Qimonda)
Note: Consult factory for other vendor options.
G = RoHS COMPLIANT
July 2007
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG264M64EEU-D6
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED DIMM
DRAM DIE OPTIONS:
• QIMONDA: B-Die
Revision History
Rev #
Rev 0
History
Release Date Status
Created
July 2007
Concept
Rev 1
July 2007
Advanced
1.0 Moved to advanced
July 2007
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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