WE32K32-120G2UCA [MICROSEMI]
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68;
| 型号： | WE32K32-120G2UCA |
| 厂家： | 
Microsemi |
| 描述： | EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE32K32-XXX
White Electronic Designs
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
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ꢀ
ꢀ
Data Retention at 25°C, 10 Years
ꢀ
ꢀ
ꢀ
Access Times of 80**, 90, 120, 150ns
MIL-STD-883 Compliant Devices Available
Packaging:
Write Endurance, 10,000 Cycles
Organized as 32Kx32; User Configurable 64Kx16
or 128Kx8
• 68 lead, Hermetic CQFP (G2U), 122.4mm
(0.880") square, 3.56mm (0.140") height
(Package 510).
ꢀ
Commercial, Industrial and Military Temperature
Ranges
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5 Volt Power Supply
• 66-pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400)
* This product is subject to change without notice.
** 80ns speed is not fully characterized and is subject to change or cancellation without
notice.
Low Power CMOS, 10mA Standby Typical
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
FIGURE 1 – PIN CONFIGURATION FOR
WE32K32N-XH1X
Pin Description
Top View
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O8
I/O9
I/O10
A13
WE2#
CS2#
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE#
NC
I/O24
I/O25
I/O26
A6
VCC
CS4#
WE4#
I/O27
A3
I/O31
I/O30
I/O29
I/O28
A0
VCC
GND
NC
Not Connected
A14
A7
NC
A11
NC
A4
A1
Block Diagram
NC
A12
WE1#
I/O7
A8
A5
A2
WE1
#
CS1
#
WE2
#
CS2
#
WE3
#
CS3
#
WE4# CS4
NC
VCC
A9
WE3#
CS3#
GND
I/O19
I/O23
I/O22
I/O21
I/O20
OE#
A
0-14
I/O0
I/O1
I/O2
CS1#
NC
I/O6
I/O16
I/O17
I/O18
32K x 8
32K x 8
32K x 8
32K x 8
I/O5
I/O3
I/O4
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
FIGURE 2 – PIN CONFIGURATION FOR WE32K32-XG2UX
Top View
Pin Description
I/O0-31
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
A0-14
WE1-4#
CS1-4#
OE#
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
GND
NC
Not Connected
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
WE1# CS1#
WE2# CS2#
WE3# CS3#
WE4# CS4#
OE#
A
0-14
32K x 8
32K x 8
32K x 8
32K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O8-15
I/O0-7
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
TSTG
VG
Unit
°C
°C
V
CS#
H
L
L
X
OE#
X
L
H
H
WE#
X
H
L
X
Mode
Standby
Read
Write
Out Disable
Write
Data I/O
High Z
Data Out
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
Data In
High Z/Data Out
V
NOTE:
X
X
X
L
H
X
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Inhibit
CAPACITANCE
TA = +25°C
Parameter
Symbol
Conditions
Max Unit
RECOMMENDED OPERATING CONDITIONS
Address input capacitance
OE# capacitance
CAD
COE
VIN = 0 V, f = 1.0 MHz 50 pF
Parameter
Symbol
VCC
VIH
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
Unit
V
Supply Voltage
WE# capacitance
CWE
CCS
CI/O
VIN = 0 V, f = 1.0 MHz 50 pF
VIN = 0 V, f = 1.0 MHz 25 pF
VI/O = 0 V, f = 1.0 MHz 40 pF
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
VCC + 0.3
+0.8
+125
+85
V
V
°C
°C
CS1-4# capacitance
Data I/O capacitance
VIL
TA
TA
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-80
-90
-120
-150
Parameter
Symbol Conditions
Unit
Min Max Min Max Min Max Min Max
Input Leakage Current
Output Leakage Current
ILI
ILOx32
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, VOUT = GND to
VCC
10
10
10
10
10
10
10
10
µA
µA
Operating Supply Current (x32)
Standby Current
Output Low Voltage
ICCx32
ISB
VOL
VOH
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIH, OE# = VIH, f = 5MHz
IOL = 2.1mA, VCC = 4.5V
320
2.5
0.45
250
2.5
0.45
200
2.5
0.45
150
2.5
0.45
mA
mA
V
Output High Voltage
IOH = -400µA, VCC = 4.5V
2.4
2.4
2.4
2.4
V
FIGURE 3
AC Test Circuit
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Notes: VZ is programmable from -2V to +7V.
VIL = 0, VIH = 3.0
V
ns
V
5
1.5
1.5
≈
V
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
V
I
.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
WRITE
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
Awrite cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
AC Write Characteristics
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-80 -90
-120
-150
WRITE CYCLE
Write Cycle Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
Address Set-up Time
tWC
tAS
tWP
tCS
10
10
10
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
100
0
0
100
0
30
150
0
30
150
0
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
tAH
50
0
50
0
100
10
0
100
10
0
Data Hold Time
tDH
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
0
0
50
50
10
10
50
50
10
10
100
50
10
10
100
50
10
10
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
tWPH
tOES
tOEH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
t
WC
OE#
t
t
OEH
OES
ADDRESS
t
CSH
t
AS
t
AH
CS1-4
WE1-4
#
#
t
CS
t
WP
t
WPH
DH
t
t
DS
DATA IN
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
t
WC
OE#
t
t
OEH
OES
ADDRESS
WE1 - 4#
CS1 - 4#
t
CSH
t
t
AS
AH
t
CS
t
WP
t
WPH
DH
t
t
DS
DATA IN
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
READ
The WE32K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE#
are low and WE# is high, this data is present on the
outputs. When CS# and OE# are high, the outputs are in
a high impedance state. This 2 line control prevents bus
contention.
AC Read Characteristics (See Figure 6)
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
READ CYCLE
Symbol
-80
-90
-120
-150
Unit
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
80
90
120
150
ns
ns
ns
ns
ns
ns
Address Access Time
80
80
90
90
120
120
150
150
CS Access Time
Output Hold from Add. Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to Output in High Z
0
0
0
0
tOE
40
40
50
50
85
70
85
70
tDF
FIGURE 6 – READ WAVEFORMS
t
RC
ADDRESS VALID
ADDRESS
CS#
OE#
t
ACS
t
OE
t
DF
t
ACC
t
OH
HIGH Z
OUTPUT
VALID
OUTPUT
NOTES:
1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after
an address change without impact on tACC.
2. tCHZ, tOHZ are specified from OE# or CS# whichever occurs first (CL = 5pF).
3. All I/O transitions are measured 200 mV from steady state with loading as specified in "Load Test Circuits."
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
DATA POLLING CHARACTERISTICS
DATA POLLING
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
The WE32K32-XXX offers a data polling feature which
allows a faster method of writing to the device. Figure 7
shows the timing diagram for this function. During a byte
or page write cycle, an attempted read of the last byte
written will result in the complement of the written data
on D7 (for each chip.) Once the write cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. Data polling may begin at any time during
the write cycle.
Parameter
Symbol Min
Max
Unit
ns
Data Hold Time
OE# Hold Time
OE# To Output Valid
Write Recovery Time
tDH
tOEH
tOE
10
10
ns
100
ns
tWR
0
ns
FIGURE 7 – DATA POLLING WAVEFORMS
WE1-4#
CS1-4#
OE#
tOEH
tOE
tDH
I/O7
HIGH Z
tWR
ADDRESS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
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WE32K32-XXX
White Electronic Designs
PAGE WRITE OPERATION
The usual procedure is to increment the least significant
address lines fromA0 throughA5 at each write cycle. In this
manner a page of up to 64 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively
long interval programming cycle.
The WE32K32-XXX has a page write operation that allows
one to 64 bytes of data to be written into the device and
consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the first data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150µs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
PAGE WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-80
-90
-120
-150
PAGE MODE WRITE CHARACTERISTICS
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
tWC
tDS
tDH
tWP
tBLC
tWPH
10
10
10
10
ms
ns
ns
ns
µs
ns
50
0
100
50
0
100
100
10
150
100
10
150
150
150
150
150
50
50
50
50
FIGURE 8 – PAGE WRITE WAVEFORMS
OE#
CS#
tWP
tBLC
tWPH
WE#
tDS
tDH
ADDRESS (1)
VALID
ADDRESS
tWC
VALID DATA
DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE n
BYTE n + 1
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
WRITES ENABLED(2)
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
ENTER DATA
PROTECT STATE
LAST ADDRESS
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 64 bytes of data to be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
FIGURE 10 –
SOFTWARE DATA PROTECTION
SOFTWARE BLOCK DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the WE32K32-XXX has the feature
disabled. Write access to the device is unrestricted.
DISABLE ALGORITHM(1)
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
Each 32KByte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions,
or unauthorized modification using a PROM programmer.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE32K32-XXX. These are included to improve reliability
during normal operation:
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d) Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
NOTES:
1. Data Format: I/O15-0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 64 bytes of data may loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE32K32-XXX
White Electronic Designs
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.60 (0.181)
MAX
3.81 (0.150)
0.13 (0.005)
1.42 (0.056) 0.13 (0.005)
0.76 (0.030) 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
11
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WE32K32-XXX
White Electronic Designs
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
25.15 (0.990) 0.25 (0.010) SQ
3.51 (0.140) MAX
22.36 (0.880) 0.25 (0.010) SQ
0.25 (0.010) 0.10 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
0.25 (0.010)
0.53 (0.021)
0.18 (0.007)
1
/ 7
1.01 (0.040)
0.13 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2U
CQFP fills the same fit and
function as the JEDEC 68
lead CQFJ or 68 PLCC.
But the G2U has the TCE
and lead inspection advan-
tage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
12
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WE32K32-XXX
White Electronic Designs
ORDERING INFORMATION
W E 32K32 X - XXX X X X
WHITE ELECTRONIC DESIGNS CORP.
EEPROM
ORGANIZATION, 32K x 32
User Configurable as 64Kx16 or 128Kx8
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
ACCESS TIME (ns)
PACKAGE TYPE:
H1 = Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 510)
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
120ns
90ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94614 01HXX
5962-94614 02HXX
5962-94614 03HXX
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
120ns
90ns
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
5962-94614 01HZX
5962-94614 02HZX
5962-94614 03HZX
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
WE32K32-120G2UI
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120G2UI
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MERCURY
WE32K32-120G2UIA
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120G2UIA
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MERCURY
WE32K32-120G2UM
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120G2UM
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MERCURY
WE32K32-120G2UMA
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120G2UMA
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MERCURY
WE32K32-120G2UQ
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120G2UQA
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WE32K32-120H1C
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
MERCURY
WE32K32-120H1Q
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
MERCURY
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