WED3EG72M18S335JD3ISG [MICROSEMI]
DDR DRAM Module, 16MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184;
| 型号： | WED3EG72M18S335JD3ISG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 16MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总12页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
ꢀ
Double-data-rate architecture
The WED3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
ꢀ
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specified
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Serial presence detect
Power supply:
•
•
V
CC = VCCQ = 2.5V±0.2V
(100, 133 and 166MHz)
CC = VCCQ = 2.6V±0.1V
(200MHz)
V
ꢀ
JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") Max
NOTE: Consult factory for availability of:
• RoHS Products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR400 @CL=3
DDR333 @CL=2.5
166MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
200MHz
3-3-3
2.5-3-3
2-2-2
2.5-3-3
2-2-2
June 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0 – A12
Address input (Multiplexed)
Select Bank Address
Data Input/Output
Check bits
Pin
1
Front
VREF
DQ0
VSS
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
DQS8
A0
Pin
93
Front
VSS
Pin
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Front
VSS
BA0-BA1
DQ0-DQ63
CB0-CB7
2
94
DQ4
DQ5
VCCQ
DQM0
DQ6
DQ7
VSS
DQM8
A10
3
CB2
95
DQS0-DQS8
CK0, CK1, CK2
Data Strobe Input/Output
Clock input
4
DQ1
DQS0
DQ2
VCC
VSS
96
CB6
5
CB3
97
VCCQ
CB7
CK0#, CK1#, CK2# Clock input
6
BA1
98
CKE0
CS0#
Clock Enable input
7
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
99
VSS
Chip select Input
8
DQ3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
RAS#
CAS#
WE#
Row Address Strobe
Column Address Strobe
Write Enable
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
NC
NC
VSS
*A13
VCCQ
DQ12
DQ13
DQM1
VCC
DQM4
DQ38
DQ39
VSS
DQM0-DQM8
VCC
Data-in Mask
DQ8
DQ9
DQS1
VCCQ
CK1
CK1#
VSS
Power Supply (2.5V)
Power Supply for DQS (2.5V)
BA0
VCCQ
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
*CS1#
DQM5
VSS
VSS
Ground
VREF
Power Supply for Reference
Serial EEPROM Power Supply (2.3V to 3.6V)
Serial data I/O
DQ14
DQ15
*CKE1
VCCQ
*BA2
DQ20
A12
VCCSPD
SDA
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
SCL
Serial clock
SA0-SA2
VDDID
NC
Address in EEPROM
VDD Identification Flag
No Connect
DQS5
DQ42
DQ43
VCC
DQ46
DQ47
*CS3#
VCCQ
DQ52
DQ53
NC
VSS
* Not Used
CS2#
DQ48
DQ49
VSS
DQ21
A11
A9
DQM2
VCC
DQ18
A7
CK2#
CK2
DQ22
A8
VCCQ
DQ19
A5
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
DQ23
VSS
DQM6
DQ54
DQ55
VCCQ
NC
DQ24
VSS
A6
DQ28
DQ29
VCCQ
DQM3
A3
DQ25
DQS3
A4
VDDID
DQ56
DQ57
VCC
DQ60
DQ60
VSS
VCC
DQ26
DQ27
A2
DQ30
VSS
DQM7
DQ62
DQ63
VCCQ
SA0
DQS7
DQ58
DQ59
VSS
DQ31
CB4
VSS
A1
CB5
CB0
CB1
VCC
NC
VCCQ
CK0
SA1
SDA
SCL
SA2
CK0#
VCCSPD
June 2006
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS4
DQM4
DQS0
DQM0
DM
DM
CS#
DQS
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DQM1
DQS5
DQM5
DM
DM
CS#
DQS
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DQM6
DQS2
DQM2
DM
CS#
DQS
DM
CS#
DQS
DQ48
DQ16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQM3
DQS7
DQM7
DM
DM
CS#
DQS
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ56
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS8
DQM8
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
SERIAL PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SDA
SCL
WP
A2
SA2
A0
A1
SA1
SA0
VCCSPD
SPD
V
CCQ
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
RAS#
CAS#
V
CC
V
REF
BA0-BA1
WE#
V
SS
A0-A12
CKE0
CLOCK INPUT
CK0, CK0#
3 SDRAMS
3 SDRAMS
3 SDRAMS
CK1, CK1#
CK2, CK2#
NOTE: All resistor values are 22 ohms unless otherwise specified
June 2006
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-0.5 ~ 3.6
V
-1.0 ~ 3.6
V
-55 ~ +150
°C
W
Power Dissipation
PD
9
Short Circuit Current
I0S
50
mA
Notes:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
(0°C TA 70°C, VCC = 2.5V ± O.2V)
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
V
1.15
1.35
V
VIH
VREF+0.15
-0.3
VCCQ+0.3
VREF+0.15
—
V
VIL
V
VOH
VTT+0.76
—
V
VOL
VTT-0.76
V
CAPACITANCE
(TA = 25°C. f = 1MHz, VCC = 2.5V)
Parameter
Symbol
CIN1
Max
45
45
45
40
44
15
45
15
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#, CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Data Input/Output capacitance (DQ0-DQ63)(DQS)
Data Input/Output Capacitance (CB0-CB7)
COUT
COUT
June 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
ICC SPECIFICATIONS AND TEST CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V includes DDR SDRAM component only
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
Parameter
Symbol Conditions
One device bank; Active =
Units
Precharge; TRC=TRC(MIN);
TCK=TCK(MIN); DQ,DM and DQS
inputs changing once per clock cycle;
Address and control inputs changing
once every two cycles
Operating
Current
ICC0
990
990
810
mA
One device bank; Active-read-
Precharge; Burst = 2; TRC=TRC(MIN);
TCK=TCK(MIN); lout=0mA; Address
and control inputs changing once per
clock cycle
Operating
Current
ICC1
1260
270
1260
270
1035
255
mA
mA
Precharge
Power-Down
Standby
All device banks idle; Power-down
mode; TCK=TCK(MIN); CKE=(low)
ICC2P
Current
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE=high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Idle Standby
Current
ICC2F
495
315
495
315
405
270
mA
mA
Active Power-
Down Standby
Current
One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
ICC3P
CS# = High; CKE = High; One
device bank; Active-Precharge; TRC
= TRAS(MAX); TCK = TCK(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.
Active Standby
Current
ICC3N
540
540
450
mA
Burst = 2; Reads; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle;
Operating
Current
ICC4R
1800
1800
1485
mA
mA
TCK = TCK(MIN); lout = 0mA
Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; TCK = TCK(MIN); DQ, DM
and DQS inputs changing twice per
clock cycle.
Operating
Current
ICC4W
1935
1935
1935
1935
1530
1530
Auto Refresh
Current
ICC5
TRC = TRC(MIN)
mA
mA
Standard
CKE 0.2V
18
9
18
9
18
9
Self Refresh
Current
ICC6
Low Power
June 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
June 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/265
Min Max
-0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75
202
Parameter
Symbol Min
tAC
tCH
Max
Min
Max
Min
Max
Units Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
ns
0.45
0.45
5
0.55
0.55
7.5
13
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
16
16
tCL
Clock cycle time
CL=3
tCK (3)
22
CL=2.5 tCK (2.5)
6
6
13
13
7.5
7.5
13
13
7.5
10
13
13
22
CL=2
tCK (2)
tDH
7.5
0.40
0.40
1.75
13
7.5
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.45
0.45
1.75
0.5
0.5
0.5
1.75
14,17
14,17
17
tDS
0.5
tDIPW
1.75
tDQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75
tDQSH
tDQSL
tDQSQ
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
0.40
1.28
0.45
1.25
0.5
0.5
13,14
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.72
0.2
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.2
0.2
0.2
0.2
tCH, tCL
tCH, tCL
tCH, tCL
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
tHZ
+0.70
+0.70
+0.75
+0.75
tLZ
-0.70
0.60
0.60
0.60
0.60
2.2
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
-0.75
0.90
0.90
1
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tIHf
tISf
6
tIHs
6
tISs
1
1
6
tIPW
tMRD
2.2
2.2
10
12
15
15
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
13,14
15
Data hold skew factor
tQHS
0.50
0.55
0.75
0.75
ns
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRAS
tRAP
tRC
40
15
55
70
70,000
42
15
60
72
70,000
40 120,000 45 120,000 ns
15
60
75
20
65
75
ns
ns
ns
tRFC
21
June 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/265
202
Parameter
Symbol Min
Max
Min
15
Max
Min
Max
Min
20
Max
Units Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRCD
tRP
15
15
0.9
0.4
10
0.25
0
15
15
0.9
0.4
15
0.25
0
ns
ns
15
20
tRPRE
tRPST
tRRD
1.1
0.6
0.9
0.4
12
1.1
0.6
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
tCK
ns
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
tCK
DQS write preamble setup time
DQS write postamble
ns
tCK
ns
tCK
ns
μs
μs
ns
ns
tCK
10,11
9
0.4
15
2
0.6
0.4
15
0.6
0.4
15
1
0.6
0.4
15
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
NA
1
1
tQH-tDQSQ
70.3
7.8
tQH-tDQSQ
70.3
7.8
tQH-tDQSQ
tQH-tDQSQ
70.3
7.8
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
tVTD
70.3
7.8
0
0
0
0
tXSNR
tXSRD
70
75
75
75
200
200
200
200
June 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
Notes
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
1.
All voltages referenced to VSS
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
high during this time, depending on tDQSS
.
12. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125μs. However, an AUTO REFRESH command must
be asserted at least once every 70.3μs; burst refreshing or posting
by the DRAM controller greater than eight refresh cycles is not
allowed.
3.
Outputs are measured with equivalent load:
V
TTT
50Ω
RReeffeerreennccee
Outtppuut
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
Poiint
30pF
(VOUT
)
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
14. Referenced to each output group: x8 = DQS with DQ0-DQ7.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
5.
6.
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. tIH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403
and 335, slew rates must be greater than or equal to 0.5V/ns.
18.
tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19.
t
HZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)
7.
8.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE 0.3 x VCCQ is
recognized as LOW.
condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX)
condition.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
9.
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition
LOW (below VIHDC) prior to tDQSH (MIN).
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
June 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR JD3
Speed/Data Rate
CAS Latency
Frequency
Part Number
tRCD
tRP
Height*
WED3EG7218S403JD3xxx
WED3EG7218S335JD3xxx
WED3EG7218S262JD3xxx
WED3EG7218S265JD3xxx
WED3EG7218S202JD3xxx
200MHz/400Mb/s
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
3
2.5
2
3
3
2
3
2
3
3
2
3
2
30.48mm (1.20")
30.48mm (1.20")
30.48mm (1.20")
30.48mm (1.20")
30.48mm (1.20")
2.5
2
NOTES:
• Consult Factory for availability of RoHS products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
2.54
(0.100)
128.95
(5.077")
3.99
(0.157 (2x))
30.48
(1.20)
MAX
3.99
(0.157)
(MIN)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.01
(0.050 TYP.)
(0.394)
6.35
(0.250)
49.53
(1.950)
64.77
1.27 0.10
(0.050 0.004)
(2.550)
6.35
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
June 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
PART NUMBERING GUIDE
WED 3 E G 72M 18 S xxx JD3 x x G
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH
BUS WIDTH
2.5V
SPEED (Mb/s)
PACKAGE 184 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
June 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
Document Title
128MB – 16Mx72 DDR SDRAM UNBUFFERED
DRAM DIE OPTIONS:
• SAMSUNG: H-Die
• MICRON: T26Z: G-Die
Revision History
Rev #
History
Release Date Status
Rev A
Rev 0
Created Datasheet
3-6-02
11-04
Advanced
0.1 Updated IDD and CAP specs
0.2 Updated AC specs
Preliminary
0.3 Moved from Advanced to Preliminary
0.4 Added Lead-Free and RoHS note
Rev 1
Rev 2
1.0 Added JEDEC PCB option (JD3)
11-05
6-06
Preliminary
Preliminary
1.1 D3 PCB option "NOT RECOMMENDED FOR NEW
DESIGNS"
2.1 Removed "D3" package option
2.2 Added "Part Numbering Guide"
2.3 Added DRAM die options
2.4 Added DDR400 and DDR333 ICC & AC specifications
June 2006
Rev. 2
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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