WEDPZ512K72S-133BC [MICROSEMI]
SRAM Module, 512KX72, 4.2ns, CMOS, PBGA152, 17 X 23 MM, PLASTIC, BGA-152;
| 型号： | WEDPZ512K72S-133BC |
| 厂家： | 
Microsemi |
| 描述： | SRAM Module, 512KX72, 4.2ns, CMOS, PBGA152, 17 X 23 MM, PLASTIC, BGA-152 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM
FEATURES
DESCRIPTION
The WEDC SyncBurst - SRAM employs high-speed,
low-power CMOS design that is fabricated using an
advanced CMOS process. WEDC’s 32Mb SyncBurst
SRAMs integrate two 512K x 36 SSRAMs into a single
BGA package to provide 512K x 72 configuration. All
synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The ZBL
or Zero Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied “High or Low.” Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing flexibility
for incoming signals.
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Fast clock speed: 150, 133, and 100MHz
Fast access times: 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns
High performance 3-1-1-1 access rate
2.5V ± 5% power supply
Common data inputs and data outputs
Byte write enable and global write control
Six chip enables for depth expansion and address
pipeline
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Internally self-timed write cycle
Burst control pin (interleaved or linear burst
sequence)
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Automatic power-down for portable applications
Commercial, industrial and military temperature
ranges
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Packaging:
* This product is under development, is not qualified or characterized and is subject to
• 152 PBGA package 17 x 23mm
change without notice.
BENEFITS
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30% space savings compared to equivalent TQFP
solution
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Reduced part count
24% I/O reduction
Laminate interposer for optimum TCE match
Low Profile
Reduce layer count for board routing
Suitable for hi-reliability applications
User configurable as 1M x 36 or 2M x 18
Upgradable to 1M x 72 (contact factory for
availability)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
FUNCTIONAL BLOCK DIAGRAM
512K x 36 SSRAM
A0-18
BWa#
BWb#
BWc#
BWd#
WE0#
OE0#
SA
BWa#
BWb#
BWc#
BWd#
WE0#
OE0#
CLK
DQPA
DQPA
DQA0-7
DQPB
DQB0-7
DQPC
DQC0-7
DQPD
DQD0-7
DQA0-7
DQPB
DQB0-7
DQPC
DQC0-7
DQPD
DQD0-7
CLK0#
CKE0#
CKE#
CS1#
CS2#
CS2
CS10
CS20
#
#
CS20
ADV0
LB0#
ZZ
ADV
LB0#
ZZ
512K x 36 SSRAM
SA
BWe#
BWf#
BWa#
BWb#
BWc#
BWd#
WE0#
OE0#
CLK
BWg#
BWh#
WE1#
OE1#
DQPA
DQA0-7
DQPB
DQB0-7
DQPC
DQC0-7
DQPH
DQD0-7
DQPE
DQE0-7
DQPF
DQF0-7
DQPG
DQG0-7
DQPH
DQH0-7
CLK1#
CKE1#
CKE
CS1#
CS2#
CS2
CS113
CS21
CS21
#
#
#
ADV1
ADV
LB0#
ZZ
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
-
ADV0
WE0#
OE0#
DQB7
DQC2
DQC3
DQC4
DQC5
DQC7
DQC6
DQF2
DQF3
DQF6
DQF7
DQPF
DQF1
DQF0
DQG0
DQG3
DQB2
DQB5
DQPC
VSS
DQB4
DQB3
DQPB
VSS
DQB6
DQB0
DQB1
VSS
DNU
DQA6
DQA3
DQA4
DQA5
DQPD
DNU*
A1
DQA2
DQA1
DQA0
DQPA
ZZ
CKE0#
CLK0
BWA#
BWC#
DQA7
DQD7
DQD6
DQD5
DQD4
DQD3
DQD2
DQD1
DQD0
DQE6
DQE7
DQE5
DQE4
DQH2
DQH4
DQH3
CS20
#
BWB#
BWD#
CS20
VCCQ
VCCQ
VSS
VCCQ
VCCQ
VCC
VCCQ
VSS
CS10
A7
#
A0
G
H
J
DQC0
DQC1
A6
VCC
A3
A18
A9
VCC
VCC
VCC
A2
A5
VSS
VSS
VSS
A4
A16
K
L
A8
DQF4
DQF5
OE1#
WE1#
VCC
VCC
VCC
A14
A15
A17
VCC
VCC
VSS
A12
A13
M
N
P
R
T
ADV1
CKE1#
CLK1
VSS
VCCQ
VCCQ
VSS
VSSQ
VCCQ
VSS
A10
A11
VCCQ
VSS
DQE3
DQE2
DQE1
DQH7
DQH5
LBO#
DQE0
DQPE
DQPH
DQH6
CS21
#
BWE#
BWG#
CS11#
BWF#
BWH#
CS21
DQG1
DQG2
DQPG
DQG4
DQG5
DQG6
DQH1
DQH0
DQG7
U
NOTES:
DNU means Do Not Use and are reserved for future use.
* Pin F8 reserved for A19 upgrade to 1M x 72.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
FUNCTION DESCRIPTION
The WEDPZ512K72S-XBX is an ZBL SSRAM designed
Write operation occurs when WE# is driven low at the
rising edge of the clock. BW#[h:a] can be used for byte
write operation. The pipe-lined ZBL SSRAM uses a late-
late write cycle to utilize 100% of the bandwidth.At the first
rising edge of the clock, WE# and address are registered,
and the data associated with that address is required two
cycles later.
to sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa.All inputs (with the exception of OE#, LBO# and ZZ)
are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV). ADV should
be driven to Low once the device has been deselected in
order to load a new address for next operation.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO# pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.
Clock Enable (CKE#) pin allows the operation of the chip to
be suspended as long as necessary. When CKE# is high,
all synchronous inputs are ignored and the internal device
registers will hold their previous values. NBL SSRAM
latches external address and initiates a cycle when CKE
and ADV are driven low at the rising edge of the clock.
During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after two cycles. At this time, internal state of the SRAM
is preserved. When ZZ returns to low, the SRAM operates
after two cycles of wake up time.
Output Enable (OE#) can be used to disable the output
at any given time. Read operation is initiated when at
the rising edge of the clock, the address presented to
the address inputs are latched in the address register,
CKE# is driven low, the write enable input signals WE#
are driven high, and ADV driven low. The internal array is
read between the first rising edge and the second rising
edge of the clock and the data is latched in the output
register. At the second clock edge the data is driven out
of the SRAM. During read operation OE# must be driven
low for the device to drive out the requested data.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO# = High)
(Linear Burst, LBO# = Low)
Case 1
Case 2
Case 3
Case 4
Case 1
Case 2
Case 3
Case 4
LBO# Pin
High
LBO# Pin
High
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
1
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
First Address
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Fourth Address
Fourth Address
NOTE: LBO pin must be tied to High or Low, and Floating State must not be allowed.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CE#x
ADV
L
WE#
X
BW#x
OE#
X
CKE#
CLK
↑
Address Accessed
N/A
Operation
H
X
L
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
Deselect
H
L
X
X
↑
N/A
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
H
X
L
↑
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
H
L
L
↑
H
X
H
H
X
↑
X
L
H
L
↑
L
↑
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
H
L
X
L
X
↑
L
H
H
X
X
↑
X
X
H
X
X
X
↑
Next Address
Current Address
X
X
↑
Ignore Clock
NOTES:
1)
2)
3)
4)
X means “Don’t Care.”
The rising edge of clock is symbolized by ( ↑ ).
A continue deselect cycle can only be entered if a deselect cycle is executed first.
WRITE# = L means Write operation in WRITE TRUTH TABLE.
WRITE# = H means Read operation in WRITE TRUTH TABLE.
Operation finally depends on status of asynchronous input pins (ZZ and OE#).
CE#x refers to the combination of CS#1 and CS#2.
5)
6)
WRITE TRUTH TABLE
WE#
BW#a
BW#b
BW#c
BW#d Operation
H
L
L
L
L
L
L
X
L
X
H
L
X
H
H
L
X
H
H
H
L
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
H
H
H
L
H
H
L
H
L
L
H
H
H
H
Write Abort/NOP
NOTES:
1)
2)
3)
X means “Don’t Care.”
All inputs in this table must meet setup and hold time around the rising edge of CLK (↑ ).
Replace BW#a with BW#e, BW#b, with BW#f, BW#c with BW#g and BW#d with BW#h for
operation of IC2.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
ABSOLUT MAXIMUM RATINGS*
VIN Voltage or any other pin relative to VSS -0.3V to +3.6V
Voltage on VCC supply relative to VSS
Storage temperature (BGA)
-0.3V to +3.6V
-55°C to +150°C
* Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended
periods may affect reliability.
ELECTRICAL CHARACTERISTICS
(-55°C TA +125°C)
Description
Symbol
VIH
Conditions
Min
1.7
Max
VCC +0.3
0.7
Units
V
Notes
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
1
1
2
VIL
-0.3
-4
V
IIL
VCC = Max, 0V VIN VCC
Output(s) Disabled, VOUT = VSS to VCCQ
IOH = -1.0mA
+4
μA
μA
V
ILO
-2
+2
VOH
VOL
VCC
VCCQ
2.0
---
1
1
1
1
IOL = 1.0mA
---
0.4
V
2.375
2.375
2.625
2.625
V
I/O Power Supply
NOTES:
V
1)
2)
All voltages referenced to VSS (GND)
ZZ pin has an internal pull-up and input leakage = ± 20 μA.
DC CHARACTERISTICS
(-55°C TA + 125°C)
150MHz 133MHz 100MHz
Description
Symbol Conditions
Units Notes
(Max)
(Max)
(Max)
Power Supply
Current: Operating
Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle
Time ≥ TCYC MIN; VCC = MAX; Output Open
IDD
ISB2
ISB
700
650
600
mA
mA
mA
1
Device Deselected; VCC = MAX; All Inputs ≤ VIL or ≥ VIH
All Inputs Static; CLK Frequency = MAX
Output Open, ZZ ≥ VCC - 0.2V
Power Supply
Current: Standby
120
180
120
180
120
160
Clock Running
Standby Current
Device Deselected; VCC = MAX; All Inputs
≤ VSS + 0.2 or VCC - 0.2; f = MAX ; ZZ ≤ VIL
NOTE:
I
DD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.
BGA CAPACITANCE
THERMAL RESISTANCE
(TA = + 25°C, f = 1MHz)
Description
Symbol
CIC
Max
Units Notes
Parameter
Symbol
Max
28.7
16.0
7.1
Unit
°C/W
°C/W
°C/W
Control Input Capacitance (LBO#, ZZ)
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
16
8
pF
pF
pF
pF
pF
1
1
1
1
1
Thermal Resistance: Die Junction to Ambient
Thermal Resistance: Die Junction to Ball
Thermal Resistance: Die Junction to Case
θJA
θJB
θJC
CI
CO
10
16
6
CA
Note: Refer to Application Note “PBGA Thermal Resistance Corrleation” for further
information regarding WEDC’s thermal modeling.
Clock Capacitance
CCK
NOTE:
1)
This parameter is not tested but guaranteed by design.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
AC CHARACTERISTICS
(-55°C TA +125°C)
150MHz
133MHz
100MHz
Units
Parameter
Symbol
Min
6.7
--
Max
Min
7.5
--
Max
Min
10.0
--
Max
Clock Time
tCYC
tCD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Access Time
3.8
3.8
--
4.2
4.2
--
5.0
5.0
--
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
--
--
--
tLZC
tOH
1.5
1.5
0.0
--
1.5
1.5
0.0
--
1.5
1.5
0.0
--
--
--
--
tLZOE
tHZOE
tHZC
tCH
--
--
--
3.0
3.0
--
3.5
3.5
--
3.5
3.5
--
--
--
--
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Clock Low Pulse Width
tCL
--
--
--
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
tAS
--
--
--
tCES
tDS
--
--
--
--
--
--
tWS
--
--
--
tADVS
tCSS
tAH
--
--
--
--
--
--
--
--
--
--
--
--
--
--
tCEH
tDH
Data Hold to Clock High
--
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
NOTES:
tWH
--
tADVH
tCSH
--
---
1)
All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CS#x is sampled valid.
All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both
cases must meet setup and hold times.
2)
3)
AC TEST CONDITIONS
Parameter
Value
Input Pulse Level
0 to 2.5V
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.0V/ns
1.25V
See Output Load (A & B)
OUTPUT LOAD (A)
OUTPUT LOAD (B)
(for TLZC, TLZOE, THZOE, and THZC
)
Dout
RL=50Ω
+2.5V
VL=1.25V
50pF*
1667Ω
Zo=50Ω
Dout
1538Ω
5pF*
*Including Scope and Jig Capacitance
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in
When ZZ becomes a logic HIGH, ISB2z is guaranteed after
the setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.
which the device is deselected and current is reduced to
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated inputs
and are ignored. ZZ is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE.
SNOOZE MODE
Description
Conditions Symbol
Min
Max
20
2
Units
mA
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
ISB2Z
tZZ
cycle
cycle
cycle
ns
tRZZ
tZZI
2
2
tRZZI
O
SNOOZE MODE TIMING DIAGRAM
CLOCK
t
ZZ
t
RZZ
ZZ
t
ZZI
t
RZZI
ISUPPLY
I
ISB2Z
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Deselect or Read Only
Normal
Operation Cycle
Output (Q)
HIGH-Z
DON'T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TIMING WAVEFORM OF READ CYCLE
t
CH
tCL
CLKX
tCYC
tCES
t
CEH
CKEX#
tAS
tAH
A1
A2
A3
Address
WRITE#
t
WS
tWH
tCSH
t
CSS
CSX#
tADVS
tADVH
ADVX
OE#
t
OE
t
CD
tHZOE
tHZC
tOH
t
LZOE
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
Data Out
NOTES: WRITE# = L means WEx# = L, and BWx# = L
CSx# refers to the combination of CS1 #, CS2
Don¢t Care
Undefined
0
0
and CS2
0
#, or CS1
1
#, CS2
1
1
and CS2 #.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TIMING WAVEFORM OF WRITE CYCLE
tCL
tCH
CLKX
CKEX#
Address
WRITE#
CSX#
tCYC
t
CES tCEH
A2
A3
A1
ADVX
OE#
tDS
tDH
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
D3-2
D3-3
Data In
Data Out
D3-4
tHZOE
Q0-3
Q0-4
Don’t Care
Undefined
NOTES: WRITE# = L means WEx# = L, and BWx# = L
0 0 1 1 1
CSx# refers to the combination of CS1 #, CS2 and CS2 #, or CS1 #, CS2 and CS2 #.
0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TIMING WAVEFORM OF SINGLE READ/WRITE
tCH
tCL
CLKX
CKEX#
Address
WRITE#
CSX#
tCYC
t
CES tCEH
A8
A4
A9
A1
A2
A3
A5
A6
A7
ADVX
OE#
t
OE
LZOE
t
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
tDH
t
DS
D2
D5
NOTES: WRITE# = L means WEx# = L, and BWx# = L
CSx# refers to the combination of CS1 #, CS2
0
0
and CS2
0
#, or CS1
1
#, CS2
1
1
and CS2 #.
Don’t Care
Undefined
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TIMING WAVEFORM OF CKE OPERATION
t
CL
tCH
CLKX
CKEX#
Address
WRITE#
CSX#
tCEH
CES
t
t
CYC
A1
A2
A3
A4
A5
A6
ADVX
OE#
t
CD
LZC
tHZC
t
Q1
Q3
Q4
Data Out
Data In
tDH
t
DS
D2
NOTES: WRITE# = L means WEx# = L, and BWx# = L
CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don¢t Care
Undefined
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
TIMING WAVEFORM OF CE OPERATION
tCH
tCL
CLKX
CKEX#
Address
WRITE#
CSX#
tCYC
tCEH
tCES
A1
A2
A3
A4
A5
ADVX
OE#
tHZC
Q2
tOE
tLZOE
tCD
tLZC
Data Out
Data In
Q1
Q4
tDH
tDS
D3
D5
NOTES: WRITE# = L means WEx# = L, and BWx# = L
CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don’t Care
Undefined
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
PACKAGE DIMENSION:
152 BUMP PBGA
BOTTOM VIEW
∅ 0.762 (0.030) NOM
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
23.1 (0.909)
MAX
20.32 (0.800)
NOM
K
L
1.27
(0.050)
NOM
M
N
P
R
T
U
1.27 (0.050) NOM
0.61
(0.024)
NOM
10.16 (0.400)
NOM
17.1 (0.673)
MAX
2.03 (0.080)
MAX
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P Z 512K 72 S - XXX B X
DEVICE GRADE:
M
I
=
=
=
Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
Industrial
Commercial
C
PACKAGE:
152 Plastic Ball Grid Array (PBGA)
B
=
FREQUENCY (MHz)
100
133
150
=
=
=
100MHz
133MHz
150MHz
2.5V Voltage
CONFIGURATION, 512K x 72
SSRAM ZBL
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
14
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPZ512K72S-XBX
White Electronic Designs
PRELIMINARY*
Document Title
512K x 72 Synchronous SRAM – NBL
Revision History
Rev #
Rev 0
History
Release Date Status
Initial Release
February 2001
April 2001
Advanced
Advanced
Rev 1
Changes (Pg. 1, 5, 6, 13)
1.1 Block Diagram: Change DQD to DQPD, Font Consistency
1.2 Electrical Characteristics Note 2: Change reference to mA instead of MA.
1.3 DC Characteristics: Adjust location of Units & Notes for ISB2.
1.4 AC Characteristics: Change temperature range to (-55°C ≤ TA ≤ +125°C)
1.5 Package Dimension: Adjust length line to end of package
1.6 Block Diagram: Adjust look for consistency
1.7 DC Characteristics: ISB2 condition should read All Inputs ≤ VIL or ≥ VIH instead of > VIH
1.8 Figure 2: Inputs transition should not be shown fully connected.
1.9 Figure 6: Unknown text deleted from timing diagram
1.10 Package Dimension: Ball diameter arrow corrected to point to ball.
Rev 2
Rev 3
Change (Pg. 1)
1.1 Change status from Advanced to Preliminary
November 2001
November 2001
Preliminary
Preliminary
Changes (Pg. 1, 2)
1.1 Block Diagram: Address lines should be A0-18
1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72.
Rev 4
Changes (Pg. 1, 5)
November 2002
Preliminary
1.1 BGA Capacitance: Remove references to temperature in individual conditions
1.2 Change CI from 10pF to 8pF
1.3 Change CA from 20pF to 16pF
1.4 Change CCK from 7pF to 6pF
1.5 Add Control Input Capacitance (CIC) 16pF
Rev 5
Rev 6
Changes (Pg. 5)
1.1 Add Thermal Resistance table
1.2 Update current values
May 2003
Preliminary
Preliminary
1.3 Update package mechanical drawing
Changes (Pg. 1, 13, 14, 15)
November 2003
1.1 Change mechanical drawing to new style
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2003
Rev. 6
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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