WS512K32-17G2UI [MICROSEMI]
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68;
| 型号： | WS512K32-17G2UI |
| 厂家： | 
Microsemi |
| 描述： | SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68 静态存储器 |
| 文件： | 总11页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS512K32-XXX
White Electronic Designs
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
ꢀ
ꢀ
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Packaging
ꢀ
ꢀ
ꢀ
ꢀ
TTL Compatible Inputs and Outputs
5 Volt Power Supply
Low Power CMOS
•
•
•
66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400).
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
68 lead, 40mm Hermetic Low Profile CQFP,
3.5mm (0.140") (Package 502)1
ꢀ
Weight
68 lead, Hermetic CQFP (G2U), 22.4mm
(0.880") square (Package 510) 3.56mm
(0.140") height.
WS512K32N-XH1X - 13 grams typical
WS512K32-XG2UX - 8 grams typical
WS512K32-XG4TX1 - 20 grams typical
WS512K32-XG2LX - 8 grams typical
•
68 lead, Hermetic CQFP (G2L), 22.4mm
(0.880") square, 5.08mm (0.200") high
(Package 528).
* This product is subject to change without notice.
Note 1: Package Not Recommended For New Design
ꢀ
ꢀ
Organized as 512Kx32, User Configurable as
1Mx16 or 2Mx8
Commercial, Industrial and Military Temperature
Ranges
FIGURE 1 – PIN CONFIGURATION FOR WS512K32N-XH1X
Top View
Pin Description
I/O0-31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
1
12
23
34
45
56
A0-18
I/O8
I/O9
I/O10
A13
WE2#
CS2#
GND
I/O11
A10
I/O15
I/O24
I/O25
I/O26
A6
VCC
CS4#
WE4#
I/O27
A3
I/O31
I/O30
I/O29
I/O28
A0
WE1-4
#
I/O14
I/O13
I/O12
OE#
A18
CS1-4
OE#
VCC
#
Output Enable
Power Supply
Ground
GND
NC
A14
A7
Not Connected
A15
A11
NC
A4
A1
Block Diagram
A16
A12
WE1#
I/O7
A8
A5
A2
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
4 4
WE # CS #
A17
VCC
A9
WE3#
CS3
GND
I/O19
I/O23
I/O22
I/O21
I/O20
OE#
A
0-18
I/O0
I/O1
I/O2
CS1#
NC
I/O6
I/O16
I/O17
I/O18
512K X 8
512K X 8
512K X 8
512K X 8
I/O5
I/O3
I/O4
8
8
8
8
11
22
33
44
55
66
I/O0 - 7
I/O8 - 15
I/O16 - 23
I/O24 - 31
May 2006
Rev. 17
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
FIGURE 2 – PIN CONFIGURATION FOR WS512K32-XG4TX1
Top View Pin Description
I/O0-31
A0-18
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
WE#
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
CS1-4
OE#
VCC
#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
Output Enable
Power Supply
Ground
GND
NC
Not Connected
GND
Block Diagram
I/O
8
I/O
9
CS
1
#
CS
2
#
CS
3
#
4
CS #
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
WE#
OE#
A
0-18
512K X 8
512K X 8
512K X 8
512K X 8
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
8
I/O0 - 7
I/O8 - 15
I/O16 - 23
I/O24 - 31
Note 1: Package Not Recommended For New Design
FIGURE 3 – PIN CONFIGURATION FOR WS512K32-XG2UX AND WS512K32-XG2LX
Top View Pin Description
I/O0-31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
A0-18
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60 I/O16
WE1-4
#
I/O0 10
I/O1 11
I/O2 12
I/O3 13
I/O4 14
I/O5 15
I/O6 16
I/O7 17
GND 18
I/O8 19
I/O9 20
I/O10 21
I/O11 22
I/O12 23
I/O13 24
I/O14 25
I/O15 26
59 I/O17
58 I/O18
57 I/O19
56 I/O20
55 I/O21
54 I/O22
53 I/O23
52 GND
51 I/O24
50 I/O25
49 I/O26
48 I/O27
47 I/O28
46 I/O29
45 I/O30
44 I/O31
CS1-4
OE#
VCC
#
Output Enable
Power Supply
Ground
GND
NC
Not Connected
Block Diagram
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
4 4
WE # CS #
OE#
A0-18
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
512K X 8
512K X 8
512K X 8
512K X 8
8
8
8
8
I/O0 - 7
I/O8 - 15
I/O16 - 23
I/O24 - 31
May 2006
Rev. 17
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
Min
-55
-65
-0.5
Max
+125
+150
VCC+0.5
150
Unit
°C
°C
V
CS
H
L
OE
X
WE
X
Mode
Standby
Read
Data I/O
High Z
Power
Standby
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
TSTG
VG
L
H
Data Out
High Z
L
H
H
Out Disable
Write
Active
TJ
°C
V
L
X
L
Data In
Active
VCC
-0.5
7.0
RECOMMENDED OPERATING CONDITIONS
CAPACITANCE
Ta = +25°C
Parameter
Symbol
VCC
VIH
Min
4.5
Max
5.5
Unit
V
Parameter
Symbol
COE
Conditions
Max Unit
Supply Voltage
OE# capacitance
VIN = 0 V, f = 1.0 MHz 50 pF
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
2.2
VCC + 0.3
+0.8
V
WE1-4# capacitance
HIP (PGA)
CWE
VIN = 0 V, f = 1.0 MHz
pF
VIL
-0.5
-55
V
20
50
20
TA
+125
°C
CQFP G4T
CQFP G2U/G2L
CS1-4# capacitance
CCS
CI/O
CAD
VIN = 0 V, f = 1.0 MHz 20 pF
VI/O = 0 V, f = 1.0 MHz 20 pF
VIN = 0 V, f = 1.0 MHz 50 pF
Data I/O capacitance
Address input capacitance
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
Conditions
Units
Min
Max
10
Input Leakage Current
Output Leakage Current
ILI
ILO
VCC = 5.5, VIN = GND to VCC
µA
µA
mA
mA
V
CS# = VIH, OE# = VIH, VOUT = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
10
Operating Supply Current x 32 Mode
Standby Current
I
CC x 32
ISB
660
80
Output Low Voltage
VOL
IOL = 6mA for 15 - 35ns,
0.4
IOL = 2.1mA for 45 - 55ns, VCC = 4.5
Output High Voltage
VOH
IOH = -4.0mA for 15 - 35ns,
2.4
V
IOH = -1.0mA for 45 - 55ns, VCC = 4.5
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
DATA RETENTION CHARACTERISTICS
(Ta = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
Max
5.5
28
Data Retention Supply Voltage
Data Retention Current
VDR
CS ≥ VCC − 0.2V
VCC = 3V
2.0
V
ICCDR1
ICCDR2
mA
mA
Low Power Data Retention Current
(WS512K32L-XXX)
VCC = 3V
16
May 2006
Rev. 17
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tRC
tAA
15
0
17
0
20
0
25
0
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
17
20
25
35
45
55
tOH
tACS
tOE
15
8
17
9
20
10
25
12
35
25
45
25
55
25
1
tCLZ
2
0
2
0
2
0
2
0
4
0
4
0
4
0
1
tOLZ
tCHZ
tOHZ
1
12
12
12
12
12
12
12
12
15
15
20
20
20
20
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle
Symbol
-15
-17 -20 -25
-35
-45
-55
Units
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
15
13
13
10
13
2
17
15
15
11
15
2
20
15
15
12
15
2
25
17
17
13
17
2
35
25
25
20
25
2
45
35
35
25
35
2
55
50
50
25
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tAH
0
2
0
2
0
3
0
4
0
4
5
5
5
5
1
tOW
1
tWHZ
tDH
8
9
11
13
15
20
20
0
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2U, G1U and H1 packages. tAS minimum for the G4T package is 0ns.
FIGURE. 4 – AC TEST CIRCUIT
AC Test Conditions
Parameter
Input Pulse Levels
Typ
Unit
V
IOL
VIL = 0, VIH = 3.0
Current Source
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
5
1.5
1.5
ns
V
V
D.U.T.
eff = 50 pf
VZ ≈ 1.5V
(Bipolar Supply)
C
Notes:
V
Z is programmable from -2V to +7V.
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
V
I
.
IOH
Current Source
May 2006
Rev. 17
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
FIGURE 5 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2, (CS# = OE# = VIL, WE# = VIH
)
READ CYCLE 2 (WE# = VIH)
FIGURE 6 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
FIGURE 7 – WRITE CYCLE - CS# CONTROLLED
WS32K32-XHX
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
May 2006
Rev. 17
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
4.60 (0.181)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)1
Note 1: Package Not
Recommended
For New Design
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
May 2006
Rev. 17
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 528: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2L)
25.15 (0.990) 0.25 (0.010) MAX
5.10 (0.200) MAX
22.36 (0.880) 0.25 (0.010) MAX
0.25 (0.010) 0.10 (0.002)
0.23 (0.009) REF
24.0 (0.946)
0.25 (0.010)
R 0.127
(0.005)
1.37 (0.054) MIN
0.004
2O / 9O
1.01 (0.040)
0.13 (0.005)
1.27 (0.050) TYP
0.38 (0.015) 0.05 (0.002)
20.31 (0.800) REF
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
May 2006
Rev. 17
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
ORDERING INFORMATION
W S 512K 32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M= Military Screened -55°C to +125°C
I = Industrial
-40°C to 85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1 = Ceramic Hex-In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
G2L = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 528)
G4T1 = 40mm Low Profile CQFP (Package 502)
ACCESS TIME (ns)
IMPROVEMENT MARK:
Blank = Standard Power
N = No Connect at pin 21 and 39 in HIP for Upgrades
L = Low Power Data Retention
ORGANIZATION, 512Kx32
User configurable as 1Mx16 or 2Mx8
SRAM
WHITE ELECTRONIC DESIGNS CORP.
Note 1: Package Not Recommended For New Design
May 2006
Rev. 17
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
15ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94611 05HTX
5962-94611 06HTX
5962-94611 07HTX
5962-94611 08HTX
5962-94611 09HTX
5962-94611 10HTX
5962-94611 19HTX
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
68 lead CQFP Low Profile (G4T)1
68 lead CQFP Low Profile (G4T)1
68 lead CQFP Low Profile (G4T)1
68 lead CQFP Low Profile (G4T)1
68 lead CQFP Low Profile (G4T)1
68 lead CQFP Low Profile (G4T)1
5962-94611 05HYX
5962-94611 06HYX
5962-94611 07HYX
5962-94611 08HYX
5962-94611 09HYX
5962-94611 10HYX
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
15ns
68 lead CQFP (G2U)
68 lead CQFP (G2U)
68 lead CQFP (G2U)
68 lead CQFP (G2U)
68 lead CQFP (G2U)
68 lead CQFP (G2U)
66 pin HIP (H1)
5962-94611 05HMX
5962-94611 06HMX
5962-94611 07HMX
5962-94611 08HMX
5962-94611 09HMX
5962-94611 10HMX
5962-94611 19HMX
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
512K x 32 SRAM Module
55ns
45ns
35ns
25ns
20ns
17ns
15ns
68 lead CQFP (G2L)
68 lead CQFP (G2L)
68 lead CQFP (G2L)
68 lead CQFP (G2L)
68 lead CQFP (G2L)
68 lead CQFP (G2L)
66 pin HIP (H1)
5962-94611 05HAX
5962-94611 06HAX
5962-94611 07HAX
5962-94611 08HAX
5962-94611 09HAX
5962-94611 10HAX
5962-94611 19HAX
Note 1: Package Not Recommended For New Design
May 2006
Rev. 17
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
White Electronic Designs
Document Title
512K x 32 SRAM Multi-Chip Package
Revision History
Rev # History
Release Date
Status
Initial
October 1996
January 1997
Preliminary
Preliminary
Change (Pg. 1, 3)
1.1 Change Operation Supply Current from 520mA To 540mA
1.2 Change Data Retention Current from 12mA to 28mA.
Change (Pg. 1, 2, 8, 10, 11)
1.1 Delete G2 Package
November 1997
February 1998
April 1998
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Change (Pg. 1, 9)
1.1 Add SMD Case Outline M for G2T
Change (Pg. 1, 3, 8)
1.1 Remove Low Capacitance package option
Change (Pg. 1, 6, 8)
1.1 Add H1 package
December 1998
March 1999
Change (Pg. 1, 4, 6, 9, 10)
1.1 Remove H2 package
1.2 Change logo to WEDC logo
Rev 2
Change (Pg. 1, 3, 4, 8)
May 1999
Final
1.1 Change status from Preliminary to Final
1.2 Make package descriptions consistent
1.3 Add 15ns as available in Commercial and Industrial Temperatures only.
Rev 4
Rev 5
Rev 6
Change (Pg. 1, 3)
1.1 Change Standby Current (Isb) from 60mA to 80mA Maximum
June 1999
Final
Final
Final
Change (Pg. 1, 2, 3, 4, 7, 8)
1.1 Add G1U package
November 1999
February 2000
Change (Pg. 1, 8)
1.1 Change G1U lead foot length from 0.64mm to 0.84mm Ref
May 2006
Rev. 17
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WS512K32-XXX
White Electronic Designs
Rev 7
Change (Pg. 1, 3, 9)
October 2000
Final
1.1 Change Operating Supply Current from 540mA to 660mA Maximum
1.2 Add Low Power Data Retention Current of 16mA to Data Retention Characteristics table
1.3 Add Low Power Data Retention (L) option to Ordering Information
Rev 8
Rev 9
Change (Pg. 1, 2, 6, 7, 9, 10)
1.1 Change G2T and G4T package status to Not Recommended For New Design
October 2001
Final
Final
Change (Pg. 1, 2, 3, 8, 9, 10)
1.1 Add G1T package
1.2 Remove ‘Hi-Reliability Product’ Title
November 2001
August 2002
Rev 10 Change (Pg. 1, 2, 3, 4, 7, 8, 9, 10, 11)
1.1 Remove G2T package
Final
1.2 Add G2U package
1.3 Remove ‘Package to be Developed’ note for G4T
Rev 11
Change (Pg. 1,2,4,8,10,11,13)
1.1 Change G1U package status to Not Recommended For New Designs
February 2002
Final
Final
Final
Rev 12 Change (Pg. 1,2,3,7,8,10,11,13)
1.1 Add G2L package
May 2003
Rev 13 Change (Pg. 1,2,3,7,8,10,11,13)
1.1 Remove all reference to G1U package
1.2 Remove all reference to G1T package
December 2003
Rev 14 Change (Pg. 1,3,11)
May 2004
Final
Final
1.1 Change IOL to 6mA for 15-35 ns
Rev 15 Change (Pg. 1,4,11)
November 2004
1.1 Add 15ns for Military Temperature
Rev 16 Change (Pg. 1, 6, 11)
1.1 Correct thickness to 0.181"per PCN#140A00143
March 2006
May 2006
Final
Final
Rev 17 Change ( Pg. 1, 2, 11)
1.1 Correct pinout of G4T
1.2 Correct G2L foot length
May 2006
Rev. 17
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
WS512K32-17G2UM
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G4TCA
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 40 X 40 MM, 3.50 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17G4TM
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, 40 X 40 MM, 3.50 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WS512K32-17H1CA
SRAM Module, 512KX32, 17ns, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
MICROSEMI
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