WS512K32V-100G2TIA [MICROSEMI]

Standard SRAM, 512KX32, 100ns, CMOS, CQFP68, 22.40 X 22.40 MM, 4.57 MM HEIGHT, CERAMIC, QFP-68;


型号：	WS512K32V-100G2TIA
厂家：	Microsemi
描述：	Standard SRAM, 512KX32, 100ns, CMOS, CQFP68, 22.40 X 22.40 MM, 4.57 MM HEIGHT, CERAMIC, QFP-68 静态存储器
文件：	总8页 (文件大小：319K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

WS512K32V-XXX

White Electronic Designs

ADVANCED*

512Kx32 SRAM 3.3V MODULE

FEATURES

ꢀ

Access Times of 70, 85, 100, 120ns

Packaging

ꢀ

TTL Compatible Inputs and Outputs

ꢀ

Low Voltage Operation:

• 3.3V 10% Power Supply

Low Power CMOS

• 66-pin, PGA Type, 1.185 inch square, Hermetic

Ceramic HIP (Package 401)

ꢀ

• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880

inch), 4.57mm (0.180") high (Package 510).

Designed to ﬁt JEDEC 68 lead 0.990" CQFJ

footprint

Built-in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation

ꢀ

Weight

WS512K32V-XG2TX - 8 grams typical

WS512K32V-XHX - 13 grams typical

ꢀ

Organized as 512Kx32; User Conﬁgurable as

1024Kx16 or 2Mx8

Commercial, Industrial and Military Temperature

Ranges

* This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

PIN CONFIGURATION FOR WS512K32NV-XHX

Top View

Pin Description

I/O_0-31

A_0-18

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power Supply

Ground

I/O8

I/O9

I/O10

A13

WE2#

CS²#

GND

I/O¹¹

A10

I/O15

I/O24

I/O25

I/O26

VCC

CS4#

WE⁴#

I/O²⁷

I/O31

I/O30

I/O29

I/O28

WE_1-4

I/O14

I/O13

I/O12

OE#

A¹⁸

CS_1-4

OE#

V_CC

GND

Not Connected

A14

A15

A11

Block Diagram

A16

A12

WE1#

I/O⁷

A⁸

WE₁# CS₁#

WE₂# CS₂#

WE₃# CS₃#

WE₄# CS₄#

OE#

A_0-18

A17

VCC

WE3#

CS³#

GND

I/O¹⁹

I/O23

I/O22

I/O21

I/O20

I/O0

I/O1

I/O2

CS1#

I/O6

I/O16

I/O17

I/O18

512K x 8

I/O5

I/O³

I/O4

I/O_0-7

I/O_8-15

I/O_16-23

I/O_24-31

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

FIGURE 2 – PIN CONFIGURATION FOR WS512K32V-XG2TX

Top View Pin Description

I/O_0-31

A_0-18

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power Supply

Ground

68 67 66 65 64 63 62 61

60 I/O₁₆

WE_1-4

I/O₀10

I/O₁11

I/O₂12

I/O₃13

I/O₄14

I/O₅15

I/O₆16

I/O₇17

GND 18

I/O₈19

I/O₉20

I/O₁₀21

I/O₁₁22

I/O₁₂23

I/O₁₃24

I/O₁₄25

I/O₁₅26

CS_1-4

OE#

V_CC

59 I/O₁₇

58 I/O₁₈

57 I/O₁₉

56 I/O₂₀

55 I/O₂₁

54 I/O₂₂

53 I/O₂₃

52 GND

51 I/O₂₄

50 I/O₂₅

49 I/O₂₆

48 I/O₂₇

47 I/O₂₈

46 I/O₂₉

45 I/O₃₀

44 I/O₃₁

GND

Not Connected

Block Diagram

4 4

WE # CS #

OE#

0-18

2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

512K x 8

I/O^0-7

I/O^8-15

I/O^16-23

I/O^24-31

The WEDC 68 lead G2T CQFP

ﬁlls the same ﬁt and function as

the JEDEC 68 lead CQFJ or 68

PLCC. But the G2T has the TCE

and lead inspection advantage

of the CQFP form.

0.940"

TYP

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

ABSOLUTE MAXIMUM RATINGS

TRUTH TABLE

CS#

OE#

WE#

Mode

Standby

Read

Out Disable

Write

Data I/O

High Z

Data Out

High Z

Power

Standby

Active

Parameter

Symbol

T_A

T_STG

V_G

T_J

V_CC

Min

-55

-65

-0.5

Max

+125

+150

V_CC+0.5

150

Unit

°C

Operating Temperature

Storage Temperature

Signal Voltage Relative to GND

Junction Temperature

Supply Voltage

Data In

-0.5

4.6

RECOMMENDED OPERATING CONDITIONS

CAPACITANCE

T_A= +25°C

Parameter

Supply Voltage

Input High Voltage

Input Low Voltage

Operating Temperature (Mil)

Symbol

V_CC

V_IH

Min

3.0

2.2

Max

3.6

V_CC+ 0.3

+0.8

Unit

Parameter

Symbol

C_OE

Conditions

Max Unit

OE# capacitance

V_IN= 0V, f = 1.0 MHz 50 pF

WE_1-4# capacitance

HIP (PGA)

C_WE

V_IN= 0V, f = 1.0 MHz

V_IL

T_A

-0.3

-0.5

°C

+125

CQFP G2U

CS# capacitance

Data# I/O capacitance

Address input capacitance

C_CS

C_I/O

C_AD

V_IN= 0V, f = 1.0 MHz 20 pF

V_I/O= 0V, f = 1.0 MHz 20 pF

V_IN= 0V, f = 1.0 MHz 50 pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS

V_CC= 5.0V, V_SS= 0V, -55°C ≤ T_A≤ +125°C

Parameter

Sym

Conditions

Units

Min

Max

100

2.0

0.4

Input Leakage Current

Output Leakage Current

Operating Supply Current

Standby Current

Output Low Voltage

Output High Voltage

I_LI

I_LO

I_{CC x 32}

I_SB

V_OL

V_OH

V_CC= 3.6, V_IN= GND to V_CC

µA

CS# = V_IH, OE# = V_IH, V_OUT= GND to V_CC

CS# = V_IL, OE# = V_IH, f = 5MHz, V_CC= 3.6

CS# = V_IH, OE# = V_IH, f = 5MHz, V_CC= 3.6

I_OL= 2.1mA, V_CC= 3.0

I_OH= -1.0mA, V_CC= 3.0

2.4

NOTE: DC test conditions: V^IH= VCC -0.3V, VIL = 0.3V.

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

AC CHARACTERISTICS

V_CC= 3.3V, GND = 0V, -55°C ≤ T_A≤ +125°C

Parameter

Symbol

-70

-85

-100

-120

Units

Read Cycle

Min

Max

Min

Max

Min

Max

Min

Max

Read Cycle Time

Address Access Time

t_RC

t_AA

100

120

100

120

Output Hold from Address Change

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output in Low Z

Output Enable to Output in Low Z

Chip Disable to Output in High Z

Output Disable to Output in High Z

t_OH

t_ACS

t_OE

100

120

t_CLZ

t_OLZ

t_CHZ

t_OHZ

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS

V_CC= 3.3V, GND = 0V, -55°C ≤ T_A≤ +125°C

Parameter

Symbol

-70

-85

-100

-120

Units

Write Cycle

Min

Max

Min

Max

Min

100

Max

Min

120

100

Max

Write Cycle Time

t_WC

t_CW

t_AW

t_DW

t_WP

t_AS

Chip Select to End of Write

Address Valid to End of Write

Data Valid to End of Write

Write Pulse Width

Address Setup Time

Address Hold Time

Output Active from End of Write

Write Enable to Output in High Z

Data Hold from Write Time

t_AH

t_OW

t_WHZ

t_DH

1. This parameter is guaranteed by design but not tested.

FIGURE 3 – AC TEST CIRCUIT

AC Test Conditions

Parameter

Input Pulse Levels

Typ

Unit

IOL

V_IL= 0, V_IH= 2.5

Current Source

Input Rise and Fall

1.5

Input and Output Reference Level

Output Timing Reference Level

NOTES:

≈

1.5V

D.U.T.

(Bipolar Supply)

eff = 50 pf

_Zis programmable from -2V to +7V.

_OL& I_OHprogrammable from 0 to 16mA.

Tester Impedance Z₀= 75 Ω.

_Zis typically the midpoint of V_OHand V_OL

_OL& I_OHare adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

IOH

Current Source

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

TIMING WAVEFORM – READ CYCLE

t_RC

ADDRESS

t_AA

t_RC

CS#

ADDRESS

DATA I/O

t_AA

t_CHZ

t_ACS

t_CLZ

t_OH

OE#

PREVIOUS DATA VALID

DATA VALID

t_OE

t_OLZ

t_OHZ

READ CYCLE 1 (CS# = OE# = V , WE# = V

IL IH

)

DATA I/O

DATA VALID

HIGH IMPEDANCE

READ CYCLE 2 (WE# = V

)

WRITE CYCLE – WE# CONTROLLED

t_WC

ADDRESS

t_AW

t_AH

t_CW

CS#

WE#

t_AS

t_WP

t_OW

t_DH

t_WHZ

t_DW

DATA I/O

DATA VALID

WRITE CYCLE 1, WE# CONTROLLED

WRITE CYCLE – CS# CONTROLLED

t_WC

ADDRESS

t_AW

t_AH

t_AS

t_CW

CS#

t_WP

WE#

t_DW

t_DH

DATA I/O

DATA VALID

WRITE CYCLE 2, CS# CONTROLLED

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)

30.1 (1.185) 0.38 (0.015) SQ

PIN 1 IDENTIFIER

SQUARE PAD

ON BOTTOM

25.4 (1.0) TYP

6.22 (0.245)

MAX

3.81 (0.150)

0.13 (0.005)

1.27 (0.050) 0.1 (0.005)

0.76 (0.030) 0.1 (0.005)

2.54 (0.100)

TYP

1.27 (0.050) TYP DIA

15.24 (0.600) TYP

25.4 (1.0) TYP

0.46 (0.018) 0.05 (0.002) DIA

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)

25.15 (0.990) 0.26 (0.010) SQ

4.57 (0.180) MAX

22.36 (0.880) 0.26 (0.010) SQ

0.27 (0.011) 0.04 (0.002)

Pin 1

0.25 (0.010) REF

R 0.25

(0.010)

24.03 (0.946)

0.26 (0.010)

0.19 (0.007)

0.06 (0.002)

1° / 7°

1.0 (0.040)

0.127 (0.005)

23.87

(0.940) REF

DETAIL A

1.27

(0.050)

TYP

SEE DETAIL "A"

0.38 (0.015) 0.05 (0.002)

20.3 (0.800) REF

The WEDC 68 lead G2T CQFP

ﬁlls the same ﬁt and function as

the JEDEC 68 lead CQFJ or 68

PLCC. But the G2T has the TCE

and lead inspection advantage

of the CQFP form.

0.940"

TYP

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WS512K32V-XXX

White Electronic Designs

ADVANCED

ORDERING INFORMATION

W S 512K 32 X V - XXX X X X

LEAD FINISH:

Blank = Gold plated leads

A = Solder dip leads

DEVICE GRADE:

M = Military

-55°C to +125°C

-40°C to +85°C

0°C to +70°C

= Industrial

C = Commercial

PACKAGE TYPE:

H = Ceramic Hex In Line Package, HIP (Package 401)

G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)

ACCESS TIME (ns)

Low Voltage Supply 3.3V 10ꢀ

IMPROVEMENT MARK:

N = No Connect at pin 21 and 39 in HIP for Upgrades

ORGANIZATION, 512Kx32

User conﬁgurable as 1Mx16 or 2Mx8

SRAM

WHITE ELECTRONIC DESIGNS CORP.

February 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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