WV3EG128M72EFSR265D3S [MICROSEMI]
DDR DRAM Module, 128MX72, 0.75ns, CMOS, DIMM-184;
| 型号： | WV3EG128M72EFSR265D3S |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX72, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总13页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED*
1GB – 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
FEATURES
DESCRIPTION
ꢀ
Double-data-rate architecture
The WV3EG128M72EFSR is a 128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eighteen
64Mx8 DDR components in FBGA packages mounted on
a 184 Pin FR4 substrate.
ꢀ
DDR266 and DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Serial presence detect
Power Supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
ꢀ
ꢀ
184 pin DIMM package
PCB height:
• D3: 29.97mm (1.18")
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature options
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
Clock Speed
CL-tRCD-tRP
2.5-3-3
2-2-2
2.5-3-3
March 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
A0-A12
Address input (Multiplexed)
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
1
2
3
4
5
6
7
8
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
47
48
49
50
51
52
53
54
55
56
57
56
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQS8
A0
CB2
VSS
CB3
93
94
95
96
97
VSS
DQ4
DQ5
VCCQ
139
VSS
140 DM8/DQS17
141
142
A10
CB6
VCCQ
CB7
VSS
DQ36
DQ37
VCC
DM0/DQS9 143
CK0#
Clock Input
BA1
98
99
DQ6
DQ7
VSS
NC
NC
144
145
146
147
148
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
DM0-DM8
WE#
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Data-in Mask
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
100
101
102
103
104
105
106
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
NC
149 DM4/DQS13
VCCQ
DQ12
DQ13
150
151
152
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
Write Enable
Power Supply
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
107 DM1/DQS10 153
108
109
110
111
112
113
114
115
116
117
118
VCC
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
154
155
156
157
158
NC
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
159 DM5/DQS14
160
161
162
163
164
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
NC
RESET#
Reset Enable
NC
DQ21
A11
DQ48
DQ49
VSS
NC
NC
119 DM2/DQS11 165
120
121
122
123
124
125
126
127
128
VCC
DQ22
A8
DQ23
VSS
166
167
168
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
169 DM6/DQS15
170
171
172
173
174
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
A6
DQ28
DQ29
VCCQ
DQ25
DQS3
A4
129 DM3/DQS12 175
VCC
130
131
132
133
134
135
136
137
138
A3
DQ30
VSS
DQ31
CB4
CB5
VCCQ
CK0
CK0#
176
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
177 DM7/DQS16
178
179
180
181
182
183
184
DQ62
DQ63
VCCQ
SA0
SA1
SA2
NC
SDA
SCL
VCCSPD
March 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RCS1#
RCS0#
DQS5
DQS0
DM5/DQS14
DM0/DQS9
DM
I/O7
CS# DQS
DM
I/O0
CS# DQS
DM
CS# DQS
CS# DQS
CS# DQS
DM
I/O0
CS# DQS
CS# DQS
CS# DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQS6
DQS1
DM6/DQS15
DM1/DQS10
DM
CS# DQS
DM
CS# DQS
DM
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS7
DQS2
DM6/DQS16
DM2/DQS11
DM
CS# DQS
DM
CS# DQS
DM
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS8
DQS3
DM7/DQS17
DM3/DQS12
DM
CS# DQS
DM
CS# DQS
DM
CS# DQS
DM
CS# DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
DQS4
DM4/DQS13
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
DM
CS# DQS
DM
CS# DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
120
CK0
PLL
CK0#
SERIAL PD
CS0#
RCS0#
RCS1#
RBA0-RBA1
RA0-RA12
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
SCL
WP
R
E
G
I
SDA
CS1#
BA0-BA1
A0-A12
RAS#
A0 A1 A2
BA0-BA1: SDRAMs
A0-A12: SDRAMs
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs
CKE: SDRAMs
WE#: DQRAMs
SA0 SA1 SA2
S
T
E
R
CAS#
CKE0
CKE1
CCSPD
V
SPD
V
CCQ
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
WE#
PCK
PCK#
VCC
RESET#
VREF
VSS
Note: All resistor values are 22Ω unless otherwise indicated.
March 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
VCC, VCCQ
TSTG
PD
-1.0 to 3.6
-55 to +150
18
V
°C
W
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C TA 70°C, VCC = 2.5V ± 0.2V
Parameter
Supply Voltage (for device with nominal VCC of 2.5V)
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (systems)
Input Logic High Voltage
Input Logic Low Voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
Input Leakage Current
Symbol
VCC
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
IL
Min
2.3
2.3
Max
2.3
2.3
Unit
V
V
V
V
V
V
V
V
VCCQ/2-50mV
VREF -0.04
VCCQ/2+50mV
VREF +0.04
VCCQ +0.3
VREF -0.15
VCCQ +0.3
VCCQ +0.6
1.35
VREF +0.15
-0.3
-0.3
0.3
1.15
-2
V
2
5
uA
uA
mA
mA
mA
mA
Output Leakage Current
IOZ
IOH
IOL
IOH
-5
Output High Current (Normal strength driver); VOUT = VTT + 0.84V
Output High Current (Normal strength driver); VOUT = VTT - 0.84V
Output High Current (Half strength driver); VOUT = VTT + 0.45V
Output High Current (Half strength driver); VOUT = VTT - 0.45V
-16.8
16.8
-9
IOL
9
Notes:
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV
margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The
DRAM must accommodate DRAM current spikes on VREF and internal DRAM
noise coupled TO VREF, both of which may result in VREF noise. VREF should be
de-coupled with an inductance of ≤ 3nH.
4. These parameters should be tested at the pin on actual components and may
be checked at either the pin or the pad in simulation. The AC and DC input
specifications are relative to a VREF envelop that has been bandwidth limited to
200MHZ.
5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must
track variations in the dc level of the same.
2.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF, and must track variations
in the DC level of VREF
6. These charactericteristics obey the SSTL-2 class II standards.
3. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A12)
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max
11
11
11
12
11
15
11
15
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CK0#, CK0)
Input Capacitance (CS0#, CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
March 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
DDR333@
CL=2.5
Max
DDR266@
DDR266@
CL=2.5
Max
CL=2
Max
Parameter
Symbol Conditions
IDD0
Units
Operating Current
One device bank; Active - Precharge; tRC=tRC (MIN);
4140
4140
4140
mA
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
4680
4680
4680
mA
Precharge Power-
IDD2P
IDD2F
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
180
180
180
rnA
mA
Down Standby Current
Idle Standby Current
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM.
1620
1620
1620
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
1260
1800
1260
1800
1260
1800
mA
mA
Active Standby Current
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
4770
4590
4770
4590
4770
4590
mA
rnA
IDD4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC (MIN)
CKE 0.2V
7020
180
7020
180
7020
180
mA
mA
mA
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
9090
9000
9000
March 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
DDR333@
CL=2.5
Max
DDR266@
DDR266@
CL=2.5
Max
CL=2
Max
Parameter
Symbol Conditions
IDD0
Units
Operating Current
One device bank; Active - Precharge; tRC=tRC (MIN);
4725
4725
4725
mA
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
5265
5265
5265
mA
Precharge Power-
IDD2P
IDD2F
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
180
180
180
rnA
mA
Down Standby Current
Idle Standby Current
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM.
1930
1930
1930
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
1260
2110
1260
2110
1260
2110
mA
mA
Active Standby Current
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
5355
5535
5355
5175
5355
5175
mA
rnA
IDD4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC (MIN)
CKE 0.2V
7640
455
7605
455
7605
455
mA
mA
mA
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
9675
9585
9585
March 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
March 2005
Rev. 0
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WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
262
265
Parameter
Symbol
tAC
Min
-0.7
0.45
0.45
6
Max
+0.7
0.55
0.55
13
Min
Max
Min
Max
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
-0.75 +0.75 -0.75 +0.75
tCH
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
7.5
0.55
0.55
13
16
16
tCL
Clock cycle time
CL=3
tCK (3)
22
CL=2.5 tCK (2.5)
6
12
7.5
12
7.5
12
22
CL=2
tCK (2)
tDH
7.5
12
7.5
12
10
12
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
0.45
0.45
1.75
-0.6
0.35
0.35
0.5
0.5
14,17
14,17
17
tDS
0.5
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
1.75
1.75
+0.6
-0.75 +0.75 -0.75 +0.75
DQS input high pulse width
0.35
0.35
0.35
0.35
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.4
0.5
0.5
13,14
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
0.2
tCH, tCL
tCH, tCL
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
+0.7
+0.75
+0.75
tLZ
-0.7
0.75
0.75
0.8
-0.75
0.90
0.90
1
-0.75
0.90
0.90
1
tIHf
tISf
6
tIHs
6
tISs
0.8
1
1
6
tIPW
tMRD
tQH
2.2
2.2
2.2
12
15
15
tHP-tQHS
tHP-tQHS
tHP-tQHS
13,14
15
tQHS
tRAS
tRAP
tRC
0.55
0.75
0.75
ACTIVE to PRECHARGE command
42
18
60
72
70,000
45
15
60
75
120,000
45
20
65
75
120,000
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRFC
21
March 2005
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WV3EG128M72EFSR-D3
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ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
262
265
Parameter
Symbol
tRCD
Min
18
Max
Min
20
Max
Min
20
Max
Units
ns
Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRP
18
20
20
ns
tRPRE
tRPST
tRRD
0.9
0.4
12
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
tCK
ns
19
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
0.25
0
tCK
ns
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
7.8
0.4
15
0.6
7.8
0.4
15
0.6
7.8
tCK
ns
Write recovery time
Internal WRITE to READ command delay
Average periodic refresh interval
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tWTR
1
1
1
tCK
μs
tREFI
12
tXSNR
tXSRD
75
75
75
ns
200
200
200
tCK
March 2005
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ADVANCED
Notes
12. The refresh period is 64ms. This equates to an average refresh
rate of 15.625μs (256Mb component) or 7.8125μs (512 Mb
component). However, an AUTO REFRESH command must be
asserted at least once every 140.6μs (256 Mb component) or
70.3μs (512Mb component); burst refreshing or posting by the
DRAM controller greater than eight refresh cycles is not allowed.
1.
All voltages referenced to VSS
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
3.
Outputs are measured with equivalent load:
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
V
TT
50Ω
RReeffeerreennccee
Outpuutt
Point
(VOUT
)
30pF
14. Referenced to each output group: x4 = DQS with DQ0-DQ4.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
5.
6.
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
18.
tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the
slew rate is less than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
19. This maximum value is derived from the referenced test load. In
practice, the values obtained in a typical terminated design may
reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will
prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN)
will prevail over tDQSCK (MIN) + PRE (MAX) condition.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
7.
8.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE 0.3 x VCCQ is
recognized as LOW.
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tREF later.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
9.
The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on tDQSS
.
March 2005
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
WV3EG128M72EFSR335D3
WV3EG128M72EFSR262D3
WV3EG128M72EFSR265D3
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
2.5
2
29.97 (1.18")
29.97 (1.18")
29.97 (1.18")
2
2
2.5
3
3
NOTES:
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above
and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.35 (5.25)
128.95 (5.076)
1.27 +/-0.1
(0.05+/-0.004)
2x 3.00 (2x 0.118)
4x 4.00+/-0.1
(4x 0.157+/-0.004)
1.0 0.05
2x DIA. 2.50 +0.1/-0.00
6.35 (0.25)
(0.039 0.002)
(2x DIA 0.098 + 0.004/-0.00)
2.175 (0.085)
3.80 (0.149)
4.175 (0.164)
92
1
3.99 MAX
(0.157 MAX)
1.80 (0.070)
0.20 0.15
6.35
(0.25)
1.27
(0.008 0.006)
(0.05)
2.50 (0.098)
64.77 (2.55)
49.53 (1.95)
120.65 (4.75)
93
184
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2005
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 128M 72 E F S R xxx D3 x F/G
WEDC
MEMORY
DDR
GOLD
DEPTH
BUS WIDTH
x8
FBGA
2.5V
REGISTERED
SPEED (MHz)
PACKAGE 184 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
F = LEAD-FREE,
G = ROHS COMPLIANT
March 2005
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG128M72EFSR-D3
White Electronic Designs
ADVANCED
Document Title
1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
Revision History
Rev #
History
Release Date Status
Rev 0
Created
3-05
Advanced
March 2005
Rev. 0
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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