WV3HG264M72EEU403D7IMG [MICROSEMI]
DDR DRAM Module, 128MX72, 0.6ns, CMOS, ROHS COMPLIANT, MINI, DIMM-244;
| 型号： | WV3HG264M72EEU403D7IMG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX72, 0.6ns, CMOS, ROHS COMPLIANT, MINI, DIMM-244 动态存储器 双倍数据速率 |
| 文件： | 总11页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL, Mini-DIMM
DESCRIPTION
FEATURES
The WV3HG264M72EEU is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
ꢀ
ꢀ
ꢀ
Unbuffered 244-pin, dual in-line memory module
(Mini-DIMM)
Fast data transfer rates: PC2-6400*, PCS-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
* This product is under development, is not qualified or characterized and is subject to
change without notice.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
CC = VCCQ = 1.8V 0.1V
CCSPD = 1.7V to 3.6V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Programmable burst: Length (4, 8)
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
JEDEC Standard 1.8V I/O (SSTK_18 Compatible)
Gold (Au) edge contacts
Dual Rank
RoHS compliant
Package option
• 244 Pin Mini-DIMM
• PCB – 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
*Consult factory for availability.
May 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Function
Pin No.
1
Symbol
VREF
Pin No.
Symbol
Pin No.
Symbol
Pin No.
184
Symbol
VCCQ
Pin Name
62
A4
123
VSS
A0-A13
BA0,BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DM (0-8)
VCCSPD
VCC
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
2
3
4
5
6
7
8
9
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VCCQ
A2
VCC
VSS
VSS
NC
VCC
A10/AP
BA0
124
125
DQ4
DQ5
VSS
DM0
NC
185
186
A3
A1
VCC
CK0
CK0#
VCC
A0
BA1
VCC
RAS#
VCCQ
CS0#
VCCQ
ODT0
A13
VCC
NC
VSS
DQ36
DQ37
VSS
DM4
NC
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
VSS
Data strobes
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
Data strobes complement
On-die termination control
Clock Inputs, positive line
Clock Enables
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
VCC
WE#
VCCQ
CAS#
VCCQ
CS1#
ODT1
VCCQ
NC
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Data Masks
SPD Power
Voltage Supply
I/O Power
Ground
NC
NC
VSS
NC
NC
VSS
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
VCCQ
VSS
SA0-SA2
SDA
SCL
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
SPD address
SPD Data Input/Output
SPD Clock Input
Input/Output Reference
No connect
VREF
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
NC
NC
VSS
DM6
NC
SA2
NC
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SA0
SA1
VSS
CB6
CB7
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
SDA
SCL
VCCSPD
NC
NC
VCCQ
CKE1
VCC
NC
NC
VCCQ
A12
A9
VCC
A8
VCCQ
CKE0
VCC
NC
NC
VCCQ
A11
A7
VCC
A5
A6
RESET (pin 18) is connected to both OE of the PLL and Reset# of the register .
May 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DQS
DQS#
DQS
DQS#
DQS
DQS#
DQS
DQS#
DM/
RDQS
CS#
DM/
RDQS
CS#
DM/
RDQS
CS#
DM/
RDQS
CS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5#
DM5
DQS1
DQS1#
DM1
DQS
DQS#
DQS
DQS#
DQS
DQS#
DQS
DQS#
DM/
RDQS
CS#
DM/
RDQS
CS#
DM/
RDQS
CS#
DM/
RDQS
CS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DQS
DQS#
DQS
DQS#
DQS
DQS#
DQS
DQS#
DM/
CS#
DM/
CS#
DM/
CS#
DM/
CS#
RDQS
RDQS
RDQS
I/O 0
RDQS
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DQS
DQS#
DQS
DQS#
DQS
DQS#
DQS
DQS#
DM/
CS#
DM/
CS#
DM/
CS#
DM/
CS#
RDQS
RDQS
RDQS
I/O 0
RDQS
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8#
DM8
DQS
DQS#
DQS
DQS#
DM/
RDQS
CS#
DM/
RDQS
CS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
CCSPD
Serial PD
Serial PD
VCC/VCCQ
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SCL
SDA
VREF
WP A0 A1 A2
SA0 SA1 SA2
V
SS
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
CS0#
CS0# : DDR2 SDRAMs
CS1# : DDR2 SDRAMs
CS1#
120
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
BA0-BA1 : DDR2 SDRAMs
A0-A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE0 : DDR2 SDRAMs
CKE1 : DDR2 SDRAMs
ODT0 : DDR2 SDRAMs
ODT1 : DDR2 SDRAMs
CK
CK#
CK
CK#
PLL
NOTE: All resistor values are 22 ohms 5ꢀ unless otherwise specified.
May 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
Max
1.9
Unit
V
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
1.8
0.50 x VCC
VREF
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.51 x VCC
VREF+0.04
3.6
V
VTT
V
VCCSPD
-
V
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
3. CCQ of all IC's are tied to VCC
.
V
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
2.3
V
100
°C
Command/Address,
RAS#, CAS#, WE#,
-90
90
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
CS#, CKE, ODT
-45
45
µA
IL
CK, CK#
-10
-10
-10
-36
10
10
10
36
µA
µA
µA
µA
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
IVREF
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Symbol
CIN1
Min
22
13
13
6
Max
40
22
22
7
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0, CKE1), (ODT0, ODT1)
Input capacitance (CS0#, CS1#)
CIN2
CIN3
Input capacitance (CK0, CK0#)
CIN4
CIN5 (665)
9
11
12
11
12
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
CIN5 (534, 403)
COUT1 (665)
9
9
COUT1 (534, 403)
9
May 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (Commercial)
TOPER
0°C to 85°C
°C
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.300
Max
Unit
V
Input High (Logic 1 ) Voltage
Input Low (Logic 0) Voltage
VREF + 0.300
VREF - 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
—
Unit
V
AC Input High (Logic 1 ) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1 ) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 1 ) Voltage DDR2-667
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF + 0.250
VREF + 0.200
—
V
—
—
VREF - 0.250
VREF - 0.200
V
V
May 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; VCC = +1.8V 0.1V
Symbol Parameter Condition
806
665
534
403
Unit
Operating
one bank
active-
tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid
CC CC
commands; Address bus inputs are SWITCCCHING; Data bus inputs are SWITCHING
ICC0*
1,337 1,292 1,292
mA
TBD
precharge;
Operating
one bank
active-
IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is
CC
CC
ICC1*
HIGH, CS# is HIGH between valid commanCdCs; Address bus inputs are SWITCHING;
1,272 1,227 1,227
mA
mA
TBD
TBD
read-
Data bus inputs are SWITCHING; Data pattern is same as ICC4W.
precharge;
Precharge
power-
All banks idle; tCK = tCK(I ); CKE is LOW; Other control and address bus inputs are
CC
ICC2P**
444
444
444
down
STABLE; Data bus inputs are FLOATING
current;
Precharge
quite
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; DatCaCbus inputs are FLOATING
ICC2Q**
930
840
930
840
930
mA
mA
TBD
TBD
standby
current;
Precharge
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; DatCaCbus inputs are SWITCHING
ICC2N** standby
current;
1,020
Fast PDN Exit
Active
840
516
840
516
840
516
mA
mA
TBD
TBD
All banks open; tCK = tCK(I ), CKE is LOW; Other control
CC
MRS(12) = 0
power-
ICC3P**
and address bus inputs are STABLE; Data bus inputs are
down
current;
Slow PDN Exit
MRS(12) = 1
FLOATING
Active
ICC3N** standby
current;
All banks open; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS#
CC
is HIGH between valid coCmCmands; OthCeCr control and address bus inputs are
1,290 1,200 1,200
1,632 1,452 1,362
1,677 1,497 1,362
3,000 2,820 2,820
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
SWITCHING; Data bus inputs are SWITCHING
Operating All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I
;
)
CC
ICC4W* burst write tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid commands;
CC
CC
current;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;
ICC4R* burst read tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between
CC
CC
CC
current;
valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.
Burst auto tCK = tCK(I ); Refresh command at every tRC(I ) interval; CKE is HIGH; CS# is HIGH
refresh
current;
CC
CC
ICC5**
between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self
refresh
current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus
Normal
ICC6**
144
144
144
inputs are FLOATING; Data bus inputs are FLOATING
Operating
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I ) - 1*tCK(I
;
)
CC
tCK = tCK(I ); tRC = tRC(I ); tRRD = tRRD MIN(I ) = 1*tCK(I ); CKE is HIGH; CS# is HIGCHC
bank
CC
CC
CC
between valid commands; Address bus inputs are STCACBLE during DESELECTs; Data
ICC7*
interleave
read
current;
2,352 2,352 2,352
mA
TBD
bus inputs are SWITCHING
Notes:
CC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
I
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
May 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS
VCC = +1.8V 0.1V
806
665
534
403
Parameter
Symbol
Unit
Min
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
Min
Max
Min
Max
Min
Max
CL=6
CL=5
CL=4
CL=3
tCK(6)
tCK(5)
3000
3750
5000
0.45
0.45
8000
-
-
-
-
ps
ps
ps
tCK
tCK
Clock cycle time
t
CK(4)
8000 3,750 8,000 5,000 8,000
8000 5,000 8,000 5,000 8,000
tCK(3)
tCH
CK high-level width
CK low-level width
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCL
MIN(tCH
,
MIN (tCH
,
MIN (tCH,
tCL)
Half clock period
tHP
ps
TBD
TBD
tCL)
tCL
)
Clock jitter
tJIT
tAC
-125
-450
125
+450
-125
-500
125
+500
-125
-600
125
+600
ps
ps
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
tDS
100
175
0.35
100
225
0.35
150
275
0.35
tDH
tDIPW
tQHS
tCK
ps
340
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
ns
TBD
TBD
TBD
TBD
tQH
- tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
Data valid output window (DVW)
tDVW
DQS input high pulse width
tDQSH
tDQSL
tDQSCK
tDSS
0.35
0.35
-400
0.2
0.35
0.35
-450
0.2
0.35
0.35
-500
0.2
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
+400
240
+450
300
+500
350
tCK
tCK
tDSH
0.2
0.2
0.2
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDQSQ
ps
TBD
TBD
DQS read preamble
tRPRE
tRPST
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
tDQSS
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
Write command to first DQS latching transition
WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK
AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
May 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (continued)
VCC = +1.8V 0.1V
806
Symbol
665
534
403
Parameter
Address and control input pulse width for each input
Unit
Min
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
0.6
200
275
2
54
7.5
15
37.5
45
Max
Min
0.6
250
375
2
55
7.5
15
37.5
45
Max
Min
0.6
250
475
2
55
7.5
15
37.5
45
Max
tIPW
tCK
ps
ps
ps
ns
ns
ns
ns
TBD
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tIS
TBD
tIH
TBD
tCCD
TBD
tRC
TBD
tRRD
TBD
tRCD
TBD
tFAW
37.5
37.5
37.5
TBD
tRAS
70,000
70,000
70,000 ns
TBD
tRTP
7.5
15
7.5
15
7.5
15
ns
ns
ns
ns
ns
ns
tCK
ns
TBD
tWR
TBD
tDAL
tWR + tRP
7.5
tWR + tRP
7.5
tWR + tRP
10
TBD
tWTR
TBD
tRP
15
15
15
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
REFRESH to Active or Refresh to Refresh command interval
Average periodic refresh interval
tRPA
tRP + tCK
2
tRP + tCK
2
tRP + tCK
2
tIS+tCK+tIH
TBD
tMRD
TBD
tDELAY
tIS+ CK+ IH
t
t
tIS+ CK+ IH
t
t
TBD
tRFC
105 70,000 105 70,000 105 70,000 ns
TBD
tREFI
7.8
7.8
7.8
ns
TBD
tRFC(MIN)
+ 10
tRFC(MIN)
+ 10
tRFC(MIN)
+ 10
Exit self refresh to non-READ command
tXSNR
ns
TBD
TBD
Exit self refresh to READ
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tlSXR
tAOND
200
tIS
2
200
tIS
2
200
tIS
2
tCK
ps
tCK
TBD
TBD
TBD
TBD
TBD
2
2
2
TBD
tAC(MAX)
+ 1000
2.5
tAC(MAX)
+ 1000
2.5
tAC(MAX)
+ 1000
2.5
ODT turn-on
tACN
tAC(MIN)
2.5
tAC(MIN)
2.5
tAC(MIN)
2.5
ps
TBD
TBD
TBD
ODT turn-off delay
tAOFD
tCK
TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
ODT turn-off
tAOF
tAC(MIN)
+
tAC(MIN)
+
tAC(MIN)
+
ps
TBD
TBD
TBD
600
600
600
2 x tCK +
tAC(MAX) ps
+ 1000
2 x tCK
tAC(MAX)
+ 1000
+
2 x tCK
tAC(MAX)
+ 1000
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
ODT turn-on (power-down mode)
tAONPD
TBD
2 x tCK
+
2 x tCK +
2 x tCK
+
tAC(MIN) + tAC(MAX) tAC(MIN) + tAC(MAX) tAC(MIN)
2000 + 1000 2000 + 1000 2000
+
ODT turn-off (power-down mode)
tAOFPD
tAC(MAX) ps
+ 1000
TBD
TBD
+1000
+1000
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
tANPD
tAXPD
tXARD
tXARDS
tXP
tCKE
3
8
2
7-AL
2
3
3
8
2
6-AL
2
3
3
8
2
6-AL
2
3
tCK
tCK
tCK
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
May 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D7
Clock Speed/
Data Rate
Part Number
CAS Latency
tRCD
tRP
Height*
WV3HG264M72EEU806D7xxG** 400MHz/800Mb/s
WV3HG264M72EEU665D7xxG** 333MHz/667Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
WV3HG264M72EEU534D7xxG
WV3HG264M72EEU403D7xG
266MHz/533Mb/s
200MHz/400Mb/s
** Contact factory for availability.
NOTES:
• RoHS product. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case“x” in
the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron,
S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D7
FRONT VIEW
3.80 (0.150)
MAX
82.15 (3.234)
81.15 (3.222)
4.10 (0.161)
3.90 (0.154)
2.10 (0.083)
30.15 (1.187)
1.90 (0.075)
29.85 (1.175)
20.0 (0.787)
1.80 (0.071) D
X2
TYP
10.0 (0.394)
TYP
6.0 (0.236)
TYP
0.50 (0.02) R
1.0 (0.039)
TYP
2.0 (0.079)
TYP
PIN 122
PIN 1
1.10 (0.043) MAX
42.90 (1.689)
TYP
78.0 (3.071)
TYP
3.60 (0.142)
FULL R
BACK VIEW
3.80 0.10
(0.150 0.004)
1.30
(0.051)
1.00 0.05
(0.039 0.002)
Detail A
0.25
(0.010) MAX
2.55 (0.100)
3.3 (0.130)
TYP
0.60 TYP
0.45 0.03
(0.018 0.001)
3.6 (0.142) TYP
(0.024)TYP
PIN 244
PIN 123
33.6 (1.323)
38.4 (1.512)
TYP
Detail B
TYP
3.2 (0.126)
TYP
Detail A
Detail B
Tolerances: + /- 0.13 (0.005) unless otherwise specified.
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 64M 72 E E U xxx D7 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH (x8)
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 244 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
May 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D7
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL, Mini-DIMM
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• MICRON: U37Y: B-Die
Revision History
Rev #
History
Release Date Status
Rev 0
Created
May 2006
Advanced
May 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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