WV3HG32M72EEU665PD4GG [MICROSEMI]
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200;
| 型号： | WV3HG32M72EEU665PD4GG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总14页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED*
256MB – 32Mx72 DDR2 SDRAM SO-DIMM UNBUFFERED, w/PLL
FEATURES
DESCRIPTION
Unbuffered 200-pin, Small-Outline DIMM (SO-
DIMM)
The WV3HG32M72EEU is a 32Mx72 Double Data Rate 2
SDRAM memory module based on 256Mb DDR2 SDRAM
components. The module consists of nine 32Mx8, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
Support ECC error detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
V
CC = VCCQ =1.8V ± 0.1V
CCSPD = 1.7V to 3.6V
V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Different clock inputs (CK, CK#)
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Posted CAS# additive latency: 0, 1, 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
RoHS Compliant
Single Rank
JEDEC Proposed pin out
• 200 Pin (SO-DIMM): 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-6400*
400MHz
6-6-6
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
June 2006
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
SYMBOL
A0-A12
BA0, BA1
ODT0
DESCRIPTION
Address input
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VCC
A6
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VSS
VSS
2
Bank Address Inputs
On-Die Termination
Differential Clock Inputs
Check Bits
3
4
5
6
7
8
9
DQ0
DQ4
VSS
DQ5
DQ1
VSS
DQS0#
DM0
DQS0
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
DQ25
DM3
VSS
A5
A4
A3
VCC
A2
A1
VCC
A0
A10/AP
BA1
BA0
VCC
RAS#
WE#
VCC
CS0#
CAS#
ODT0
NC
NC
VCC
VCC
NC
CK
NC
CK#
DQ32
VSS
DQS5#
DM5
DQS5
VSS
CK, CK#
CB0-CB7
CKE0
Clock Enable input
Clock Input
VSS
DQ46
DQ42
DQ47
DQ43
VSS
CK, CK#
CS0#
Chip select
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RAS#, CAS#, WE# Command Inputs
DM0-DM8
DQ0-DQ63
Input Data Masks
Data Input/Output
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
DQS0-DQS8
DQS0#-DQS8#
DQ6
DQ2
DQ7
DQ3
VSS
DQ52
DQ48
DQ53
DQ49
VSS
Data Strobe
SCL
Serial Clock for Presence Detect
Presence Detect Address Inputs
Serial Presence Detect Data
Core Power
SA0-SA1
SDA
VCC
VSS
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
DM6
DQS6#
VSS
DQS6
DQ54
VSS
DQ55
DQ50
VSS
DQ51
DQ60
VSS
DQ61
DQ56
VSS
DQ57
DM7
VSS
DQ62
DQS7#
VSS
DQS7
DQ63
DQ58
SDA
VREF
VSS
SSTL_18 reference voltage
Ground
VCCSPD
NC
Serial EEPROM Power Supply
No Connect
VSS
VSS
CB0
DM8
CB1
VSS
DM1
DQS1#
VSS
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
DQ20
VSS
DQ21
DQ16
VSS
DQ17
RESET#
VSS
DM2
DQS2#
VSS
DQS2
DQ22
VSS
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
DQ36
DQ33
DQ37
DQS4#
VSS
DQS4
DM4
VSS
VSS
CB2
CKE0
CB3
NC
VSS
NC
NC
VCC
NC
A12
VSS
DQ34
DQ38
DQ35
DQ39
VSS
VSS
SCL
DQ59
SA1
VCCSPD
SA0
A11
A9
VCC
A7
VSS
DQ40
DQ44
DQ41
DQ45
DQ23
A8
June 2006
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1#
DQS5#
DQS1
DM1
DQS5
DM5
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
DQ
RDQS
DQ
DQ8
DQ40
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2#
DQS6#
DQS2
DM2
DQS6
DM6
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3#
DQS7#
DQS3
DM3
DQS7
DM7
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ24
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS8#
VCCSPD
VCC
VREF
VSS
Serial PD
DQS8
DM8
Serial PD
WP A0 A1 A2
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SCL
SDA
DM/
CS#
DQS
DQS#
RDQS
DQ
CB0
SA0 SA1
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
CK#
PCK0, PCK4-PCK6, PCK9 -> CK: DDR2 SDRAMs
P
L
L
PCK0#, PCK4#-PCK6#, PCK9# -> CK#: DDR2 SDRAMs
CS#: SDRAMs
CS0#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
BA0-BA1: DDR2 SDRAMs
A0-A12: DDR2 SDRAMs
RAS#: DDR2 SDRAMs
CAS#: DDR2 SDRAMs
WE#: DDR2 SDRAMs
CKE: DDR2 SDRAMs
ODT: DDR2 SDRAMs
CKE0
ODT0
NOTE: 1. All resistor values are 22 ohm unless otherwise specified.
June 2006
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
2.3
100
45
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
°C
μA
Command/Address,
RAS#, CAS#, WE#,
-45
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
IL
CK, CK#
-10
-5
10
5
μA
μA
μA
μA
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
-5
5
IVREF
-18
18
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
1.8
Max
1.9
Unit
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
V
V
V
V
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
3.6
VTT
VCCSPD
-
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
3. CCQ of all IC's are tied to VCC
V
.
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
Min
13
Max
22
22
22
7
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12, BA0~BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0), (ODT0)
Input Capacitance (CS0#)
CIN1
CIN2
13
CIN3
13
Input Capacitance (CK, CK#)
CIN4
6
CIN5 (665)
CIN5 (534, 403)
COUT (665)
COUT (534, 403)
6.5
6.5
6.5
6.5
7.5
8
Input Capacitance (DQS0~DQS8)
7.5
8
Input Capacitance (DQ0~DQ63), (CB0~CB7)
June 2006
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature (Commercial)
TOPER
0ºC to 85ºC
ºC
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIL(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
VREF+ 0.250
VREF+ 0.200
V
V
V
V
VREF - 0.250
VREF + 0.200
June 2006
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
806
665
553
403
Units
ICC0*
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,245
1,200
1,155
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
ICC1*
TBD
1,335
1,290
1,200
mA
Precharge power-down current;
ICC2P* All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
372
570
615
372
525
570
372
525
570
mA
mA
mA
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
TBD
Active power-down current;
Fast PDN Exit MRS(12) = 0
615
435
570
435
570
435
mA
mA
ICC3P** All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1 TBD
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
ICC3N**
ICC4W*
ICC4R*
TBD
TBD
TBD
975
930
885
mA
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
2,190
1,965
1,875
1,740
1,515
1,470
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC5B**
TBD
TBD
1,830
45
1,785
45
1,740
45
mA
mA
Self refresh current;
ICC6**
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
ICC7*
t
CK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
TBD
2,685
2,595
2,595
mA
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
June 2006
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
806
665
553
403
Units
ICC0*
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
858
795
750
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
ICC1*
TBD
939
840
795
mA
Precharge power-down current;
ICC2P* All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
345
570
705
341
525
615
341
480
552
mA
mA
mA
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
TBD
Active power-down current;
Fast PDN Exit MRS(12) = 0
471
345
444
341
417
341
mA
mA
ICC3P** All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1 TBD
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
ICC3N**
ICC4W*
ICC4R*
TBD
TBD
TBD
705
615
570
975
930
mA
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,335
1,290
1,155
1,110
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC5B**
TBD
TBD
1,115
40.5
1,110
40.5
1,065
40.5
mA
mA
Self refresh current;
ICC6**
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
ICC7*
t
CK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
TBD
1,542
1,515
1,425
mA
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note: ICC specification is based on QIMONDA/INFINEON components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
June 2006
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
ps
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
TBD
ps
CK high-level width
CK low-level width
Half clock period
Clock jitter
TBD
TBD
tCK
tCK
ps
tCL
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tHP
MIN(tCH, CL
-125
-450
t
)
MIN(tCH, CL
-125
-500
t
)
MIN(tCH, CL
-125
-600
t
)
tJIT
125
125
125
ps
DQ output access time from CK/CK#
tAC
+450
+500
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
tLZ
TBD
TBD
TBD
TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
ps
Data-out low-impedance window from
CK/CK#
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
DQ and DM input setup time relative to
DQS
tDS
tDH
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
100
225
0.35
100
225
0.35
150
275
0.35
ps
ps
tCK
ps
ps
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
input)
tDIPW
tQHS
tQH
Data hold skew factor
340
400
450
DQ - DQS hold, DQS to first DQ to go
nonvalid, per access
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
-400
0.2
+400
240
-450
0.2
+450
300
-500
0.2
+500
350
tCK
tCK
tDSH
0.2
0.2
0.2
DQ - DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
TBD
TBD
ps
DQS read preamble
tRPRE
tRPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
Write command to first DQS latching
transition
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tDQSS
tIPW
TBD
TBD
TBD
TBD
tCK
tCK
Address and control input pulse width for
each input
0.6
0.6
0.6
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
June 2006
Rev. 3
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
55
MAX
MIN
60
MAX
MIN
55
MAX
UNIT
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tRC
TBD
tRRD
7.5
15
7.5
15
7.5
15
ns
TBD
tRCD
ns
TBD
tFAW
37.5
40
37.5
40
37.5
40
ns
TBD
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRAS
70,000
70,000
70,000
ns
TBD
tRTP
7.5
15
7.5
15
7.5
15
ns
TBD
tWR
ns
TBD
Auto precharge write recovery + precharge
time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
TBD
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
TBD
TBD
TBD
TBD
TBD
tRP
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
tRPA
tRP+tCK
2
tRP+tCK
2
tRP+tCK
2
TBD
tMRD
TBD
tIS+tCK
tIH
tIS+tCK
tIH
tIS+tCK
tIH
CKE low to CK,CK# uncertainty
tDELAY
ns
ns
TBD
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
75
70,000
7.8
75
70,000
7.8
75
70,000
7.8
TBD
Average periodic refresh interval
tREFI
μs
TBD
TBD
TBD
tRFC(MIN)
+10
tRFC(MIN)
+10
tRFC(MIN)
+10
Exit self refresh to non-READ command
tXSNR
ns
TBD
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
200
tIS
200
tIS
200
tIS
tCK
ps
TBD
TBD
TBD
TBD
tISXR
TBD
tAOND
2
2
2
2
2
2
tCK
TBD
tAC(MAX)
+700
tAC(MAX)
+1000
tAC(MAX)
+1000
ODT turn-on
tAON
tAC(MIN)
tAC(MIN)
tAC(MIN)
ps
TBD
TBD
ODT turn-off delay
ODT turn-off
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
TBD
TBD
TBD
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAOF
tAC(MIN)
tAC(MIN)
tAC(MIN)
TBD
2 x tCK
+
2 x tCK
+
2 x tCK+
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ps
ps
TBD
TBD
TBD
2.5 x
2.5 x
2.5 x
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK+
tAOFPD
TBD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
tAXPD
TBD
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
TBD
A Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
CKE minimum high/low time
tCKE
TBD
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
June 2006
Rev. 3
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
ps
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
TBD
ps
CK high-level width
CK low-level width
Half clock period
Clock jitter
TBD
TBD
tCK
tCK
ps
tCL
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tHP
MIN(tCH, CL
-125
-450
t
)
MIN(tCH, CL
-125
-500
t
)
MIN(tCH, CL
-125
-600
t
)
tJIT
125
125
125
ps
DQ output access time from CK/CK#
tAC
+450
+500
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
tLZ
TBD
TBD
TBD
TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
ps
Data-out low-impedance window from
CK/CK#
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
DQ and DM input setup time relative to
DQS
tDS
tDH
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
100
175
0.35
100
225
0.35
150
275
0.35
ps
ps
tCK
ps
ps
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
input)
tDIPW
tQHS
tQH
Data hold skew factor
340
400
450
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
-400
+400
240
-450
+450
300
-500
+500
350
0.2
0.2
0.2
tCK
DQS falling edge from CK rising … hold
time
tDSH
TBD
TBD
TBD
TBD
0.2
0.2
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
Write command to first DQS latching
transition
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tDQSS
tIPW
TBD
TBD
TBD
TBD
tCK
tCK
Address and control input pulse width for
each input
0.6
0.6
0.6
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
* AC specification is based on QIMONDA/INFINEON components. Other DRAM manufactures specification may be different.
Continued on next page
June 2006
Rev. 3
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
55
MAX
MIN
55
MAX
MIN
55
MAX
UNIT
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tRC
TBD
tRRD
7.5
15
7.5
15
7.5
15
ns
TBD
tRCD
ns
TBD
tFAW
37.5
40
37.5
40
37.5
40
ns
TBD
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRAS
70,000
70,000
70,000
ns
TBD
tRTP
7.5
15
7.5
15
7.5
15
ns
TBD
tWR
ns
TBD
Auto precharge write recovery + precharge
time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
TBD
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
TBD
TBD
TBD
TBD
TBD
tRP
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
tRPA
tRP+tCK
2
tRP+tCK
2
tRP+tCK
2
TBD
tMRD
TBD
tIS+tCK
tIH
tIS+tCK
tIH
tIS+tCK
tIH
CKE low to CK,CK# uncertainty
tDELAY
ns
ns
TBD
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
75
70,000
7.8
75
70,000
7.8
75
70,000
7.8
TBD
Average periodic refresh interval
tREFI
μs
TBD
TBD
TBD
tRFC(MIN)
+10
tRFC(MIN)
+10
tRFC(MIN)
+10
Exit self refresh to non-READ command
tXSNR
ns
TBD
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
200
tIS
200
tIS
200
tIS
tCK
ps
TBD
TBD
TBD
TBD
tISXR
TBD
tAOND
2
2
2
2
2
2
tCK
TBD
tAC(MAX)
+700
tAC(MAX)
+1000
tAC(MAX)
+1000
ODT turn-on
tAON
tAC(MIN)
tAC(MIN)
tAC(MIN)
ps
TBD
TBD
ODT turn-off delay
ODT turn-off
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
TBD
TBD
TBD
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAOF
tAC(MIN)
tAC(MIN)
tAC(MIN)
TBD
2 x tCK
+
2 x tCK
+
2 x tCK+
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ps
ps
TBD
TBD
TBD
2.5 x
2.5 x
2.5 x
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK+
tAOFPD
TBD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
tAXPD
TBD
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
TBD
A Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
CKE minimum high/low time
tCKE
TBD
* AC specification is based on QIMONDA/INFINEON components. Other DRAM manufactures specification may be different.
June 2006
Rev. 3
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR PD4
Clock/Data Rate
Frequency
CAS
Latency
Part Number
tRCD
tRP
Height**
WV3HG32M72EEU806PD4xxG*
WV3HG32M72EEU665PD4xxG*
WV3HG32M72EEU534PD4xxG
WV3HG32M72EEU403PD4xxG
* Consult Factory for availability
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (G = Qimonda/Infineon, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR PD4
3.302 (0.130)
MAX
FRONT VIEW
67.75 (2.667) MAX
4.10 (0.161) (2x)
3.90 (0.154)
1.80
(0.071)
(2X)
30.00 (1.181) TYP
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
2.15 (0.085)
1.00 (0.039)
TYP
0.60 (0.024)
TYP
0.45 (0.018)
TYP
1.10 (0.043)
0.90 (0.035)
MAX
PIN 199
PIN 1
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
June 2006
Rev. 3
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 32M 72 E E U xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
DATA RATE (Mb/s)
PACKAGE 200 PIN SO-DIMM
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
(G = Qimonda/Infineon)
G = RoHS COMPLIANT
June 2006
Rev. 3
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3HG32M72EEU-PD4
White Electronic Designs
ADVANCED
Document Title
256Mb – 32Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
DRAM DIE OPTIONS:
• SAMSUNG: F-Die, will move to G-Die Q2'06
• MICRON: U26A: B-Die
• QIMONDA/INFINEON: A-Die
Revision History
Rev #
Rev 0
History
Release Date Status
Created
January 2006
Advanced
Rev 1
May 2006
Advanced
1.0 Update pin-outs to proposed JECED spec
1.1 Added "P" to indicate JECED proposed pin-out
1.2 Added die rev info
1.3 Added VCCSPD voltage specification
1.4 Indicated VCC = VCCQ on all IC's are tied to VCC
Rev 2
Rev 3
May 2006
June 2006
Advanced
Advanced
2.1 Change pin 147 to DQ40
3.1 Added Qimonda/Infineon ICC and AC specifications
3.2 Updated DRAM Die option
June 2006
Rev. 3
14
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
WV3HG32M72EEU665PD4IGG
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU665PD4ISG
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU665PD4MG
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU665PD4SG
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU806D4MG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SODIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU806D4SG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SODIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG32M72EEU806PD4IMG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSEMI
WV3HG32M72EEU806PD4ISG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSEMI
WV3HG32M72EEU806PD4MG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROSEMI
WV3HG32M72EEU806PD4SG
DDR DRAM Module, 32MX72, CMOS, ROHS COMPLIANT, SO-DIMM-200Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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MICROSEMI
WV3HG64M32EEU-D4
256MB - 64Mx32 DDR2 SDRAM UNBUFFEREDWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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