ZL30773 [MICROSEMI]

IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers;


型号：	ZL30773
厂家：	Microsemi
描述：	IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers
文件：	总6页 (文件大小：362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZL30771, ZL30772, ZL30773

IEEE 1588 & Synchronous Ethernet

Packet Clock Network Synchronizers

Product Brief

November 2019

Features

Ordering Information

• One, Two or Three DPLL Channels

ZL30771LFG7 1-Channel 80-lead LGA Trays

ZL30772LFG7 2-Channel 80-lead LGA Trays

ZL30773LFG7 3-Channel 80-lead LGA Trays

• Packet and/or physical-layer frequency, phase

and time synchronization

• Physical-layer compliance with ITU-T G.8262,

G.8261.1, G.813, G.812, Telcordia GR-1244,

GR-253

NiAu (Pb-free)

Package size: 11 x 11 mm



-40 C to +85 C

• Packet-timing compliance with ITU-T G.8261,

G.8263, G.8273.2 (class A, B, C, D), G.8273.4

• Per-output programmable duty cycle

• Enables 5G wireless applications with sub-

• Precise output alignment circuitry and per-

100ns time/phase alignment requirements

output phase adjustment

• Programmable bandwidth, 0.1mHz to 470Hz

• Hitless reference switching and mode switching

• High-resolution holdover averaging

• Per-output enable/disable and glitchless

start/stop (stop high or low)

• Local Oscillator

• Programmable phase slope limit for transients,

• Operates from a single TCXO or OCXO: 23.75-

downto 1 ns/s

25MHz, 47.5-50MHz, 114.285-125MHz

• Per-DPLL phase adjustment, 1ps resolution

• Very-low-jitter applications can connect a TCXO

or OCXO as the stability reference and a low-

jitter XO as the jitter reference

• Input Clocks

• Accepts up to 10 differential or CMOS inputs

• Any input frequency from 0.5Hz to 900MHz

• Per-input activity and frequency monitoring

• Automatic or manual reference switching

• Fast lock to 1 PPS input, <30 seconds

• General Features

• Automatic self-configuration at power-up from

internal Flash memory

• Input-to-output alignment <2ns

• Internal compensation (1ppt) for local oscillator

• Any input can be a 1PPS SYNC input for

frequency error in DPLLs and input monitors

REF+SYNC frequency/phase/time locking

• Numerically controlled oscillator behavior in

• Per-input phase adjustment, 1ps resolution

• Output Clock Frequency Generation

each DPLL and each fractional output divider

• Programmable Time of Day counters

• Any output frequency from <0.5Hz to 1045MHz

• Easy-to-configure design requires no external

(180MHz max for Synth0)

VCXO or loop filter components

• High-resolution fractional frequency conversion

• 7 GPIO pins with many possible behaviors

• SPI or I²C processor Interface

with 0ppm error

• Synthesizers 1 & 2 have integer and fractional

• 1.8V and 3.3V core VDD voltages

dividers to make a total of 5 frequency families

• Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out

• Easy-to-use evaluation/programming software

• Factory programmable power-up configuration

• Output jitter from Synths 1 & 2 is <0.3ps RMS

• Output jitter from fractional dividers is typically

< 1ps RMS, many frequencies <0.5ps RMS

• Each HPOUTP/N pair can be LVDS, LVPECL,

Applications

HCSL, 2xCMOS, HSTL or programable diff.

•

Central system timing ICs for SyncE and/or

IEEE 1588, SONET/SDH, OTN, wireless base

station and other carrier-grade systems

• Four output banks each with VDDO pin; CMOS

output voltages from 1.5V to 3.3V

• Per-synthesizer phase adjust, 1ps resolution

•

G.8262/813 EEC/SEC, Telcordia Stratum 2-4

Microsemi Confidential

ZL30771, ZL30772, ZL30773

Data Sheet

1. Block Diagram

PACKET_REF[2:0]

DIV

GPOUT0

GPOUT1

GP Synthesizer 0

general purpose

DPLL0

REF0P

REF0N

One Diff / Two

Single-Ended

REF1P

REF1N

HPOUT0P

HPOUT0N

One Diff / Two

Single-Ended

IntDiv

DIV

HP Synthesizer 1

low-jitter

DPLL1

DPLL2

HPOUT1P

HPOUT1N

REF2P

REF2N

One Diff / Two

Single-Ended

FracDiv

IntDiv

HPOUT2P

HPOUT2N

REF3P

REF3N

One Diff / Two

Single-Ended

HP Synthesizer 2

low-jitter

HPOUT3P

HPOUT3N

REF4P

REF4N

One Diff / Two

Single-Ended

FracDiv

HPOUT4P

HPOUT4N

HPOUT5P

HPOUT5N

Reference Monitors

& State Machines

HPOUT6P

HPOUT6N

Microprocessor Port

SPI or I2C I/F & GPIO Pins

Master

Clock

Optional x2

HPOUT7P

HPOUT7N

DPLL1 only present on ZL30772 and ZL30773

DPLL2 only present on ZL30773

Figure 1 - Functional Block Diagram

2. Application Example

1.544 or 2.048MHz

TCXO

CMOS to BITS/SSU

to BITS/SSU system

DPLL0

Synth0

T4 path

1 PPS or clock w/ embedded PPS

BITS/SSU

2x 156.25MHz

2x 125MHz

GPS (1PPS)

SyncE signals to

system components

DPLL1

Synth1

Synth2

SyncE

Line

Extracted

Clocks[7:0]

155.52MHz, 161.1328125MHz

or other frequency

25MHz

1 PPS

1588 signals to

system components

DPLL2

1588

Control info from

IEEE 1588 algorithm

Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application

Microsemi Confidential

ZL30771, ZL30772, ZL30773

Data Sheet

3. Detailed Features

3.1 Input Block Features

•

Ten input reference pins; each can accept a CMOS signal or the POS side of a differential pair; or two

can be paired to accept both sides of a differential pair

•

Any input can be a SYNC signal for REF+SYNC frequency/phase/time locking

Input clocks can be any frequency from 0.5Hz up to 900MHz (180MHz max for CMOS inputs)

Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless

Inputs constantly monitored by programmable frequency and single-cycle monitors

Single-cycle monitor can quickly disqualify a reference when measured period is incorrect

Frequency measurement (ppb or Hz) and monitoring (coarse, fine, and frequency-step monitors)

Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs

Input-to-input phase measurement, 1ps resolution

Input-to-DPLL phase measurement, 1ps resolution

Per-input phase adjustment, 1ps resolution

3.2 DPLL Features

•

One, two or three full-featured DPLLs

Very high-resolution DPLL architecture

State machine automatically transitions among freerun, tracking and holdover states

Revertive or nonrevertive reference selection algorithm

Programmable bandwidth from 0.1mHz to 470Hz

Less than 0.1dB gain peaking

Fast frequency/phase/time lock capability for 1PPS or clock+1PPS input references

Programmable phase-slope limiting (PSL)

Programmable frequency rate-of-change limiting (FCL)

Programmable tracking range (i.e. hold-in range)

Truly hitless reference switching and mode switching

•

Physical-to-physical reference switching

Physical-to-packet reference switching

Packet-to-physical reference switching

Packet-to-packet reference switching

•

Per-DPLL phase adjustment, 1ps resolution

High-resolution frequency and phase measurement

Fast detection of input clock failure and transition to holdover mode

High-resolution holdover frequency averaging, better than 0.01ppb when using <10mHz filter

Time-of-Day registers: 48-bit seconds, 32-bit nanoseconds, writeable on input PPS edge

3.3 Synthesizer Features

•

Any-to-any frequency conversion with 0ppm error

Two low-jitter synthesizers (Synth1, Synth2) with very high-resolution fractional scaling (i.e. non-integer

multiplication)

•

Two output dividers per low-jitter synthesizer: one integer (4 to 15 plus half divides 4.5 to 7.5) and one

40-bit fractional

•

One general-purpose synthesizer (Synth0)

A total of five output frequency families

Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter

components

3.4 Low-Jitter Output Clock Features

•

Up to 16 single-ended outputs (up to 8 differential outputs) from Synth1 and Synth2

Each output can be one differential output or two CMOS outputs

Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for CMOS and HSTL outputs)

Output jitter from Synth1 and Synth2 integer dividers is <0.3ps RMS

Microsemi Confidential

ZL30771, ZL30772, ZL30773

Data Sheet

•

Output jitter from fractional dividers is <1ps RMS, many frequencies <0.5ps RMS

In CMOS mode, the HPOUTxN frequency can be an integer divisor of the HPOUTxP frequency

(Example 1: HPOUT3P 125MHz, HPOUT3N 25MHz. Example 2: HPOUT2P 25MHz, HPOUT2N 1Hz)

Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components

Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN

Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components

Can produce PCIe clocks

Sophisticated output-to-output phase alignment

Per-synthesizer phase adjustment, 1ps resolution

Per-output phase adjustment

Per-output duty cycle / pulse width configuration

•

Per-output enable/disable

Per-output glitchless start/stop (stop high or low)

3.5 General-Purpose Output Clock Features

•

Two CMOS outputs from Synth0

Any frequency from 0.5Hz to 180MHz

Output jitter is typically 20-30ps

Useful for applications where the component or system receiving the signal has low bandwidth such as

a central timing IC

•

Can output a clock signal with embedded PPS (ePPS) (duty cycle distortion indicates PPS location)

3.6 Local Oscillator

•

Operates from a single TCXO or OCXO. Acceptable frequencies: 23.75MHz to 25MHz, 47.5MHz to

50MHz, 114.285MHz to 125MHz. Best jitter: 48MHz.

Very-low-jitter applications can connect a TCXO or OCXO (any frequency, any output jitter) as the

stability reference and a low-cost low-jitter XO as the jitter reference

This ability to have separate jitter and stability references greatly reduces the cost of the TCXO or

OCXO (no jitter requirement, no high-frequency-requirement) and allows reuse of already-qualified

TCXO and OCXO components

•

Supports redundant TCXOs connected to two REF pins

3.7 General Features

•

Automatic self-configuration at power-up from internal Flash memory

Input-to-output alignment <200ps with external feedback

Fast REF+SYNC locking for frequency and 1PPS phase alignment with lower-cost oscillator

Generates output SYNC signals: 1PPS (IEEE 1588), 2kHz or 8kHz (SONET/SDH) or other frequency

JESD204B clocking: device clock and SYSREF signal generation with skew adjustment

Internal compensation for local oscillator frequency error in DPLLs and input monitors, 1ppt resolution

Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency or

fractional output divider frequency with resolution better than 0.005ppt

•

Spread-spectrum modulation available in each fractional output divider (PCIe compliant)

Seven general-purpose I/O pins each with many possible status and control options

SPI or I²C serial microprocessor interface

3.8 Evaluation Software

•

Simple, intuitive Windows-based graphical user interface

Supports all device features and register fields

Makes lab evaluation of the device quick and easy

Generates configuration scripts to be stored in internal Flash memory

Generates full or partial configuration scripts to be run on a system processor

Works with or without an evaluation board

Microsemi Confidential

ZL30771, ZL30772, ZL30773

Data Sheet

4. Package Outline Drawing

SYM

COMMON DIMENSIONS

MIN

---

NOR.

---

0.21

0.54

0.25

0.4

1.65

0.5

1.8

9.5

0.25

0.9

---

MAX.

0.9

TOTAL THICKNESS

SUBSTRATE THICKNESS

MOLD THICKNESS

REF

BSC

0.3

0.45

1.7

BODY SIZE

LEAD WIDTH

LEAD LENGTH

EP WIDTH

EP LENGTH

LEAD PITCH

EP PITCH

0.2

0.35

1.6

SD1

SE1

1.6

BSC

LEAD COUNT

EP COUNT

BSC

---

EDGE LEAD CENTER TO CENTER

BODY CENTER TO CENTER LEAD

BODY CENTER TO CENTER EP

PRE-SOLDER

---

PACKAGE EDGE TOLERANCE

MOLD FLATNESS

COPLANARITY

aaa

bbb

ddd

0.1

0.08

Microsemi Confidential

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ZL30773 [MICROSEMI]

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