AS1419AF-IT
更新时间：2024-09-18 18:36:41
品牌：MICROSS
描述：ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, FP-28
概述
数据手册AS1419AF-IT 概述
ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, FP-28
AS1419AF-IT 数据手册
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PDF下载ADC
AS1419
Austin Semiconductor, Inc.
14 Bit, 800ksps Sampling
AS1419A
PIN ASSIGNMENT
A/D Converter with Shutdown
(Top View)
FEATURES
• Sample Rate: 800ksps
28-Pin Flat Pack (F)
• Power Dissipation: 150mW
• 81.5dB S/(N+D) and 93dB THD
• No Missing Codes
+AIN
-AIN
VREF
1
2
3
4
5
6
7
8
9
28 AVDD
27 DVDD
26 VSS
REFcomp
AGND
D13
25 BUSY\
• No Pipeline Delay
24 CS\
• Nap and Sleep Shutdown Modes
• Operates with 2.5V Internal 15ppm/°C Reference or
External Reference
23 CONVST\
22 RD\
21 SHDN\
20 D0
D12
D11
D10
• True Differential Inputs Reject Common Mode Noise
• 20MHz Full-Power Bandwidth Sampling
• Bipolar Input Range: ±2.5V
• 28-pin LCC and Flatpack packages
D9 10
D8 11
19 D1
18 D2
D7 12
17 D3
D6 13
16 D4
DGND 14
15 D5
OPTIONS
• Package(s)
28-Pin Flat-pack
28-Pin LCC
MARKING
28-Pin LCC (ECA)
F
ECA
• Operating Temperature Ranges
Extended Temperature (-55oC to +125oC)
Industrial Temperature (-40°C to +85°C)
Military Processing (-55°C to +125°C)
Space Processing (-55oC to +125oC)
4
3
2
28 27 26
25
AGND
D13
D12
D11
D10
D9
BUSY\
CS\
CONVST\
RD\
SHDN\
D0
D1
5
1
XT
IT
MIL
SPACE
6
7
8
9
10
11
24
23
22
21
20
19
D8
12 13 14 15 16 17 18
GENERAL DESCRIPTION
The AS1419 is a 1ms, 800ksps, 14-bit sampling A/D
converter that draws only 150mW from ±5V supplies. This
easy-to-use device includes a high dynamic range sample-and-
hold and a precision reference. Two digitally selectable power
shutdown modes provide flexibility for low power systems.
The AS1419 has a full-scale input range of ±2.5V.
Outstanding AC performance includes 81.5dB S/(N + D) and
93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB THD
at the Nyquist input frequency of 400kHz.
Typical applications are telecommunications, digital
signal processing, multiplexed data acquisition systems, high
speed data acquisitions, spectrum analysis, and imaging
systems.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows users to
eliminate ground loops and common mode noise by measuring
signals differentially from the source.
TheADC has a microprocessor compatible, 14-bit parallel
output port. There is no pipeline delay in the conversion
results. A separate convert start input and data ready signal
(BUSY\) ease connections to FIFOs, DSPs and
microprocessors.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
1
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
1,2
AVDD = VDD = DVDD
SupplyVoltage (VDD)........................................................................6V
Negative SupplyVoltage (VSS)....................................................-6V
Total SupplyVoltage (VDD toVSS)................................................12V
Analog InputVoltage3...........................(VSS - 0.3V) to (VDD + 0.3V)
Digital InputVoltage4...........................................(VSS - 0.3V) to 10V
*Stresses at or greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operation section of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods will affect reliability.
Digital OutputVoltage...........................(VSS - 0.3V) to (VDD + 0.3V)
Power Dissipation....................................................................500mW
Operating Temperature Range
Military........................................................-55°C to +125°C
Industrial.......................................................-40°C to +85°C
StorageTemperature Range .....................................-65°C to +150°C
LeadTemperature (soldering, 10s) .........................................+300°C
COVERTED CHARACTERISTICS (* denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA =
+25°C. With Internal Reference5,6)
AS1419
AS1419A
PARAMETER
MIN TYP MAX MIN TYP MAX UNITS
CONDITIONS
Resolution (No Missing Codes)
Integral Linearity Error7
Differential Linearity Error
Offset Error8
*
*
*
*
13
14
Bits
±0.8
±0.6 ±1.25 LSB
±0.7 ±2
±5 ±1.5
±0.5 ±1
LSB
±5 ±20 LSB
Internal Reference
External Reference = 2.5V
±10 ±20
±5 ±60
±10 ±60 LSB
Full-Scale Error
±5
LSB
Full Scale Tempco
IOUT(REF) = 0
±15
±15
ppm/°C
ANALOG INPUT (* denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = +25°C.5)
PARAMETER
CONDITIONS
4.75V < V < 5.25V, -5.25V < V < -4.75V *
SYM MIN TYP MAX UNITS
9
V
±2.5
V
DD
SS
IN
Analog Input Range
Analog Input Leakage Current
Analog Input Capacitance
CS\ = HIGH
*
*
I
±1
µA
pF
pF
ns
ns
IN
Between Conversions
During Conversions
C
C
15
5
IN
IN
Sample-and-Hold Acquisition Time
t
90
-1.5
2
300
ACQ
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
t
AP
t
ps
RMS
jitter
-2.5V < (-A = A ) < 2.5V
CMRR
60
dB
IN
IN
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
2
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
DYNAMIC ACCURACY (* denotes specifications which apply over the full
operating temperature range, otherwise specifications are TA = +25°C.)5
PARAMETER
CONDITIONS
100kHz Input Signal
390 kHz Input Signal
SYM
MIN TYP MAX UNITS
*
*
*
*
*
S/(N + D) 78 81.5
S/(N + D)
THD
THD
SFDR
dB
dB
dB
dB
dB
Signal-to(Noise + Distortion) Ratio
80.0
-93 -86
-86
100kHz Input Signal, First 5 Harmonics
390 kHz Input Signal, First 5 Harmonics
100KHz Input Signal
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
-95 -86
f
= 29.37kHz, f = 32.446kHz
IN2
IMD
-86
dB
IN1
Full-Power Bandwidth
Full-Linear Bandwidth
20
1
MHz
MHz
S/(N + D) > 77dB
5
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
CONDITIONS
SYM
MIN TYP MAX UNITS
Output Voltage
I
= 0
= 0
V
V
V
V
2.480 2.500 2.520
V
ppm/°C
LSB/V
kΩ
OUT
REF
REF
REF
REF
Output Tempco
Line Regulation
Output Resistance
Output Voltage
I
±15
0.05
2
OUT
4.75V < V < 5.25V, -5.25V < V < -4.75V
DD
SS
-0.1mA < | I
| < 0.1mA
OUT
I
= 0
REFcomp
4.06
V
OUT
DIGITAL INPUTS AND DIGITAL OUTPUTS (* denotes specifications which
apply over the full operating temperature range, otherwise specifications are
TA = +25°C.)5
PARAMETER
CONDITIONS
SYM
MIN
TYP
MAX
UNITS
High Level Input Voltage
V
V
= 5.25V
= 4.75V
*
*
*
V
V
2.4
V
DD
DD
IH
IL
Low Level Input Voltage
Digital Input Current
0.8
V
V
= 0V to V
I
IN
±10
µA
pF
IN
DD
Digital Input Capacitance
C
5
IN
V
V
= 4.75V
DD
DD
High Level Output Voltage
Low Level Output Voltage
I
= -10µA
V
V
4.5
V
V
O
OH
OL
I
O
= -200µA
*
4.0
= 4.75V
I
= 160µA
= 1.6mA
0.05
0.10
V
O
I
O
*
*
*
0.4
±10
15
V
High-Z Output Leakage D13 to D0
High-Z Output Capacitance D13 to D0
Output Source Current
V
= 0V to V , CS\ High
DD
I
µA
pF
mA
mA
OUT
OZ
9
C
OZ
SOURCE
CS\ High
V
= 0V
I
-10
10
OUT
Output Sink Current
V
= V
I
SINK
OUT
DD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
3
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
POWER REQUIREMENTS (* denotes specifications which apply over the full
operating temperature range, otherwise specifications are
TA = +25°C.)5
PARAMETER
CONDITIONS
SYM MIN TYP MAX UNITS
10
V
V
4.75
4.75
5.25
V
V
DD
SS
Positive Supply Voltage
10
-5.25
20
Negative Supply Voltage
*
*
*
11
1.2
250
19
100
1
mA
mA
µA
mA
mA
µA
mW
mW
mW
Positive Supply Current
I
Nap Mode: SHDN\ = 0V, CS\ = 0V
Sleep Mode: SHDN\ = 0V, CS\ = 5V
DD
30
Negative Supply Current
Power Dissipation
I
SS
Nap Mode: SHDN\ = 0V, CS\ = 0V
Sleep Mode: SHDN\ = 0V, CS\ = 5V
150 240
7.5 12
1.2
P
Nap Mode: SHDN\ = 0V, CS\ = 0V
Sleep Mode: SHDN\ = 0V, CS\ = 5V
DIS
TIMING CHARACTERISTICS (* denotes specifications which apply over the
full operating temperature range, otherwise specifications are
TA = +25°C.)5
PARAMETER
CONDITIONS
SYM
MIN TYP MAX UNITS
Maximum Sampling Frequency
*
*
*
*
*
*
f
800
kHz
ns
ns
ns
ns
ns
ns
ns
ns
SAMPLE(MAX)
Conversion Time
t
950 1150
90 300
CONV
Acquisition Time
t
ACQ
ACQ + CONV
Acquisition + Conversion Time
t
1040 1250
9,10
t
t
t
t
t
0
1
2
3
4
5
CS\ to RD\ Setup Time
9,10
40
40
CS\ to CONVST\ Setup Time
9,10
CS\ to SHDN\ Setup Time
10
400
SHDN\ to CONVST\ Wake-up Time
10,11
*
*
40
CONVST\ Low Time
C = 25pF
20
50
50
ns
ns
ns
ns
ns
L
CONVST\ to BUSY\ Delay
Data Ready Before BUSY\
t
t
6
7
20
15
40
*
*
10
t
t
8
9
Delay Between Conversions
9
*
-5
ns
Wait Time RD\ After BUSY\
C = 25pF
15
20
10
25
35
35
50
20
ns
ns
ns
ns
ns
L
*
*
Data Access Time After RD\
Bus Relinquish Time
t
t
10
11
C = 100pF
L
0°C < T < 70°C
*
*
*
*
25
30
ns
ns
ns
ns
A
-40°C < T < 85°C
A
RD\ Low Time
t
t
t
10
12
13
CONVST\ High Time
40
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
4
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
N O T E S :
1. Absolute Maximum Ratings are those values beyond which
the life of a device may be impaired.
2.All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
7. Integral nonlinearity is defined as the deviation of a code
from a straight line passing through the actual endpoints of the
transfer curve. The deviation is measured from the center of
the quantization band.
8. Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
9. Guaranteed by design, not subject to test.
10. Recommended operating conditions.
11. The falling edge of CONVST\ starts a conversion. If
CONVST\ returns high at a critical point during the conversion
it can create small errors. For best performance ensure that
CONVST\ returns high either within 650ns after the start of the
conversion or after BUSY\ rises.
3. When these pin voltages are taken below VSS or above VDD
,
they will be clamped by internal diodes. This product can handle
input currents greater than 100mA below VSS or above VDD
without latchup.
4. When these pin voltages are taken below VSS, they will be
clamped by internal diodes. This product can handle input
currents greater than 100mA below VSS without latchup. These
pins are not clamped to VDD
.
5. VDD = 5V, VSS = –5V, fSAMPLE = 800kHz, tr = tf = 5ns unless
otherwise specified.
6. Linearity, offset and full-scale specifications apply for a single
ended +AIN input with – AIN grounded.
FUNCTIONAL BLOCK DIAGRAM
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
5
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
TYPICAL PERFORMANCE CHARACTERISTICS
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
6
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuit for Access timings
PIN FUNCTIONS
+AIN (Pin 1): ±2.5V PositiveAnalog Input.
–AIN (Pin 2): ±2.5V NegativeAnalog Input.
CONVST\ (Pin 23): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
VREF (Pin 3): 2.5V Reference Output. Bypass toAGND with CS\ (Pin 24): Chip Select. The input must be low for theADC to
1µF.
recognize CONVST\ and RD\ inputs. CS\ also sets the
REFCOMP(Pin 4): 4.06V Reference Output. Bypass toAGND shutdown mode when SHDN goes low. CS\ and SHDN\ low
with 10?F tantalum in parallel with 0.1µF or 10µF ceramic.
AGND (Pin 5): Analog Ground.
select the quick wake-up nap mode. CS\ high and SHDN\ low
select sleep mode.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The BUSY\ (Pin 25): The BUSY\ output shows the converter
output format is 2’s complement.
status. It is low when a conversion is in progress. Data valid on
DGND (Pin 14): Digital Ground for Internal Logic. Tie toAGND. the rising edge of BUSY\.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The
output format is 2’s complement.
SHDN\ (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
RD\ (Pin 22): Read Input. This enables the output drivers when
CS is low.
AS1419 & AS1419A
Rev. 0.1 1/04
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
DVDD (Pin 27): 5V Positive Supply. Short to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass toAGND with 10µF
tantalum in parallel with 0.1µF or 10µF ceramic.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
DYNAMIC PERFORMANCE
CONVERSION DETAILS
TheAS1419 has excellent high speed sampling capability.
FFT (Fast Fourier Transform) test techniques are used to test
theADC’s frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, theADC’s
spectral content can be examined for frequencies outside the
fundamental. Figure 2 shows a typicalAS1419 FFT plot.
The AS1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an analog
signal to a 14-bit parallel output. The ADC is complete with a
precision reference and an internal clock. The control logic
provides easy interface to microprocessors and DSPs (please
refer to Digital Interface section for the data format).
Conversion start is controlled by the CS\ and CONVST\
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion cycle
has begun, it cannot be restarted.
FIGURE 1: Simplified Block Diagram
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the most
significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +AIN and –AIN inputs are connected
to the sample-and-hold capacitors (CSAMPLE) during the
acquire phase and the comparator offset is nulled by the zero-
ing switches. In this acquire phase, a minimum delay of 200ns
will provide enough time for the sample-and-hold capacitors to
acquire the analog signal. During the convert phase, the
comparator zeroing switches open, putting the comparator into
compare mode. The input switches the CSAMPLE capacitors to
ground, transferring
the differential analog input charge onto the summing junction.
This input charge is successively compared with the binary
weighted charges supplied by the differential capacitive DAC.
Bit decisions are made by the high speed comparator. At the
end of a conversion, the differential DAC output balances the
+AIN and –AIN input charges. The SAR contents (a 14-bit data
word) which represents the difference of +AIN and –AIN are
loaded into the 14-bit output latches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
8
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
Signal-to-Noise Ratio
Total Harmonic Distortion
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited to
frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with a
800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is expressed
as:
Effective Number of Bits
where V1 is the RMS amplitude of the fundamental frequency
and V2 through Vn are the amplitudes of the second through
nth harmonics. THD vs Input Frequency is shown in Figure 4.
TheAS1419 has good distortion performance up to the Nyquist
frequency and beyond.
The effective number of bits (ENOBs) is a measurement of
the resolution of anADC and is directly related to the S/(N + D)
by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling rate of
800kHz, the AS1419 maintains near ideal ENOBs up to the
Nyquist input frequency of 400kHz (refer to Figure 3).
FIGURE 4: Distortion vs. Input Frequency
FIGURE 3: Effective Bits and Signal/
(Noise+Distortion) vs. Input Frequency
FIGURE 5: Intermodulation Distortion
Plot
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
9
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
then the AS1419 inputs can be driven directly. As source
impedance increases so will acquisition time (see Figure 6). For
minimum acquisition time with high source impedance, a buffer
amplifier should be used. The only requirement is that the
amplifier driving the analog input(s) must settle after the small
current spike before the next conversion starts (settling time
must be 200ns for full throughput rate).
Intermodulation Distortion
If theADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can pro-
duce intermodulation distortion (IMD) in addition to THD. IMD
is the change in one sinusoidal input caused by the presence of
another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc. For
example, the 2nd order IMD terms include (fa + fb). If the two
input sine waves are equal in magnitude, the value (in decibels)
of the 2nd order IMD products can be expressed by the
following formula:
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value is
expressed in decibels relative to the RMS value of a full-scale
FIGURE 6: tACQ vs. Source Resistance
Input Filtering
input signal.
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to the
AS1419 noise and distortion. The small-signal bandwidth of
the sample-and-hold circuit is 20MHz. Any noise or distortion
products that are present at the analog inputs will be summed
over this entire bandwidth. Noisy input circuitry should be
filtered prior to the analog inputs to minimize noise. A simple
1-pole RC filter is sufficient for many applications. For example,
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by
3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits). The
AS1419 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far beyond
Nyquist.
Figure 7 shows a 1000pF capacitor from +AIN to ground and a
Driving the Analog Input
The differential analog inputs of the AS1419 are easy to
drive. The inputs may be driven differentially or as a singleended
input (i.e., the –AIN input is grounded). The +AIN and –AIN
inputs are sampled at the same instant. Any unwanted signal
that is common mode to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging the
sample-and-hold capacitors at the end of conversion. During
conversion, the analog inputs draw only a small leakage
current. If the source impedance of the driving circuit is low,
FIGURE 7: RC Input Filter
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
10
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
100Ω source resistor to limit the input bandwidth to 1.6MHz.
The 1000pF capacitor also acts as a charge reservoir for the
input sample-and-hold and isolates the ADC input from
sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can also
generate distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors are
much less susceptible to both problems.
Input Range
The ±2.5V input range of theAS1419 is optimized for low
noise and low distortion. Most op amps also perform well over
this same range, allowing direct coupling to the analog inputs
and eliminating the need for special translation circuitry.
Some applications may require other input ranges. The
AS1419 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
FIGURE 8a: AS1419 Reference Circuit
Internal Reference
The AS1419 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory trimmed
to 2.500V. It is connected internally to a reference amplifier and
is available at VREF (Pin 3) see Figure 8a.A2k resistor is in series FIGURE 8b: Using an External Reference
with the output so that it can be easily overdriven by an exter-
nal reference or other circuitry, see Figure 8b. The reference
amplifier gains the voltage at the VREF pin by 1.625 to create the
required internal reference voltage. This provides buffering
between the VREF pin and the high speed capacitive DAC. The
reference amplifier compensation pin (REFCOMP, Pin 4) must
be bypassed with a capacitor to ground. The reference
amplifier is stable with capacitors of 1µF or greater. For the best
noise performance, a 10µF ceramic or 10µF tantalum in parallel
with a 0.1µF ceramic is recommended.
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the peak
input signal amplitude may vary. The input span of the ADC
can then be adjusted to match the peak input signal, maximizing
the signal-to-noise ratio. The filtering of the internal AS1419
FIGURE 9: Driving VREF with a DAC
reference amplifier will limit the bandwidth and settling time of
this circuit. Asettling time of 5ms should be allowed for after a
reference adjustment.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
11
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
Differential Inputs
Full-Scale and Offset Adjustment
The AS1419 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
Figure 11a shows the ideal input/output characteristics
for the AS1419. The code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB, – FS + 1.5LSB,
–FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s
complement binary with 1LSB = FS – (– FS)/16384 = 5V/16384 =
305.2µV. In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset error
must be adjusted before full-scale error. Figure 11b shows the
extra components required for full-scale error adjustment. Zero
offset is achieved by adjusting the offset applied to the –AIN
convert the difference of +AIN – (–AIN) independent of the
common mode voltage (see Figure 11a). The common mode
rejection holds up to extremely high frequencies, see Figure
10a. The only requirement is that both inputs can not exceed
theAVDD orAVSS power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage. Dynamic
performance is also affected by the common mode voltage.
THD will degrade as the inputs approach either power supply
rail, from 86dB with a common mode of 0V to 76dB with a
common mode
input. For zero offset error, apply –152µV (i.e., – 0.5LSB) at +AIN
and adjust the offset at the –AIN input until the output code
flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For
full-scale adjustment, an input voltage of 2.499544V (FS/2 –
1.5LSBs) is applied to +AIN and R2 is adjusted until the output
code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.
of 2.5V or – 2.5V. Differential inputs allow greater flexibility for
accepting different input ranges. Figure 10b shows a circuit
that converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
12
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
BOARD LAYOUT AND GROUNDING
leads to +AIN (Pin 1) and –AIN (Pin 2) should be kept as short as
possible. In applications where this is not possible, the +AIN
and –AIN traces should be run side by side to equalize
coupling.
Wire wrap boards are not recommended for high
resolution or high speed A/D converters. To obtain the best
performance from theAS1419, a printed circuit board with ground
plane is required. Layout should ensure that digital and analog
signal lines are separated as much as possible. Particular care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.The analog input
should be screened by AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC. Pin
5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other
analog grounds should be connected to this single analog
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins as
shown in the Typical Application on the fist page of this data
sheet. Surface mount ceramic capacitors provide excellent by-
passing in a small board space. Alternatively, 10µF tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
ground point. The REFCOMP bypass capacitor and the DVDD
bypass capacitor should also be connected to this analog possible. The traces connecting the pins and the bypass
ground plane. No other digital grounds should be connected capacitors must be kept short and should be made as wide as
to this analog ground plane. Low impedance analog and digital possible.
power supply common returns are essential to low noise
operation of theADC and the foil width for these tracks should
DIGITAL INTERFACE
be as wide as possible. In applications where the ADC data
outputs and control signals are connected to a continuously
active microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough from
the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate theADC data bus. The traces
connecting the pins and bypass capacitors must be kept short
and should be made as wide as possible.
The A/D converter is designed to interface with
microprocessors as a memory mapped device. The CS\ and RD\
control inputs are common to all peripheral memory interfacing.
A separate CONVST\ is used to initiate a conversion.
Internal Clock
TheA/D converter has an internal clock that eliminates the
need of synchronization between the external clock and the CS\
and RD\ signals found in other ADCs. The internal clock is
factory trimmed to achieve a typical conversion time of 0.95µs
and a maximum conversion time over the full operating
temperature range of 1.15µs. No external adjustments are
required. The guaranteed maximum acquisition time is 300ns. In
addition, a throughput time of 1.25µs and a minimum sampling
rate of 800ksps are guaranteed.
The AS1419 has differential inputs to minimize noise
coupling. Common mode noise on the +AIN and –AIN leads will
be rejected by the input CMRR. The –AIN input can be used as
a ground sense for the +AIN input; the AS1419 will hold and
convert the difference voltage between +AIN and –AIN. The
FIGURE 12: Power Supply Grounding Practice
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
13
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
conversion. The data outputs are always enabled and data can
be latched with the BUSY\ rising edge. Mode 1a shows
operation with a narrow logic low CONVST\ pulse. Mode 1b
shows a narrow logic high CONVST\ pulse.
In mode 2 (Figure 18), CS is tied low. The falling edge of the
CONVST\ signal again starts the conversion. Data outputs are
in three-state until read by the MPU with the RD\ signal. Mode
2 can be used for operation with a shared MPU databus.
In slow memory and ROM modes (Figures 19 and 20), CS\
is tied low and CONVST\ and RD\ are tied together. The MPU
starts the conversion and reads the output with the RD\ signal.
Conversions are started by the MPU or DSP (no external sample
clock).
In slow memory mode, the processor applies a logic low
to RD\ (= CONVST\), starting the conversion. BUSY\ goes low,
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on
the data outputs; BUSY\ goes high, releasing the processor
and the processor takes RD\ (= CONVST\) back high and reads
the new conversion data.
In ROM mode, the processor takes RD\ (= CONVST\) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can read
the new result and initiate another conversion.
Power Shutdown
The AS1419 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap mode
reduces the power by 95% and leaves only the digital logic and
reference powered up. The wake-up time from nap to active is
400ns. In sleep mode, the reference is shut down and only a
small current remains, about 250µA. Wake-up time from sleep
mode is much slower since the reference circuit must power up
and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-
up time is dependent on the value of the capacitor connected
to the REFCOMP (Pin 4). The wake-up time is 10ms with the
recommended 10mF capacitor. Shutdown is controlled by Pin
21 (SHDN\); theADC is in shutdown when it is low. The shut-
down mode is selected with Pin 20 (CS\); low selects nap.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST\, CS\ and RD\. A logic “0”
applied to the CONVST\ pin will start a conversion after the
ADC has been selected (i.e., CS\ is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY\ output. BUSY\ is
low during a conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17), CS\ and RD\
are both tied low. The falling edge of CONVST\ starts the
FIGURE 14a: CS\ to SHDN\ Timing
FIGURE 14a: SHDN\ to CONVST\
Wake-Up Timing
FIGURE 15: CS\ to CONVST
Set-Up Timing
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
14
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
FIGURE 16: Mode 1a. CONVST\ Starts a Conversion. Data
Outputs Always Enabled. (CONVST\ =
)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
15
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
16
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
28-Pin Flat Pack
(Package Designator F)
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
17
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
28-Pin LCC Package
(Package Designator ECA)
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
18
ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS1419F-SPACE
Package Operating
Device Number
Type
Temp.
AS1419
AS1419A
F
F
-*
-*
EXAMPLE: AS1419AECA-883C
Package Operating
Device Number
Type
ECA
ECA
Temp.
AS1419
AS1419A
-*
-*
*AVAILABLE PROCESSES
XT= Extended Temperature Range
IT = IndustrialTemperature Range
MIL = Military Processing
-55oC to +125oC
-40oC to +85oC
-55°C to +125°C
-55oC to +125oC
SPACE = Space Processing
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 0.1 1/04
19
AS1419AF-IT 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AS1419AF-MIL | AUSTIN | 14 Bit, 800ksps Sampling A/D Converter with Shutdown | 获取价格 |
|
| AS1419AF-MIL | MICROSS | ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, FP-28 | 获取价格 |
|
| AS1419AF-SPACE | AUSTIN | 14 Bit, 800ksps Sampling A/D Converter with Shutdown | 获取价格 |
|
| AS1419AF-SPACE | MICROSS | 暂无描述 | 获取价格 |
|
| AS1419AF-XT | AUSTIN | 14 Bit, 800ksps Sampling A/D Converter with Shutdown | 获取价格 |
|
| AS1419AF-XT | MICROSS | ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, FP-28 | 获取价格 |
|
| AS1419ECA-IT | AUSTIN | 14 Bit, 800ksps Sampling A/D Converter with Shutdown | 获取价格 |
|
| AS1419ECA-IT | MICROSS | ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, LCC-28 | 获取价格 |
|
| AS1419ECA-MIL | AUSTIN | 14 Bit, 800ksps Sampling A/D Converter with Shutdown | 获取价格 |
|
| AS1419ECA-MIL | MICROSS | ADC, Successive Approximation, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, LCC-28 | 获取价格 |
|
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