AS5SP128K36DQC-6/IT [MICROSS]
Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | AS5SP128K36DQC-6/IT |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSRAM
AS5SP128K36
Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
DQPc
1
80
79
78
77
76
DQPb
DQb
2
3
DQc
FEATURES
DQb
DQc
VDDQ
VSSQ
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
4
VDDQ
VSSQ
DQb
5
6
DQc
75
74
73
72
7
DQb
DQc
8
DQb
DQc
9
DQb
DQc
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
VSSQ
VDDQ
DQb
10
11
12
13
14
15
16
VSSQ
VDDQ
71
70
69
68
67
DQc
DQc
NC
DQb
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
VSS
NC
66
VDD
NC
SSRAM [SPB]
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
ZZ
17
18
19
20
21
22
23
24
25
VSS
DQd
DQd
VDDQ
VSSQ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa
DQd
DQd
DQd
• 3.3V/2.5V IO Power Supply
DQd
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
26
27
28
29
30
VSSQ
VDDQ
DQd
DQd
• TQFP in copper lead frame for superior thermal
performance
DQPd
• RoHs compliant options available
FAST ACCESS TIMES
Parameter
Symbol 200Mhz 166Mhz 133Mhz
Units
Cycle Time
tCYC
5.0
6.0
7.5
ns
Clock Access Time
Output Enable Access Time
tCD
tOE
3.0
3.0
3.5
3.5
4.0
4.0
ns
ns
GENERAL DESCRIPTION
TheAS5SP128K36 is a 4.5Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address
counter supporting four (4) double-word transfers. Writes are
internally self-timed and synchronous to the rising edge of
clock.
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
I/O Gating and Control
The AS5SP128K36 includes advanced control options
including Global Write, Byte Write as well as anAsynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled byAddressAdvance
(ADV) control input.
CE3\
BWE\
BWx\
Memory Array
Output Output
Register Driver
CONTROL
BLOCK
x36
SBP
GW\
❑
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
BURST CNTL.
❋
❋
ADV
DQx, DQPx
ADSC\
ADSP\
MODE
Address
Registers
Input
Register
❋
Row
Decode
Column
Decode
A0-Ax
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
1
SSRAM
AS5SP128K36
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Symbol
Type
Pin
Description
Clock
CLK
Input
89
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Address
Address
A0, A1
A
Input
37, 36
Input(s)
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
Synchronous Address Inputs
Chip Enable
Chip Enable
CE1\, CE3\
CE2
Input
Input
Input
Input
Active Low True Chip Enables
Active High True Chip Enable
97
Global Write Enable
Byte Enables
GW\
88
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
93, 94, 95, 96
Byte Write Enable
Output Enable
Address Strobe Controller
Input
Input
Input
87
86
85
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted LOW, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Address Strobe from Processor
ADSP\
Input
84
Address Advance
Power-Down
ADV\
ZZ
Input
Input
83
64
Data Parity Input/Outputs
DQPa, DQPb
DQPc, DQPd
Input/
Output
51, 80, 1, 30
Data Input/Outputs
DQa, DQb, DQc Input/
52, 53, 56, 57, 58, 59, Bidirectional I/O Data lines. As inputs they reach the memory
62, 63, 68, 69, 72, 73, array via an input register, the address stored in the register on the
74, 75, 78, 79, 2, 3, 6, rising edge of clock. As and output, the line delivers the valid data
7, 8, 9, 12, 13, 18, 19, stored in the array via an output register and output driver. The data
22, 23, 24, 25, 28, 29 delieverd is from the previous clock period of the READ cycle.
DQd
Output
Burst Mode
Power Supply [Core]
Ground [Core]
MODE
VDD
VSS
Input
31
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Supply
Supply
Supply
91, 15, 41, 65
90, 17, 40, 67
Power Supply I/O
VDDQ
4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply
70, 77
I/O Ground
VSSQ
NC
Supply
NA
5, 10, 21, 26, 55, 60,
71, 76
14, 16, 38, 39, 66
38,39,42,43
Isolated Input/Output Buffer Ground
No connections to internal silicon
No Connection(s)
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
2
SSRAM
AS5SP128K36
LOGIC BLOCK DIAGRAM
A0, A1,
A
ADDRESS
REGISTER
2
A
[1:0]
MODE
Q1
Q0
ADV
CLK
BURST
COUNTER
AND
CLR
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQP D
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
BW
D
DQ
BYTE
WRITE DRIVER
C ,DQP C
DQ
BYTE
WRITE REGISTER
C ,DQP C
C
OUTPUT
OUTPUT
MEMORY
ARRAY
DQs
SENSE
AMPS
BUFFERS
REGISTERS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE DRIVER
B ,DQP B
E
DQ
BYTE
WRITE REGISTER
B ,DQP B
B
C
D
BW
B
A
DQ
BYTE
A
,
DQP
A
DQ
A
,
DQP
BYTE
WRITE REGISTER
A
BW
BWE
WRITE DRIVER
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
3
SSRAM
AS5SP128K36
Functional Description
Micross Components AAS5SP128K36 Synchronous SRAM is A Single ADSP\ controlled WRITE operation is initiated when
manufactured to support today’s High Performance platforms both of the following conditions are satisfied at the time of
utilizing the Industries leading Processor elements including Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
those of Intel and Motorola. The AS5SP128K36 supports Syn- Enable(s) are asserted ACTIVE. The address presented to the
chronous SRAM READ and WRITE operations as well as Syn- address bus is registered and loaded on CLK HIGH, then pre-
chronous Burst READ/WRITE operations. All inputs with the sented to the core array. The WRITE controls Global Write,
exception of OE\, MODE and ZZ are synchronous in nature and Byte Write Enable (GW\, BWE\) as well as the individual
and sampled and registered on the rising edge of the devices Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are ig-
input clock (CLK). The type, start and the duration of Burst nored on the first machine cycle. ADSP\ triggered WRITE ac-
Mode operations is controlled by MODE, ADSC\, ADSP\ and cesses require two (2) machine cycles to complete. If Global
ADV as well as the Chip Enable pins CE1\, CE2, and CE3\. Write is asserted LOW on the second Clock (CLK) rise, the
All synchronous accesses including the Burst accesses are data presented to the array via the Data bus will be written
enabled via the use of the multiple enable pins and wait state into the array at the corresponding address location specified
insertion is supported and controlled via the use of the Ad- by the Address bus. If GW\ is HIGH (inactive) then BWE\ and
vance control (ADV).
one or more of the Byte Write controls (BWa\, BWb\, BWc\ and
BWd\) controls the write operation. All WRITES that are initi-
TheAS5SP128K36 supports both Interleaved as well as Linear ated in this device are internally self timed.
Burst modes therefore making it an architectural fit for either
the Intel or Motorola CISC processor elements available on A Single ADSC\ controlled WRITE operation is initiated when
the Market today.
the following conditions are satisfied: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combina-
The AS5SP128K36 supports Byte WRITE operations and
enters this functional mode with the Byte Write Enable (BWE\) tion of the WRITE inputs (GW\, BWE\, BWx\) are asserted
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). (ACTIVE). Thus completing the WRITE to the desired Byte(s)
Global Writes are supported via the Global Write Enable (GW\) or the complete data-path. ADSC\ triggered WRITE accesses
and Global Write Enable will override the Byte Write inputs and require a single clock (CLK) machine cycle to complete. The
will perform a Write to all Data I/Os.
address presented to the input Address bus pins at time of
clock HIGH will be the location that the WRITE occurs. The
The AS5SP128K36 provides ease of producing very dense ADV pin is ignored during this cycle, and the data WRITTEN to
arrays via the multiple Chip Enable input pins and Tri-state the array will either be a BYTE WRITE or a GLOBAL WRITE
outputs.
depending on the use of the WRITE control functions GW\ and
BWE\ as well as the individual BYTE CONTOLS (BWx\).
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1]
ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
Deep Power-Down Mode (SLEEP)
The AS5SP128K36 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous input
and asserting this pin places the SSRAM in a deep power-
down mode (SLEEP). White in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in mul-
tiple memory page designs where the mode recovery time can
be hidden.
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specified by either the Clock
to Data valid specification or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to se-
lect state where its outputs are tristated in the first machine
cycle and controlled by its Output Enable (OE\) on following
cycle. Consecutive single cycle READS are supported. Once
the READ operation has been completed and deselected by
use of the Chip Enable(s) and either ADSP\ or ADSC\, its out-
puts will tri-state immediately.
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
4
SSRAM
AS5SP128K36
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
CE2
CE3\
ADSP\
ADSC\
ADV
WT / RD
X
CLK
Address Accessed
NA
Operation
X
X
X
L
X
X
L
L
X
L
X
Not Selected
L
X
L
X
H
H
H
X
X
X
X
H
X
H
L
L
L
X
X
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
NA
NA
NA
NA
Not Selected
Not Selected
Not Selected
Not Selected
X
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
WT
RD
RD
RD
WT
WT
RD
RD
WT
WT
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
Notes:
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
BURST SEQUENCE TABLES
CAPACITANCE
Interleaved Burst
Parameter
Symbol
Max.
Units
Burst Control
Pin [MODE]
First Address
State
HIGH
Case 1
Case 2
Case 3
Case 4
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
CI
CIO
CCLK
6
8
6
pF
pF
pF
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Linear Burst
Burst Control
Pin [MODE]
State
LOW
Case 1
Case 2
A1
Case 3
Case 4
ASYNCHRONOUS TRUTH TABLE
A1
A0
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Operation
ZZ
OE\
I/O Status
Power-Down (SLEEP)
H
L
X
L
High-Z
DQ
Fourth Address
READ
L
L
L
H
X
X
High-Z
Din, High-Z
High-Z
WRITE
De-Selected
WRITE TABLE
GW\
BW\
BWa\
BWb\
BWc\
BWd\
Operation
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
H
L
H
H
L
X
H
H
L
H
L
X
H
H
H
L
X
H
H
H
L
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
L
X
L
X
AC TEST LOADS
X
X
ABSOLUTE MAXIMUM RATINGS*
Output
Rt = 50 ohm
Absolute Maximum Ratings
Zo=50 ohm
Parameter
Symbol
Min.
Max.
Units
Diagram [A]
30 pF
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
VDD
VDDQ
VIN
VIO
PD
tSTG
/IT
/ET
-0.3
VDD
-0.3
-0.3
4.6
V
V
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
Vt= Termination Voltage
Rt= Termination Resistor
VDD+0.3
VDDQ+0.3
1.6
V
V
W
οC
οC
οC
οC
R= 317 ohm@3.3v
R= 1667 ohm@2.5v
-65
-40
-40
-55
150
85
Output
5 pF
3.3/2.5v
105
/XT
125
R= 351 ohm@3.3v
R= 1538 ohm@2.5v
Diagram [B]
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
manent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum conditions for any
duration or segment of time may affect device reliability.
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
5
SSRAM
AS5SP128K36
DC ELECTRICAL CHARACTERISTICS (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Symbol
Parameter
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
2.375
2.4
Max
3.630
VDD
Units
V
V
V
V
V
V
V
V
Notes
1
VDD
VDDQ
VoH
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
Output High Voltage
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
2
VoL
VIH
VIL
Output Low Voltage
Input High Voltage
Input Low Voltage
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
2
1.7
-0.3
-0.3
-5
-30
-5
V
V
IIL
Input Leakage (except ZZ)
Input Leakage, ZZ pin
Output Leakage
VDD=Max., VIN=VSS to VDD
uA
uA
uA
mA
mA
mA
IZZL
IOL
IDD
3
Output Disabled, VOUT=VSSQ to VDDQ
VDD=Max., f=Max.,
Operating Current
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
265
240
225
IOH=0mA
ISB1
ISB2
Automatic CE. Power-down
Current -TTL inputs
Max. VDD, Device De-Selected,
VIN>/=VIH or VIN</=VIL
f=fMAX=1/tCYC
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
110
100
90
mA
mA
mA
mA
Automatic CE. Power-down
Current - CMOS Inputs
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
65
f=0
THERMAL RESISTANCE
DQ
Package Package
Unit
DQC
Parameter
Description
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
oC/W
Θ JA
30.32
6.85
35.25
7.96
oC/W
Θ JC
Notes:
[1] All Voltages referenced to VSS (Logic Ground)
[2] Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
[3] MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
[4] The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies. AC load current is higher than stated values, AC I/O
curves can be made available upon request
[5] VDDQ should never exceed VDD, VDD and VDDQ can be connected together
[6] This parameter is sampled
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
6
SSRAM
AS5SP128K36
AC SWITCHING CHARACTERISTICS (VDD=3.3V -5%/+10%,
TA= MIN. AND MAX TEMPERATURES OF SCREENING LEVEL CHOSEN)
-5 [200Mhz]
Min. Max.
-6 [166Mhz]
Min. Max.
-7.5 [133Mhz]
Parameter
Symbol
tCYC
tCH
tCL
tCD
tCLZ
tCHZ
tOE
Min.
7.50
3.00
3.00
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
cycles
Notes
Clock (CLK) Cycle Time
Clock (CLK) High Time
Clock (CLK) Low Time
Clock Access Time
5.00
2.00
2.00
-
-
6.00
2.50
2.50
-
-
-
-
1
1
2
-
3.00
-
3.00
3.00
-
-
3.50
-
3.50
3.50
-
-
4.00
-
3.50
4.00
-
Clock (CLK) High to Output Low-Z
Clock High to Output High-Z
Output Enable to Data Valid
1.00
1.00
-
1.00
0.00
-
1.00
1.00
-
1.00
0.00
-
1.00
1.00
-
1.00
0.00
-
2,3,4,5
2,3,4,5
6
Output Hold from Clock High
tOH
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Address Set-up to CLK High
tOELZ
tOEHZ
tAS
-
-
-
2,3,4,5
2,3,4,5
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
3.00
3.50
3.50
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
Address Hold from CLK High
tAH
Address Status Set-up to CLK High
Address Status Hold from CLK High
Address Advance Set-up to CLK High
Address Advance Hold from CLK High
Chip Enable Set-up to CLK High (CEx\, CE2)
Chip Enable Hold from CLK High (CEx\, CE2)
Data Set-up to CLK High
tASS
tASH
tADVS
tADVH
tCES
tCEH
tDS
Data Hold from CLK High
tDH
Write Set-up to CLK High (GW\, BWE\, BWx\)
Write Hold from CLK High (GW\, BWE\, BWX\)
ZZ High to Power Down
tWES
tWEH
tPD
7,8
2
2
2
ZZ Low to Power Up
tPU
2
2
2
Notes to Switching Specifications:
1. Measured as HIGH when above VIH and Low when below VIL
2. This parameter is measured with the output loading shown in AC Test Loads
3. This parameter is sampled
4. Transition is measured +500mV from steady state voltage
5. Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention
6. OE\ is a Don't Care when a Byte or Global Write is sampled LOW
7. A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required
SET-UP and HOLD times
8. This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising
edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous
inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during
device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when
either ADSP\ or ADSC\ is LOW to remain enabled.
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
7
SSRAM
AS5SP128K36
AC SWITCHING WAVEFORMS
WRITE CYCLE TIMING
Single Write
tCYC
Burst Write
Pipelined Write
tCH
CLK
tASS
tASH
tCL
ADSP\
ADSP\ Ignored with CE1\ inactive
ADSC\
tASS
tASH
ADV\
Ax
tADVS
A1
ADV\ Must be Inactive for ADSP\ Write
tADVH
A2
A3
tAS
tAH
GW\
tWES
tWEH
tWEH
tWES
BWE\, BWx\
CE1\
CE2
tCES
tCEH
CE1\ Masks ADSP\
CE3\
OE\
tDS
tDH
W1
W2a
W2d
W3
W2b
W2c
DQx,DQPx
DON'T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
8
SSRAM
AS5SP128K36
AC SWITCHING WAVEFORMS
READ CYCLE TIMING
Single Read
tCYC
Burst Read
tCL
Pipelined Read
tCH
CLK
tASS
ADSP\ Ignored with CE1\ Inactive
tASH
ADSP\
ADSC\ Initiated Read
ADSC\
ADV\
Ax
Suspend Burst
tADVS
A1
tADVH
A2
A3
tAS
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
CE1\ Masks ADSP\
tCEH
CE1\
CE2
CE3\
OE\
Unselected with CE2
tOEHZ
tOE
tCD
tOH
R2b
R2a
R2c
R1
R2d
R3a
DQx,DQPx
DON'T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
9
SSRAM
AS5SP128K36
AC SWITCHING WAVEFORMS
READ / WRITE CYCLE TIMING
Pipelined Read
Burst Read
tCH
tCYC
tCL
CLK
tASS
tASH
ADSP\
ADSC\
ADV\
Ax
tADVS
A1R
tADVH
A2W
tAS
A3W
A4R
A5R
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
tCEH
tCEH
CE1\
CE2
CE3\
OE\
tCES
tOEHZ
A2I
tOE
tOH
A4O
[a]
A4O
[b]
A4O
[c]
A4O
[d]
A1O
A3I
DQx,DQPx
tOELZ
DON'T CARE
tCD
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
10
SSRAM
AS5SP128K36
POWER DOWN (SNOOZE MODE)
Power Down or Snooze is a Power conservation mode
which when building large/very dense arrays, using
multiple devices in a multi-banked or paged array, can
greatly reduce the Operating current requirements of
your total memory array solution.
While in the Power Down or Snooze mode, Data integ-
rity is guaranteed. Accesses pending when the device
entered the mode are not considered valid nor is the
completion of the operation guaranteed. The device
must be de-selected prior to entering the Power Down
mode, all Chip Enables, ADSP\ and ADSC\ must remain
inactive for the duration of ZZ recovery time (tZZREC).
The device is placed in this mode via the use of the ZZ
pin, an asynchronous control pin which when asserted,
places the array into the lower power or Power Down
mode. Awakening the array or leaving the Power Down
(SNOOZE) mode is done so by deasserting the ZZ pin .
ZZ MODE ELECTRICAL CHARACTERISTICS
Parameter
Symbol
IDDzz
Test Conditon
ZZ >/- VDD - 0.2V
ZZ >/- VDD - 0.2V
ZZ </- 0.2V
Min.
Max.
Units
Power Down (SNOOZE) Mode
ZZ Active (Signal HIGH) to Power Down tZZS
ZZ Inactive (Signal Low) to Power Up
70
2 tCYC
mA
ns
ns
tZZR
2 tCYC
ZZ MODE TIMING DIAGRAM
CLK
ADSP\
ADSC\
CEx\
CE2
ZZ
tZZS
tZZREC
IDDzz
IDD
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
11
SSRAM
AS5SP128K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQ)
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
12
SSRAM
AS5SP128K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQC & DQCR)
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
13
SSRAM
AS5SP128K36
ORDERING INFORMATION
TQFP
tCD
(ns)
Clock
(Mhz)
Part Number
Configuration
AS5SP128K36DQ-5/IT
AS5SP128K36DQ-6/IT
AS5SP128K36DQ-7.5/IT
AS5SP128K36DQ-5/ET
AS5SP128K36DQ-6/ET
AS5SP128K36DQ-7.5/ET
AS5SP128K36DQ-6/XT
AS5SP128K36DQ-7.5/XT
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
3.0
3.5
4.0
3.0
3.5
4.0
3.5
4.0
200
166
133
200
166
133
166
133
TQFP- Copper Lead Frame-Pb/Sn Lead Finish
tCD
(ns)
Clock
(Mhz)
Part Number
Configuration
AS5SP128K36DQC-5/IT
AS5SP128K36DQC-6/IT
AS5SP128K36DQC-7.5/IT
AS5SP128K36DQC-5/ET
AS5SP128K36DQC-6/ET
AS5SP128K36DQC-7.5/ET
AS5SP128K36DQC-5/XT
AS5SP128K36DQC-6/XT
AS5SP128K32DQC-7.5/XT
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
3.0
3.5
4.0
3.0
3.5
4.0
3.0
3.5
4.0
200
166
133
200
166
133
200
166
133
TQFP- Copper Lead Frame-NiPdAu Lead Finish (RoHS Compliant)
tCD
Clock
(Mhz)
Part Number
Configuration
(ns)
AS5SP128K36DQCR-5/IT
AS5SP128K36DQCR-6/IT
AS5SP128K36DQCR-7.5/IT
AS5SP128K36DQCR-5/ET
AS5SP128K36DQCR-6/ET
AS5SP128K36DQCR-7.5/ET
AS5SP128K36DQCR-5/XT
AS5SP128K36DQCR-6/XT
AS5SP128K32DQCR-7.5/XT
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
3.0
3.5
4.0
3.0
3.5
4.0
3.0
3.5
4.0
200
166
133
200
166
133
200
166
133
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
ET = Enhanced Temperature Range
XT = Military Temperature Range
-40oC to +85oC
-40oC to +105oC
-55oC to +125oC
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
14
SSRAM
AS5SP128K36
DOCUMENT TITLE
4.5Mb, 128K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
REVISION HISTORY
Rev #
History
Release Date
Status
1.1
Updated Micross information,
corrected ordering info table, pin
description, thermal resistance,
updated package outline drawing,
and updated IDDZZ limit
November 2010
Release
1.2
Added copper lead frame and RoHS
compliant options, changed IDDzz
from 40mA to 70mA max.
Changed:
May 2011
Release
From
To
ISB3max
85mA
75mA
1.25ns
1.3ns
95mA (for -6)
95mA (for -7.5)
1.0ns
tCLZ & tCHZ min
tAS, tASS, tADVS
tCES, tDS, tWES
,
1.4ns (for -5)
tAH, tASH, tADVH
tCEH, tDH, tWEH
,
0.5ns
0.4ns (for -5)
1.3
1.4
1.5
Added Thermal Resistance for DQC
package, page 6.
September 2011
October 2011
March 2013
Release
Release
Release
Changed ISB2 from 40mA to 65mA max,
and ISB4 from 45mA to 70mA max, page 6
Updated DC Electrical Characteristics
Removed ISB3 and ISB4. Changed
ISB2 to f=0.
Micross Components reserves the right to change products or specifications without notice.
AS5SP128K36
Rev. 1.5 03/13
15
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