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AS7S32K32P-20L [MICROSS]

SRAM Module, 32KX32, 20ns, CMOS, CPGA66, 1.090 X 1.090 INCH, CERAMIC, PGA-66;
AS7S32K32P-20L
型号： AS7S32K32P-20L
厂家： MICROSS COMPONENTS    MICROSS COMPONENTS
描述：

SRAM Module, 32KX32, 20ns, CMOS, CPGA66, 1.090 X 1.090 INCH, CERAMIC, PGA-66

静态存储器 内存集成电路
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AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
SRAM MODULE  
FEATURES  
MIL-STD 883  
•
•
•
•
•
•
•
•
SMD- 5962-94614 Pin Compatible  
Access times of 20, 25, 35, 45 ns  
Built in decoupling capacitors for low noise operation  
Organized as 32K x 32  
Operation with single 5 volt supply  
Low power CMOS  
TTL Compatible Inputs and Outputs  
Packaging  
66 pin PGA type 1.09 inch square  
68 lead J leaded LCC (contact factory)  
68 lead quad flatpack (contact factory)  
GENERAL DESCRIPTION  
The Austin Semiconductor, Inc. AS7S32K32P is a 1 Mega-  
bit CMOS SRAM Module organized as 32Kx32 and user  
configurable to 64Kx16 or 128Kx8. The AS7S32K32 achieves  
high speed access, low power consumption and high reliability by  
employing advanced CMOS memory technology.  
These advanced features make ASI modules ideally suited  
for military applications.  
The AS7S32K32 module is constructed using a 1.09 inch  
square ceramic pin grid array substrate. This compact layout re-  
duces space requirements for board assembly to a minimum.  
PIN CONFIGURATION  
I/O8  
I/O9  
1
2
WE 12 I/O15 23  
CE2 13 I/O14 24  
1/O24 34 VCC 45 I/O31 56  
I/O25 35 CE4 46 I/O30 57  
I/O26 36 WE4 47 I/O29 58  
I/O10 3 GND 14 I/O13 25  
A13  
A14  
NC  
4
5
8
9
I/O11 15 I/O12 26  
A6  
A7  
A9  
37 I/O27 48 I/O28 59  
38 A3 49 AO 60  
41 WE3 52 I/O23 63  
AS7S32K32  
A10 16 OE  
VCC 19 I/O7  
CE1 20 I/O6  
27  
30  
31  
32  
33  
I/O0  
I/O16 42 CE3 53 I/O22 64  
I/O17 43 GND 54 I/O21 65  
I/O18 44 I/O19 55 I/O20 66  
I/O1 10 NC  
21 I/O5  
I/O2 11 I/O3 22 I/O4  
AS7S128K32  
Rev. 10/97  
DS000064  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
7-1  
AS7S32K32  
AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
ABSOLUTE MAXIMUM RATINGS*  
Voltage of Vcc Supply Relative to Vss..........-1V to +7V  
Storage Temperature..............................-55°C to +150°C  
Short Circuit Output Current(per I/O).....................50mA  
Voltage on Any Pin Relative to Vss...............-1V to +7V  
Junction Temperature**.......................................+150°C  
This is a stress rating only and functional operation on the device at  
these or any other conditions above those indicated in the opera-  
tional sections of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended periods may af-  
fect reliability.  
**Maximum junction temperature depends upon package type,  
*Stresses greater than those listed under “Absolute Maximum Rat- cycle time, loading, ambient temperature and airflow.  
ings” may cause permanent damage to the device.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS  
(-55°C ≤ TA ≤ 125°C; VCC = 5V ± 10%)  
DESCRIPTION  
CONDITIONS  
SYMBOL  
VIH  
MIN  
2.2  
-0.5  
-5  
MAX  
VCC+.5  
0.8  
UNITS  
V
NOTES  
1
Input High (Logic 1) Voltage  
Input Low (Logic 0) Voltage  
Input Leakage Current  
Output Leakage Current  
VIL  
V
1, 2  
0V ≤ VIN ≤ VCC  
ILI  
5
µA  
µA  
Outputs Disabled  
ILO  
-5  
5
0V ≤ VOUT ≤ VCC  
Output High Voltage  
Output Low Voltage  
IOH = -4.0mA  
IOL = 8.0mA  
VOH  
VOL  
2.4  
4.5  
V
V
1
1
0.4  
5.5  
Supply Voltage  
VCC  
V
1
MAX  
-35  
DESCRIPTION  
CONDITIONS  
SYMBOL  
-20  
-25  
-45  
UNITS  
NOTES  
Power Supply  
Current: Operating  
CE ≤ VIL; VCC = MAX  
f = MAX = 1/ RC (MIN)  
t
ICC  
600 560 540 520  
mA  
3, 13  
Output Open  
Power Supply  
Current: Standby  
CE ≥ VIH; VCC = MAX  
f = MAX = 1/ RC (MIN)  
t
ISBT1  
ISBT2  
180 160 160 160  
mA  
mA  
Output Open  
CE ≥ VIH, All Other Inputs  
≤ VIL or ≥ VIH, VCC = MAX  
f = 0 Hz  
100 100 100 100  
CE ≥ VCC -0.2V;VCC = MAX  
VIL ≤ VSS +0.2V  
VIH ≥ VCC -0.2V; f = 0 Hz  
ISBC2  
ISBC2  
20  
16  
20  
16  
20  
16  
20  
16  
mA  
mA  
“L” Version Only  
CAPACITANCE  
DESCRIPTION  
CONDITIONS  
= 25°C, f = 1MHz  
SYMBOL  
CI  
MIN  
MAX  
32  
UNITS  
pF  
NOTES  
Input Capacitance  
Output Capacitance  
T
4
4
A
VCC = 5V  
CO  
12  
pF  
AS7S128K32  
Rev. 10/97  
DS000064  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
7-2  
AS7S32K32  
AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(-55°C ≤ T ≤ 125°C;VCC = 5V ±10%)  
A
-20  
-25  
-35  
MIN  
DESCRIPTION  
SYM  
MIN  
MAX  
MIN  
MAX  
MAX  
UNITS  
NOTES  
READ Cycle  
READ cycle Time  
tRC  
tAA  
tACE  
tOH  
20  
25  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
20  
20  
25  
25  
35  
35  
Chip Enable access time  
Output hold from address change  
Chip Enable to output in Low-Z  
Chip disable to output in High-Z  
Chip Enable to power-up time  
Chip disable to power-down time  
Output Enable access time  
Output Enable to output in Low-Z  
Output disable to output in High-Z  
WRITE Cycle  
2
3
2
3
2
3
tLZCE  
tHZCE  
tPU  
9
10  
12  
6,7  
4
0
0
0
0
0
0
tPD  
20  
8
25  
10  
35  
12  
4
tAOE  
tLZOE  
tHZOE  
9
10  
12  
6
WRITE cycle time  
tWC  
tCW  
tAW  
tAS  
20  
15  
15  
0
25  
17  
17  
0
35  
20  
20  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable to end of write  
Address valid to end of write  
Address setup time  
Address hold from end of write  
WRITE pulse width  
tAH  
1
1
1
tWP1  
tDS  
15  
10  
17  
12  
20  
15  
Data setup time  
Data hold time tDH  
0
0
0
ns  
15  
Write disable to output in Low-Z  
Write Enable to output in High-Z  
tLZWE  
tHZWE  
3
3
3
ns  
ns  
7
10  
12  
6,7  
AS7S128K32  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
Rev. 10/97  
DS000064  
7-3  
AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
AC TEST CONDITIONS  
+5V  
+5V  
480  
Input pulse levels........................................VSS to 3V  
Input rise and fall times........................................5ns  
Input timing reference levels...............................1.5V  
Output reference levels........................................1.5V  
Output load..................................See Figures 1 and 2  
480  
Q
Q
255  
255  
5pF  
30pF  
Fig. 2 OUTPUT LOAD  
EQUIVALENT  
Fig. 1 OUTPUT LOAD  
EQUIVALENT  
NOTES  
7. At any given temperature and voltage condition,  
HZCE is less than tLZCE and tHZWE is less than tLZWE.  
1. All voltages referenced to VSS (GND).  
2. -3v for pulse width <20ns.  
t
8. WE is HIGH for READ cycle.  
3. ICC is dependent on output loading and cycle rates.  
The specified value applies with the outputs  
4. This parameter is sampled.  
9. Device is continuously selected. Chip enables and output  
enable are held in their active state.  
10. Address valid prior to or coincident with latest occurring  
chip enable.  
11. tRC= READ cycle time.  
12. Chip enable (CE) and write enable (WE) can initiate and  
terminate a WRITE cycle.  
1
HZ.  
unloaded, and f=  
tRC(MIN)  
5. Test conditions as specified with output loading as  
shown in Fig. 1 unless otherwise noted.  
6. tHZCE, tHZOE and tHZWE are specified with CL= 5pF  
as in Fig. 2. Transition is measured +/- 500 mV  
typical from steady state voltage, allowing for actual  
tester RC time constant.  
13. ICC is for 32 bit mode.  
DESCRIPTION  
CONDITIONS  
SYMBOL  
MIN  
MAX  
—
UNITS  
V
NOTES  
VCC for Retention Data  
Data Retention Current  
VDR  
2
CE ≥ (VCC - 0.2V) VCC = 2V  
VIN ≥ (VCC - 0.2V)  
ICCDR  
4
mA  
or ≤ 0.2V  
VCC = 3V  
8
mA  
ns  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
0
—
4
Operation Recovery Time  
tRC  
ns  
4, 11  
DATA RETENTION MODE  
VCC  
VDR>2V  
VDR  
4.5V  
4.5V  
tCDR  
tR  
VIH-  
VIL-  
CE  
AS7S128K32  
Rev. 10/97  
DS000064  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
7-4  
AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
READ CYCLE NO. 18, 9  
t
RC  
ADDR  
VALID  
t
AA  
t
OH  
PREVIOUS DATA VALID  
DATA VALID  
Q
READ CYCLE NO. 2 7, 8, 10  
t
RC  
CE  
OE  
t
AOE  
t
t
t
LZOE  
HZOE  
t
ACE  
HZCE  
t
LZCE  
HIGH-Z  
DATA VALID  
DQ  
Icc  
t
t
PD  
PU  
AS7S128K32  
Rev. 10/97  
DS000064  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
7-5  
AS7S32K32  
32K x 32 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
WRITE CYCLE NO. 1 12  
(Chip Enable Controlled)  
t
WC  
ADDR  
t
AW  
t
t
t
AH  
AS  
CW  
CE  
t
WP  
WE  
t
t
DH  
DS  
DQ  
DATA VALID  
WRITE CYCLE NO. 2 7, 12  
(Write Enable Controlled)  
t
WC  
ADDR  
t
AW  
t
t
AH  
CW  
CE  
t
t
AS  
WP  
WE  
t
t
DH  
DS  
DATA VALID  
DQ  
AS7S128K32  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
7-6  
Rev. 10/97  
DS000064  

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