AS8F512K32Q-150/883C
更新时间：2024-09-18 18:25:26
品牌：MICROSS
描述：Flash Module, 512KX32, 150ns, CQFP68, QFP-68
概述
数据手册AS8F512K32Q-150/883C 概述
Flash Module, 512KX32, 150ns, CQFP68, QFP-68
AS8F512K32Q-150/883C 数据手册
通过下载AS8F512K32Q-150/883C数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载FLASH
AS8F512K32
Austin Semiconductor, Inc.
512K x 32 FLASH
PIN ASSIGNMENT
(Top View)
FLASH MEMORY ARRAY
68 Lead CQFP (Q)
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
SMD5962-94612
MIL-STD-883
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast Access Times: 70, 90, 120 and 150ns
Operation with single 5V (±10%)
Theta JC= 1.00°C/w
User configurable as 512Kx32, 1Mx16, or 2Mx8
Eight Equal Sectors of 64K Bytes for each 512Kx8
Compatible with JEDEC EEPROM command set
Any Combination of Sectors can be Erased
Supports Full Chip Erase
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Built in decoupling caps for low noise operation
Suspend Erase/Resume Function
66 Lead PGA (P)
Individual Byte Read/ Write Control
10,000 Program/Erase Cycles
OPTIONS
MARKINGS
•
Timing
70ns
90ns
120ns
150ns
-70
-90
-120
-150
•
Package
Ceramic Quad Flat pack
Pin Grid Array
Q
P
No. 702
No. 904
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F512K32 is a 16 Megabit
CMOS FLASH Memory Module organized as 512Kx32 bits. The
AS8F512K32 achieves high speed access (70 to 150 ns), low power
consumption and high reliability by employing advanced CMOS memory
technology.
An on-chip state machine controls the program and erase func-
tions. The embedded byte-program and sector/chip erase functions are
fully automatic. Data-protection of any sector combination is accom-
plished using a hardware sector-protection feature.
The Erase/Resume function allows the sector erase operation to
read data from, or program to a non-erasing sector, then resume the
erase operation.
Device operations are selected by using standard commands into
the command register using standard microprocessor write timings. The
command register acts as an input to an internal state machine that
interprets the commands, controls the erase and programming opera-
tions, outputs the status of the device, and outputs data stored in the
device. On initial power-up operation, the device defaults to the read
mode.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
1
FLASH
AS8F512K32
Austin Semiconductor, Inc.
sequence transpires. The command register does not fill an
addressable memory location. The register is used to store the
command sequence, along with the address and data needed
OPERATIONS
Read Mode
A low-level logic signal is applied to CE\ and OE\ pins to
read the output of the AS8F512K32. The CE\ is power control
and is used for device selection.
by the memory array. Commands are written by setting CE\=V
IL
and OE\= V and bring WE\ from logic-high to logic-low. Ad-
IH
dresses are latched on the falling edge of WE\ and data is
The delay from stable address to valid output data is the
latched on the rising edge of WE\. Holding WE\ =V and
IL
address access time (t
). The delay from CE\ equals logic
AVQA
toggling CE\ can be used as an alternative.
low and stable addresses to valid output data is the chip-en-
able access time (t ). The output-enable access time
ELQV
) is the delay from OE\ =low logic to valid output data,
Read/Reset Command
(t
GLQV
when CE\ =low logic and addresses are stable for at least t
The read/reset mode is activated by writing either of the
two read/reset command register. The device remains in this
mode until one of the other valid command sequences is input
into the command register. Memory data can be read with stan-
dard microprocessor read-cycle timing in the read mode.
On power up, the device defaults to the read/reset mode.
A read/reset command sequence if not required and memory
data is available.
-
AVQA
t
.
GLQV
Standby Mode
Icc supply current is reduced by applying a logic-high on
the CE\ to enter the standby mode. In the standby mode, the
outputs are placed in the high impedance state.
If the device is deselected during erasure or programming,
the device continues to draw active current until the operation
is complete.
Algorithm-Selection Command
The algorithm-selection command allows access to binary
code that matches the device with the proper programming -
and erase-command operations. After writing the three bus
cycle command sequence, the first byte of the algorithm-selec-
tion code (01) can be read from address XX00. The second
byte of the code (A4) can be read from address XX01. This
mode remains in effect until another valid command sequence
is written to the device.
Output Disable
OE\= V or CE\=V , output from the device is disabled
IL
IH
and the output pins (DQ0 - DQ7) are placed in the high-imped-
ance state.
Erasure and Programming
Erasure and programming of the AS8F512K32 are accom-
plished by writing a sequence of commands using standard
microprocessor write timings. The commands are written to a
command register and input to the command state machine.
The command state machine interprets the command entered
and initiates program, erase, suspend, and resume operations
as instructed. The command state machine acts as the inter-
face between the write-state machine and external chip opera-
tions. The write-state machine controls all voltage generation,
pulse generation, preconditioning and verification of the con-
tents of the memory. Program and block/chip-erase functions
are fully automatic. Once the end of a program or erase opera-
tion has been reached, the device internally resets to the read
mode. If Vcc drops below the low-voltage-detect level (VLKO),
any operation in progress is aborted and the device resets to
the read mode. If a byte-program or chip-erase operation is in
progress, additional program/erase operations are ignored un-
til the operation completes.
Byte-Program Command
Byte-programming is a four-bus-cycle-command sequence.
The first three bus cycles put the device into the program-
setup state. The fourth bus cycle loads the address location
and the data to be programmed into the device. The addresses
are latched on the falling edge of WE\ and the data is latched
on the rising edge of WE\ in the fourth cycle. The raising edge
of WE\ starts the byte-program operation. The embedded
byte-programming function automatically provides needed
voltage and timing to program and verify the cell margin. Any
further commands written to the device during the program
operation are ignored.
Programming can be preformed at any address location in
any order. When erased, all bits are in a logic state 1. Logic 0s
are programmed into the device. Attempting to program logic 1
into a bit that has been previously programmed to logic 0 causes
the internal pulse counter to exceed the pulse-count limit. This
sets the exceed-timing-limit indicator (DQ5) to a logic high state.
Only an erase operation can change bits from logic 0 to logic 1.
The status of the device during the automatic program-
ming operation can be monitored for the completion using the
data-polling feature or the toggle-bit feature . See the “opera-
Command Definitions
Operating modes are selected by writing particular address
and data sequences into the command register Command Se-
quence Table . The device will reset to read mode if an incor-
rect address and data value or writing them in the incorrect
tion status” for the full description.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
2
FLASH
AS8F512K32
Austin Semiconductor, Inc.
The embedded sector erase function automatically
Chip Erase Command
provides voltage and timings needed to program and verify all
the memory cells prior to electrical erase and then erases and
verifies the cell margin automatically. The user is not required
to program the memory cells prior to erase. The status of the
device during the automatic sector erase operation can be moni-
tored for completion using the data-polling feature or the toggle
bit feature. See the "operation status" section for a full de-
scription.
Chip-erase is a six-bus-cycle command sequence. The first
three bus cycles put the device into the erase-setup state. The
next two bus cycles unlock the erase mode. The sixth bus cycle
loads the chip erase command. This command sequence is
required to ensure that the memory contents are not erased
accidentally. The rising edge of WE\ starts the chip erase op-
eration. Any further commands written to the device during
the chip erase operation is ignored.
Erase-Suspend Command
The embedded chip erase function automatically provides
voltage and timings needed to program and verify all the memory
cells prior to electrical erase. It then erases and verifies the cell
margin automatically. The user is not required to program the
memory cells prior to erase. The status of the device during the
automatic chip erase operation can be monitored for comple-
tion using the data-polling feature. See the "operation status"
section for a full description.
Sector-erase operations may be interrupted by the erase-
suspend command (B0) , in order to read data from an unaltered
sectors of the device. Erase-suspend is a one-bus-cycle com-
mand. The addresses can be V or V and the erase-suspend
IL
IH
command (B0) is latched on the rising edge of WE\. Once the
sector-erase operation is in progress, the erase-suspend com-
mand request the internal write-state-machine to halt operation
at predetermined break points. The erase-suspend command is
valid only during the sector-erase operation and is valid only
during the byte-programming and chip-erase operations. The
sector-erase delay timer expires immediately if the erase-sus-
pend command is issued while the delay is active.
Sector-Erase Command
Sector erase is a six-bus-cycle command sequence. The
first three bus cycles put the device into the erase-setup state.
The next two bus cycles unlock the erase mode. The sixth bus
cycle loads the sector erase command and the sector address
location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling
edge of WE\ in the sixth bus cycle. After a delay of 100-ms
from the rising edge of WE\, the sector erase operation begins
in the selected source.
Sectors can be selected to be erased concurrently during
the sector-erase command sequence. For each additional sec-
tor selected for erase, another bus cycle is issued. The bus
cycle loads the next sector-address location and the sector-
erase command. The time between the end of the previous bus
cycle and the start of the next bus cycle must be less than 100
ms-other wise, the new sector location is not loaded. A time
delay of 100 ms from the raising edge of the last WE\ starts the
sector erase operation. If there is a falling edge of WE\ within
the 100 ms time delay, the timer is reset.
After erase-suspend is issued, the device takes between
0.1ms and 15 ms to suspend the operation. The toggle bit must
be monitored to determine when the suspend has been ex-
ecuted. When the toggle bit stops toggling, data can be read
from sectors that are not selected for erase. See the “operation
status” section for a full definition. Reading from a sector
marked for erase can result in invalid data.
Once the sector-erase operation is suspended, further
writes of the erase-suspend command are ignored. Any com-
mand other than erase-suspend (B0) or erase-resume (30H)
written to the device during the erase-suspend mode causes
the device to exit the suspend mode. To complete the sector-
erase operation, reissue the sector-erase command sequence.
Erase-Resume Command
The erase-resume command (30H) restarts a suspended
sector erase operation from where it was halted to completion.
Erase-resume is a one-bus-cycle command. The addresses can
be V or V and the erase-resume command (30H) is latched
on the rising edge of WE\. When an erase-suspend/ erase-
resume command combination is written, the internal pulse
counter (exceed timing limit) is reset. The erase-resume com-
mand is valid only in the erase-suspend state. After the erase-
resume command is executed, the device returns to the valid
sector-erase state and further writes of the erase-resume com-
mands are ignored. After the device has resumed the sector-
erase operation, another erase-resume command can be issued
to the device.
One to eight sector address locations can be loaded in any
order. The state of the delay timer can be monitored using the
sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time
delay has not expired. See the “operation status” for the full
description.
Any commands other than erase-suspend (B0) or sector
erase (30) written to the device during the sector erase opera-
tion causes the device to exit the sector erase mode. The con-
tents of the sector(s) selected for erase is not valid. To com-
plete the sector-erase operation, reissue the sector erase com-
mand.
IL
IH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
3
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Operation Status Flags1 Table
Device Operations2
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Byte-programming in progress
Byte-programming exceed time limit
Byte-programming complete
Sector/chip erase in progress
Sector/chip erase exceed time limit
Sector/chip erase complete
T
T
D
T
T
1
0
1
D
0
1
1
X
X
D
X
X
1
0
0
D
1
1
1
X
X
D
X
X
1
X
X
D
X
X
1
X
X
D
X
X
1
D\
D\
D
0
0
1
NOTES:
1. T= toggle, D=data, X=data undefined
2. DQ4, DQ2, DQ1, DQ0 are reserved for future use.
bit DQ6 stops toggling after two consecutive reads to the same
address, the operation is complete. The toggle-bit is only
available during the byte-programming, chip-erase, and sector-
erase timing delay. Toggle-bit data is valid after the raising
OPERATION STATUS
Status Bit Definition
During operation of the automatic embedded program and
erase functions, the status of the device can be determined by
reading the data state of designated outputs. The data-polling
bit (DQ7) and toggle-bit (DQ6) require multiple successive reads
to observe a change in the state of the designated output.
Operation Status Flags Table defines the values of the Flag
status.
edge of
?WE in the last bus cycle of the command sequence
loaded into the command register. Depending on the read tim-
ing, DQ6 can stop toggling while other DQ pins are still invalid.
A subsequent read of the device is valid.
ExceedTime Limit DQ5
Data-Polling DQ7
The program and erase operations use an internal pulse
counter to limit the number of pulses applied. If the pulse count
limit is exceeded, DQ5 is set to a 1 data state. This indicates that
the program or erase operation has failed. DQ7 will not change
from complemented data to true data and DQ6 will not stop
toggling when read. To continue operation, the device must be
reset.
This condition occurs when attempting to program a logic
1 state into a bit that has been programmed previously to a
logic 0. Only an erase operation can change bits from 0 to 1.
After reset, the device is functional and can be erased and
reprogrammed.
The data-polling status outputs the complement of the data
latched into the DQ7 data register while the write-state machine
is engaged in a program or erase operation. Data bit DQ7 chang-
ing from complement to true indicates the end of an operation.
Data-polling is available only during the byte-programming,
chip-erase, sector-erase, and sector-erase timing delay. Data-
polling is valid after the rising edge of WE in the last bus cycle
of the command sequence loaded into the command register.
During a byte-program operation, reading DQ7 outputs
the complement of the DQ7 data to be programmed at the se-
lected address location. Upon completion, reading DQ7 out-
puts the true DQ7 data loaded into the program data register.
During the erase operations, reading DQ7 outputs a 0. Upon
completion, reading DQ7 outputs a 1. Also, data polling must
be performed at a new sector address that is within a sector
being erased; otherwise the status is not valid. When using
data-polling, the address should remain stable throughout the
operation.
Sector-Load-Timer DQ3
DQ3 is the sector-load timer status bit it determines if the
time to load additional sector addresses has expired. DQ3 re-
mains a logic low for 80 µs after completion of a sector-erase
sequence. This indicates another sector-erase command se-
quence can be issued. If DQ3 is at logic high, it indicates that
the delay has expired and attempts to issue additional sector-
erase commands are ignored.
The data polling bit and toggle bit are valid during the 100
µs time delay and can be used to determine if a valid sector
erase command has been issued. To ensure additional sector
erase commands have been accepted, the status of DQ3 should
be read before and after each additional sector-erase command.
If DQ3 is at a logic low on both reads, then the additional sec-
tor-erase was accepted.
During a data-polling read, while WE is low, data bit DQ7
can change asynchronously. Depending on the read timing,
the system can read valid data on DQ7, while other DQ pins are
still invalid. A subsequent read of the device is valid.
Data-Polling DQ6
The function of toggle-bit status, is to output data on
DQ6 that toggles between 1 and 0 while the write-state ma-
chine is engaged in a program or erase operation. When toggle-
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
4
FLASH
AS8F512K32
Austin Semiconductor, Inc.
DATA PROTECTION
Hardware-Sector Protection Feature
Sector Unprotect
Prior to sector unprotected, all sectors should be protected
This feature disables both programming and erase opera-
tions on any combination of one to eight sectors. Commands using the sector unprotect mode. The sector unprotect is acti-
to program or erase a protected sector do not change the data vated when WE\=V , and control pin CE\, OE\, and address
IH
contained in the sector. The data-polling and toggle bits oper- pin A9 are forced to V . Address pins A6, A12, and A16 are
ID
ate for 2ms to 100ms and then return to valid data. This feature set to V . The sector select address pins A18, A17, and A16
IH
is enabled using high-voltage V (11.5V to 12V) on address can be V or V . All eight sectors are unprotected in parallel.
ID
IL
IH
pin A9 and control pin OE\ and V on control pin CE\.
Once the inputs are stable, WE\ is pulsed low for 10ms. The
IL
The device is delivered with all sector unprotected. unprotect operation begins on the falling edge of WE\ and
Sector-unprotected mode is available to unprotect protected terminates on the raising edge of WE\.
sectors.
Sector UnprotectVerify
Sector Protect Operation
Verification of the sector unprotected is activated when
The sector protect mode is activated when WE\=V , WE\ = V , OE\ = V , CE\ = V , and address pin A9 = V .
IH
IH
IL
IL
ID
CE\=V , and address pin A9 and control pin OE\ are forced to Select the sector to be verified. Address A1 and A6 are set to
IL
V . The sector-select address pins A18, A17, and A16 are
V
and A0 to V . The other addresses can be V or V . If
ID
IH IL IL IH
used to select the sector to be protected. Address pins A0-A15 the sector selected is protected, the DQs output a 01, if sector
and I/O pins DQ0- DQ7 must be stable and can be V or V . selected is unprotected the DQs output a 00. Sector unprotect
IL
IH
Once the addresses are stable, WE\ is pulsed low for 100 ms. can also be read using the algorithm selection command.
The operation begins on the falling edge of WE\ and terminates
on the raising edge of WE\.
LowVCCWrite Lock Out
During power-up and power-down , are locked out for V
CC
Sector ProtectVerify
less than VLKO If V <VLKO, the command inputs is dis-
CC
Verification of sector protection is activated when abled and the device is reset to the read mode. On power-up, if
WE\=V , CE\=V , OE\=V , and address pin A9 is V . CE\=V , WE\= V , and OE\=V , the device does not accept
IH
IL
IL
ID
IL
IL
IH
Address pins A0 and A6 are set to V , and A1 is set to V . commands on the raising edge of WE. The device automati-
IL
IH
The sector address pins A18, A17, and A16 select the sector to cally powers up in the read mode.
be verified. The other addresses can be V or V . If the
IH
IL
sector selected if protected, the DQs output O1. If the sector Glitiching
selected is unprotected the DQs output is 00.
Pulses of less than 5ns (typical) on WE\, OE\, and CE\ will
Sector protection can also be verified using the algorithm- not issue a write cycle.
selection command. After issuing the three bus-cycle command
sequence, the sector protection status can be read on DQ0. Set Power Supply Consideration
address pins A0 = V , A1 = V , and A6 = V . Sector
Each device should have as a maximum of 0.1 mF ceramic
IL
IH
IL
address pins A18, A17, and A16 select the sector to be verified. capacitor connected between Vcc and Vss to suppress circuit
The remaining addresses are set to V . If the sector selected is noise. Printed circuit traces to Vcc should have be appropriate
IL
protected. DQ0 outputs a 1 state, and if the sector selected is to handle the current demand and minimize inductance.
unprotected DQ0 outputs a 0 state. This mode remains in effect
until another valid sequence is written to the device.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
5
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Flow Chart 1.
Sector Protect Algorithm
Start
Select Sector Address
A18,A17,A16
X=1
OE and, A9=VID
CE=VIL
Apply One
100 µs Pulse
OE, A0 and A6 = VIL
A1 = VIH
X = X+1
Select Sector Address
A18, A17, A16 = VIL
Read Data
No
No
X = 25
?
Data = 01
?
Yes
Yes
Protect
Additional
Sector
?
Sector-Protect Failed
Yes
Yes
A9=VIH or VIL
Write Reset Command
End
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
6
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Flow Chart 2.
Sector Unprotect Algorithm
Start
Protect All Sectors
X=1
CE,OE,A9=VID
A6, A12, A16=VIH
Apply One
10 ms Pulse
CE, OE, A0 = VIL
A6, A1 = VIH
X = X+1
Select Sector Address
A18, A17, A16 = VIL
Read Data
No
No
Next Sector Address
X = 1000
Data = 00
Yes
Yes
No
Last Sector?
Sector-unprotect Failed
Yes
A9=VIH or VIL
Write Reset Command
End
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
7
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operation section of this specification is not im-
plied, Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Vcc (Note 1) .......................................................-2.0V to +7.0V
A9 (Note 2)…...............................................…. -2.0V to +14V
All Other Pins (Note 1)................…….............-2.0V to +7.0V
Operating Temperature, TA (Ambient)...........55°C to +125°C
Storage Temperature .....................................-65°C to +150°C
Power Dissipation…………………........................…...1.5W
Short Circuit Output Current (Note 3)…......................200mA
Lead Temperature (soldering 10 seconds)..................+300°C
Junction Temperature................................................+165°C
NOTES:
1. Minimum DC voltage on input or I/O pins is -0.5V. During Voltage transitions, inputs may overshoot Vss to -2.0V for periods
of up to 20 ns. Maximum DC voltage on input or I/O pins is Vcc +0.5V. During Voltage transitions, inputs may overshoot Vcc
to +2.0V for periods of up to 20 ns.
2. Minium DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 pins may overshoot Vss to -2.0V for periods of up
to 20 nS. Maximum DC input voltage on A9 is +12.5V inputs which may overshoot to +13.5V for periods of up to 20 ns.
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Capacitance Table
V = 0V, f = 1MHz, TA =25ºC
IN
Symbol
Parameter
Maximum Units
CADD
COE
A0-A18 Capactiance
OE\ Capactiance
50
50
20
20
pF
pF
pF
pF
CWE, CCE WE\ and CE\ Capactiance
CIO
I/O 0 - I/O 31 Capactiance
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
8
FLASH
AS8F512K32
Austin Semiconductor, Inc.
User Bus Operations
Operation
Read
CS\ 1-4
OE\ WE\ 1-4
A0
X
X
X
A0
X
L
L
L
A1
X
X
X
A1
X
H
H
H
A6
X
X
X
A6
X
L
H
H
A9
X
X
I/O
L
L
H
L
L
L
L
H
X
H
H
X
L
Data Out
HIGH Z
HIGH Z
Data In
X
Data Out
Data Out
Data Out
Output Disable
Standby and Write Inhibit
Write
Sector Protect
Verify Sector Protect
Sector Unprotect
Verify Sector Unprotect
Erase Operations
X
H
A9
VID
VID
VID
L
L
H
L
See Chart 1 See Chart 1
See Chart 1
L
L
L
H
VID
H
See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1
LEGEND:
L = VIL, H = VIH, X = Don't Care, VID = 12V, See DC Charateristics for voltage levels
NOTE:
1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings.
Sector Address Table
SECTOR
SA0
A18
0
A17
0
A16
0
ADDRESS RANGE
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
SA1
0
0
1
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
Pin Description
Pin
Function
A0-A18 Address Inputs
I/O 0-31 Data Input/Outputs
CE\ 1-4 Chip Enable
WE\ 1-4 Write Enable
OE\
VSS
VCC
Output Enable
Device Ground
Device Internal Power Supply
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
9
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Command Denfinitions Table
Bus Cycles
Third Fourth
Command Sequence
First
Second
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset
Read
Algorithm Selection
Program
Chip Erase
Sector Erase
1
4
4
4
6
6
XXXX F0
5555 AA 2AAA
5555 AA 2AAA
5555 AA 2AAA
5555 AA 2AAA
5555 AA 2AAA
55
55
55
55
55
5555
5555
5555
5555
RA
RA
PA
RD
RD
PD
5555 AA 2AAA
5555 AA 2AAA
55
55
5555
SA
10
30
Sector Erase Supend
Sector Erase Resume
XXXX B0 Erase-supend vaild during sector-erase operation
XXXX 30 Erase-resume vaild only after erase supend
LEGEND:
RA = Address of the location to be read
PA = Address of the location to be programed
SA = Address of the sector to erased
Addresses A18, A17, A16 select 1 of 8 sectors
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location
*Address pin A18, A17, A16, A15 = VIL or VIH for al bus cycle addresses except for program address (PA),
sector address(SA), and read address (RA).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C < TA < 125°C;VCC = 5V +5%/-10%)
µΑ
µΑ
µΑ
NOTES:
1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress.
2. Not 100% tested.
3. Applies to 32 bit operations.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
10
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C;VCC = 5V -5%/+10%)
Parameter
Speed Options
Symbol
JEDEC Std.
-70 -90 -120 -150
Parameter Description
Test Setup
CE\=VIL,
OE\=VIL
Units
tAVAV
tAVQV
tRC
Read Cycle Time (Note 3)
Min
70
90 120 150
ns
CE\=VIL,
OE\=VIL
tACC
Address to Output Delay
Max
Max
70
70
90 120 150
90 120 150
ns
ns
tELQV
tGLQV
tCE
tOE
Chip Enable Low to Output Valid
Output Enable to Output Delay
Max
Min
30
0
35
0
50
0
55
0
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
(Note 3)
Data\Polling
Chip Enable High to Output High Z
(Note 2, 3)
Min
10
20
10
20
10
30
10
35
ns
ns
tEHQZ
tGHQZ
tAXQX
tHZ
tDF
tOH
Max
Output Enable to Output High Z
(Note 2,3)
Output Hold Time from Addresses, CE\
or OE\, Whichever Occurs First
20
0
20
0
30
0
35
0
ns
ns
Min
NOTES:
1. See Test Specification for test conditions.
2. Output driver disable time.
3. Guaranteed but not Tested.
Read OperationTimings
t
RC
Addresses
CE\
Addresses Stable
t
ACC
t
t
DF
CE
OE\
t
OEH
t
CE
t
WE\
OH
High-Z
High-Z
Outputs
Output Valid
OV
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
11
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C;VCC = 5V +/- 10%)
Erase and Program WE\ Controlled
Parameter
Symbol
Speed Options
Units
Parameter Description
Write Cycle Time
-70
70
JEDEC
Std.
tWC
-90
90
-120
120
-150
150
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
tAS
tAH
0
Address Setup Time
Address Hold Time
Data Setup Time
45
30
45
45
50
50
50
50
tDS
tDH
tOES
0
0
Write Enable High to Input Transition
Output Enable Setup Time
Read Recover time Before Write
(OE\ high to WE\ low)
tGHWL
tGHWL
0
Min
ns
tELWL
tWHEH
tWLWH
tWHWL
tCS
tCH
tWP
tWPH
0
0
Min
Min
Min
Min
Min
ns
ns
ns
ns
us
CE\ Setup Time
CE\ Hold Time
35
45
50
50
Write Pulse Width
20
16
Write Pulse Width High
Programming Operation
Sector Erase Operation
tWHWH1 tWHWH1
tWHWH2 tWHWH2
tWHWH3 tWHWH3
tVCHEL
Max
Max
Min
sec
sec
us
30
Chip Erase Operation
VCC Setup Time
120
50
Chip Program Time
Max
sec
50
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
12
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Program OperationTimings
t
t
AS
WC
555h
Addresses
PA
PA
PA
t
AH
CE\
OE\
t
t
GHWL
CH
t
WHWH1
t
WP
WE\
t
t
t
WPH
DH
CS
DS
t
Status
DOUT
PD
Data
AOh
t
VCS
Vcc
NOTE: PA= Program Address, PD= Program data, DOUT is the true data at the program address.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
13
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Chip/Sector Erase OperationTimings
t
t
AS
WC
2AAh
Addresses
SA
VA
VA
t
555h for Chip Erase
AH
CE\
OE\
t
t
GHWL
CH
t
WHWH2
t
WP
WE\
t
t
t
WPH
DH
CS
DS
t
In
Progress
30th
Complete
Data
55h
10 for Chip Erase
t
VCS
Vcc
NOTE: SA= Sector Address. VA = Valid Address for reading status data.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
14
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Data Polling Timings (During Embedded Algorithms)
t
RC
Addresses
VA
VA
VA
ACC
t
t
CE
CE\
OE\
t
CH
t
OE
t
t
OEH
DF
WE\
t
OH
High-Z
High-Z
Complement
Valid Data
Valid Data
True
True
Complement
Status Data
DQ7
Status Data
DQ0-DQ6
NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Toggle Bit Timings ( During Embedded Algorithms)
t
RC
Addresses
VA
VA
VA
VA
ACC
CE
t
t
CE\
OE\
t
CH
t
OE
t
t
OEH
DF
WE\
t
OH
Valid Status
Valid Status
Valid Status
Valid Status
DQ6/DQ2
(first read)
NOTE: VA=Valid address; not required for DQ6. Illustration shows first two status cycles after command sequence, last
status read cycle, and array data read cycle.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
15
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C;VCC = 5V +/- 10%)
Erase and Program CE\ Controlled (Alternate CE\ Controlled Writes)
Parameter
Symbol
Speed Options
Units
Parameter Description
JEDEC
Std.
-70
-90
-120
-150
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWC
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
90
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Write Cycle Time
tAS
tAH
0
Address Setup Time
Address Hold Time
45
30
45
45
50
50
50
50
tDS
Data Setup Time
tDH
0
0
0
0
Data Hold Time
tGHEL
tWS
tWH
tCP
Read Recover time Before Write
Setup Time, WE\
Hold Time, WE\
35
45
50
50
Pulse Duration CE\ Low
Pulse Duration CE\ High
Byte Programming Operation
tCPH
20
16
tWHWH1 tWHWH1
tWHWH2 tWHWH2
Max
Max
Max
Sector Erase Operation
Chip Erase
Chip Programming
sec
sec
sec
30
120
50
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
16
FLASH
AS8F512K32
Austin Semiconductor, Inc.
Alternate CE\ Controlled Write Operation Timings
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
17
FLASH
AS8F512K32
Austin Semiconductor, Inc.
AC TEST CONDITIONS
I
OL
Current Source
Device
-
+
Vz = 1.5V
(Bipolar
Supply)
Under
Test
+
Ceff = 50pf
I
Current Source
OH
NOTES:
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load circuit.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
18
FLASH
AS8F512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #702 (Package Designator Q)
SMD 5962-94612, Case Outline M
D2
D1
DETAIL A
D
R
1o - 7o
B
b
L1
e
SEE DETAIL A
A
A2
E
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.200
0.186
0.015
A
A1
A2
B
b
D
0.123
0.118
0.005
0.010 REF
0.800 BSC
0.013
0.017
D1
D2
E
0.870
0.980
0.936
0.890
1.000
0.956
e
R
0.050 BSC
0.010 TYP
L1
0.035
0.045
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
19
FLASH
AS8F512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P)
SMD 5962-94612, Case Outline 4
4 x D
D1
A
A1
D2
Pin 56
Pin 1
(identified by
0.060 square pad)
φb1
E
E1
e
φ b
Pin 66
Pin 11
L
e
φb2
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.195
0.035
0.020
0.055
0.075
1.086
A
A1
φb
φb1
φb2
D
0.135
0.025
0.016
0.045
0.065
1.064
D1/E1
D2
E
1.000 BSC
0.600 BSC
1.020
0.145
1.060
0.155
e
L
0.100 BSC
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
20
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS8F512K32Q-120/XT
Package
Type
Q
Speed
ns
-70
-90
-120
-150
Device Number
Process
AS8F512K32
AS8F512K32
AS8F512K32
AS8F512K32
/*
/*
/*
/*
Q
Q
Q
EXAMPLE: AS8F512K32P-120/XT
Package
Type
Speed
ns
Device Number
Process
AS8F512K32
AS8F512K32
AS8F512K32
AS8F512K32
P
P
P
P
-70
-90
-120
-150
/*
/*
/*
/*
*AVAILABLE PROCESSES
CT = Commercial Temperature Range
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
21
FLASH
AS8F512K32
Austin Semiconductor, Inc.
ASI TO DSCC PART NUMBER*
CROSS REFERENCE
ASI Package Designator Q
ASI Part #
SMD Part #
AS8F512K32Q-150/883C
AS8F512K32Q-120/883C
AS8F512K32Q-90/883C
AS8F512K32Q-70/883C
AS8F512K32Q-150/883C
AS8F512K32Q-120/883C
AS8F512K32Q-90/883C
AS8F512K32Q-70/883C
5962-9461201HMA
5962-9461202HMA
5962-9461203HMA
5962-9461204HMA (pending)
5962-9461201HMC
5962-9461202HMC
5962-9461203HMC
5962-9461204HMC (pending)
ASI Package Designator P & PN
ASI Part #
SMD Part #
AS8F512K32P-150/883C
AS8F512K32P-120/883C
AS8F512K32P-90/883C
AS8F512K32P-70/883C
AS8F512K32P-150/883C
AS8F512K32P-120/883C
AS8F512K32P-90/883C
AS8F512K32P-70/883C
5962-9461201H4A
5962-9461202H4A
5962-9461203H4A
5962-9461204H4A (pending)
5962-9461201H4C
5962-9461202H4C
5962-9461203H4C
5962-9461204H4C (pending)
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8F512K32
Rev. 4.0 6/01
22
AS8F512K32Q-150/883C 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AS8F512K32Q-150/CT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-150/IT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-150/XT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-70 | AUSTIN | Flash Memory Array | 获取价格 |
|
| AS8F512K32Q-70/883C | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-70/883C | MICROSS | Flash Module, 512KX32, 70ns, CQFP68, QFP-68 | 获取价格 |
|
| AS8F512K32Q-70/CT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-70/IT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-70/XT | AUSTIN | 512K x 32 FLASH FLASH MEMORY ARRAY | 获取价格 |
|
| AS8F512K32Q-90 | AUSTIN | Flash Memory Array | 获取价格 |
|
AS8F512K32Q-150/883C 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
