AS8S128K32Q1-17/IT [MICROSS]
SRAM Module, 128KX32, 17ns, CMOS, CQFP68, CERAMIC, QFP-68;
| 型号： | AS8S128K32Q1-17/IT |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | SRAM Module, 128KX32, 17ns, CMOS, CQFP68, CERAMIC, QFP-68 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRAM
AS8S128K32
GENERAL DESCRIPTION
128K x 32 SRAM
The AS8S128K32 is a 4 Megabit CMOS SRAM Module or-
ganized as 128Kx32-bits and user configurable to 256Kx16 or
512Kx8. The AS8S128K32 achieves high speed access, low
power consumption and high reliability by employing advanced
CMOS memory technology.
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY SPECIFICATIONS
• SMD 5962-95595 (-Q); SMD 5962-93187 (-P or -PN);
MIL-STD-883
FEATURES
• Operation with single 5V supply • Built in decoupling caps for
The military temperature grade product is suited for military
applications.
• 2V Data Retention, Low power
standby
• Vastly improved Icc Specs
• Access times of 12, 15, 17, 20,
25, 35, and 45 ns
low noise operation
• Organized as 128K x32; User
configured as 256Kx16 or
512K x8
• TTL Compatible Inputs and
Outputs
TheAS8S128K32 is offered in a ceramic quad flatpack module
per SMD-5962-95595 with a maximum height of 0.140 inches.
This module makes use of
a low profile, mutlichip
CE4
WE4
• Low power CMOS
M3
module design.
OPTIONS
CE3
WE3
This device is also offered
in a 1.075 inch square
ceramic pin grid array per
SMD 5692-93187, which
Timing
12ns
Markings
-12
-15
Timing
25ns
35ns
Markings
-25
-35
M2
I/O 24 - I/O 31
CE2
15ns
17ns
M1
WE2
I/O 16 - I/O 23
-17
45ns
-45
has a maximum height of
0.195 inches. This pack-
age is also a low profile,
multi-chip module design
reducing height require-
ments to a minimum.
20ns
-20
CE1
*No connect
on pins 8, 21,
28, 39
WE1
OE
M0
I/O 8 - I/O 23
Package
Ceramic Quad Flatpack
Pin Grid Array -8 Series
Markings
Q (No. 702); Q1
A0 - 16
P (No. 802); PN* (No. 802)
I/O 0 - I/O 7
PIN ASSIGNMENT (Top View)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
68 Lead
I/O 4
I/O 5
CQFP
(BQFP)
Military SMD
I/O 6
68 Lead CQFP
(Q & Q1)
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
Pinout Option
I/O 12
I/O 13
I/O 14
26
I/O 15
66 Lead
66 Lead
PGA- Pins 8,
21, 28, 39 are
grounds (P)
PGA- Pins 8,
21, 28, 39 are
no connects
(PN)
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
1
SRAM
AS8S128K32
*Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device.
ABSOLUTE MAXIMUM RATINGS*
Voltage of Vcc Supply Relative to Vss................-1V to +7V
Storage Temperature...................................-65°C to +150°C
Short Circuit Output Current(per I/O).........................20mA
Voltage on Any Pin Relative to Vss..............-.5V to Vcc+1V
Maximum Junction Temperature**...........................+175°C
This is a stress rating only and functional operation on the device
at these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow. See theApplication Infor-
mation section at the end of this datasheet for more information.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C<TA<125°C; Vcc = 5v 1ꢀ0)
µΑ
µΑ
µΑ
MAX
PARAMETER
CONDITIONS
CE\<VIL; VCC=MAX
SYM
-12
-15
-17
-20
-25
-35
-45 UNITS NOTES
Power Supply Current:
Operating
3, 13 (1)
f = MAX = 1/tRC (MIN)
Outputs Open
250
200
175
150
140
130
120
30
mA
mA
mA
I
cc
CE\>VIH; VCC=MAX
f = MAX = 1/tRC (MIN)
Outputs Open
40
30
40
30
40
30
35
30
35
30
30
30
(1)
ISBT1
CE\ > Vcc -0.2V; Vcc = MAX
VIL < Vss +0.2V;
30
(2)
(2)
ISBC1
Power Supply Current:
Standby
VIH > VCC -0.2V; f = 0 Hz
CE\ > Vcc -0.2V; Vcc = MAX
IL < Vss +0.2V;
V
20
20
20
20
20
20
20
mA
ISBC2
VIH > Vcc -0.2V; f = 0 Hz
"L" Version Only
NOTE: 1) Address switching sequence A, A+1, A+2, etc.
2) 1/2 input at HIGH, 1/2 input at LOW.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
2
SRAM
AS8S128K32
CAPACITANCE TABLE (VIN = ꢀV, f = 1 MHz, T = 25oC)
A
SYMBOL
PARAMETER
MAX
UNITS
NOTES
CADD
A0 - A18 Capacitance
40
pF
pF
pF
pF
4
COE
OE\ Capacitance
40
20
20
4
4
4
CWE, CCE
CIO
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
TRUTH TABLE
MODE
Read
Write
Standby
Not Selected
OE\
L
X
X
H
CE\
L
L
H
L
WE\
H
L
X
H
I/O
Q
D
POWER
ACTIVE
ACTIVE
STANDBY
ACTIVE
HIGH Z
HIGH Z
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels........................................VSS to 3V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Output reference levels........................................1.5V
Output load.............................................See Figures 1
I
OL
Current Source
Device
-
+
Vz = 1.5V
(Bipolar
Supply)
Under
Test
+
Ceff = 50pf
I
Current Source
OH
NOTES:
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
Figure 1
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
3
SRAM
AS8S128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55°C≤TA≤125°C; Vcc = 5v ±10%)
-12
-15
-17
-20
-25
-35
-45
DESCRIPTION
READ CYCLE
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tRC
READ cycle time
12
15
17
20
25
35
45
ns
ns
ns
ns
ns
ns
tAA
tACE
tOH
Address access time
12
12
15
15
17
17
20
20
25
25
35
35
45
45
Chip enable access time
Output hold from address change
Chip enable to output in Low-Z
Chip disable to output in High-Z
Chip enable to power-up time
Chip disable to power-down time
Output enable access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
2
2
2
2
2
2
2
2
2
2
2
2
2
2
tLZCE
tHZCE
tPU
4, 6, 7
6.5
7
8
9
10
14
15
4, 6, 7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
tPD
12
15
6
17
7
20
7
25
8
35
12
45
12
tAOE
tLZOE
tHZOE
5.5
ns
ns
ns
4, 6
6
6
7
7
9
12
12
4, 6, 7
tWC
tCW
tAW
tAS
WRITE cycle time
12
10
10
0
15
12
12
0
17
12
12
0
20
15
15
0
25
17
17
0
35
20
20
0
45
22
22
0
ns
ns
ns
ns
ns
Chip enable to end of write
Address valid to end of write
Address setup time
tAH
Address hold from end of write
1
1
1
1
1
1
1
1
1
1
tWP1
WRITE pulse width
10
12
12
15
17
20
20
ns
1
1
1
tWP2
tDS
WRITE pulse width
10
7
12
8
12
9
15
10
0
17
12
0
20
15
0
20
15
0
ns
ns
ns
ns
ns
Data setup time
tDH
Data hold time
0
0
0
tLZWE
tHZWE
Write disable to output in Low-z
Write enable to output in High-Z
2
2
2
2
2
2
2
4, 6, 7
4, 6, 7
6.5
7
9
10
11
14
15
NOTES:
1) Spec listed is for OE\ = HIGH condition. For OE\ = LOW condition tWP1 = tWP2 = 15 ns MIN.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
4
SRAM
AS8S128K32
NOTES
1. All voltages referenced to VSS (GND).
2. -3v for pulse width <20ns.
7. At any given temperature and voltage condition,
tHZCE, is less than tLZCE, and tHZWE is less than tLZWE
.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
8. ?W/E is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. tRC= READ cycle time.
12. Chip enable (?C/E) and write enable (?W/E) can initiate
and terminate a WRITE cycle.
1
open, and f=
HZ.
tRC(MIN)
4. This parameter is sampled.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. tHZCE, tHZOE and tHZWE are specified with CL= 5pF
as in Fig. 2. Transition is measured +/- 200 mV
typical from steady state coltage, allowing for actual
tester RC time constant.
13. 32 bit operation
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
--
V
CE\ > VCC - 0.2V
VIN > VCC - 0.2V
VCC = 2.0V
VCC = 3V
ICCDR
ICCDR
--
--
10
12
mA
mA
Data Retention Current
Chip Deselect to Data
Retention Time
tCDR
tR
0
--
ns
ns
4
tRC
4, 11
Operation Recovery Time
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
>2V
VDR
VDR
4.5V
4.5V
Vcc
tCDR
tR
VIH
CE\
V
IL
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
5
SRAM
AS8S128K32
READ CYCLE NO. 1(8,9)
tRC
VALID
ADDRESS
DQ
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 2(7,8,10)
tRC
CE\
tAOE
tHZOE
tLZOE
OE\
DQ
Icc
tLZCE
tPU
tACE
tHZCE
DATA VALID
tPD
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
6
SRAM
AS8S128K32
WRITE CYCLE NO. 1
(Chip Enable Controlled)
tWC
ADDRESS
tAW
tAH
tCW
tAS
CE\
tWP1
WE\
tDS
tDH
DATA VAILD
D
Q
HIGH Z
WRITE CYCLE NO. 2
(Write Enable Controlled)
tWC
ADDRESS VALID
ADDRESS
tAW
tCW
tAH
CE\
WE\
D
tAS
tWP2
tDS
tDH
DATA VALID
tLZWE
tHZWE
Q
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
7
SRAM
AS8S128K32
MECHANICAL DEFINITIONS*
Micross Case #7ꢀ2 (Package Designator Q)
SMD 5962-95595, Case Outline M
D2
D1
DETAIL A
D
R
1o - 7o
B
b
L1
e
SEE DETAIL A
A
A2
E3
MICROSS SPECIFICATIONS
SYMBOL
MIN
MAX
0.200
0.186
0.015
A
A1
A2
B
b
D
0.123
0.118
0.005
0.010 REF
0.800 BSC
0.013
0.017
D1
D2
E
0.870
0.980
0.936
0.890
1.000
0.956
e
R
0.505 BSC
0.010 TYP
L1
0.035
0.045
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
8
SRAM
AS8S128K32
MECHANICAL DEFINITIONS*
Micross Case (Package Designator Q1)
SMD 5962-95595, Case Outline A
SMD SPECIFICATIONS
SYMBOL
MIN
---
0.054
0.013
MAX
0.200
---
A
A1
b
0.017
0.010 TYP
B
c
0.009
0.980
0.870
0.012
1.000
0.890
D/E
D1/E1
D2/E2
e
0.800 BSC
0.050 BSC
L
0.035
0.045
0.010 TYP
R
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
9
SRAM
AS8S128K32
MECHANICAL DEFINITIONS*
Micross Case #8ꢀ2 (Package Designator P & PN)
SMD 5962-93187, Case Outline 4 and 5
4 x D
A
D1
D2
A1
Pin 56
Pin 1
(identified by
0.060 square pad)
φb1
E1
e
φb
Pin 66
e
φb2
Pin 11
L
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.195
0.035
0.020
0.055
0.075
1.086
A
A1
φb
φb1
φb2
D
0.135
0.025
0.016
0.045
0.065
1.064
D1/E1
D2
e
1.000 BSC
0.600 BSC
0.100 BSC
L
0.145
0.155
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
10
SRAM
AS8S128K32
ORDERING INFORMATION
EXAMPLE: AS8S128K32Q-25/XT
EXAMPLE: AS8S128K32Q1-15/IT
Package
Type
Speed
ns
Package
Type
Q1
Speed
ns
Device Number
Process
Device Number
Process
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
Q
Q
Q
Q
Q
Q
Q
-12
-15
-17
-20
-25
-35
-45
/*
/*
/*
/*
/*
/*
/*
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
-12
-15
-17
-20
-25
-35
-45
/*
/*
/*
/*
/*
/*
/*
Q1
Q1
Q1
Q1
Q1
Q1
EXAMPLE: AS8S128K32PN-20/883C
Package
Type
Speed
ns
Device Number
Process
AS8S128K32
AS8S128K32
P
PN
-12
-12
/*
/*
AS8S128K32
AS8S128K32
P
PN
-15
-15
/*
/*
AS8S128K32
AS8S128K32
P
PN
-17
-17
/*
/*
AS8S128K32
AS8S128K32
P
PN
-20
-20
/*
/*
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
AS8S128K32
P
PN
P
PN
P
-25
-25
-35
-35
-45
-45
/*
/*
/*
/*
/*
/*
PN
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE NOTES
P = Pins 8, 21, 28, and 39 are grounds.
PN = Pins 8, 21, 28, and 39 are no connects.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
11
SRAM
AS8S128K32
MICROSS TO DSCC PART NUMBER
CROSS REFERENCE
Micross Package Designator Q
Micross Package Designator Q1
Micross Part #
AS8S128K32Q-55/883C
AS8S128K32Q-55/883C
AS8S128K32Q-45/883C
AS8S128K32Q-45/883C
AS8S128K32Q-35/883C
AS8S128K32Q-35/883C
AS8S128K32Q-25/883C
AS8S128K32Q-25/883C
AS8S128K32Q-20/883C
AS8S128K32Q-20/883C
AS8S128K32Q-17/883C
AS8S128K32Q-17/883C
SMD Part #
Micross Part #
AS8S128K32Q1-55/883C
AS8S128K32Q1-55/883C
AS8S128K32Q1-45/883C
AS8S128K32Q1-45/883C
AS8S128K32Q1-35/883C
AS8S128K32Q1-35/883C
AS8S128K32Q1-25/883C
AS8S128K32Q1-25/883C
AS8S128K32Q1-20/883C
AS8S128K32Q1-20/883C
AS8S128K32Q1-17/883C
AS8S128K32Q1-17/883C
SMD Part #
5962-9559505HMA
5962-9559505HMC
5962-9559506HMA
5962-9559506HMC
5962-9559507HMA
5962-9559507HMC
5962-9559508HMA
5962-9559508HMC
5962-9559509HMA
5962-9559509HMC
5962-9559510HMA
5962-9559510HMC
5962-9559505HAA
5962-9559505HAC
5962-9559506HAA
5962-9559506HAC
5962-9559507HAA
5962-9559507HAC
5962-9559508HAA
5962-9559508HAC
5962-9559509HAA
5962-9559509HAC
5962-9559510HAA
5962-9559510HAC
Micross Part #
AS8S128K32Q-55/883C
AS8S128K32Q-55/883C
AS8S128K32Q-45/883C
AS8S128K32Q-45/883C
AS8S128K32Q-35/883C
AS8S128K32Q-35/883C
AS8S128K32Q-25/883C
AS8S128K32Q-25/883C
AS8S128K32Q-20/883C
AS8S128K32Q-20/883C
AS8S128K32Q-17/883C
AS8S128K32Q-17/883C
SMD Part #
Micross Part #
SMD Part #
5962-9559512HMA
5962-9559512HMC
5962-9559513HMA
5962-9559513HMC
5962-9559514HMA
5962-9559514HMC
5962-9559515HMA
5962-9559515HMC
5962-9559516HMA
5962-9559516HMC
5962-9559517HMA
5962-9559517HMC
AS8S128K32Q1-55/883C
AS8S128K32Q1-55/883C
AS8S128K32Q1-45/883C
AS8S128K32Q1-45/883C
AS8S128K32Q1-35/883C
AS8S128K32Q1-35/883C
AS8S128K32Q1-25/883C
AS8S128K32Q1-25/883C
AS8S128K32Q1-20/883C
AS8S128K32Q1-20/883C
AS8S128K32Q1-17/883C
AS8S128K32Q1-17/883C
5962-9559512HAA
5962-9559512HAC
5962-9559513HAA
5962-9559513HAC
5962-9559514HAA
5962-9559514HAC
5962-9559515HAA
5962-9559515HAC
5962-9559516HAA
5962-9559516HAC
5962-9559517HAA
5962-9559517HAC
Micross Package Designator P & PN
Micross Part #
SMD Part #
Micross Part #
AS8S128K32PN-55/883C
AS8S128K32PN-55/883C
AS8S128K32PN-45/883C
AS8S128K32PN-45/883C
AS8S128K32PN-35/883C
AS8S128K32PN-35/883C
AS8S128K32PN-25/883C
AS8S128K32PN-25/883C
AS8S128K32PN-20/883C
AS8S128K32PN-20/883C
AS8S128K32PN-17/883C
AS8S128K32PN-17/883C
SMD Part #
AS8S128K32P-55/883C
AS8S128K32P-55/883C
AS8S128K32P-45/883C
AS8S128K32P-45/883C
AS8S128K32P-35/883C
AS8S128K32P-35/883C
AS8S128K32P-25/883C
AS8S128K32P-25/883C
AS8S128K32P-20/883C
AS8S128K32P-20/883C
AS8S128K32P-17/883C
AS8S128K32P-17/883C
5962-9318705H5A
5962-9318705H5C
5962-9318706H5A
5962-9318706H5C
5962-9318707H5A
5962-9318707H5C
5962-9318708H5A
5962-9318708H5C
5962-9318709H5A
5962-9318709H5C
5962-9318710H5A
5962-9318710H5C
5962-9318705H4A
5962-9318705H4C
5962-9318706H4A
5962-9318706H4C
5962-9318707H4A
5962-9318707H4C
5962-9318708H4A
5962-9318708H4C
5962-9318709H4A
5962-9318709H4C
5962-9318710H4A
5962-9318710H4C
Please note, -15 not currently available on the SMD's.
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
12
SRAM
AS8S128K32
DOCUMENT TITLE
128K x 32 SRAM, SRAM MEMORY ARRAY
REVISION HISTORY
Rev #
History
Release Date
Status
4.2
Updated iCCDR(2V) limit from 6mA to 8mA
June 2008
January 2010
June 2011
Release
4.3
4.4
ꢀ
Added Micross Information
Page 3, 4 & 5 changes:
Release
Release
From
To
ꢀ
ꢀ
•ICC(mA)
-15
700
650
600
560
520
500
200
175
150
140
130
120
-17
-20
-25
-35
-45
ꢀ
•ISBT1 (mA)
-15
260
220
200
180
160
150
40
40
40
35
35
30
30
30
20
10
12
0
-17
-20
-25
-35
-45
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ISBC1 (mA)
•ISBC2 (mA) 24
•2VꢀICCDR (mA) 6
•3VꢀICCDR (mA) 11.6
•tDH (ns)
1
•Addedꢀ-12ꢀspeedꢀoption,ꢀpageꢀ1,ꢀ2,ꢀ4ꢀ&ꢀ11
•DeletedꢀISBT2 spec due to redundancy
4.5
Added 68 Lead CQFP (BQFP)
Military SMD Pinout Option
August 2013
Release
Micross Components reserves the right to change products or specifications without notice.
AS8S128K32
Rev. 4.5 08/13
13
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