AS8SLC512K32P-12/IT [MICROSS]
SRAM Module, 512KX32, 12ns, CMOS, PGA-66;
| 型号： | AS8SLC512K32P-12/IT |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | SRAM Module, 512KX32, 12ns, CMOS, PGA-66 静态存储器 |
| 文件： | 总12页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRAM
AS8SLC512K32
512K x 32 SRAM
SRAM Memory Array MCM
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q & Q1)
FEATURES
•
•
•
•
•
•
•
•
•
Fast access times: 10, 12, 15, 17 and 20ns
Fast OE\ access times: 6ns
Ultra-low operating power < 1W worst case
Single +3.3V ±0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Easy memory expansion with CE\ and OE\ options
Automatic CE\ power down
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 0
I/O 1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
High-performance, low-power consumption, CMOS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OPTIONS
MARKINGS
•
Timing
10ns
12ns
15ns
17ns
20ns
66 Lead PGA (P)
-10
-12
-15
-17
-20
C S
C S
•
Package
Ceramic Quad Flatpack
Ceramic Quad Flatpak(.054min SO) Q1
Pin Grid Array
\
Q
No. 702
No.904
P
•
•
Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
C S
C S
XT
IT
2V data retention/low power
L
GENERAL DESCRIPTION
M4
M3
M2
M1
The AS8SLC512K32 is a 3.3V 16 Megabit CMOS SRAM
Module organized as 512Kx32 bits. The AS8SLC512K32 achieves
very high speed access, low powerconsumption and high reliability
by employing advanced CMOS memory technology.
This military temperature grade product is ideally suited for
commercial, industrial, and military applications when asynchronous
high speed switching and low ACTIVE opening power & ultra Fast
Asynchronous Access is mandated.
For more products and information
please visit our web site at
www.micross.com
BLOCK DIAGRAM
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
1
SRAM
AS8SLC512K32
ABSOLUTE MAXIMUM RATINGS*
This is a stress rating only and functional operation on the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow. See the Ap-
plication Information section at the end of this datasheet for
more information.
Voltage of Vcc Supply Relative to Vss...........-0.5V to +4.6V
Storage Temperature.....................................-65°C to +150°C
Short Circuit Output Current(per I/O)............................20mA
Voltage on Any Pin Relative to Vss............-.5V to Vcc+4.6V
Maximum Junction Temperature**.............................+150°C
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < 125oC and -40oC to +85oC; Vcc = 3.3V ±0.3V)
DESCRIPTION
CONDITIONS
SYMBOL MIN
MAX UNITS NOTES
Input High (logic 1) Voltage
2.2
-0.3
-10
-10
V
V
1
1
VIH
VIL
ILI1
ILI2
V
CC+0.3
Input Low (logic 1) Voltage
Input Leakage CurrentADD,OE
Input Leakage CurrentWE,CE
0.8
10
μA
μA
0V<VIN<VCC
10
Output(s) Disabled
0V<VOUT<VCC
-10
2.4
10
μA
Output Leakage CurrentI/O
ILO
Output High Voltage
Output Low Voltage
V
V
1
1
I
OH=-4.0mA
VOH
VOL
0.5
IOL=8.0mA
MAX
-15
DESCRIPTION
CONDITIONS
SYMBOL -10
-12
-17
-20 UNITS NOTES
CS\<VIL; VCC = MAX
f = MAX = 1/ tRC (MIN)
Outputs Open, OE\ = VIH
High Speed
Power Supply
Current: Operating
350
320
280
260
240
mA 2, 3,13
ICC1
Low Power (L)
280
240
---
200
---
180
---
160
---
CS\<VIL; VCC = MAX
f = 10 MHz, OE\ = VIH
Low Speed
Power Supply
Current: Operating
---
ICC2
mA
mA
2
2
Low Power (L)
120
80
---
80
---
80
---
80
---
40
CS\<VIL; VCC = MAX
f = 1 MHz, OE\ = VIH
Low Speed
Power Supply
Current: Operating
---
ICC3
Low Power (L)
CS\>VIH; VCC = MAX
f = MAX = 1/ tRC (MIN)
Outputs Open, OE\=VIH
80
40
40
40
100
80
80
80
80
Power Supply
Current: Standby
ISBT1
mA
mA
3, 13
Low Power (L)
80
60
60
36
60
60
36
60
60
36
60
60
36
VIN = VCC - 0.2V, or VSS
+0.2V
80
ISBT2
CMOS Standby
V
CC=Max; f = 0Hz
Low Power (L)
50
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
2
SRAM
AS8SLC512K32
CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)*
SYMBOL
PARAMETER
A0 - A18 Capacitance
MAX
40
UNITS
pF
CADD
COE
OE\ Capacitance
40
pF
CWE, CCS
CIO
WE\ and CS\ Capacitance
I/O 0- I/O 31 Capacitance
12
pF
15
pF
NOTE:
*This parameter is sampled.
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels...........................................VSS to 3V
Input rise and fall times...........................................1ns/V
Input timing reference levels...............................1.5V
Output reference levels........................................1.5V
Output load..........................................See Figure 1, 2
3.3V
RL = 50Ω
319Ω
VL = 1.5V
Q
ZO = 50Ω
30 pF
Q
5 pF
333Ω
FIGURE 1
FIGURE 2
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
3
SRAM
AS8SLC512K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTE 5) (-55oC<TA < 125oC and -40oC to +85oC; VCC = 3.3V ±0.3V)
-10
-12
-15
-17
-20
DESCRIPTION
READ CYCLE
SYMBOL
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tRC
tAA
tACS
tOH
tLZCS
tHZCS
tAOE
tLZOE
tHZOE
READ cycle time
10
12
15
17
20
ns
ns
ns
ns
Address access time
10
10
12
12
15
15
17
17
20
20
Chip select access time
Output hold from address change
Chip select to output in Low-Z
Chip select to output in High-Z
Output enable access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
1
1
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
4,6,7
4,6,7
5
5
6
6
7
7
7.5
7.5
8
8
0
0
0
0
0
0
0
0
0
4,6
4,6
5
6
7
7.5
8
tWC
tCW
WRITE cycle time
10
7
7
0
0
9
9
5
1
2
5
12
8
15
10
10
0
17
11
11
0
20
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address valid to end of write
Address setup time
tAW
8
tAS
0
tAH
Address hold from end of write
WRITE pulse width, CS\ controlled
WRITE pulse width, WE\ controlled
Data setup time
0
0
0
0
tWP1
tWP2
tDS
10
10
6
12
12
7
14
14
7.5
1
15
15
8
tDH
tLZWE
tHZWE
Data hold time
1
1
1
Write disable to output in Low-z
Write enable to output in High-Z
2
2
2
2
4,6,7
4,6,7
5
6
6.5
7
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
4
SRAM
AS8SLC512K32
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
V
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
VCC = 2V
CC = 3V
ICCDR
ICCDR
24
32
mA
mA
Data Retention Current
V
CS\ = Vcc + 0.2V
Chip Deselect to Data
Retention Time
0
ns
4
t
CDR
Operation Recovery Time
20
ms
4, 11
t
R
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tCDR
tR
VDR
CS\ 1-4
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE
.
3. ICC is dependent on output loading and cycle rates.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
1
HZ.
unloaded, and f=
t
RC(MIN)
10. Address valid prior to or coincident with latest
curring chip enable.
oc-
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. ICC is for full 32 bit mode.
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
5
SRAM
AS8SLC512K32
READ CYCLE NO. 1
t
RC
ADDRESS
DATA I/O
t
AA
t
OH
PREVIOUS DATA VALID
NEW DATA VALID
READ CYCLE NO. 2
t
RC
ADDRESS
t
AA
CS\
t
ACS
t
t
HZCS
LZCS
OE\
t
AOE
t
LZOE
DATA VALID
DATA I/O
HIGH IMPEDANCE
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
6
SRAM
AS8SLC512K32
WRITE CYCLE NO. 1
(Chip Select Controlled)
t
WC
ADDRESS
t
AW
t
t
t
AS
AH
CW
CS\
t
WP21
WE\
t
t
DH
DS
DATA VALID
DATA I/O
WRITE CYCLE NO. 2
(Write Enable Controlled)
t
WC
ADDRESS
t
t
AW
t
AH
CW
CS\
t
t
AS
WP11
WE\
t
LZ-
t
t
t
HZWE
DS
DATA VALID
DH
DATA I/O
NOTES
1. All voltages referenced to VSS (GND).
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
7
SRAM
AS8SLC512K32
MECHANICAL DEFINITIONS*
Micross Case #702 (Package Designator Q)
4 x D2
4 x D1
D
DETAIL A
R
b
e
1o - 7o
B
L1
SEE DETAIL A
A1
A
A2
E
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.196
0.186
0.020
A
A1
A2
B
b
D
0.123
0.118
0.000
0.010 REF
0.800 BSC
0.013
0.017
D1
D2
E
0.870
0.980
0.936
0.890
1.000
0.956
0.050 BSC
e
R
L1
0.005
0.035
---
0.045
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
8
SRAM
AS8SLC512K32
MECHANICAL DEFINITIONS*
Micross Case #904 (Package Designator P)
4 x D
A
D1
D2
A1
Pin 56
Pin 1
(identified by
0.060 square pad)
φb1
E1
e
φb
Pin 66
Pin 11
e
L
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.181
0.035
0.020
0.055
1.085
A
A1
φb
φb1
D
0.144
0.025
0.016
0.045
1.065
D1/E1
D2
e
1.000 TYP
0.600 TYP
0.100 TYP
L
0.145
0.155
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
9
SRAM
AS8SLC512K32
MECHANICAL DEFINITIONS*
Micross Case (Package Designator Q1)
Case Outline A
SMD SPECIFICATIONS
SYMBOL
MIN
---
0.054
0.013
MAX
0.196
---
A
A1
b
0.017
0.010 TYP
B
c
0.009
0.980
0.870
0.012
1.000
0.890
D/E
D1/E1
D2/E2
e
0.800 BSC
0.050 BSC
L
0.035
0.045
0.010 TYP
R
*All measurements are in inches.
AS8SLC512K32
Micross Components reserves the right to change products or specifications without notice.
Rev. 2.6 01/10
10
SRAM
AS8SLC512K32
ORDERING INFORMATION
*AVAILABLE PROCESSES
XT = Extended Temperature Rang
IT = Industrial Temperature Range
883C = Military Processing
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
OPTION DEFINITIONS
L = 2V data retention/low power
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
11
SRAM
AS8SLC512K32
DOCUMENT TITLE
512K x 32 SRAM SRAM Memory Array MCM
REVISION HISTORY
Rev #
History
Release Date
Status
2.5
Updated Q & Q1 Package Specs
Page 8 & 10
May 2009
Release
2.6
Added Micross Information
January 2010
Release
Micross Components reserves the right to change products or specifications without notice.
AS8SLC512K32
Rev. 2.6 01/10
12
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