MT42C4256DCJ-8/883C [MICROSS]
Video DRAM, 256KX4, 80ns, CMOS, CDSO28, CERAMIC, SOJ-28;
| 型号： | MT42C4256DCJ-8/883C |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Video DRAM, 256KX4, 80ns, CMOS, CDSO28, CERAMIC, SOJ-28 动态存储器 CD 内存集成电路 |
| 文件： | 总38页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
256K x 4 DRAM
VRAM
WITH 512 x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATION
PIN ASSIGNMENT (Top View)
•
•
SMD 5962-89497
MIL-STD-883
28-Pin DIP
(400 MIL)
28-Pin SOJ
28-Pin LCC
FEATURES
SC
SDQ1
SDQ2
TR/OE
DQ1
1
2
3
4
5
6
7
8
9
28 Vss
SC
SDQ1
SDQ2
TR/OE
DQ1
1
2
3
4
5
6
7
8
9
28 Vss
27 SDQ4
26 SDQ3
25 SE
•
•
•
•
•
Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V ±10% power supply
Inputs and outputs are fully TTL compatible
Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
27 SDQ4
26 SDQ3
25 SE
24 DQ4
23 DQ3
22 DSF
21 CAS
20 QSF
24 DQ4
23 DQ3
22 DSF
21 CAS
20 QSF
19 A0
DQ2
DQ2
ME/WE
NC
ME/WE
NC
RAS
RAS
A0
A8 10
A6 11
A5 12
A4 13
Vcc 14
A8 10
A6 11
A5 12
A4 13
Vcc 14
19
•
•
•
512-cycle refresh within 8ms
18 A1
18 A1
17 A2
16 A3
15 A7
Optional FAST PAGE MODE access cycles
Dual port organization: 256K x 4 DRAM port
512 x 4 SAM port
17 A2
16 A3
15 A7
•
•
No refresh required for serial access memory
Low power: 15mW standby; 275mW active, typical
28-Pin FP
(F-12)
SPECIAL FUNCTIONS
•
•
•
•
•
•
JEDEC Standard Function set
PERSISTENT MASKED WRITE
SPLIT READ TRANSFER
WRITE TRANSFER/ SERIAL INPUT
ALTERNATE WRITE TRANSFER
BLOCK WRITE
SC
SDQ1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
DSF
CAS
QSF
A0
SDQ2
TR/OE
DQ1
DQ2
ME/WE
NC
RAS
A8
A6
9
10
11
12
13
14
OPTIONS
•
MARKING
Timing [DRAM, SAM (cycle/ access)]
A1
A2
A3
A7
A5
A4
Vcc
80ns, 30ns/ 25ns
100ns, 30ns/ 27ns
120ns, 35ns/ 35ns
- 8
-10
-12
•
Packages
Ceramic SOJ
DCJ No. 500
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
C
No. 109
EC No. 203
No. 302
The DRAM portion ofthe VRAM is functionally identical
to the MT4C4256 (256K x 4 DRAM). Four 512-bit data
registers make up the SAM portion of the VRAM. Data I/ O
and internal data transfer are accomplished using three
separate bidirectional data paths; the 4-bit random access
I/ O port, the four internal 512 bit wide paths between the
DRAM and the SAM, and the 4-bit serial I/ O port for the
SAM. The rest of the circuitry consists of the control, timing
and address decoding logic.
F
GENERAL DESCRIPTION
The MT42C4256 883C is a high-speed, dual port CMOS
dynamic random access memory or video RAM (VRAM)
containing 1,048,576 bits. These bits may be accessed by a
4-bit wide DRAM port or a 512 x 4-bit serial access memory
(SAM) port. Data may be transferred bidirectionally be-
tween the DRAM and the SAM.
Each port may be operated asynchronously and indepen-
dently of the other except when data is being transferred
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-27
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
internally. As with all DRAMs, the VRAM must be re-
freshed to maintain data. Refresh cycles must be timed so
that all 512 combinations of RAS addresses are executed at
least every 8ms, (regardless of sequence). Micron recom-
mends evenly spaced refresh cycles for maximum data
integrity. An internal transfer between the DRAM and the
SAM counts as a refresh cycle. The SAM portion of the
VRAM is fully static and does not require any refresh.
The operation and control of the MT42C4256 are opti-
mized for high performance graphics and communication
designs. The dual port architecture is well suited to buffer-
ing the sequential data used in raster graphics display,
serial and parallel networking and data communications.
Special features, such as SPLIT READ TRANSFER and
BLOCK WRITE allow further enhancements to system
performance.
FUNCTIONAL BLOCK DIAGRAM
COLUMN
MASK
4
4
DRAM
OUTPUT
BUFFERS
4
9
COLUMN DECODER
8
DQ1
DQ4
512
SENSE AMPLIFIERS
512
4
4
4
M
A
S
K
WRITE
CONTROL
LOGIC
MUX
4
DRAM
INPUT
BUFFERS
4
4
4
4
512 x 512 x 4
DRAM ARRAY
A0-A8
512
9
9
RAS
BLOCK
WRITE
CONTROL
LOGIC
TIMING
GENERATOR
&
CONTROL
LOGIC
CAS
TR/OE
ME/WE
DSF
SC
SE
MASKED WRITE
CONTROL
LOGIC
MASK DATA
REGISTER
4
9
256
256
REFRESH
COUNTER
TRANSFER
CONTROL
TRANSFER
GATE
TRANSFER
GATE
LOWER
SAM
UPPER
SAM
SAM
OUTPUT
BUFFERS
256
256
SDQ1
SDQ4
SAM LOCATION
4
4
4
DECODER
SAM
INPUT
BUFFERS
9
9
SPLIT SAM
STATUS & CONTROL
QSF
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-28
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
PIN DESCRIPTIONS
PIN
NUMBERS
SYMBOL
TYPE
DESCRIPTION
1
SC
Input
Serial Clock: Clock input to the serial address counter for the SAM
registers.
4
TR/OE
Input
Transfer Enable: Enables an internal TRANSFER operation at RAS
(H > L), or
Output Enable: Enables the DRAM output buffers when taken LOW
after RAS goes LOW (CAS must also be LOW), otherwise the
output buffers are in a High-Z state.
7
ME/WE
Input
Mask Enable: If ME/WE is LOW at the falling edge of RAS a
MASKED WRITE cycle is performed, or
Write Enable: ME/WE is also used to select a READ (ME/WE = H)
or WRITE (ME/WE = L) cycle when accessing the DRAM. This
includes a READ TRANSFER (ME/WE = H) or
WRITE TRANSFER (ME/WE = L).
25
S
E
Input
Serial Port Enable: SE enables the serial I/O buffers and allows a
serial READ or WRITE operation to occur, otherwise the output
buffers are in a High-Z state. SE is also used during a WRITE
TRANSFER operation to indicate whether a WRITE TRANSFER or
a SERIAL INPUT MODE ENABLE cycle is performed.
22
9
DSF
RAS
Input
Input
Special Function Select: DSF is used to indicate which special
functions (BLOCK WRITE, MASKED WRITE vs. PERSISTENT
MASKED WRITE, etc.) are used on a particular access cycle.
Row Address Strobe: RAS is used to clock-in the 9 row-address bits
and strobe the ME/WE, TR/OE, DSF, SE, CAS and DQ inputs. It
also acts as the master chip enable and must fall for initiation of any
DRAM or TRANSFER cycle.
21
/
A
S
Input
Input
Column Address Strobe: CAS is used to clock-in the 9 column-
address bits, enable the DRAM output buffers (along with TR/OE),
and strobe the DSF input.
19, 18, 17,
Address Inputs: For the DRAM operation, these inputs are multi-
plexed and clocked by RAS and CAS to select one 4-bit word out of
the 256K available. During TRANSFER operations, A0 to A8
indicate the DRAM row being accessed (when RAS goes LOW) and
the SAM start address (when CAS goes LOW).
5, 6, 23, 24
DQ1-DQ4
Input/
Output
DRAM Data I/O: Data input/output for DRAM cycles; inputs for
Mask Data Register and Color Register load cycles, and DQ and
Column Mask inputs for BLOCK WRITE.
2, 3, 26, 27
SDQ1-SDQ4
QSF
Input/
Output
Serial Data I/O: Input, output, or High-Z.
20
8
Output
Split SAM Status: QSF indicates which half of the SAM is being
accessed. LOW if address is 0-255, HIGH if address is 256-511.
NC
–
No Connect: This pin should be left either unconnected or tied to
ground.
14
28
VCC
VSS
Supply
Supply
Power Supply: +5V ±10%
Ground
MT42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-29
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
FUNCTIONAL DESCRIPTION
The MT42C4256 may be divided into three functional
blocks (see Figure 1): the DRAM, the transfer circuitry, and
the SAM. All of the operations described below are shown
in the AC Timing Diagrams section of this data sheet and
summarized in the Truth Table.
The 18 address bits that are used to select a 4-bit word
from the 262,144 available are latched into the chip using
the A0-A8, RAS and CAS inputs. First, the 9 row-address
bits are set up on the address inputs and clocked into the
part when RAS transitions from HIGH-to-LOW. Next, the
9 column address bits are set up on the address inputs and
clocked-in when CAS goes from HIGH-to-LOW.
Note:
For dual-function pins, the function not being
discussed will be surrounded by parentheses. For
example, the TR/OE pin will be shown as TR/(OE) in
references to transfer operations.
Note:
RAS also acts as a “master” chip enable for the
VRAM. If RAS is inactive, HIGH, all other DRAM
control pins (CAS, TR/OE, ME/WE, etc.) are “don’t
care” andmaychangestatewithout effect. NoDRAM
or TRANSFER cycles will be initiated without RAS
falling.
DRAM OPERATION
DRAM REFRESH
Like any DRAM based memory, the MT42C4256 VRAM
must be refreshed to retain data. All 512 row address
combinationsmust beaccessed within 8ms.TheMT42C4256
supports CAS-BEFORE-RAS, RAS-ONLY and HIDDEN
types of refresh cycles.
For the CAS-BEFORE-RAS REFRESH cycle, the row ad-
dresses are generated and stored in an internal address
counter. The user need not supply any address data, and
simply must perform 512 CAS-BEFORE-RAS cycles within
the 8ms time period.
The refresh address must be generated externally and
applied to A0-A8 inputs for RAS-ONLY refresh cycles. The
DQ pins remain in a High-Z state for both the RAS-ONLY
and CAS-BEFORE-RAS refresh cycles.
HIDDEN REFRESH cycles are performed by toggling
RAS (and keeping CAS LOW) after a READ or WRITE
cycle.This performs CAS-BEFORE-RAScycles but does not
disturb the DQ lines.
For single port DRAMS,the OEpin is a “don’t care” when
RAS goes LOW. However, for the VRAM, when RAS goes
LOW, TR/ (OE) selects between DRAM access or TRANS-
FER cycles. TR/ (OE) must be HIGH at the RAS HIGH-to-
LOW transition for all DRAM operations (except CAS-
BEFORE-RAS).
If (ME)/ WE is HIGH when CAS goes LOW, a DRAM
READ operation isperformed and thedata from thememory
cells selected will appear at the DQ1-DQ4 port. The (TR)/
OE input must transition from HIGH-to-LOW some time
after RAS falls to enable the DRAM output port.
For single port normal DRAMs, WE is a “don’t care”
when RAS goes LOW. For the VRAM, ME/ (WE) is used,
when RASgoes LOW, to select between a MASKED WRITE
cycle and a normal WRITE cycle. If ME/ (WE) is LOW at the
RAS HIGH-to-LOW transition, a MASKED WRITE opera-
tion is selected. For any DRAM access cycle (READ or
WRITE), ME/ (WE) must be HIGH at the RAS HIGH-to-
LOW transition. If (ME)/ WE is LOW before CAS goes
LOW,a DRAM EARLY-WRITEoperation is performed and
the data present on the DQ1-DQ4 data port will be written
into the selected memory cells. If (ME)/ WE goes LOW after
CAS goes LOW, a DRAM LATE-WRITE operation is per-
formed. Refer to the AC timing diagrams.
The VRAM can perform all the normal DRAM cycles
inclu d ing READ, EARLY-WRITE, LATE-WRITE,
READ-MODIFY-WRITE, FAST-PAGE-MODE READ,
FAST-PAGE-MODE WRITE (Late or Early), and FAST-
PAGE-MODE READ-MODIFY-WRITE. Refer to the AC
timing parameters and diagrams in the data sheet for more
details on these operations.
Any DRAM READ, WRITE, or TRANSFER cycle also
refreshes the DRAM row being accessed. The SAM portion
of the MT42C4256 is fully static and does not require any
refreshing.
DRAM READ AND WRITE CYCLES
The DRAM portion of the VRAM is nearly identical to
standard 256Kx 4DRAMs.However,because severalofthe
DRAM control pins are used for additional functions on
this part, several conditions that were undefined or in
“don’t care” states for the DRAM are specified for the
VRAM. These conditions are highlighted in the following
discussion. In addition, the VRAM has several special func-
tions that can be used when writing to the DRAM.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-30
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
NONPERSISTENT MASKED WRITE
The MASKED WRITE feature eliminates the need for a
READ-MODIFY-WRITEcycle when changing only specific
bits within a 4-bit word. The MT42C4256 supports two
types of MASKED WRITE cycles, NONPERSISTENT
MASKED WRITE and PERSISTENT MASKED WRITE.
If ME/ (WE) and DSF are LOW at the RAS HIGH-to-
LOW transition, a NONPERSISTENT MASKED WRITE is
performed and the data (mask data) present on the DQ1-
DQ4 inputs will be written into the mask data register. The
mask data acts as an individual write enable for each of the
four DQ1-DQ4 pins. If a LOW (logic “0”) is written to a
mask data register bit, the input port for that bit is disabled
during the subsequent WRITE operation and no new data
will be written to that DRAM cell location. A HIGH (logic
“1”) on a mask data register bit enables the input port and
allows normal WRITE operation to proceed. Note that CAS
is still HIGH. When CAS goes LOW, the bits present on the
DQ1-DQ4 inputs will be either written to the DRAM (if the
mask data bit is HIGH) or ignored (if the mask data bit is
LOW). The DRAM contents that correspond to masked
input bits will not be changed during the WRITE cycle. The
MASKED WRITE is nonpersistent (must be re-entered at
every RAS cycle) if DSF is LOW when RAS goes LOW. The
mask data register is cleared at the end of every NONPER-
SISTENT MASKED WRITE. FAST PAGE MODE can be
used with NONPERSISTENT MASKED WRITE to write
several column locations in an addressed row. The same
mask is used during the entire FAST-PAGE-MODE RAS
cycle. An example NONPERSISTENT MASKED WRITE
cycle is shown in Figure 1.
NONPERSISTENT MASKED WRITE
NONPERSISTENT MASKED WRITE
RAS
CAS
ME/WE
DSF
STORED
MASK
INPUT
STORED STORED
MASK
STORED
STORED
DATA
DATA
DATA (RE-WRITE)
DATA
1
0
1
0
1
X
0
X
1
1
0
0
1
0
0
0
0
0
1
0
1
X
1
X
1
0
1
1
0
0
0
1
BEFORE
AFTER BEFORE
AFTER
ADDRESS 0
X = NOT EFFECTIVE (DON’T CARE)
ADDRESS 1
DON’T CARE
Figure 1
NONPERSISTENT MASKED WRITE EXAMPLE
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-31
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
PERSISTENT MASKED WRITE
The PERSISTENT MASKED WRITE feature eliminates
the need to rewrite the mask data before each MASKED
WRITE cycle if the same mask data is being used repeat-
edly. To initiate a PERSISTENT MASKED WRITE, a LOAD
MASK REGISTER cycle is performed by taking ME/ (WE)
and DSF HIGH when RAS goes LOW. The mask data is
loaded into the internal register when CAS goes LOW.
PERSISTENT MASKED WRITE cycles may then be per-
formed by taking ME/ (WE) LOW and DSF HIGH when
RAS goes LOW. The contents of the mask data register will
then be used as the mask data for the DRAM inputs. Unlike
the NONPERSISTENT MASKED WRITE cycle, the data
present on the DQ inputs is not loaded into the mask
register when RAS falls, and the mask data register will not
be cleared at the end of the cycle. Any number of PERSIS-
TENT MASKED WRITE cycles, to any address, may be
performed without having to reload the mask data register.
Figure 2 shows the LOAD MASK REGISTER and two
PERSISTENT MASKED WRITE cycles in operation. The
LOAD MASK REGISTER and PERSISTENT MASKED
WRITE cycles allow controllers that cannot provide mask
data to the DQ pins at RAS time to perform MASKED
WRITE operations. PERSISTENT MASKED WRITE opera-
tions may be performed during FAST PAGE MODE cycles
and the same mask will apply to all addressed columns in
the addressed row.
LOAD MASK REGISTER
PERSISTENT MASKED WRITE
PERSISTENT MASKED WRITE
RAS
CAS
ME/WE
DSF
MASK
STORED
INPUT
STORED STORED
INPUT
STORED
DATA
DATA
DATA
DATA
0
1
X
0
X
1
1
0
X
1
X
1
0
APPLY
MASK
REG.
APPLY
MASK
REG.
1
0
1
0
0
1
0
0
0
1
0
0
0
1
1
(Stored in
Mask Data
Register)
BEFORE
AFTER
BEFORE
AFTER
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON’T CARE)
Figure 2
PERSISTENT MASKED WRITE EXAMPLE
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-32
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
COLUMN
(A2-A8 at CAS)
ROW
(A0-A8 at RAS)
DQ1
COLUMN MASK (A0,A1)
DQ2
ON THE DQ INPUTS AT CAS
DQ3
DQ4
CAS
(DQ1)
(DQ2)
(DQ3)
(DQ4)
D1
MASK
DATA
REGISTER
D2
D3
D4
4
4
DQ1
DQ2
DQ3
DQ4
RAS * DSF
LOAD
COLOR
REGISTER
RAS
COLOR REGISTER
(must be previously loaded)
Figure 3
BLOCK WRITE EXAMPLE
BLOCK WRITE
If DSF is HIGH when CAS goes LOW, the MT42C4256
will perform a BLOCK WRITE cycle instead of a normal
WRITE cycle. In BLOCK WRITE cycles, the contents of the
color register are directly written to four adjacent column
locations (see Figure 3). The color register must be loaded
prior to beginning BLOCK WRITE cycles (see LOAD
COLOR REGISTER). Each DQ location of the color register
is written to the four column locations (or any of the four
that are enabled) in the corresponding DQ bit plane.
The row is addressed as in a normal DRAM WRITEcycle.
However, when CAS goes LOW only the A2-A8 inputs are
used. A2-A8 specify the “block” of four adjacent column
locations that will be accessed. The DQ inputs are then used
to determine what combination of the four column loca-
tions will be changed. DQ1acts as a write enable for column
location A0 = 0, A1 = 0; DQ2 controls column location
A0= 1,A1= 0;DQ3controls A0= 0,A1= 1;and DQ4controls
A0 = 1, A1 = 1. The write enable controls are active HIGH;
the WRITE function is enabled by a logic 1 and disabled by
a logic 0.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-33
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
NONPERSISTENT MASKED BLOCK WRITE
The MASKED WRITE functions can also be used during
BLOCK WRITE cycles. NONPERSISTENT MASKED
BLOCK WRITE operates exactly like the normal NONPER-
SISTENT MASKED WRITE, except that the mask is now
applied to four column locations instead of just one.
Like NONPERSISTENT MASKED WRITE, the combina-
tion ofME/ (WE)LOW and DSFLOW when RASgoes LOW
initiates a NONPERSISTENT MASKED cycle. The DSF pin
must be driven HIGH when CAS goes LOW, to perform the
NONPERSISTENT MASKED BLOCK WRITE. By using
both the column mask input and the MASKED WRITE
function, any combination of the four bit planes or column
locations may be masked.
TER cycle. DSF is used when CAS goes LOW to select the
register to be loaded and must be LOW for a LOAD MASK
REGISTER cycle. The data present on the DQ lines will then
be written to the mask data register.
Note:
For a normal DRAM WRITE cycle, the mask data
register is disabled but not modified. The contents of
mask data register will not be changed unless a NON-
PERSISTENT MASKED WRITE cycle or a LOAD
MASK REGISTER cycle is performed.
The row address supplied will be refreshed, but it is not
necessary to provide any particular row address. The col-
umn address inputs are ignored during a LOAD MASK
REGISTER cycle.
PERSISTENT MASKED BLOCK WRITE
This cycle is also performed exactly like the normal
PERSISTENT MASKED WRITE except that DSF is HIGH
when CAS goes LOW to indicate the BLOCK WRITE func-
tion. Both the mask data register and the color register must
be loaded with the appropriate data prior to starting a
PERSISTENT MASKED BLOCK WRITE.
The mask data register contents are used during PERSIS-
TENT MASKED WRITE and PERSISTENT MASKED
BLOCK WRITE cycles to selectively enable writes to the
four DQ planes.
LOAD COLOR REGISTER
A LOAD COLOR REGISTER cycle is identical to the
LOAD MASK REGISTER cycle except DSF is HIGH when
CAS goes LOW. The contents of the color register are
retained until changed by another LOAD COLOR REGIS-
TER cycle (or the part loses power) and are used as data
inputs during BLOCK WRITE cycles.
LOAD MASK DATA REGISTER
The LOAD MASK REGISTER operation and timing are
identical to a normal WRITE cycle except that DSF is HIGH
when RAS goes LOW. As shown in the Truth Table, the
combination of TR/ (OE), ME/ (WE), and DSF being HIGH
when RAS goes LOW indicates the cycle is a LOAD REGIS-
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-34
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
TRANSFER OPERATIONS
TRANSFER operations are initiated when TR/ (OE) is
LOW then RAS goes LOW. The state of (ME)/ WE when
RAS goes LOW indicates the direction of the TRANSFER
(to or from the DRAM), and DSF is used to select between
NORMAL TRANSFER, SPLIT READ TRANSFER, and AL-
TERNATE WRITE TRANSFER cycles. Each of the TRANS-
FER cycles available is described below.
with SC (REAL-TIME READ TRANSFER), T/ /R/ (?OE/ ) is
taken HIGH after CAS goes LOW. If the transfer does not
have to be synchronized with SC (READ TRANSFER), TR/
(OE) may go HIGH before CAS goes LOW (refer to the AC
Timing Diagrams). The 2,048bits ofDRAM data are written
into the SAM data registers and the serial shift start
address is stored in an internal 9-bit register. QSF will be
LOW if access is from the lower half (addresses 0 through
255), and HIGH ifaccess is from the upper half(256through
511). If SE is LOW, the first bits of the new row data will
appear at the serial outputs with the first SC clock pulse.
SE enables the serial outputs and may be either HIGH or
LOW during this operation. The SAM address pointer will
increment with the SC LOW-to-HIGH transition, regard-
less ofthe state ofSE. Performing a READ TRANSFERcycle
sets the direction of the SAM I/ O buffers to the output
mode.
READ TRANSFER (DRAM-TO-SAM TRANSFER)
If (ME)/ WE is HIGH and DSF is LOW when RAS goes
LOW, a READ TRANSFER cycle is selected. The row ad-
dress bits indicate the four 512-bit DRAM row planes that
are to be transferred to the four SAM data register planes.
The column address bits indicate the start address (or Tap
address) of the serial output cycle from the SAM data
registers. CAS must fall for every TRANSFER in order to
load a valid Tap address. A read transfer may be accom-
plished in two ways. If the transfer is to be synchronized
RAS
CAS
A0-A7 = TAP
A8 = X
A0-A7 = TAP
A0-A8
ROW 0
A0-A8 = 0
ROW 0
ROW 1
A8 = X
ME/WE
TR/OE
DSF
SC
SDQ
0
1
7
8
9
255
ROW 0
260
319
320
321
Output
ROW 0
ROW 0
ROW 0
QSF
(NORMAL) READ TRANSFER
SPLIT READ TRANSFER
(OPTIONAL)
SPLIT READ TRANSFER
FROM: ROW 0
FROM: ROW 0
SERIAL OUTPUT
FROM: ROW 1
TO:
FULL SAM,
TO:
UPPER SAM,
SWITCHES FROM
LOWER SAM TO
UPPER SAM (QSF
GOES HIGH)
TO:
LOWER SAM,
SAM I/O IS SET TO OUTPUT
MODE AND SERIAL OUTPUT
FROM LOWER SAM BEGINS
(QSF GOES LOW)
TAP ADDRESS = 4
SERIAL OUTPUT FROM
LOWER SAM CONTINUES
TAP ADDRESS = 0 TO 255
SERIAL OUTPUT FROM
UPPER SAM CONTINUES
(QSF REMAINS HIGH)
DON’T CARE
UNDEFINED
Figure 4
TYPICAL SPLIT-READ-TRANSFER INITIATION SEQUENCE
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-35
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
SPLIT READ TRANSFER (SPLIT DRAM-TO-SAM
TRANSFER)
The SPLIT READ TRANSFER (SRT) cycle eliminates the
critical transfer timing required to maintain a continuous
serial output data stream. When using normal TRANSFER
cycles, the REAL-TIME READ TRANSFER cycle has to
occur immediately after the last bit of “old data” was
clocked out of the SAM port.
When using the SPLIT TRANSFER mode, the SAM is
divided into an upper half and a lower half. While data is
being serially read from one half of the SAM, new DRAM
data may be transferred to the other half. The transfer may
occur at any time while the other half is sending data and
need not be synchronized with the SC clock.
Figure 4 shows a typical SPLIT READ TRANSFER initia-
tion sequence. The normal READ TRANSFER is first per-
formed,followed by a SPLITREAD TRANSFERofthe same
row to the upper half of the SAM. The SRT to the upper half
is optional and need only be done if the Tap for the upper
half is ≠ 0. Serial access continues, and when the SAM
address counter reaches 255 (“A8” = 0, A0-A7 = 1), the new
Tap address is loaded for the next half (“A8” = 1, A0-A7 =
Tap) and the QSF output goes HIGH. Once the serial access
has switched to the upper SAM, new data may be trans-
ferred to the lower SAM. The controller must wait for the
state of QSF to change and then the new data may be
transferred to the SAM half not being accessed. For
example, the next step in Figure 4 would be to wait until
QSFwent LOW (indicating that row-1data is shifting out of
the lower SAM) and then transfer the upper half of row 1 to
the upper SAM. If the half boundary is reached before an
SRT is done for the next half a Tap address of “0” will be
used. Access will start at 0 if going to the lower half, or 256
if going to the upper half. See Figure 5.
The /T/R/ (?O/E) tim ing is also relaxed for SPLIT
TRANSFER cycles. The rising edge of TR/ (OE) is not used
to complete the TRANSFER cycle and therefore is inde-
pendent of the rising edges of RAS or CAS. The transfer
timing is generated internally for SPLIT TRANSFER cycles.
A SPLIT READ TRANSFER does not change the direction
of the SAM port.
A normal, non-split READ TRANSFER cycle must pre-
cede any sequence of SPLIT READ TRANSFER cycles to set
SAM I/ O direction and provide a reference to which half of
the SAM the access will begin. Then SPLIT READ TRANS-
FERS may be initiated by taking DSF HIGH when RAS
goes LOW during the TRANSFER cycle. As in nonsplit
transfers, the row address is used to specify the DRAM row
to be transferred. The column address, A0-A7, is used to
input theSAM Tap address.Addresspin A8isa “don’t care”
when the Tap address is loaded at the HIGH-to-LOW
transition of CAS. It is internally generated so that the
SPLIT TRANSFER will be to the SAM half not currently
being accessed.
WRITE TRANSFER (SAM-TO-DRAM TRANSFER)
The operation ofthe WRITETRANSFERisidenticalto the
READ TRANSFER described previously except (ME)/ WE
and SE must be LOW when RAS goes LOW. The row
address indicates the DRAM row to which the SAM data
registers will be written. The column address (Tap) indi-
cates the starting address of the next SERIAL INPUT cycle
for the SAM data registers. A WRITE TRANSFER changes
the direction ofthe SAM I/ O buffers to the input mode.QFS
is LOW if access is to the lower half of the SAM, and HIGH
if access is to the upper half.
LOWER HALF
NO SRT
UPPER HALF
NO SRT
0
TAP
255
256
511
Start Split
Figure 5
SPLIT SAM TRANSFER
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-36
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE
ENABLE)
The PSEUDO WRITE TRANSFER cycle is used to change
the direction of SAM port from output to input without
performing a WRITETRANSFERcycle.A PSEUDO WRITE
TRANSFER cycle is a WRITE TRANSFER cycle with SE
held HIGH instead of LOW. The DRAM data will not be
disturbed and the SAM will be ready to accept input data.
and will wrap around (after count 255 or 511) to the Tap
address of the next half for split modes. If an SRT was not
performed before the half boundary is reached the count
will progress as illustrated in Figure 5. Address count will
wrap around (after count 511) to Tap address 0 if in the
“full” SAM modes.
SC is also used to clock-in data when the device is in the
serial input mode. As in the serial output operation, the
contents of the SAM address counter (loaded when the
serial input mode was enabled) will determine the serial
address of the first 4-bit word written. SE acts as a write
enable for serial input data and must be LOW for valid
serial input. If SE = HIGH, the data inputs are disabled and
the SAM contents will not be modified. The serial address
counter is incremented with every LOW-to-HIGH transi-
tion of SC, regardless of the logic level on the SE input.
ALTERNATE WRITE TRANSFER (SAM-TO-DRAM
TRANSFER)
The operation ofthe ALTERNATEWRITETRANSFERis
identical to the WRITE TRANSFER except that the DSF pin
is HIGH and (ME)/ WE is LOW when RAS goes LOW,
allowing SE to be a “don’t care.” This allows the outputs to
be disabled using SE during a WRITE TRANSFER cycle.
ALTERNATE WRITE TRANSFER will change the SAM I/
O direction to an input condition.
SERIAL INPUT AND SERIAL OUTPUT
POWER-UP AND INITIALIZATION
The control inputs for SERIALINPUTand SERIALOUT-
PUT are SC and SE. The rising edge of SC increments the
serial address counter and provides access to the next SAM
location. SE enables or disables the serial input/ output
buffers.
Serial output of the SAM contents will start at the serial
start address that was loaded in the SAM address counter
during a READ or SPLIT READ TRANSFER cycle. The SC
input increments the address counter and presents the
contents ofthe next SAM location to the 4-bit port.SEis used
as an output enable during the SAM output operation. The
serial address is automatically incremented with every SC
After Vcc is at specified operating conditions, for 100µs
minimum, eight RAS cycles must be executed to initialize
the dynamic memory array. Micron recommends that
/RA? /S = (TR)/ OE ≥ VIH during power up to ensure that the
DRAM I/ O pins (DQs) are in a High-Z state. The DRAM
array will contain random data.
The SAM portion of the MT42C4256 is completely static
in operation and does not require refresh or initialization.
The SAM port will power-up in the serial input mode
(WRITE TRANSFER) and the I/ O pins (SDQs) will be
High-Z, regardless of the state of SE. The mask and color
register will contain random data after power-up. QSF
initializes in the LOW state.
LOW-to-HIGH transition, regardless of whether /S/E is
HIGH or LOW. The address progresses through the SAM
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-37
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
CODE
FUNCTION
RAS FALLING EDGE
CAS FALL
DSDF
A0 - A81
DQ1 - DQ42
S3
REGISTERS
CAS
T/
R/OE ME/
W
E
DSF
SE
R
A
S
CA
S
R
A
S
C
A
/
MASK COLOR
WE
DRAM OPERATIONS
CBR CAS-BEFORE-RAS REFRESH
ROR RAS-ONLY REFRESH
0
1
1
1
X
1
1
X
1
X
X
0
X
X
X
X
X
–
–
X
–
–
X
–
X
X
X
X
X
X
X
ROW
X
X
RW NORMAL DRAM READ OR WRITE
1
0
ROW COLUMN
DATA
RWNM NONPERSISTANT (LOAD AND USE) MASKED
WRITE TO DRAM
1
0
0
0
ROW COLUMN WRITE DATA LOAD &
MASK
USE
RWOM PERSISTENT (USE REGISTER) MASKED
WRITE TO DRAM
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
1
X
X
X
X
0
1
1
1
ROW COLUMN
X
DATA
USE
X
BW BLOCK WRITE TO DRAM (NO DATA MASK)
ROW COLUMN
(A2 - A8)
X
COLUMN
MASK
X
USE
BWMN NO PERSISTENT (LOAD & USE) MASKED
BLOCK WRITE TO DRAM
ROW COLUMN WRITE COLUMN LOAD & USE
MASK MASK USE
BWOM PERSISTENT (USE MASKED REGISTER) MASKED BLOCK
WRITE TO DRAM
ROW COLUMN
(A2 - A8)
X
COLUMN USE
MASK
USE
REGISTER OPERATIONS
4
LMR LOAD MASK REGISTER
1
1
1
1
1
1
1
1
X
X
0
1
ROW
X
X
X
X
WRITE
MASK
LOAD
X
X
4
LCR LOAD COLOR REGISTER
ROW
COLOR
DATA
LOAD
TRANSFER OPERATIONS
RT
READ TRANSFER (DRAM-TO-SAM TRANSFER
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
X
X
0
X
X
X
X
X
ROW
ROW
ROW
TAP5
TAP5
TAP5
TAP5
TAP5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SRT SPLIT READ TRANSFER (SPILT DRAM-TO-SAM TRANSFER)
WT WRITE TRANSFER (SAM-TO-DRAM TRANSFER)
4
PWT PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE ENABLE)
1
ROW
AWT ALTERNATE WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
X
ROW
NOTE:
1. These columns show what must be present on the A0-A8 inputs when RAS falls and when CAS falls.
2. These columns show what must be present on the DQ1-DQ4 inputs when RAS falls and when CAS falls.
3. On WRITE cycles (except BLOCK WRITE), the input data is latched at the falling edge of CAS or ME/WE, whichever is later.
Similarly, on READ cycles, the output data is activated at the falling edge of CAS or
TR/OE, whichever is later.
4. The ROW that is addressed will be refreshed, but no particular ROW address is required.
5. This is the SAM location that the first SC cycle will access. For split SAM transfers, the Tap will be the first address location
accessed of the “new” SAM half after the boundary of the current half is reached (255 for lower half, 511 for upper half).
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-38
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss .............. -1V to +7V
Operating Temperature, T (Ambient) ..... 55°C to +125°C
A
Storage Temperature (Plastic).................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
Lead Temperature (soldering 10 seconds) .............. +300°C
Junction Temperature ............................................... +165°C
RECOMMENDED DC OPERATING CONDITIONS
(-55°C ≤ T ≤ 125°C)
A
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
Supply Voltage
VCC
VIH
VIL
4.5
2.4
-.5
5.5
VCC+.5
0.8
V
V
V
1
1
1
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
DC ELECTRICAL CHARACTERISTICS
(-55°C ≤ T ≤ 125°C; VCC = 5V ±10%)
A
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
INPUT LEAKAGE CURRENT
IL
-5
5
µA
Any input (0V ≤ VIN ≤ VCC); all other pins not under test = 0V
OUTPUT LEAKAGE CURRENT
IOZ
-5
5
µA
(DQ, SDQ disabled, 0V ≤ VOUT ≤ VCC)
OUTPUT LEVELS
Output High Voltage (IOUT = -2.5mA)
Output Low Voltage (IOUT = 2.5mA)
VOH
2.4
V
V
1
VOL
0.5
CAPACITANCE
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
Input Capacitance: A0-A8
CI1
CI2
7
7
7
9
pF
pF
pF
pF
2
2
2
2
Input Capacitance: RAS, CAS, ME/WE, TR/OE, SC, SE, DSF
Input/Output Capacitance: DQ, SDQ
Output Capacitance: QSF
CI/O
CO
MT42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-39
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
CURRENT DRAIN, SAM IN STANDBY
(-55°C ≤ T ≤ 125°C; VCC = 5V ±10%)
A
MAX
PARAMETER/CONDITION
SYMBOL -8
-10
-12 UNITS NOTES
OPERATING CURRENT
(/R/A/
ICC1
95
90
80
mA
3, 4
26
t
t
ICC2
85
75
65
mA
3, 4
27
t
t
(/R/A/S = VIL; CAS = Cycling: PC = PC (MIN))
STANDBY CURRENT: TTL INPUT LEVELS
Power supply standby current
(/R/A/S = CAS = VIH after 8 R/ A/ S/ cycles (MIN), other inputs ≥ VIH or ≤ VIL)
ICC3
ICC4
ICC5
ICC6
8
8
8
mA
4
REFRESH CURRENT: RAS-ONLY
(RAS = Cycling; CAS = VIH)
95
90
90
95
80
80
95
mA 3, 26
REFRESH CURRENT:
?C/A/
95
mA
mA
3, 5
3
105
t
CURRENT DRAIN, SAM ACTIVE ( SC = MIN)
(-55°C ≤ T ≤ 125°C; VCC = 5V ±10%)
A
MAX
-10
PARAMETER/CONDITION
SYMBOL -8
150
-12 UNITS NOTES
OPERATING CURRENT
(RAS and CAS = Cycling: RC = RC (MIN))
ICC7
130 120
mA 3, 4,
26
t
t
OPERATING CURRENT: FAST PAGE MODE
(RAS = VIL; CAS = Cycling: PC = PC (MIN))
ICC8
140
120 110
mA 3, 4,
27
t
t
STANDBY CURRENT: TTL INPUT LEVELS
Power supply standby current
(/R/A/S = CAS = VIH after 8 R/ A/ S/ cycles (MIN), other inputs ≥ VIH or ≤ VIL)
ICC9
ICC10
ICC11
ICC12
35
30
25
mA
3, 4
REFRESH CURRENT: RAS-ONLY
(RAS = Cycling; CAS = VIH)
150
150
160
130 120
130 120
130 125
mA 3, 4,
26
REFRESH CURRENT: CAS-BEFORE-RAS
(RAS and CAS = Cycling)
mA 3, 4, 5
SAM/DRAM DATA TRANSFER
mA
3, 4
MT42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-40
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ T ≤ +125°C; VCC = 5V ±10%)
A
AC CHARACTERISTICS
-8
-10
-12
PARAMETER
SYM
tRC
tRWC
tPC
MIN
150
195
45
MAX
MIN
180
235
55
MAX
MIN
210
275
65
MAX
UNITS NOTES
Random READ or WRITE cycle time
READ-MODIFY-WRITE cycle time
ns
ns
ns
FAST-PAGE-MODE READ or WRITE
cycle time
FAST-PAGE-MODE READ-MODIFY-WRITE
cycle time
tPRWC
90
110
130
ns
Access time from RAS
tRAC
tCAC
tOE
80
20
100
25
120
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
Access time from CAS
Access time from (TR)/OE
Access time from column address
Access time from CAS precharge
20
25
30
tAA
40
50
60
tCPA
tRAS
tRASP
tRSH
tRP
tCAS
tCSH
tCP
tRCD
tCRP
tASR
tRAH
tRAD
45
50
50
RAS pulse width
80
80
20
60
20
80
10
20
5
20,000
100
100
25
70
25
100
12
25
5
20,000
100
100
30
80
30
120
15
25
10
0
20,000
RAS pulse width (FAST PAGE MODE)
RAS hold time
100,000
10,000
60
100,000
10,000
75
100,000
10,000
90
/R/A/
C
A
/
CAS hold time
CAS precharge time
R
A
/
17
18
/C/A/
Row address setup time
Row address hold time
0
0
10
15
15
20
15
20
RAS to column
40
50
60
address delay time
Column address setup time
Column address hold time
tASC
tCAH
tAR
0
0
0
ns
ns
ns
15
60
20
70
20
80
Column address hold time
(referenced to RAS)
Column address to
tRAL
40
50
60
ns
/R/A/S lead time
Read command setup time
tRCS
tRCH
0
0
0
0
0
0
ns
ns
Read command hold time
(referenced to CAS)
19
19
Read command hold time
(referenced to RAS)
tRRH
0
0
0
ns
CAS to output in Low-Z
tCLZ
tOFF
0
0
0
0
0
0
ns
ns
Output buffer
turn-off delay
20
20
20
20
20
25
20, 23
Output disable
tOD
tOEH
tROH
0
20
0
0
20
0
0
25
0
ns
ns
ns
20, 23
25
Output disable hold time from start of WRITE
?O/E LOW to RAS HIGH delay time
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-41
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM TIMING PARAMETERS (continued)
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ T ≤ +125°C; VCC = 5V ±10%)
A
AC CHARACTERISTICS
PARAMETER
-8
-10
-12
SYM
tWCS
tWCH
tWCR
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX UNITS NOTES
Write command setup time
Write command hold time
ns
ns
ns
21
15
60
20
70
25
80
Write command hold time
(referenced to RAS)
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWP
tRWL
tCWL
tDS
tDH
tDHR
15
20
20
0
20
25
25
0
25
30
30
0
ns
ns
ns
ns
ns
ns
22
22
Data-in hold time
15
60
20
70
25
80
Data-in hold time
(referenced to RAS)
RAS to WE delay time
tRWD
tAWD
105
65
125
75
150
90
ns
ns
21
21
Column address
to WE delay time
CAS to WE delay time
tCWD
tT
tREF
tRPC
tCSR
45
3
50
3
60
3
ns
ns
ms
ns
ns
21
Transition time (rise or fall)
Refresh period (512 cycles)
50
8
50
8
50
8
9, 10
R
A
/
0
0
0
C
A
/
10
10
10
5
5
(/C/A/
tCHR
15
20
25
ns
(/C/A/
tWSR
tRWH
tMS
0
15
0
0
15
0
0
15
0
ns
ns
ns
ns
?M/
Mask Data to RAS setup time
Mask Data to RAS hold time
tMH
15
15
15
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-42
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
TRANSFER AND MODE CONTROL TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes 6, 7, 8, 9, 10) (-55° C ≤ T ≤ +125°C; VCC = 5V ±10%)
A
AC CHARACTERISTICS
PARAMETER
-8
-10
-12
SYM
tTLS
tTLH
tRTH
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
UNITS NOTES
T
R/(OE) LOW to RAS setup time
ns
ns
ns
TR/(OE) LOW to RAS hold time
10
75
10,000
10,000
15
80
10,000
10,000
15
90
10,000
10,000
TR/(OE) LOW to RAS hold time
(REAL-TIME READ TRANSFER only)
TR/(OE) LOW to CAS hold time
tCTH
25
25
30
ns
(REAL-TIME READ TRANSFER only)
TR/(OE) HIGH to SC lead time
tTSL
tTRP
tTRW
tTSD
5
5
5
ns
ns
ns
ns
TR/(OE) HIGH to RAS precharge time
60
20
15
70
30
15
80
35
15
/T/R/(OE) precharge time
First SC edge to TR/(OE) HIGH
delay time
Serial output buffer turn-off
delay from RAS
tSDZ
7
40
7
40
7
40
ns
SC to RAS setup time
tSRS
tSZE
tSDD
tSZS
tESR
30
0
35
0
40
0
ns
ns
ns
ns
ns
Serial data input to SE delay time
Serial data input delay from RAS
Serial data input to RAS delay time
50
0
50
0
55
0
Serial-input-mode enable
(SE) to RAS setup time
0
0
0
Serial-input-mode enable
tREH
10
15
15
ns
(/S/
tYS
tYH
0
10
0
0
15
0
0
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
/
DSF to RAS setup time
DSF to RAS hold time
SC to QSF delay time
tFSR
tRFH
tSQD
tSTS
tSTH
tRQD
tFHR
tFSC
tCFH
tTQD
tCQD
tRSD
tCSD
10
15
15
30
75
30
75
30
75
SPLIT TRANSFER setup time
SPLIT TRANSFER hold time
RAS to QSF delay time
DSF to RAS hold time
DSF to CAS setup time
DSF to CAS hold time
30
0
30
0
30
0
60
0
70
0
80
0
15
20
25
T
R/OE to QSF delay time
30
40
30
40
30
40
/C/A/
R
A
/
85
30
100
40
115
45
CAS to first SC delay
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-43
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
SAM TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes 6, 7, 8, 9, 10) (-55° C ≤ T ≤ +125°C; VCC = 5V ±10%)
A
AC CHARACTERISTICS
-8
-10
-12
PARAMETER
SYM
tSC
tSAC
tSP
tSAS
tSEA
tSEP
tSE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
Serial clock-cycle time
Access time from SC
25
30
35
ns
25
30
35
ns
ns
ns
ns
ns
ns
ns
24, 28
24
SC precharge time (SC LOW time)
SC pulse width (SC HIGH time)
Access time from SE
10
10
10
10
10
10
20
15
25
15
30
15
SE precharge time
7
10
0
10
15
0
15
15
0
SE pulse width
Serial data-out hold time after
SC high
tSOH
24, 28
20, 24
Serial output buffer turn-off
delay from SE
tSEZ
0
0
0
ns
Serial data-in setup time
Serial data-in hold time
tSDS
tSDH
tSWS
0
10
0
0
15
0
0
20
0
ns
ns
ns
Serial input (Write) Enable
setup time
Serial input (Write) Enable
hold time
tSWH
tSWIS
tSWIH
15
0
20
0
25
0
ns
ns
ns
Serial input (Write) disable
setup time
Serial input (Write) disable
hold time
15
20
25
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-44
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
NOTES
t
t
1. All voltages referenced to VSS.
19. Either RCH or RRH must be satisfied for a READ
cycle.
2. This parameter is sampled. VCC = 5V ±10%, f = 1 MHz.
3. ICC is dependent on cycle rates.
4. ICC is dependent on I/ O loading. Specified values are
obtained with minimum cycle time and the I/ Os
open.
t
t
t
20. OD, OFF and SEZ define the time when the output
achieves open circuit (VOH -200mV, VOL +200mV).
This parameter is sampled and not 100 percent tested.
t
t
t
t
21. WCS, RWD, AWD and CWD are restrictive
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
operating parameters in LATE-WRITE, READ-WRITE
t
and READ-MODIFY-WRITE cycles only. If WCS ≥
t
WCS (MIN), the cycle is an EARLY-WRITE cycle and
temperature range (-55°C ≤ T ≤ +125°C) is assured.
the data output will remain an open circuit through-
A
t
7. An initial pause of 100µs is required after power-up
followed by any eight RAS cycles before proper
device operation is assured. The eight RAS cycle
out the entire cycle, regardless of TR/ OE. If WCS ≤
t
WCS (MIN), the cycle is a LATE-WRITE and
TR/ OE must control the output buffers during the
t
t
t
wake-up should be repeated any time the REF
WRITE to avoid data contention. If RWD ≥ RWD
t
t
t
t
refresh requirement is exceeded.
(MIN), AWD ≥ AWD (MIN) and CWD ≥ CWD
(MIN), the cycle is a READ-WRITE and the data
output will contain data read from the selected cell. If
neither of the above conditions is met, the state of the
output buffers (at access time and until CAS goes
back to VIH) is indeterminate but the WRITE will be
t
8. AC characteristics assume T = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH). Input signals transition between 0V and 3V
for AC testing.
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, DRAM data output (DQ1-DQ4) is
High-Z.
12. If CAS = VIL, DRAM data output (DQ1-DQ4) may
contain data from the last valid READ cycle.
13. DRAM output timing measured with a load equiva-
lent to 2 TTL gates and 100pF. Output reference
levels: VOH = 2.0V; VOL = 0.8V.
t
t
valid, if OD and OEH are met. See the LATE-WRITE
AC Timing diagram.
22. These parameters are referenced to CAS leading edge
in EARLY-WRITE cycles and ME/ WE leading edge in
LATE-WRITE or READ-WRITE cycles.
23. During a READ cycle, if TR/ OE is LOW then taken
HIGH, DQ goes open. The DQs will go open with OE
or CAS, whichever goes HIGH first.
24. SAM output timing is measured with a load
equivalent to 1 TTL gate and 30pF. Output reference
levels: VOH = 2.0V; VOL = 0.8V.
t
t
t
t
t
14. Assumes that RCD < RCD (MAX). If RCD is greater
than the maximum recommended value shown in this
25. OD and OEH must be met in LATE-WRITE and
READ-MODIFY-WRITE cycles (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide previously read data if CAS
t
t
table, RAC will increase by the amount that RCD
exceeds the value shown.
t
t
15. Assumes that RCD ≥ RCD (MAX).
t
16. If CAS is LOW at the falling edge of RAS, DQ will be
maintained from the previous cycle. To initiate a new
cycle and clear the data out buffer, CAS must be
remains LOW and OE is taken LOW after OEH is
met. If CAS goes HIGH prior to OE going back LOW,
the DQs will remain open.
t
pulsed HIGH for CPN.
26. Address (A0-A8) may be changed two times or less
while RAS = VIL.
t
17. Operation within the RCD (MAX) limit ensures that
t
t
RAC (MAX) can be met. RCD (MAX) is specified as
27. Address (A0-A8) may be changed once or less while
CAS = VIH and RAS = VIL.
t
a reference point only; if RCD is greater than the
specified RCD (MAX) limit, then access time is
controlled exclusively by CAC.
t
t
t
28. SAC is MAX at +125°C and 4.5V Vcc; SOH is MIN at
-55°C and 5.5V Vcc. These limits will not occur
t
t
18. Operation within the RAD (MAX) limit ensures that
simultaneously at any given voltage or temperature.
t
t
t
t
RCD (MAX) can be met. RAD (MAX) is specified as
SOH = SAC - output transition time; this is guaran-
teed by design.
t
a reference point only; if RAD is greater than the
specified RAD (MAX) limit, then access time is
controlled exclusively by AA.
t
t
MT42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-45
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM READ CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
t
RRH
RSH
t
t
t
CAS
CRP
RCD
V
V
IH
IL
CAS
t
t
AR
t
t
RAD
RAL
t
t
t
ASR
RAH
ASC
CAH
V
V
IH
IL
ADDR
ROW
ROW
COLUMN
t
t
RCH
RCS
V
V
IH
IL
ME/WE
DSF
t
FHR
t
t
CFH
t
t
RFH
FSC
FSR
V
V
IH
IL
t
AA
t
RAC
t
OFF
t
CAC
t
ROH
V
V
IOH
IOL
DQ
OPEN
OPEN
VALID DATA
t
t
YH
YS
t
t
OE
OD
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-46
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM FAST-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS
CAS
t
t
t
PC
RSH
CSH
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
t
AR
t
t
RAD
RAL
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
t
ROW
COLUMN
t
t
RRH
RCS
t
RCH
RCS
t
RCS
t
t
RCH
RCH
V
V
IH
IL
ME/WE
t
t
FHR
FSC
t
t
t
t
t
t
t
FSR
RFH
CFH
FSC
CFH
FSC
CFH
V
V
IH
IL
DSF
t
t
t
AA
AA
AA
t
t
t
t
CPA
RAC
CPA
t
t
OFF
t
t
CAC
OFF
CAC
CAC
t
OFF
t
t
CLZ
CLZ
V
V
IOH
IOL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OPEN
t
t
YH
t
t
t
t
t
t
YS
OE
OD
OE
OD
OE
OD
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: WRITE cycles or READ-MODIFY-WRITE cycles may be mixed with READ cycles while in FAST PAGE MODE.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-47
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
WRITE CYCLE FUNCTION TABLE 1
LOGIC STATES
RAS Falling Edge
CAS Falling Edge
2
FUNCTION
A
B
C
D
E
ME/WE DSF
DQ (Input)
DSF
DQ (Input)
Normal DRAM WRITE
1
0
0
0
X
0
0
DRAM Data
NONPERSISTENT (Load and Use)
MASKED WRITE to DRAM
Write
Mask
DRAM
Data (Masked)
PERSISTENT (Use Register)
MASKED WRITE to DRAM
0
1
X
0
DRAM
Data (Masked)
3
BLOCK WRITE to DRAM (No Data Mask)
1
0
0
0
X
1
1
Column Mask
NONPERSISTENT (Load and Use)
MASKED BLOCK WRITE to DRAM
Write
Mask
Column
3
Mask
PERSISTENT (Use Register)
MASKED BLOCK WRITE to DRAM
0
1
X
1
Column
Mask
3
Load Mask Register
Load Color Register
1
1
1
1
X
X
0
1
Write Mask
Color Data
NOTE: 1. Refer to this function table to determine the logic states of “A”, “B”, “C”, “D” and “E” for the WRITE cycle
timing diagrams on the following pages.
2. CAS or ME/WE, whichever occurs later (Except BLOCK WRITE).
3. WE = “don’t care” for BLOCK WRITE. The DQ column-mask data will be latched at the falling edge of CAS,
regardless of the state of ME/WE.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-48
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM EARLY-WRITE CYCLE 1
t
RC
t
t
RAS
RP
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
CAS
CRP
RCD
V
V
IH
IL
CAS
t
AR
t
t
RAD
RAL
t
t
t
ASC
t
ASR
RAH
CAH
V
V
IH
IL
ADDR
ROW
ROW
COLUMN
t
CWL
t
RWL
t
WCR
t
t
WCH
WCS
t
t
t
WSR
RWH
t
WP
V
V
IH
IL
ME/WE
A
B
NOTE 2
t
FHR
t
FSR
RFH
t
t
CFH
FSC
V
V
IH
IL
DSF
D
t
DHR
t
t
DH
DS
t
t
MS
MH
V
V
IOH
IOL
DQ
E
C
t
t
YS
YH
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: 1. The logic states of “A”, “B”, “C”, “D” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
2. For BLOCK WRITE, ME/WE = “don’t care.” For all other EARLY-WRITE cycles, ME/WE = LOW.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-49
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM LATE-WRITE CYCLE 1
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
CAS
CRP
RCD
V
V
IH
IL
CAS
t
AR
t
t
RAD
RAL
t
t
t
t
RAH
ASC
CAH
ASR
V
V
IH
IL
ADDR
ROW
COLUMN
t
CWL
t
RWL
t
t
RWH
t
WSR
WP
V
V
IH
IL
ME/WE
A
t
t
FHR
FSC
t
t
t
FSR
RFH
CFH
V
V
IH
IL
DSF
B
C
t
DHR
t
t
DH
t
t
t
DS
MS
YS
MH
V
V
IOH
IOL
DQ
E
t
t
t
OEH
YH
OD
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: 1. The logic states of “A”, “B”, “C” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-50
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM READ-WRITE CYCLE
(READ-MODIFY-WRITE CYCLE)
t
RWC
t
t
RAS
RP
V
V
IH
IL
RAS
CAS
t
CSH
t
RSH
t
t
t
RCD
CAS
CRP
V
V
IH
IL
t
AR
t
t
RAD
RAL
t
t
t
ASC
t
ASR
RAH
CAH
V
V
IH
IL
ADDR
ROW
ROW
COLUMN
t
t
RWD
CWL
t
t
CWD
t
RCS
RWL
t
t
t
t
WSR
RWH
AWD
WP
V
V
IH
IL
ME/WE
A
B
t
FHR
t
t
t
t
FSR
RFH
FSC
CFH
V
V
IH
IL
DSF
t
AA
t
RAC
t
CAC
t
t
t
t
MS
YS
MH
DS
DH
V
V
IOH
IOL
DQ
VALID D
OPEN
C
E
OUT
t
t
t
t
OE
OD
YH
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: The logic states of “A”, “B”, “C” and “E” determine the type of WRITE operation performed. See the Write Cycle
Function Table for a detailed description.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-51
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM FAST-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
V
V
IH
IL
RAS
CAS
t
t
t
PC
CSH
RSH
t
CRP
t
t
t
t
t
t
CAS
RCD
CAS
CP
CAS
CP
t
CP
V
V
IH
IL
t
AR
t
t
RAD
RAL
t
CAH
t
t
t
t
t
t
ASC
t
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
COLUMN
COLUMN
t
COLUMN
t
ROW
ROW
t
CWL
CWL
CWL
t
t
t
t
WCS
t
t
WCH
WCS
WCH
WCS
WCH
t
t
t
WP
t
t
RWH
WP
WP
WSR
V
V
IH
IL
ME/WE
A
B
A
B
t
FHR
t
t
t
t
t
t
CFH
t
t
FSC
FSR
RFH
CFH
FSC
CFH
FSC
V
V
IH
IL
DSF
D
E
D
E
D
E
t
t
WCR
RWL
t
DHR
t
t
t
t
t
t
DH
t
t
MH
DS
DH
DS
DH
DS
MS
V
V
IOH
IOL
DQ
C
t
t
YH
YS
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: 1. READ cycles or READ-MODIFY-WRITE cycles can be mixed with WRITE cycles while in FAST PAGE
MODE.
2. The logic states of “A”, “B”, “C”, “D” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-52
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM FAST-PAGE-MODE READ-WRITE CYCLE
(READ-MODIFY-WRITE OR LATE-WRITE CYCLES)
t
RASP
t
RP
V
V
IH
IL
RAS
CAS
t
t
t
PRWC
t
RSH
CSH
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
t
AR
t
t
RAD
RAL
t
CAH
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ROW
ADDR
COLUMN
COLUMN
ROW
COLUMN
t
RWD
t
t
t
RWL
CWL
WP
t
RCS
t
t
t
CWL
CWL
WP
t
WP
t
t
t
AWD
AWD
AWD
t
t
WSR
FSR
RWH
RFH
t
t
t
CWD
CWD
CWD
V
V
IH
IL
ME/WE
DSF
A
B
t
t
t
t
t
t
CFH
FSC
CFH
FSC
CFH
FSC
t
t
V
V
IH
IL
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
DS
t
t
CPA
CPA
t
t
t
DS
DS
t
t
t
t
CAC
CAC
CLZ
CAC
CLZ
t
t
MS
MH
t
V
V
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
IOH
IOL
DQ
OPEN
D
D
D
D
D
D
C
t
OEH
t
t
OD
OD
t
t
t
OD
YS
YH
t
t
t
OE
OE
OE
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: 1. READ or WRITE cycles can be mixed with READ-MODIFY-WRITE cycles while in FAST PAGE MODE. Use
the Write Function Table to determine the proper DSF state for the desired WRITE operation.
2. The logic states of “A”, “B” and “C” determine the type of WRITE operation performed. See the Write Cycle
Function Table for a detailed description.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-53
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM RAS-ONLY REFRESH CYCLE
(ADDR = A0-A8)
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CRP
t
RPC
V
V
IH
IL
CAS
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
V
IH
IL
ME/WE
V
V
IH
IL
DSF
DQ
V
V
IOH
IOL
OPEN
OPEN
t
t
YH
YS
V
V
IH
IL
TR/OE
DRAM CAS-BEFORE-RAS REFRESH CYCLE
t
t
t
RAS
t
RAS
RP
RP
V
V
IH
IL
RAS
t
RPC
t
t
t
t
t
t
CSR
CHR
RPC
CSR
CHR
CP
V
V
IH
IL
CAS
V
V
IH
IL
ADDR
V
V
IH
IL
ME/WE
DSF
V
V
IH
IL
V
V
IOH
IOL
DQ
OPEN
OPEN
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
MT42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-54
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
DRAM HIDDEN-REFRESH CYCLE
(READ)
(REFRESH)
t
t
t
RAS
RP
RAS
V
V
IH
IL
RAS
CAS
t
t
t
t
CRP
RCD
RSH
CHR
V
V
IH
IL
t
AR
t
t
RAD
RAL
t
t
t
RAH
t
ASR
ASC
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
RCS
t
t
RRH
V
V
IH
IL
ME/WE
t
FHR
t
t
FSC
CFH
t
t
RFH
FSR
V
V
IH
IL
DSF
t
AA
t
RAC
t
CAC
t
OFF
V
V
IOH
IOL
DQ
VALID D
OPEN
OPEN
OUT
t
t
YH
t
YS
OE
t
OD
t
ROH
V
V
IH
IL
TR/OE
DON’T CARE
UNDEFINED
NOTE: A HIDDEN REFRESH may also be performed after a WRITE or TRANSFER cycle. In the WRITE case,
ME/WE = LOW (when CAS goes LOW) and TR/OE = HIGH and the DQ pins stay High-Z. In the TRANSFER
case, TR/OE = LOW (when RAS goes LOW) and the DQ pins stay High-Z during the refresh period, regardless
of TR/OE.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-55
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
READ TRANSFER 3
(DRAM-TO-SAM TRANSFER)
(When part was previously in the SERIAL INPUT mode or SC idle)
t
RC
t
t
t
RAS
CSH
RP
V
V
IH
IL
RAS
t
RSH
t
t
t
RCD
CRP
CAS
V
V
IH
IL
CAS
t
AR
t
t
RAL
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ME/WE
DSF
ROW
SAM START (TAP)
t
t
RWH
WSR
V
V
IH
IL
t
t
FSR
OFF
RFH
V
V
IH
IL
t
V
V
IOH
IOL
DQ
OPEN
OPEN
t
CSD
t
RSD
t
t
t
TRP
TLS
TLH
V
V
IH
IL
TR/OE
t
TRW
t
t
t
SC
RTH
SRS
t
t
t
t
SP
SAS
TSD
SAS
V
V
IH
IL
SC
NOTE 1
t
SDH
SDS
t
t
t
t
SAC
SAC
SOH
t
SZS
V
V
IOH
IOL
SDQ
VALID D
VALID D
VALID D
VALID D
OUT
IN
OUT
OUT
t
SEA
t
t
TQD
SWH
V
V
IH
IL
SE
t
CQD
t
RQD
V
V
OH
OL
QSF
NOTE 2
NOTE 2
DON’T CARE
UNDEFINED
NOTE: 1. There must be no rising edges on the SC input during this time period.
2. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
t
t
t
3. If TLH is timing for the TR/(OE) rising edge, the transfer is self-timed and the CSD and RSD times must be
t
met. If RTH is timing for the TR/(OE) rising edge, the transfer is done off of the TR/(OE) rising edge and
t
TSD must be met.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-56
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
REAL-TIME READ-TRANSFER
(DRAM-TO-SAM TRANSFER)
(When part was previously in the SERIAL OUTPUT mode)
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
CRP
RCD
CAS
V
V
IH
IL
CAS
t
AR
t
t
t
RAL
RAD
t
t
RAH
t
ASR
ASC
CAH
V
V
IH
IL
ADDR
SAM START
ROW
t
t
WSR
FSR
RWH
V
V
IH
IL
ME/WE
DSF
t
t
RFH
V
V
IH
IL
t
OFF
V
V
IOH
IOL
DQ
OPEN
OPEN
t
t
TRP
CTH
t
t
t
TRW
TLS
RTH
V
V
IH
IL
TR/OE
t
t
TSD
t
TSL
SC
t
t
t
SP
SP
SAS
V
V
IH
IL
SC
t
SAC
PREVIOUS ROW DATA
NEW ROW DATA
V
V
VALID
D
IOH
IOL
SDQ
VALID D
VALID D
t
VALID D
OUT
VALID D
OUT
VALID D
OUT
OUT
OUT
OUT
t
t
TQD
SEA
SEA
t
SEZ
t
t
SE
SEP
V
V
IH
IL
SE
NOTE 1
V
V
OH
OL
QSF
NOTE 2
NOTE 2
DON’T CARE
UNDEFINED
NOTE: 1. The SE pulse is shown to illustrate the SERIAL OUTPUT
ENABLE and DISABLE timing. It is not required.
2. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-57
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
SPLIT READ TRANSFER
(SPLIT DRAM-TO-SAM TRANSFER)
t
RC
t
t
RAS
RP
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
RCD
t
CRP
CAS
V
V
IH
IL
CAS
t
AR
t
t
RAL
RAD
t
t
t
t
RAH
ASC
ASR
t
CAH
V
V
IH
IL
ADDR
ROW
SAM START (B)
t
WSR
RWH
V
V
IH
IL
ME/WE
DSF
t
t
FSR
RFH
V
V
IH
IL
t
OFF
V
V
IOH
IOL
DQ
OPEN
OPEN
t
t
TLH
TLS
V
V
IH
IL
TR/OE
t
STH
t
STS
t
SC
t
t
t
SP
SP
SAS
V
V
IH
IL
SC
t
t
SAC
SAC
SOH
t
t
SOH
V
V
IOH
IOL
SDQ
SE
511 (255)
A (256 + A)
253 (509)
254 (510)
255 (511)
256 + B(B)
V
IH
V
IL
t
SQD
t
SQD
V
V
OH
OL
QSF
SAM MSB
(NOTE 1)
NEW MSB
DON’T CARE
UNDEFINED
NOTE: 1. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-58
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
WRITE TRANSFER and PSEUDO WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
(When part was previously in the SERIAL OUTPUT mode)
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
RCD
t
CRP
CAS
V
V
IH
IL
CAS
t
AR
t
t
RAD
t
RAL
RAH
t
t
CAH
t
ASC
ASR
V
V
IH
IL
ADDR
ROW
SAM START
t
t
WSR
RWH
RFH
V
V
IH
IL
ME/WE
t
t
FSR
V
V
IH
IL
DSF
DQ
t
OFF
V
V
IOH
IOL
OPEN
OPEN
t
CSD
t
t
t
TLH
TLS
V
V
IH
IL
TR/OE
t
t
SC
RSD
SRS
t
t
SP
t
t
SAS
SAS
SP
V
V
IH
IL
SC
NOTE 3
t
SDD
t
t
t
t
t
t
SOH
SDZ
SDS
SDH
SDS
SDH
IN
V
V
IOH
IOL
SQD
VALID D
VALID D
VALID D
VALID D
HIGH Z
IN
OUT
t
OUT
t
t
SWS
SWIS
t
ESR
REH
V
V
IH
IL
SE
NOTE 1
NOTE 2
t
CQD
t
RQD
V
V
OH
OL
QSF
NOTE 4
NOTE 4
DON’T CARE
UNDEFINED
NOTE: 1. If SE is LOW, the SAM data will be transferred to the DRAM.
If SE is HIGH, the SAM data will not be transferred to the DRAM (SERIAL-INPUT-MODE ENABLE cycle).
2. SE must be LOW to input new serial data, but the serial address register is incremented by SC regardless
of SE.
3. There must be no rising edges on the SC input during this time period.
4. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-59
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
(When part was previously in the SERIAL INPUT mode)
t
RC
t
t
RP
RAS
CSH
V
V
IH
IL
RAS
t
t
RSH
t
t
RCD
t
CRP
CAS
V
V
IH
IL
CAS
t
t
AR
t
t
RAD
t
RAL
RAH
t
t
CAH
ASC
ASR
V
V
IH
IL
ADDR
ROW
SAM START
t
t
t
WSR
RWH
RFH
V
V
IH
IL
ME/WE
t
FSR
OFF
V
V
IH
IL
DSF
DQ
t
V
V
IOH
IOL
OPEN
OPEN
t
t
TLH
TLS
t
CSD
V
V
IH
IL
TR/OE
t
t
t
SC
SRS
RSD
t
t
t
t
SAS
SAS
SP
SP
V
V
IH
IL
SC
NOTE 2
t
t
SDH
SDS
t
t
SDH
t
SDS
SDS
V
V
IOH
IOL
VALID D
VALID D
VALID D
SDQ
IN
IN
IN
t
t
SWS
t
t
ESR
REH
SWIS
V
V
IH
IL
SE
NOTE 1
t
CQD
t
RQD
V
V
OH
OL
QSF
NOTE 3
NOTE 3
DON’T CARE
UNDEFINED
NOTE: 1. SE must be LOW to input new serial data, but the serial address
register is incremented by SC regardless of SE.
2. There must be no rising edges on the SC input during this time period.
3. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-60
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
ALTERNATE WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
t
RC
t
t
RAS
RP
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
RCD
t
CRP
CAS
V
V
IH
IL
CAS
t
AR
t
t
RAD
t
RAL
RAH
t
t
CAH
t
ASC
ASR
V
V
IH
IL
ADDR
ROW
SAM START
t
t
WSR
RWH
V
V
IH
IL
ME/WE
t
t
RFH
FSR
V
V
IH
IL
DSF
DQ
t
OFF
V
V
IOH
IOL
OPEN
OPEN
t
t
TLH
TLS
t
CSD
V
V
IH
IL
TR/OE
t
t
t
SRS
SAS
RSD
SC
t
t
SP
t
t
SAS
SP
V
V
IH
IL
SC
NOTE 2
t
SDD
t
t
t
t
t
t
SOH
SDZ
SDS
SDH
SDS
SDH
IN
V
V
IOH
IOL
VALID D
VALID D
SDQ
VALID D
VALID D
HIGH-Z
IN
OUT
OUT
t
t
SWS
SWIS
V
V
IH
IL
SE
NOTE 1
t
CQD
t
RQD
V
V
OH
OL
QSF
NOTE 3
NOTE 3
DON’T CARE
UNDEFINED
NOTE: 1. SE must be LOW to input new serial data, but the serial address register
is incremented by SC regardless of SE.
2. There must be no rising edges on the SC input during this time period.
3. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-61
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
SAM SERIAL INPUT
t
t
t
t
t
SWH
SWIS
SWIH
SWS
V
V
IH
IL
SE
t
t
t
SC
SC
SC
t
t
t
t
t
t
SAS
SP
SAS
SP
SAS
SP
SAS
V
V
IH
IL
SC
t
t
t
t
t
t
SDH
SDS
SDH
SZE
SDS
SDH
V
V
IH
IL
A - 1
A
A + 2
A + 3
SDQ
SAM SERIAL OUTPUT
t
SEP
V
V
IH
IL
SE
t
t
t
SC
SC
SC
t
t
t
t
t
t
SP
SAS
SP
SAS
SP
SAS
V
V
IH
IL
SC
t
t
t
t
SAC
SAC
SAC
t
SAC
t
t
t
t
SOH
SOH
SEZ
SOH
SEA
V
V
OH
OL
A - 1
A
A + 1
A + 2
A + 3
SDQ
DON’T CARE
UNDEFINED
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-62
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883 TEST REQUIREMENTS
(per Method 5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
*
PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-63
MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-64
相关型号：
©2020 ICPDF网 联系我们和版权申明