MT48LC32M16A2TG-75L:C

512Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC128M4A2 – 32 Meg x 4 x 4 banks

MT48LC64M8A2 – 16 Meg x 8 x 4 banks

MT48LC32M16A2 – 8 Meg x 16 x 4 banks

Options

Marking

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode

• Auto refresh

• Configurations

– 128 Meg x 4 (32 Meg x 4 x 4 banks)

– 64 Meg x 8 (16 Meg x 8 x 4 banks)

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

• Write recovery (^tWR)

128M4

64M8

32M16

–

^tWR = 2 CLK¹

A2

• Plastic package – OCPL²

– 54-pin TSOP II (400 mil) (standard)

– 54-pin TSOP II (400 mil) Pb-free

• Timing – cycle time

TG

P

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

• Self refresh

– Standard

– Low power

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

• Revision

-75

-7E³

– 64ms, 8192-cycle refresh (commercial and

industrial)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

None

L⁴

None

IT

:C

1. See technical note TN-48-05 on

Micron's Web site.

Notes:

2. Off-center parting line.

3. Available on x4 and x8 only.

4. Contact Micron for availability.

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Access Time

CL = 2

Clock

Speed Grade

Frequency

143 MHz

133 MHz

100 MHz

CL = 3

5.4ns

–

Setup Time

1.5ns

Hold Time

0.8ns

-7E

-75

-7E

-75

–

1.5ns

0.8ns

5.4ns

6ns

1.5ns

0.8ns

–

1.5ns

0.8ns

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1

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x4, x8, x16 SDRAM

Features

Table 2: Address Table

32 Meg

Parameter

32 Meg x 4

32 Meg x 4 x 4 banks

8K

32 Meg x 8

x 16

8 Meg x 16 x 4 banks

8K

Configuration

Refresh count

Row addressing

Bank addressing

16 Meg x 8 x 4 banks

8K

8K A[12:0]

4 BA[1:0]

Column

4K A[9:0], A11, A12

2K A[9:0], A11

1K A[9:0]

addressing

Table 3: 512Mb SDR Part Numbering

Part Numbers

MT48LC128M4A2P

MT48LC128M4A2TG

MT48LC64M8A2P

MT48LC64M8A2TG

MT48LC32M16A2P

MT48LC32M16A2TG

Architecture

Package

128 Meg x 4

64 Meg x 8

32 Meg x 16

54-pin TSOP II

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512Mb: x4, x8, x16 SDRAM

Features

Contents

General Description ......................................................................................................................................... 6

Functional Block Diagrams ............................................................................................................................... 7

Pin and Ball Assignments and Descriptions ..................................................................................................... 10

Package Dimensions ....................................................................................................................................... 12

Temperature and Thermal Impedance ............................................................................................................ 13

Electrical Specifications .................................................................................................................................. 15

Electrical Specifications – I_DDParameters ........................................................................................................ 17

Electrical Specifications – AC Operating Conditions ......................................................................................... 18

Functional Description ................................................................................................................................... 21

Commands .................................................................................................................................................... 22

COMMAND INHIBIT .................................................................................................................................. 22

NO OPERATION (NOP) ............................................................................................................................... 23

LOAD MODE REGISTER (LMR) ................................................................................................................... 23

ACTIVE ...................................................................................................................................................... 23

READ ......................................................................................................................................................... 24

WRITE ....................................................................................................................................................... 25

PRECHARGE .............................................................................................................................................. 26

BURST TERMINATE ................................................................................................................................... 26

REFRESH ................................................................................................................................................... 27

AUTO REFRESH ..................................................................................................................................... 27

SELF REFRESH ....................................................................................................................................... 27

Truth Tables ................................................................................................................................................... 28

Initialization .................................................................................................................................................. 33

Mode Register ................................................................................................................................................ 35

Burst Length .............................................................................................................................................. 37

Burst Type .................................................................................................................................................. 37

CAS Latency ............................................................................................................................................... 39

Operating Mode ......................................................................................................................................... 39

Write Burst Mode ....................................................................................................................................... 39

Bank/Row Activation ...................................................................................................................................... 40

READ Operation ............................................................................................................................................. 41

WRITE Operation ........................................................................................................................................... 50

Burst Read/Single Write .............................................................................................................................. 57

PRECHARGE Operation .................................................................................................................................. 58

Auto Precharge ........................................................................................................................................... 58

AUTO REFRESH Operation ............................................................................................................................. 70

SELF REFRESH Operation ............................................................................................................................... 72

Power-Down .................................................................................................................................................. 74

Clock Suspend ............................................................................................................................................... 75

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512Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 128 Meg x 4 Functional Block Diagram ............................................................................................... 7

Figure 2: 64 Meg x 8 Functional Block Diagram ................................................................................................. 8

Figure 3: 32 Meg x 16 Functional Block Diagram ............................................................................................... 9

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 10

Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 12

Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 14

Figure 7: ACTIVE Command .......................................................................................................................... 23

Figure 8: READ Command ............................................................................................................................. 24

Figure 9: WRITE Command ........................................................................................................................... 25

Figure 10: PRECHARGE Command ................................................................................................................ 26

Figure 11: Initialize and Load Mode Register .................................................................................................. 34

Figure 12: Mode Register Definition ............................................................................................................... 36

Figure 13: CAS Latency .................................................................................................................................. 39

t

Figure 14: Example: Meeting ^tRCD (MIN) When 2 < RCD (MIN)/^tCK < 3 .......................................................... 40

Figure 15: Consecutive READ Bursts .............................................................................................................. 42

Figure 16: Random READ Accesses ................................................................................................................ 43

Figure 17: READ-to-WRITE ............................................................................................................................ 44

Figure 18: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 45

Figure 19: READ-to-PRECHARGE .................................................................................................................. 45

Figure 20: Terminating a READ Burst ............................................................................................................. 46

Figure 21: Alternating Bank Read Accesses ..................................................................................................... 47

Figure 22: READ Continuous Page Burst ......................................................................................................... 48

Figure 23: READ – DQM Operation ................................................................................................................ 49

Figure 24: WRITE Burst ................................................................................................................................. 50

Figure 25: WRITE-to-WRITE .......................................................................................................................... 51

Figure 26: Random WRITE Cycles .................................................................................................................. 52

Figure 27: WRITE-to-READ ............................................................................................................................ 52

Figure 28: WRITE-to-PRECHARGE ................................................................................................................. 53

Figure 29: Terminating a WRITE Burst ............................................................................................................ 54

Figure 30: Alternating Bank Write Accesses ..................................................................................................... 55

Figure 31: WRITE – Continuous Page Burst ..................................................................................................... 56

Figure 32: WRITE – DQM Operation ............................................................................................................... 57

Figure 33: READ With Auto Precharge Interrupted by a READ ......................................................................... 59

Figure 34: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 60

Figure 35: READ With Auto Precharge ............................................................................................................ 61

Figure 36: READ Without Auto Precharge ....................................................................................................... 62

Figure 37: Single READ With Auto Precharge .................................................................................................. 63

Figure 38: Single READ Without Auto Precharge ............................................................................................. 64

Figure 39: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 65

Figure 40: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 65

Figure 41: WRITE With Auto Precharge ........................................................................................................... 66

Figure 42: WRITE Without Auto Precharge ..................................................................................................... 67

Figure 43: Single WRITE With Auto Precharge ................................................................................................. 68

Figure 44: Single WRITE Without Auto Precharge ............................................................................................ 69

Figure 45: Auto Refresh Mode ........................................................................................................................ 71

Figure 46: Self Refresh Mode .......................................................................................................................... 73

Figure 47: Power-Down Mode ........................................................................................................................ 74

Figure 48: Clock Suspend During WRITE Burst ............................................................................................... 75

Figure 49: Clock Suspend During READ Burst ................................................................................................. 76

Figure 50: Clock Suspend Mode ..................................................................................................................... 77

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512Mb: x4, x8, x16 SDRAM

Features

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Address Table ..................................................................................................................................... 2

Table 3: 512Mb SDR Part Numbering ............................................................................................................... 2

Table 4: Pin and Ball Descriptions .................................................................................................................. 11

Table 5: Temperature Limits .......................................................................................................................... 13

Table 6: Thermal Impedance Simulated Values ............................................................................................... 14

Table 7: Absolute Maximum Ratings .............................................................................................................. 15

Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 15

Table 9: Capacitance ..................................................................................................................................... 16

Table 10: I_DDSpecifications and Conditions (-7E, -75) ..................................................................................... 17

Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) ............................. 18

Table 12: AC Functional Characteristics (-7E, -75) ........................................................................................... 19

Table 13: Truth Table – Commands and DQM Operation ................................................................................. 22

Table 14: Truth Table – Current State Bank n, Command to Bank n .................................................................. 28

Table 15: Truth Table – Current State Bank n, Command to Bank m ................................................................. 30

Table 16: Truth Table – CKE ........................................................................................................................... 32

Table 17: Burst Definition Table ..................................................................................................................... 38

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512Mb: x4, x8, x16 SDRAM

General Description

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain-

ing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchro-

nous interface (all signals are registered on the positive edge of the clock signal, CLK).

Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4

bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns

by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 col-

umns by 16 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the

bank; A[12:0] select the row). The address bits registered coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-

ation. This architecture is compatible with the 2n rule of prefetch architectures, but it

also allows the column address to be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank while accessing one of the other

three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-

dom-access operation.

The 512Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided, along with a power-saving, power-down mode. All inputs and out-

puts are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks to hide precharge time, and

the capability to randomly change column addresses on each clock cycle during a burst

access.

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512Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 1: 128 Meg x 4 Functional Block Diagram

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

REFRESH

COUNTER

13

MODE REGISTER

12

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

13

BANK0

MEMORY

ARRAY

1

8192

DQM

13

(8192 x 4096 x 4)

DECODER

DATA

SENSE AMPLIFIERS

OUTPUT

REGISTER

4

16384

I/O GATING

2

4

DQ[3:0]

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A[12:0]

BA[1:0]

ADDRESS

REGISTER

15

DATA

INPUT

REGISTER

2

4

4096

(x4)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

12

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512Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 2: 64 Meg x 8 Functional Block Diagram

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

REFRESH

COUNTER

13

MODE REGISTER

12

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

13

BANK0

MEMORY

ARRAY

1

8192

DQM

13

(8192 x 2048 x 8)

DECODER

DATA

OUTPUT

REGISTER

SENSE AMPLIFIERS

16384

8

I/O GATING

2

8

DQ[7:0]

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A[12:0]

BA[1:0]

ADDRESS

REGISTER

15

DATA

INPUT

REGISTER

2

8

2048

(x8)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

11

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512Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 3: 32 Meg x 16 Functional Block Diagram

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

REFRESH

COUNTER

13

MODE REGISTER

12

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

13

BANK0

MEMORY

ARRAY

2

8192

DQML,

DQMH

13

(8192 x 1024 x 16)

DECODER

DATA

OUTPUT

REGISTER

SENSE AMPLIFIERS

16384

16

I/O GATING

2

16

DQ[15:0]

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A[12:0]

BA[1:0]

ADDRESS

REGISTER

15

DATA

INPUT

REGISTER

2

16

1024

(x16)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

10

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512Mb: x4, x8, x16 SDRAM

Pin and Ball Assignments and Descriptions

Figure 4: 54-Pin TSOP (Top View)

x4

x8

x16

x8

x4

-

NC

-

DQ0

-

NC

DQ1

-

NC

DQ2

-

NC

DQ3

-

V_DD

DQ0

V_DDQ

DQ1

DQ2

V_SSQ

DQ3

DQ4

V_DDQ

DQ5

DQ6

V_SSQ

DQ7

V_DD

V_SS

DQ15 DQ7

V_SSQ

DQ14 NC

DQ13 DQ6

V_DDQ

DQ12 NC

DQ11 DQ5

V_SSQ

-

NC

-

NC

DQ3

-

NC

-

NC

DQ2

-

NC

-

1

2

3

4

5

6

7

8

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

-

NC

DQ0

-

NC

-

NC

DQ1

-

NC

-

NC

-

9

DQ10 NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ9

V_DDQ

DQ8

V_SS

DQ4

-

NC

-

NC

-

NC DQML

NC

-

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

A0

A1

A2

A3

V_DD

DQMH DQM DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

V_SS

-

1. The # symbol indicates that the signal is active LOW. A dash (-) indicates that the x8 and

x4 pin function is the same as the x16 pin function.

Notes:

2. Package may or may not be assembled with a location notch.

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512Mb: x4, x8, x16 SDRAM

Pin and Ball Assignments and Descriptions

Table 4: Pin and Ball Descriptions

Symbol

Type Description

CLK

Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

CKE

Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides precharge power-down and SELF REFRESH operation (all banks idle), active

power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-

gress). CKE is synchronous except after the device enters power-down and self refresh modes,

where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-

cluding CLK, are disabled during power-down and self refresh modes, providing low standby

power. CKE may be tied HIGH.

CS#

Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decod-

er. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in

progress will continue, and DQM operation will retain its DQ mask capability while CS# is

HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-

ered part of the command code.

CAS#, RAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

x4, x8:

DQM

Input Input/output mask: DQM is an input mask signal for write accesses and an output enable sig-

nal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle.

The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled

HIGH during a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On

the x16, DQML corresponds to DQ[7:0], and DQMH corresponds to DQ[15:8]. DQML and

DQMH are considered same state when referenced as DQM.

x16:

DQML, DQMH

LDQM, UDQM

(54-ball)

BA[1:0]

Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE

command is being applied.

A[12:0]

Input Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and

READ or WRITE command (column address A[9:0], A11, and A12 for x4; A[9:0] and A11 for x8;

A[9:0] for x16; with A10 defining auto precharge) to select one location out of the memory

array in the respective bank. A10 is sampled during a PRECHARGE command to determine if

all banks are to be precharged (A10 HIGH) or bank selected by A10 (LOW). The address inputs

also provide the op-code during a LOAD MODE REGISTER command.

x16:

DQ[15:0]

I/O

Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are NC for x8; and

pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NC for x4).

x8:

DQ[7:0]

Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4).

x4:

Data input/output: Data bus for x4.

DQ[3:0]

V_DDQ

V_SSQ

V_DD

V_SS

Supply DQ power: DQ power to the die for improved noise immunity.

Supply DQ ground: DQ ground to the die for improved noise immunity.

Supply Power supply: +3.3V ±0.3V.

Supply Ground.

NC

–

These should be left unconnected.

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512Mb: x4, x8, x16 SDRAM

Package Dimensions

Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P

0.10

1.2 MAX

0.375 ±0.075 TYP

Pin #1 ID

0.80 TYP

(for reference only)

22.22 ±0.08

2X R 0.75

2X R 1.00

2X 0.71

Plated lead finish: 90% Sn, 10% Pb or 100% Sn

Plastic package material: Epoxy novolac

Package width and length do not include

mold protrusion. Allowable protrusion is

0.25 per side.

2X 0.10

2.80

Gage plane

0.25

10.16 ±0.08

+0.10

-0.05

11.76 ±0.20

0.10

See Detail A

+0.03

-0.02

0.15

0.50 ±0.10

0.80

Detail A

1. All dimensions are in millimeters.

Notes:

2. Package width and length do not include mold protrusion; allowable mold protrusion is

0.25mm per side.

3. 2X means the notch is present in two locations (both ends of the device).

4. Package may or may not be assembled with a location notch.

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512Mb: x4, x8, x16 SDRAM

Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Table 6

(page 14), be maintained to ensure the junction temperature is in the proper operat-

ing range to meet data sheet specifications. An important step in maintaining the prop-

er junction temperature is using the device’s thermal impedances correctly. The ther-

mal impedances are listed in Table 6 (page 14) for the applicable die revision and

packages being made available. These thermal impedance values vary according to the

density, package, and particular design used for each device.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-

ces listed in Table 6 (page 14). To ensure the compatibility of current and future de-

signs, contact Micron Applications Engineering to confirm thermal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the T_C

specification is not exceeded. In applications where the device’s ambient temperature

is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-

perature specifications.

Table 5: Temperature Limits

Parameter

Symbol

Min

0

Max

80

Unit

Notes

Operating case temperature

Commercial

Industrial

T_C

°C

1, 2, 3, 4

–40

0

90

Junction temperature

Ambient temperature

Commercial

Industrial

T_J

T_A

85

°C

3

–40

0

95

Commercial

Industrial

70

3, 5

–40

–

85

Peak reflow temperature

Notes:

T_PEAK

260

1. MAX operating case temperature, TC, is measured in the center of the package on the

top side of the device, as shown in Figure 6 (page 14).

2. Device functionality is not guaranteed if the device exceeds maximum T_Cduring opera-

tion.

3. All temperature specifications must be satisfied.

4. The case temperature should be measured by gluing a thermocouple to the top-center

of the component. This should be done with a 1mm bead of conductive epoxy, as de-

fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple

bead is touching the case.

5. Operating ambient temperature surrounding the package.

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512Mb: x4, x8, x16 SDRAM

Temperature and Thermal Impedance

Table 6: Thermal Impedance Simulated Values

Θ JA (°C/W)

Airflow =

Θ JA (°C/W)

Airflow =

Θ JA (°C/W)

Airflow =

2m/s

Die

Revision

Package

Substrate

2-layer

0m/s

1m/s

Θ JB (°C/W) Θ JC (°C/W)

D

54-pin TSOP

62.6

39.2

48.4

32.3

44.2

30.6

19.2

19.3

6.7

4-layer

1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

Notes:

2. Thermal resistance data is sampled from multiple lots, and the values should be viewed

as typical.

3. These are estimates; actual results may vary.

Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View)

22.22mm

11.11mm

Test point

10.16mm

5.08mm

1. Package may or may not be assembled with a location notch.

Note:

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 7: Absolute Maximum Ratings

Voltage/Temperature

Symbol

V_DD/V_DDQ

V_IN

Min Max Unit

Notes

Voltage on V_DD/V_DDQsupply relative to V_SS

Voltage on inputs, NC, or I/O balls relative to V_SS

Storage temperature (plastic)

Power dissipation

–1

+4.6

V

1

T_STG

–55 +155

°C

W

–

1

1. V_DDand V_DDQmust be within 300mV of each other at all times. V_DDQmust not exceed

V_DD

Note:

.

Table 8: DC Electrical Characteristics and Operating Conditions

Notes 1–3 apply to all parameters and conditions; V_DD/V_DDQ= +3.3V ±0.3V

Parameter/Condition

Symbol

V_DD, V_DDQ

V_IH

Min

3

Max

Unit Notes

Supply voltage

3.6

V

Input high voltage: Logic 1; All inputs

Input low voltage: Logic 0; All inputs

Output high voltage: I_OUT= –4mA

Output low voltage: I_OUT= 4mA

Input leakage current:

2

V_DD+ 0.3

V

4

V_IL

–0.3

2.4

–

+0.8

–

V_OH

V

V_OL

0.4

5

V

I_L

–5

μA

Any input 0V ≤ V_IN≤ V_DD(All other balls not under test = 0V)

Output leakage current: DQ are disabled; 0V ≤ V_OUT≤ V_DDQ

I_OZ

T_A

–5

0

–5

μA

˚C

Operating temperature:

Commercial

Industrial

+70

+85

–40

˚C

1. All voltages referenced to V_SS.

Notes:

2. The minimum specifications are used only to indicate cycle time at which proper opera-

tion over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤

TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)).

3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (V_DDand V_DDQmust be powered

up simultaneously. V_SSand V_SSQmust be at same potential.) The two AUTO REFRESH

command wake-ups should be repeated any time the ^tREF refresh requirement is excee-

ded.

4. V_IHovershoot: V_IH,max= V_DDQ+ 2V for a pulse width ≤ 3ns, and the pulse width cannot

be greater than one-third of the cycle rate. V_ILundershoot: V_IL,min= –2V for a pulse

width ≤3ns.

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Electrical Specifications

Table 9: Capacitance

Note 1 applies to all parameters and conditions

Package

Parameter

Symbol

C_L1

Min

2.5

Max

3.5

Unit

pF

Notes

TSOP "TG" package

Input capacitance: CLK

2

3

Input capacitance: All other input-only

balls

C_L2

2.5

3.8

pF

Input/output capacitance: DQ

C_L0

4

6

pF

4

1. This parameter is sampled. V_DD, V_DDQ= +3.3V; f = 1 MHz, T_A= 25°C; pin under test

biased at 1.4V.

Notes:

2. PC100 specifies a maximum of 4pF.

3. PC100 specifies a maximum of 5pF.

4. PC100 specifies a maximum of 6.5pF.

5. PC133 specifies a minimum of 2.5pF.

6. PC133 specifies a minimum of 2.5pF.

7. PC133 specifies a minimum of 3.0pF.

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Electrical Specifications – I_DDParameters

Table 10: I_DDSpecifications and Conditions (-7E, -75)

Notes 1–5 apply to all parameters and conditions; V_DD/V_DDQ= +3.3V ±0.3V

Max

Parameter/Condition

Symbol

-7E

-75

Unit

Notes

Operating current: Active mode; Burst = 2; READ or WRITE; ^tRC = ^tRC

(MIN)

I_DD1

120

110

mA

6, 9, 10,

13

Standby current: Power-down mode; All banks idle; CKE = LOW

I_DD2

I_DD3

3.5

45

3.5

45

mA

13

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active

after ^tRCD met; No accesses in progress

6, 8, 10,

13

Operating current: Burst mode; Page burst; READ or WRITE; All banks ac-

tive

I_DD4

125

115

mA

6, 9, 10,

13

Auto refresh current: CKE = HIGH; CS# = HIGH

^tRFC = ^tRFC (MIN)

^tRFC = 7.813μs

Standard

I_DD5

I_DD6

I_DD7

255

6

255

6

mA 6, 8, 9, 10,

13, 14

mA

Self refresh current: CKE ≤ 0.2V

6

mA

Low power (L)

3

mA

7

1. All voltages referenced to V_SS.

Notes:

2. The minimum specifications are used only to indicate cycle time at which proper opera-

tion over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤

TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)).

3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (V_DDand V_DDQmust be powered

up simultaneously. V_SSand V_SSQmust be at same potential.) The two AUTO REFRESH

command wake-ups should be repeated any time the ^tREF refresh requirement is excee-

ded.

4. AC operating and I_DDtest conditions have V_IL= 0V and V_IH= 3.0V using a measurement

reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is

measured from V_{IL, max}and V_IH,minand no longer from the 1.5V midpoint. CLK should

always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.

5. I_DDspecifications are tested after the device is properly initialized.

6. I_DDis dependent on output loading and cycle rates. Specified values are obtained with

minimum cycle time and the outputs open.

7. Enables on-chip refresh and address counters.

8. Other input signals are allowed to transition no more than once every two clocks and

are otherwise at valid V_IHor V_ILlevels.

9. The I_DDcurrent will increase or decrease proportionally according to the amount of fre-

quency alteration for the test condition.

10. Address transitions average one transition every two clocks.

11. PC100 specifies a maximum of 4pF.

12. PC100 specifies a maximum of 5pF.

13. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.

14. CKE is HIGH during REFRESH command period ^tRFC (MIN) else CKE is LOW. The I_DD6limit

is actually a nominal value and does not result in a fail value.

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Electrical Specifications – AC Operating Conditions

Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75)

Notes 1, 2, 4, 5, 7, and 20 apply to all parameters and conditions

-7E

-75

Parameter

Symbol

^tAC(3)

^tAC(2)

^tAH

Min

–

Max

5.4

–

Min

–

Max

5.4

6

Unit

Notes

Access time from CLK (positive edge)

CL = 3

CL = 2

ns

18

–

Address hold time

Address setup time

CLK high-level width

CLK low-level width

Clock cycle time

0.8

1.5

2.5

7

0.8

1.5

2.5

7.5

10

0.8

1.5

0.8

1.5

0.8

1.5

–

ns

^tAS

^tCH

^tCL

^tCK(3)

^tCK(2)

^tCKH

^tCKS

^tCMH

^tCMS

^tDH

–

CL = 3

CL = 2

–

14

21

7.5

0.8

1.5

0.8

1.5

0.8

1.5

–

CKE hold time

–

ns

ms

ns

^tCK

ns

CKE setup time

–

CS#, RAS#, CAS#, WE#, DQM hold time

CS#, RAS#, CAS#, WE#, DQM setup time

Data-in hold time

–

Data-in setup time

^tDS

–

Data-out High-Z time

CL = 3

CL = 2

^tHZ(3)

^tHZ(2)

^tLZ

5.4

–

5.4

6

–

Data-out Low-Z time

1

–

Data-out hold time (load)

Data-out hold time (no load)

ACTIVE-to-PRECHARGE command

ACTIVE-to-ACTIVE command period

ACTIVE-to-READ or WRITE delay

Refresh period (8192 rows)

AUTO REFRESH period

^tOH

2.7

1.8

37

60

15

–

2.7

1.8

44

66

20

–

^tOHn

^tRAS

^tRC

^tRCD

^tREF

^tRFC

^tRP

^tRRD

^tT

^tWR

–

19

23

120,000

–

64

–

64

–

66

15

14

0.3

66

20

15

0.3

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

Transition time

–

1.2

–

1.2

–

3

WRITE recovery time

1 CLK +

7ns

1 CLK +

7.5ns

15

14

67

–

15

75

–

16

12

Exit SELF REFRESH-to-ACTIVE command

^tXSR

ns

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Electrical Specifications – AC Operating Conditions

Table 12: AC Functional Characteristics (-7E, -75)

Notes 1–5 and note 7 apply to all parameters and conditions

Parameter

Symbol

^tBDL

^tCCD

^tCDL

^tCKED

^tDAL

-7E

1

-75

1

Unit

^tCK

Notes

11

Last data-in to burst STOP command

READ/WRITE command to READ/WRITE command

Last data-in to new READ/WRITE command

CKE to clock disable or power-down entry mode

Data-in to ACTIVE command

1

11

1

11

1

8

4

5

9, 13

10, 13

11

Data-in to PRECHARGE command

^tDPL

2

DQM to input data delay

^tDQD

^tDQM

^tDQZ

^tDWD

^tMRD

^tPED

^tRDL

^tROH(3)

^tROH(2)

0

DQM to data mask during WRITEs

0

11

DQM to data High-Z during READs

2

11

WRITE command to input data delay

0

11

LOAD MODE REGISTER command to ACTIVE or REFRESH command

CKE to clock enable or power-down exit setup mode

Last data-in to PRECHARGE command

2

17

1

8

2

10, 13

11

Data-out High-Z from PRECHARGE command

CL = 3

CL = 2

3

2

11

1. The minimum specifications are used only to indicate cycle time at which proper opera-

tion over the full temperature range (0˚C ≤ T_A≤ +70˚C commercial temperature, -40˚C ≤

T_A≤ +85˚C industrial temperature, and -40˚C ≤ T_A≤ +105˚C automotive temperature) is

ensured.

Notes:

2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (V_DDand V_DDQmust be powered

up simultaneously. V_SSand V_SSQmust be at same potential.) The two AUTO REFRESH

command wake-ups should be repeated any time the ^tREF refresh requirement is excee-

ded.

3. AC characteristics assume ^tT = 1ns.

4. In addition to meeting the transition rate specification, the clock and CKE must transit

between V_IHand V_IL(or between V_ILand V_IH) in a monotonic manner.

5. Outputs measured at 1.5V with equivalent load:

Q

50pF

6. ^tHZ defines the time at which the output achieves the open circuit condition; it is not a

reference to V_OHor V_OL. The last valid data element will meet ^tOH before going High-Z.

7. AC operating and I_DDtest conditions have V_IL= 0V and V_IH= 3.0V using a measurement

reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is

measured from V_IL,maxand V_IH,minand no longer from the 1.5V midpoint. CLK should al-

ways be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.

8. Timing is specified by ^tCKS. Clock(s) specified as a reference only at minimum cycle rate.

9. Timing is specified by ^tWR plus ^tRP. Clock(s) specified as a reference only at minimum cy-

cle rate.

10. Timing is specified by ^tWR.

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Electrical Specifications – AC Operating Conditions

11. Required clocks are specified by JEDEC functionality and are not dependent on any tim-

ing parameter.

12. CLK must be toggled a minimum of two times during this period.

13. Based on ^tCK = 7.5ns for -75 and -7E, 6ns for -6A.

14. The clock frequency must remain constant (stable clock is defined as a signal cycling

within timing constraints specified for the clock pin) during access or precharge states

(READ, WRITE, including ^tWR, and PRECHARGE commands). CKE may be used to reduce

the data rate.

15. Auto precharge mode only. The precharge timing budget (^tRP) begins at 7ns for -7E and

7.5ns for -75 after the first clock delay and after the last WRITE is executed.

16. Precharge mode only.

17. JEDEC and PC100 specify three clocks.

18. ^tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

19. Parameter guaranteed by design.

20. PC100 specifies a maximum of 6.5pF.

21. For operating frequencies ≤ 45 MHz, ^tCKS = 3.0ns.

22. Auto precharge mode only. The precharge timing budget (^tRP) begins 6ns for -6A after

the first clock delay, after the last WRITE is executed. May not exceed limit set for pre-

charge mode.

23. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in reduction of the product lifetime.

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Functional Description

In general, 512Mb SDRAM devices (32 Meg x 4 x 4 banks, 16 Meg x 8 x 4 banks, and 16

Meg x 16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchro-

nous interface. All signals are registered on the positive edge of the clock signal, CLK.

Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4

bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns

by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 col-

umns by 16 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, followed by a

READ or WRITE command. The address bits registered coincident with the ACTIVE

command are used to select the bank and row to be accessed (BA0 and BA1 select the

bank, A[12:0] select the row). The address bits (x4: A[9:0], A11, A12; x8: A[9:0], A11; x16:

A[9:0]) registered coincident with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections pro-

vide detailed information covering device initialization, register definition, command

descriptions, and device operation.

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Commands

The following table provides a quick reference of available commands, followed by a

written description of each command. Additional Truth Tables (Table 14 (page 28), Ta-

ble 15 (page 30), and Table 16 (page 32)) provide current state/next state informa-

tion.

Table 13: Truth Table – Commands and DQM Operation

Note 1 applies to all parameters and conditions

Name (Function)

CS# RAS# CAS# WE# DQM ADDR

DQ Notes

COMMAND INHIBIT (NOP)

H

L

X

H

L

X

H

L

X

H

L

X

NO OPERATION (NOP)

X

ACTIVE (select bank and activate row)

READ (select bank and column, and start READ burst)

WRITE (select bank and column, and start WRITE burst)

BURST TERMINATE

L

X

Bank/row

Bank/col

X

2

3

L

H

L

L/H

X

L

Bank/col Valid

3

L

H

L

X

Active

X

4

PRECHARGE (Deactivate row in bank or banks)

AUTO REFRESH or SELF REFRESH (enter self refresh mode)

LOAD MODE REGISTER

L

X

Code

5

L

H

L

X

6, 7

8

L

X

Op-code

X

Write enable/output enable

X

L

X

Active

High-Z

9

Write inhibit/output High-Z

H

9

1. CKE is HIGH for all commands shown except SELF REFRESH.

Notes:

2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1

determine which bank is made active.

3. A[0:i] provide column address (where i = the most significant column address for a given

device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which

bank is being read from or written to.

4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-

mand could coincide with data on the bus. However, the DQ column reads a “Don’t

Care” state to illustrate that the BURST TERMINATE command can occur when there is

no data present.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-

charged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-

cept for CKE.

8. A[11:0] define the op-code written to the mode register.

9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock

delay).

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by

the device, regardless of whether the CLK signal is enabled. The device is effectively de-

selected. Operations already in progress are not affected.

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Commands

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to the selected device

(CS# is LOW). This prevents unwanted commands from being registered during idle or

wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-

dress term), BA0, and BA1(see Mode Register (page 35)). The LOAD MODE REGISTER

command can only be issued when all banks are idle and a subsequent executable com-

mand cannot be issued until ^tMRD is met.

ACTIVE

The ACTIVE command is used to activate a row in a particular bank for a subsequent

access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-

lects the row. This row remains active for accesses until a PRECHARGE command is is-

sued to that bank. A PRECHARGE command must be issued before opening a different

row in the same bank.

Figure 7: ACTIVE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Row address

Bank address

Address

BA0, BA1

Don’t Care

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Commands

READ

The READ command is used to initiate a burst read access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the READ

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Read data appears on the DQ subject to the logic level on the DQM inputs two clocks

earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-

Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.

Figure 8: READ Command

CLK

CKE

HIGH

CS#

RAS#

CAS#

WE#

Column address

EN AP

Address

1

A10

DIS AP

BA0, BA1

Bank address

Don’t Care

1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

Note:

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Commands

WRITE

The WRITE command is used to initiate a burst write access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the write

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Input data appearing on the DQ is written to the memory array, subject to the DQM in-

put logic level appearing coincident with the data. If a given DQM signal is registered

LOW, the corresponding data is written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that

byte/column location.

Figure 9: WRITE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Column address

EN AP

Address

1

A10

DIS AP

Bank address

BA0, BA1

Valid address

1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

Don’t Care

Note:

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Commands

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specified time (^tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the case where only one bank is

precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as

“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands are issued to that bank.

Figure 10: PRECHARGE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

Address

A10

All banks

Bank selected

Bank address

BA0, BA1

Valid address

Don’t Care

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or continu-

ous page bursts. The most recently registered READ or WRITE command prior to the

BURST TERMINATE command is truncated.

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Commands

REFRESH

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-

sistent, so it must be issued each time a refresh is required. All active banks must be pre-

charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command

should not be issued until the minimum ^tRP has been met after the PRECHARGE com-

mand, as shown in Bank/Row Activation (page 40).

The addressing is generated by the internal refresh controller. This makes the address

bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,

the 512Mb SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and

industrial). Providing a distributed AUTO REFRESH command every 7.813μs (commer-

cial and industrial) will meet the refresh requirement and ensure that each row is re-

freshed. Alternatively, 8192 AUTO REFRESH commands can be issued in a burst at the

minimum cycle rate (^tRFC), once every 64ms (commercial and industrial).

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest

of the system is powered-down. When in the self refresh mode, the SDRAM retains data

without external clocking.

The SELF REFRESH command is initiated like an AUTO REFRESH command except

CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs

to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain

LOW.

After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-

ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-

fresh mode for a minimum period equal to ^tRAS and may remain in self refresh mode

for an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK

must be stable (stable clock is defined as a signal cycling within timing constraints

specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the

SDRAM must have NOP commands issued (a minimum of two clocks) for ^tXSR because

time is required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the

specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

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Truth Tables

Table 14: Truth Table – Current State Bank n, Command to Bank n

Notes 1–6 apply to all parameters and conditions

Current State

CS# RAS# CAS# WE# Command/Action

Notes

Any

H

L

X

H

L

X

H

L

X

H

L

COMMAND INHIBIT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

ACTIVE (select and activate row)

Idle

L

AUTO REFRESH

7

L

LOAD MODE REGISTER

L

H

L

PRECHARGE

8

Row active

H

L

H

L

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (truncate READ burst, start PRECHARGE)

BURST TERMINATE

9

L

9

H

L

10

9

Read

H

L

H

L

(auto precharge disabled)

L

9

H

L

10

11

9

H

L

Write

H

L

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE (truncate WRITE burst, start PRECHARGE)

BURST TERMINATE

(auto precharge disabled)

L

9

H

L

10

11

H

L

1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (see Table 16 (page 32))

and after ^tXSR has been met (if the previous state was self refresh).

Notes:

2. This table is bank-specific, except where noted (for example, the current state is for a

specific bank and the commands shown can be issued to that bank when in that state).

Exceptions are covered below.

3. Current state definitions:

Idle: The bank has been precharged, and ^tRP has been met.

Row active: A row in the bank has been activated, and ^tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

COMMAND INHIBIT or NOP commands, or supported commands to the other bank

should be issued on any clock edge occurring during these states. Supported commands

to any other bank are determined by the bank’s current state and the conditions descri-

bed in this and the following table.

Precharging: Starts with registration of a PRECHARGE command and ends when ^tRP is

met. After ^tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when ^tRCD is

met. After ^tRCD is met, the bank will be in the row active state.

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Truth Tables

Read with auto precharge enabled: Starts with registration of a READ command

with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

Write with auto precharge enabled: Starts with registration of a WRITE command

with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these

states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

^tRFC is met. After ^tRFC is met, the device will be in the all banks idle state.

Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-

mand and ends when ^tMRD has been met. After ^tMRD is met, the device will be in the

all banks idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when ^tRP is met. After ^tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank specific; requires that all banks are idle.

8. Does not affect the state of the bank and acts as a NOP to that bank.

9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

10. May or may not be bank specific; if all banks need to be precharged, each must be in a

valid state for precharging.

11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-

gardless of bank.

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Truth Tables

Table 15: Truth Table – Current State Bank n, Command to Bank m

Notes 1–6 apply to all parameters and conditions

Current State

CS# RAS# CAS# WE# Command/Action

Notes

Any

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

COMMAND INHIBIT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Any command otherwise supported for bank m

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Idle

Row activating, active, or

precharging

H

L

7

L

H

L

Read

L

H

L

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

(auto precharge disabled)

H

L

7, 10

7, 11

9

L

H

L

Write

L

H

L

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

(auto precharge disabled)

H

L

7, 12

7, 13

9

L

H

L

Read

L

H

L

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

(with auto precharge)

H

L

7, 8, 14

7, 8, 15

9

L

H

L

Write

(with auto precharge)

L

H

L

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

H

L

7, 8, 16

7, 8, 17

9

L

H

L

1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (Table 16 (page 32)), and

after ^tXSR has been met (if the previous state was self refresh).

Notes:

2. This table describes alternate bank operation, except where noted; for example, the cur-

rent state is for bank n and the commands shown can be issued to bank m, assuming

that bank m is in such a state that the given command is supported. Exceptions are cov-

ered below.

3. Current state definitions:

Idle: The bank has been precharged, and ^tRP has been met.

Row active: A row in the bank has been activated, and ^tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

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Truth Tables

Read with auto precharge enabled: Starts with registration of a READ command

with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

Write with auto precharge enabled: Starts with registration of a WRITE command

with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-

sued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command/Action column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disa-

bled.

8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its

burst has been interrupted by bank m burst.

9. The burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM

should be used one clock prior to the WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered, with

the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-

tered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The

last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank

m.

14. For a READ with auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-

CHARGE to bank n will begin when the READ to bank m is registered.

15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM

should be used two clocks prior to the WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to bank m is registered.

16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered, with

the data-out appearing CL later. The PRECHARGE to bank n will begin after ^tWR is met,

where ^tWR begins when the READ to bank m is registered. The last valid WRITE bank n

will be data-in registered one clock prior to the READ to bank m.

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The

PRECHARGE to bank n will begin after ^tWR is met, where ^tWR begins when the WRITE

to bank m is registered. The last valid WRITE to bank n will be data registered one clock

to the WRITE to bank m.

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Truth Tables

Table 16: Truth Table – CKE

Notes 1–4 apply to all parameters and conditions

Current State

Power-down

Self refresh

CKE_n-1

CKE_n

Command_n

Action_n

Notes

L

X

Maintain power-down

Maintain self refresh

Maintain clock suspend

Exit power-down

X

Clock suspend

Power-down

Self refresh

X

L

H

L

COMMAND INHIBIT or NOP

X

5

6

7

Exit self refresh

Clock suspend

All banks idle

Reading or writing

Exit clock suspend

Power-down entry

Self refresh entry

Clock suspend entry

H

COMMAND INHIBIT or NOP

AUTO REFRESH

VALID

H

See Table 15 (page 30).

1. CKE_nis the logic state of CKE at clock edge n; CKE_n-1was the state of CKE at the previ-

ous clock edge.

Notes:

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND_nis the command registered at clock edge n, and ACTION_nis a result of

COMMAND_n.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time

for clock edge n + 1 (provided that ^tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state after

^tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges

occurring during the ^tXSR period. A minimum of two NOP commands must be provided

during the ^tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recog-

nize the next command at clock edge n + 1.

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Initialization

SDRAM must be powered up and initialized in a predefined manner. Operational proce-

dures other than those specified may result in undefined operation. After power is ap-

plied to V_DDand V_DDQ(simultaneously) and the clock is stable (stable clock is defined

as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-

quires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or

NOP. Starting at some point during this 100μs period and continuing at least through

the end of this period, COMMAND INHIBIT or NOP commands must be applied.

After the 100μs delay has been satisfied with at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will power up in an unknown state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH com-

mands can be issued after the LMR command.

The recommended power-up sequence for SDRAM:

1. Simultaneously apply power to V_DDand V_DDQ

.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-

ing constraints specified for the clock pin.

4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIB-

IT or NOP.

5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at

least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-

mands must be applied.

6. Perform a PRECHARGE ALL command.

7. Wait at least ^tRP time; during this time NOPs or DESELECT commands must be

given. All banks will complete their precharge, thereby placing the device in the all

banks idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least ^tRFC time, during which only NOPs or COMMAND INHIBIT com-

mands are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least ^tRFC time, during which only NOPs or COMMAND INHIBIT com-

mands are allowed.

12. The SDRAM is now ready for mode register programming. Because the mode reg-

ister will power up in an unknown state, it should be loaded with desired bit values

prior to applying any operational command. Using the LMR command, program

the mode register. The mode register is programmed via the MODE REGISTER SET

command with BA1 = 0, BA0 = 0 and retains the stored information until it is pro-

grammed again or the device loses power. Not programming the mode register

upon initialization will result in default settings which may not be desired. Out-

puts are guaranteed High-Z after the LMR command is issued. Outputs should be

High-Z already before the LMR command is issued.

13. Wait at least ^tMRD time, during which only NOP or DESELECT commands are al-

lowed.

At this point the DRAM is ready for any valid command.

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Initialization

Note:

More than two AUTO REFRESH commands can be issued in the sequence. After steps 9

and 10 are complete, repeat them until the desired number of AUTO REFRESH + ^tRFC

loops is achieved.

Figure 11: Initialize and Load Mode Register

T0

T1

Tn + 1

t

To + 1

CL

Tp + 1

Tp + 2

Tp + 3

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

CK

((

))

CH

t

CKS CKH

((

))

((

))

( (

) )

( (

) )

( (

) )

( (

) )

CKE

t

CMS CMH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

LOAD MODE

REGISTER

2

COMMAND

NOP

PRECHARGE

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

DQM/DQML,

DQMU

t

5

AS AH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

A[9:0],

A[12:11]

CODE

ROW

BANK

t

AS AH

CODE

( (

) )

( (

) )

( (

) )

( (

) )

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

A10

SINGLE BANK

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

ALL

BANKS

BA[1:0]

DQ

High-Z

((

))

((

))

T = 100µs

MIN

t

RP

RFC

MRD

Power-up:

1,3,4

Program Mode Register

AUTO REFRESH

V

and

Precharge

all banks

DD

CLK stable

DON’T CARE

UNDEFINED

1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

2. If CS is HIGH at clock HIGH time, all commands applied are NOP.

3. JEDEC and PC100 specify three clocks.

Notes:

4. Outputs are guaranteed High-Z after command is issued.

5. A12 should be a LOW at ^tP + 1.

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Mode Register

The mode register defines the specific mode of operation, including burst length (BL),

burst type, CAS latency (CL), operating mode, and write burst mode. The mode register

is programmed via the LOAD MODE REGISTER command and retains the stored infor-

mation until it is programmed again or the device loses power.

Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify

the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and

M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and

Mn + 2 should be set to zero to select the mode register.

The mode registers must be loaded when all banks are idle, and the controller must wait

^tMRD before initiating the subsequent operation. Violating either of these requirements

will result in unspecified operation.

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Mode Register

Figure 12: Mode Register Definition

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

Mode Register (Mx)

Burst Length

11 10

3

1

0

12

8

6

5

2

9

4

7

Op Mode

WB

CASLatency

BT

Burst Length

Reserved

Program

BA1, BA0 = “0, 0”

to ensure compatibility

with future devices.

M2 M1 M0

M3 = 0

M3 = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

Write Burst Mode

M9

0

4

Programmed Burst Length

Single Location Access

8

1

Reserved

Full Page

Reserved

M8

M7

0

M6-M0

Defined

–

Operating Mode

0

–

Standard Operation

–

All other states reserved

Burst Type

M3

0

Sequential

Interleaved

1

CAS Latency

Reserved

1

M6 M5 M4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

Reserved

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Mode Register

Burst Length

Read and write accesses to the device are burst oriented, and the burst length (BL) is

programmable. The burst length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,

4, 8, or continuous locations are available for both the sequential and the interleaved

burst types, and a continuous page burst is available for the sequential type. The con-

tinuous page burst is used in conjunction with the BURST TERMINATE command to

generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with fu-

ture versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst wraps within the block when a boundary is reached. The block

is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.

The remaining (least significant) address bit(s) is (are) used to select the starting loca-

tion within the block. Continuous page bursts wrap within the page when the boundary

is reached.

Burst Type

Accesses within a given burst can be programmed to be either sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst

type, and the starting column address.

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Mode Register

Table 17: Burst Definition Table

Order of Accesses Within a Burst

Burst Length

Starting Column Address

Type = Sequential

Type = Interleaved

2

A0

0

0-1

1-0

0-1

1-0

1

4

8

A1

0

A0

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0

1

0

1

A2

0

A1

0

A0

0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0

1

0

1

0

1

0

1

0

1

0

1

Continuous

n = A0–An/9/8 (location 0–y)

Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1,

Cn...

Not supported

1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16).

Notes:

2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0

selects the starting column within the block.

3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst;

A0–A1 select the starting column within the block.

4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst;

A0–A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8

(x16) select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the fol-

lowing access wraps within the block.

7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be

accessed, and mode register bit M3 is ignored.

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Mode Register

CAS Latency

The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ

command and the availability of the output data. The latency can be set to two or three

clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQ start driving as a result of the clock edge

one cycle earlier (n + m - 1), and provided that the relevant access times are met, the

data is valid by clock edge n + m. For example, assuming that the clock cycle time is

such that all relevant access times are met, if a READ command is registered at T0 and

the latency is programmed to two clocks, the DQ start driving after T1 and the data is

valid by T2.

Reserved states should not be used as unknown operation or incompatibility with fu-

ture versions may result.

Figure 13: CAS Latency

T0

T1

T2

T3

CLK

Command

READ

NOP

t

OH

LZ

D

DQ

OUT

t

AC

CL = 2

T0

T1

T2

T3

T4

CLK

Command

READ

NOP

t

OH

LZ

D

DQ

OUT

t

AC

CL = 3

Don’t Care

Undefined

Operating Mode

Write Burst Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use. Reserved states should not

be used because unknown operation or incompatibility with future versions may result.

When M9 = 0, the burst length programmed via M[2:0] applies to both READ and

WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but

write accesses are single-location (nonburst) accesses.

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Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a

row in that bank must be opened. This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated.

After a row is opened with the ACTIVE command, a READ or WRITE command can be

issued to that row, subject to the ^tRCD specification. ^tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. For example, a ^tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure 14 (page 40), which covers

any case where 2 < ^tRCD (MIN)/^tCK ≤ 3. (The same procedure is used to convert other

specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued

after the previous active row has been precharged. The minimum time interval between

successive ACTIVE commands to the same bank is defined by ^tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The mini-

mum time interval between successive ACTIVE commands to different banks is defined

by ^tRRD.

Figure 14: Example: Meeting ^tRCD (MIN) When 2 < ^tRCD (MIN)/^tCK < 3

T0

T1

T2

T3

CLK

t

CK

READ or

WRITE

Command

ACTIVE

NOP

t

RCD(MIN)

Don’t Care

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READ Operation

READ bursts are initiated with a READ command, as shown in Figure 8 (page 24). The

starting column and bank addresses are provided with the READ command, and auto

precharge is either enabled or disabled for that burst access. If auto precharge is ena-

bled, the row being accessed is precharged at the completion of the burst. In the follow-

ing figures, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address is

available following the CAS latency after the READ command. Each subsequent data-

out element will be valid by the next positive clock edge. Figure 16 (page 43) shows

general timing for each possible CAS latency setting.

Upon completion of a burst, assuming no other commands have been initiated, the DQ

signals will go to High-Z. A continuous page burst continues until terminated. At the

end of the page, it wraps to column 0 and continues.

Data from any READ burst can be truncated with a subsequent READ command, and

data from a fixed-length READ burst can be followed immediately by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst either follows the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ com-

mand should be issued x cycles before the clock edge at which the last desired data ele-

ment is valid, where x = CL - 1. This is shown in Figure 16 (page 43) for CL2 and CL3.

SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-

sociated with a prefetch architecture. A READ command can be initiated on any clock

cycle following a READ command. Full-speed random read accesses can be performed

to the same bank, or each subsequent READ can be performed to a different bank.

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READ Operation

Figure 15: Consecutive READ Bursts

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

READ

NOP

Command

X = 1 cycle

Bank,

Col n

Bank,

Col b

Address

DQ

D_OUT

n

D_OUT

n + 1

D_OUT

n + 2

D_OUT

n + 3

D_OUT

b

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ

NOP

READ

NOP

Command

X = 2 cycles

Bank,

Col n

Bank,

Col b

Address

DQ

D_OUT

CL = 3

Transitioning data

Don’t Care

1. Each READ command can be issued to any bank. DQM is LOW.

Note:

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READ Operation

Figure 16: Random READ Accesses

T0

T1

T2

T3

T4

T5

CLK

Command

Address

DQ

READ

NOP

Bank,

Col n

Bank,

Col a

Bank,

Col x

Bank,

Col m

D_OUT

CL = 2

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

Command

Address

DQ

Bank,

Col n

Bank,

Col a

Bank,

Col x

Bank,

Col m

D_OUT

CL = 3

Transitioning data

Don’t Care

1. Each READ command can be issued to any bank. DQM is LOW.

Note:

Data from any READ burst can be truncated with a subsequent WRITE command, and

data from a fixed-length READ burst can be followed immediately by data from a

WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-

tiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, there is a possibility that the device driving the input data will go Low-Z before

the DQ go High-Z. In this case, at least a single-cycle delay should occur between the

last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figure 17 (page 44) and

Figure 18 (page 45). The DQM signal must be asserted (HIGH) at least two clocks prior

to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-

ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z

(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was

active on the clock just prior to the WRITE command that truncated the READ com-

mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was

LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6

would be invalid.

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READ Operation

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 17

(page 44) shows where, due to the clock cycle frequency, bus contention is avoided

without having to add a NOP cycle, while Figure 18 (page 45) shows the case where an

additional NOP cycle is required.

A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-

mand to the same bank, provided that auto precharge was not activated. The PRE-

CHARGE command should be issued x cycles before the clock edge at which the last de-

sired data element is valid, where x = CL - 1. This is shown in Figure 19 (page 45) for

each possible CL; data element n + 3 is either the last of a burst of four or the last de-

sired data element of a longer burst. Following the PRECHARGE command, a subse-

quent command to the same bank cannot be issued until ^tRP is met. Note that part of

the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE com-

mand issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvant-

age of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command. The advantage of the

PRECHARGE command is that it can be used to truncate fixed-length or continuous

page bursts.

Figure 17: READ-to-WRITE

T0

T1

T2

T3

T4

CLK

DQM

READ

NOP

Command

Address

WRITE

Bank,

Col n

Bank,

Col b

t

CK

t

HZ

D_OUT

D_IN

DQ

t

DS

Transitioning data

Don’t Care

1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be

to any bank. If a burst of one is used, DQM is not required.

Note:

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READ Operation

Figure 18: READ-to-WRITE With Extra Clock Cycle

T0

T1

T2

T3

T4

T5

CLK

DQM

READ

NOP

WRITE

Command

Address

Bank,

Col n

Bank,

Col b

t

HZ

D

OUT

IN

DQ

t

DS

Transitioning data

Don’t Care

1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be

to any bank.

Note:

Figure 19: READ-to-PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

t

RP

READ

NOP

ACTIVE

PRECHARGE

Command

Address

DQ

X = 1 cycle

Bank

a or all)

Bank

Col

a

n

,

Bank

a,

(

Row

D_OUT

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

t

RP

READ

NOP

PRECHARGE

Bank

NOP

X = 2 cycles

NOP

ACTIVE

Command

Address

DQ

Bank

Col

a,

Bank

a,

(a or all)

Row

D_OUT

CL = 3

Transitioning data

Don’t Care

1. DQM is LOW.

Note:

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READ Operation

Continuous-page READ bursts can be truncated with a BURST TERMINATE command

and fixed-length READ bursts can be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure 20 (page 46) for each possible CAS la-

tency; data element n + 3 is the last desired data element of a longer burst.

Figure 20: Terminating a READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

BURST

READ

NOP

Command

Address

DQ

TERMINATE

X = 1 cycle

Bank,

Col n

D_OUT

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

Command

Address

DQ

BURST

READ

NOP

X = 2 cycles

NOP

TERMINATE

Bank,

Col n

D_OUT

CL = 3

Transitioning data

Don’t Care

1. DQM is LOW.

Note:

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READ Operation

Figure 21: Alternating Bank Read Accesses

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

DQM

ACTIVE

NOP

READ

t

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS

CMH

t

AS

t

AH

Row

Column m

Column b¹

Address

t

AH

AS

Enable auto precharge

Row

A10

t

AS

t

AH

Bank 0

Bank 3

BA0, BA1

Bank 0

t

AC

t

AC

OH

AC

OH

AC

OH

AC

OH

t

OH

AC

D

OUT

DQ

OUT

t

LZ

t

RP - bank 0

CL - bank 0

RCD - bank 0

Undefined

RCD - bank 0

RAS - bank 0

RC - bank 0

RRD

t

CL - bank 3

Don’t Care

RCD - bank 3

1. For this example, BL = 4 and CL = 2.

Note:

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READ Operation

Figure 22: READ Continuous Page Burst

T0

T1

T2

T3

T4

T5

T6

Tn + 1

Tn + 2

Tn + 3

Tn + 4

( (

) )

( (

) )

t

CK

CL

CLK

t

CH

t

CKS CKH

( (

) )

CKE

( (

) )

t

CMS

CMH

( (

) )

( (

) )

Command

ACTIVE

NOP

READ

t

NOP

BURST TERM

NOP

t

CMS

CMH

( (

) )

DQM

( (

) )

t

AH

AS

( (

) )

( (

) )

Address

Row

Column m

t

AH

AS

( (

) )

( (

) )

Row

A10

t

AH

AS

( (

) )

( (

) )

BA0, BA1

Bank

t

AC

t

AC

( (

) )

t

OH

( (

) )

( (

) )

D

OUT

D

OUT

DQ

OUT

t

LZ

t

HZ

t

All locations within same row

Full page completed

RCD

CAS latency

Don’t Care

Undefined

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

1. For this example, CL = 2.

Note:

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READ Operation

Figure 23: READ – DQM Operation

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

READ

NOP

t

CMH

CMS

DQM

t

AS

t

AH

Row

Column m

Address

t

AS

AH

Enable auto precharge

Row

A10

Disable auto precharge

Bank

t

AS

t

AH

BA0, BA1

Bank

t

AC

t

AC

OH

D_OUT

t

AC

OH

DQ

D_OUT

t

LZ

t

HZ

t

RCD

CL = 2

Don’t Care

Undefined

1. For this example, BL = 4 and CL = 2.

Note:

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WRITE Operation

WRITE bursts are initiated with a WRITE command, as shown in Figure 9 (page 25). The

starting column and bank addresses are provided with the WRITE command and auto

precharge is either enabled or disabled for that access. If auto precharge is enabled, the

row being accessed is precharged at the completion of the burst. For the generic WRITE

commands used in the following figures, auto precharge is disabled.

During WRITE bursts, the first valid data-in element is registered coincident with the

WRITE command. Subsequent data elements are registered on each successive positive

clock edge. Upon completion of a fixed-length burst, assuming no other commands

have been initiated, the DQ will remain at High-Z and any additional input data will be

ignored (see Figure 24 (page 50)). A continuous page burst continues until terminated;

at the end of the page, it wraps to column 0 and continues.

Data for any WRITE burst can be truncated with a subsequent WRITE command, and

data for a fixed-length WRITE burst can be followed immediately by data for a WRITE

command. The new WRITE command can be issued on any clock following the previ-

ous WRITE command, and the data provided coincident with the new command ap-

plies to the new command (see Figure 25 (page 51)). Data n + 1 is either the last of a

burst of two or the last desired data element of a longer burst.

SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-

sociated with a prefetch architecture. A WRITE command can be initiated on any clock

cycle following a previous WRITE command. Full-speed random write accesses within a

page can be performed to the same bank, as shown in Figure 26 (page 52), or each

subsequent WRITE can be performed to a different bank.

Figure 24: WRITE Burst

T0

T1

T2

T3

CLK

WRITE

NOP

Command

Address

DQ

Bank,

Col n

D_IN

Transitioning data

1. BL = 2. DQM is LOW.

Don’t Care

Note:

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WRITE Operation

Figure 25: WRITE-to-WRITE

T0

T1

T2

CLK

WRITE

NOP

WRITE

Command

Address

DQ

Bank,

Col n

Bank,

Col b

D_IN

Transitioning data

Don’t Care

1. DQM is LOW. Each WRITE command may be issued to any bank.

Note:

Data for any WRITE burst can be truncated with a subsequent READ command, and

data for a fixed-length WRITE burst can be followed immediately by a READ command.

After the READ command is registered, data input is ignored and WRITEs will not be

executed (see Figure 27 (page 52)). Data n + 1 is either the last of a burst of two or the

last desired data element of a longer burst.

Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-

CHARGE command to the same bank, provided that auto precharge was not activated.

A continuous-page WRITE burst can be truncated with a PRECHARGE command to the

same bank. The PRECHARGE command should be issued ^tWR after the clock edge at

which the last desired input data element is registered. The auto precharge mode re-

quires a ^tWR of at least one clock with time to complete, regardless of frequency.

In addition, when truncating a WRITE burst at high clock frequencies (^tCK < 15ns), the

DQM signal must be used to mask input data for the clock edge prior to and the clock

edge coincident with the PRECHARGE command (see Figure 28 (page 53)). Data n + 1

is either the last of a burst of two or the last desired data element of a longer burst. Fol-

lowing the PRECHARGE command, a subsequent command to the same bank cannot

be issued until ^tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARGE com-

mand issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvant-

age of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command. The advantage of the

PRECHARGE command is that it can be used to truncate fixed-length bursts or continu-

ous page bursts.

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WRITE Operation

Figure 26: Random WRITE Cycles

T0

T1

T2

T3

CLK

WRITE

Command

Address

DQ

Bank,

Col n

Bank,

Col a

Bank,

Col x

Bank,

Col m

D

IN

Transitioning data

Don’t Care

1. Each WRITE command can be issued to any bank. DQM is LOW.

Note:

Figure 27: WRITE-to-READ

T0

T1

T2

T3

T4

T5

CLK

WRITE

NOP

READ

NOP

Command

Address

DQ

Bank,

Col n

Bank,

Col b

D_IN

D_OUT

Don’t Care

Transitioning data

1. The WRITE command can be issued to any bank, and the READ command can be to any

bank. DQM is LOW. CL = 2 for illustration.

Note:

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WRITE Operation

Figure 28: WRITE-to-PRECHARGE

T0

T1

T2

T3

T4

T5

T6

CLK

t

WR @ CK ≥ 15ns

DQM

t

RP

NOP

WRITE

NOP

PRECHARGE

ACTIVE

Command

Address

Bank

(a or all)

Bank a,

Col n

Bank a,

Row

t

WR

D

IN

DQ

t

WR @ CK < 15ns

DQM

t

RP

NOP

WRITE

NOP

PRECHARGE

ACTIVE

Command

Address

Bank

(a or all)

Bank a,

Col n

Bank a,

Row

t

WR

D

IN

DQ

Transitioning data

Don’t Care

1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.

Note:

Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.

When truncating a WRITE burst, the input data applied coincident with the BURST

TERMINATE command is ignored. The last data written (provided that DQM is LOW at

that time) will be the input data applied one clock previous to the BURST TERMINATE

command. This is shown in Figure 29 (page 54), where data n is the last desired data

element of a longer burst.

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WRITE Operation

Figure 29: Terminating a WRITE Burst

T0

T1

T2

CLK

BURST

TERMINATE

WRITE

Command

Address

DQ

Bank,

Col n

Address

Data

D_IN

Transitioning data

1. DQM is LOW.

Don’t Care

Note:

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WRITE Operation

Figure 30: Alternating Bank Write Accesses

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

DQM

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

Row

Column m

Column b

Address

t

AH

AS

Enable auto precharge

Row

A10

t

AH

AS

BA0, BA1

Bank 0

Bank 1

t

Bank 1

Bank 0

t

DS

t

DS

t

DS DH

DS

DH

D_IN

WR - bank 0

DH

D_IN

RP - bank 0

D_IN

DQ

t

RCD - bank 0

t

RCD - bank 0

t

RAS - bank 0

RC - bank 0

RRD

t

WR - bank 1

t

RCD - bank 1

Don’t Care

1. For this example, BL = 4.

Note:

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WRITE Operation

Figure 31: WRITE – Continuous Page Burst

T0

T1

T2

T3

T4

T5

Tn + 1

Tn + 2

Tn + 3

( (

) )

( (

) )

t

CK

CL

CLK

t

CH

t

CKS

CKH

( (

) )

CKE

( (

) )

t

CMS

CMH

( (

) )

( (

) )

Command

ACTIVE

NOP

WRITE

t

NOP

BURST TERM

NOP

t

CMH

CMS

( (

) )

( (

) )

DQM

t

AS

t

AH

( (

) )

( (

) )

Column

m

Address

Row

t

AS

t

AH

( (

) )

( (

) )

Row

A10

t

AS

t

AH

( (

) )

( (

) )

BA0, BA1

Bank

t

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

( (

) )

( (

) )

D_IN

DQ

t

RCD

Full-page burst

All locations within same row

does not self-terminate.

Use BURST TERMINATE

command to stop.

1, 2

Full page completed

Don’t Care

1. ^tWR must be satisfied prior to issuing a PRECHARGE command.

2. Page left open; no ^tRP.

Notes:

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WRITE Operation

Figure 32: WRITE – DQM Operation

T0

T1

T2

T3

T4

T5

T6

T7

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

DQM

ACTIVE

NOP

WRITE

t

NOP

t

CMS CMH

t

AH

AS

Address

Row

t

Column m

AS

AH

Enable auto precharge

Row

t

A10

Disable auto precharge

Bank

AS

AH

BA0, BA1

Bank

t

DS

DH

D_IN

DS

DH

DS

DH

D_IN

DQ

t

Don’t Care

RCD

1. For this example, BL = 4.

Note:

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access

of a single column location (burst of one), regardless of the programmed burst length.

READ commands access columns according to the programmed burst length and se-

quence, just as in the normal mode of operation (M9 = 0).

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PRECHARGE Operation

The PRECHARGE command (see Figure 10 (page 26)) is used to deactivate the open row

in a particular bank or the open row in all banks. The bank(s) will be available for a sub-

sequent row access some specified time (^tRP) after the PRECHARGE command is is-

sued. Input A10 determines whether one or all banks are to be precharged, and in the

case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select

the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are

treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and

must be activated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individual-bank PRECHARGE func-

tion described previously, without requiring an explicit command. This is accomplished

by using A10 to enable auto precharge in conjunction with a specific READ or WRITE

command. A precharge of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the continuous page burst mode where auto precharge does not apply. In the

specific case of write burst mode set to single location access with burst length set to

continuous, the burst length setting is the overriding setting and auto precharge does

not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for

each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. Another command cannot be issued to the same bank until the precharge time

(^tRP) is completed. This is determined as if an explicit PRECHARGE command was is-

sued at the earliest possible time, as described for each burst type in the Burst Type

(page 37) section.

Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-

charge for READs and WRITEs are defined below.

READ with auto precharge interrupted by a READ (with or without auto precharge)

A READ to bank m will interrupt a READ on bank n following the programmed CAS la-

tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-

ure 33 (page 59)).

READ with auto precharge interrupted by a WRITE (with or without auto precharge)

A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The pre-

charge to bank n begins when the WRITE to bank m is registered (see Figure 34

(page 60)).

WRITE with auto precharge interrupted by a READ (with or without auto precharge)

A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out

appearing CL later. The precharge to bank n will begin after ^tWR is met, where ^tWR be-

gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-

ta-in registered one clock prior to the READ to bank m (see Figure 39 (page 65)).

WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)

A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to

bank n will begin after ^tWR is met, where ^tWR begins when the WRITE to bank m is reg-

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PRECHARGE Operation

istered. The last valid data WRITE to bank n will be data registered one clock prior to a

WRITE to bank m (see Figure 40 (page 65)).

Figure 33: READ With Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

Bank n

READ - AP

Bank m

NOP

Command

Bank n

Page active

READ with burst of 4

Interrupt burst, precharge

Idle

t

RP - bank m

RP - bank n

Internal

states

Precharge

Page active

READ with burst of 4

Bank m

Bank n,

Col a

Bank m,

Col d

Address

DQ

D

OUT

CL = 3 (bank n)

CL = 3 (bank m)

Don’t Care

1. DQM is LOW.

Note:

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PRECHARGE Operation

Figure 34: READ With Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

Bank n

WRITE - AP

Bank m

NOP

Command

Bank n

Page

active

READ with burst of 4

Page active

Interrupt burst, precharge

t

Idle

Internal

States

t

RP - bank

n

WR - bankm

Write-back

WRITE with burst of 4

Bank m

Address

Bank n,

Col a

Bank m,

Col d

1

DQM

D

IN

OUT

IN

DQ

CL = 3 (bank n)

Transitioning data

Don’t Care

1. DQM is HIGH at T2 to prevent D_OUTa + 1 from contending with D_INd at T4.

Note:

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PRECHARGE Operation

Figure 35: READ With Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMH

CMS

DQM

t

AH

AS

Row

Column m

Address

t

AH

AS

Enable auto precharge

Row

A10

t

AH

AS

BA0, BA1

Bank

t

AC

OH

t

AC

t

OH

DOUT

DQ

DOUT m

t

m + 1

m + 2

m + 3

LZ

t

HZ

t

RCD

CL = 2

RP

t

RAS

t

RC

Don’t Care

Undefined

1. For this example, BL = 4 and CL = 2.

Note:

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PRECHARGE Operation

Figure 36: READ Without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

t

CMS CMH

DQM

t

AS

t

AH

Row

Column m

Address

t

AS

t

AH

All banks

Row

A10

Single bank

Disable auto precharge

Bank

t

AS

AH

BA0, BA1

Bank(s)

t

Bank

t

AC

t

OH

t

OH

t

OH

t

OH

AC

D_OUT

DQ

t

LZ

t

HZ

t

RCD

CL = 2

RP

t

RAS

t

RC

Don’t Care

Undefined

1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-

CHARGE.

Note:

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PRECHARGE Operation

Figure 37: Single READ With Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS CMH

DQM

t

AS

t

AH

Row

Column m

Row

Address

t

AS

t

AH

Enable auto precharge

Row

A10

t

AS

t

AH

BA0, BA1

Bank

t

OH

AC

D_OUT

DQ

t

LZ

t

RCD

CL = 2

RP

t

RAS

t

RC

Don’t Care

Undefined

1. For this example, BL = 1 and CL = 2.

Note:

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PRECHARGE Operation

Figure 38: Single READ Without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMS CMH

DQM

t

AS

AH

Row

Column m

Row

Address

t

AS

AH

All banks

Row

A10

Single bank

Bank(s)

Disable auto precharge

Bank

t

AS

AH

BA0, BA1

Bank

t

AC

t

OH

D_OUT

DQ

t

LZ

t

HZ

t

RCD

CL = 2

RP

Don’t Care

Undefined

t

RAS

t

RC

1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRE-

CHARGE.

Note:

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PRECHARGE Operation

Figure 39: WRITE With Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

Bank n

READ - AP

Bank m

NOP

Command

Bank n

Interrupt burst, write-back Precharge

t

Page active

WRITE with burst of 4

Internal

States

RP - bank n

t

WR - bank n

t

RP - bank m

Page active

READ with burst of 4

Bank m

Bank n,

Col a

Bank m,

Col d

Address

DQ

D_IN

D_OUT

CL = 3 (bank m)

Don’t Care

1. DQM is LOW.

Note:

Figure 40: WRITE With Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

Bank n

WRITE - AP

Bank m

NOP

Command

Bank n

Page active

WRITE with burst of 4

Interrupt burst, write-back Precharge

t

RP - bank n

t

Internal

States

WR - bank n

t

WR - bank m

Write-back

Page active

WRITE with burst of 4

Bank m

Bank n,

Col a

Bank m,

Col d

Address

DQ

D_IN

Don’t Care

1. DQM is LOW.

Note:

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PRECHARGE Operation

Figure 41: WRITE With Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

DQM

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

Address

Row

Bank

Row

Column m

t

AS

AH

Enable auto precharge

Row

A10

t

AS

AH

BA0, BA1

Bank

t

DH

DS

DH

DS

DH

DS

DH

DS

D_IN

DQ

t

RP

t

RCD

WR

t

RAS

t

RC

Don’t Care

1. For this example, BL = 4.

Note:

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PRECHARGE Operation

Figure 42: WRITE Without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

DQM

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

Address

Row

Column m

Row

Bank

t

AS

AH

All banks

Row

A10

Disable auto precharge

Bank

Single bank

Bank

t

AS

Bank

AH

BA0, BA1

t

DS DH

DS

DH

D_IN

DQ

t

RP

t

RCD

WR

t

RAS

t

RC

Don’t Care

1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.

Note:

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PRECHARGE Operation

Figure 43: Single WRITE With Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

Command

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

t

CMS

CMH

DQM

t

AH

AS

Address

Row

Bank

Column m

t

AS

AH

Enable auto precharge

Row

A10

t

AS

Bank

AH

Bank

BA0, BA1

t

DS

DH

D_IN

DQ

t

RP

t

RCD

WR

t

RAS

t

RC

Don’t Care

1. For this example, BL = 1.

Note:

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PRECHARGE Operation

Figure 44: Single WRITE Without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

Command

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMS CMH

DQM

t

AS

AH

Row

Column m

Address

t

AS

AH

All banks

Row

A10

Single bank

Bank

Disable auto precharge

Bank

t

AH

AS

BA0, BA1

Bank

t

DS DH

D_IN

DQ

t

RCD

WR

RP

t

RAS

t

RC

Don’t Care

1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.

Note:

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AUTO REFRESH Operation

The AUTO REFRESH command is used during normal operation of the device to refresh

the contents of the array. This command is nonpersistent, so it must be issued each

time a refresh is required. All active banks must be precharged prior to issuing an AUTO

REFRESH command. The AUTO REFRESH command should not be issued until the

minimum ^tRP is met following the PRECHARGE command. Addressing is generated by

the internal refresh controller. This makes the address bits “Don’t Care” during an AU-

TO REFRESH command.

After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-

cutable command until ^tRFC has been met. During ^tRFC time, COMMAND INHIBIT or

NOP commands must be issued on each positive edge of the clock. The SDRAM re-

quires that every row be refreshed each ^tREF period. Providing a distributed AUTO RE-

FRESH command—calculated by dividing the refresh period (^tREF) by the number of

rows to be refreshed—meets the timing requirement and ensures that each row is re-

freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed

after every ^tREF period by issuing consecutive AUTO REFRESH commands for the num-

ber of rows to be refreshed at the minimum cycle rate (^tRFC).

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AUTO REFRESH Operation

Figure 45: Auto Refresh Mode

T0

T1

T2

Tn + 1

CL

To + 1

( (

) )

( (

) )

t

CLK

CKE

t

( (

CK

CH

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

Command

DQM

PRECHARGE

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

Row

Address

A10

( (

) )

( (

) )

( (

) )

( (

) )

All banks

Single bank

t

AH

AS

( (

) )

( (

) )

BA0, BA1

DQ

Bank(s)

Bank

( (

) )

High-Z

( (

) )

( (

) )

t

RFC

RP

RFC

Precharge all

active banks

Don’t Care

1. Back-to-back AUTO REFRESH commands are not required.

Note:

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SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the

system is powered down. When in self refresh mode, the device retains data without ex-

ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-

mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,

all the inputs to the device become “Don’t Care” with the exception of CKE, which must

remain LOW.

After self refresh mode is engaged, the device provides its own internal clocking, ena-

bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-

fresh mode for a minimum period equal to ^tRAS and remains in self refresh mode for an

indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK

must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling

within timing constraints specified for the clock ball.) After CKE is HIGH, the device

must have NOP commands issued for a minimum of two clocks for ^tXSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-

ing to the distributed refresh rate (^tREF/refresh row count) as both SELF REFRESH and

AUTO REFRESH utilize the row refresh counter.

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SELF REFRESH Operation

Figure 46: Self Refresh Mode

T0

T1

T2

Tn + 1

To + 1

To + 2

( (

) )

( (

) )

t

CL

CLK

CKE

t

( (

) )

( (

) )

t

CK

CH

t

CKS

( (

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

Command

DQM

PRECHARGE

NOP

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

Address

A10

All banks

( (

) )

( (

) )

( (

) )

( (

) )

Single bank

t

AH

AS

( (

) )

( (

) )

( (

) )

( (

) )

Bank(s)

BA0, BA1

DQ

High-Z

( (

) )

( (

) )

t

RP

XSR

Precharge all

active banks

Enter self refresh mode

Exit self refresh mode

(Restart refresh time base)

CLK stable prior to exiting

self refresh mode

Don’t Care

1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are

not required.

Note:

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Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-

HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,

this mode is referred to as precharge power-down; if power-down occurs when there is a

row active in any bank, this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CKE, for maximum power

savings while in standby. The device cannot remain in the power-down state longer

than the refresh period (64ms) because no REFRESH operations are performed in this

mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE

HIGH at the desired clock edge (meeting ^tCKS).

Figure 47: Power-Down Mode

T0

T1

T2

Tn + 1

Tn + 2

( (

) )

( (

) )

t

CK

CL

CLK

CKE

t

CH

t

CKS

( (

) )

t

CKS

CKH

t

CMS CMH

PRECHARGE

( (

) )

( (

) )

Command

DQM

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

( (

) )

Address

A10

Row

All banks

( (

) )

( (

) )

Single bank

t

AH

AS

( (

) )

( (

) )

BA0, BA1

DQ

Bank(s)

Bank

High-Z

( (

) )

Input buffers gated off

while in power-down mode

Two clock cycles

All banks idle

Precharge all

active banks

All banks idle, enter

power-down mode

Exit power-down mode

Don’t Care

1. Violating refresh requirements during power-down may result in a loss of data.

Note:

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512Mb: x4, x8, x16 SDRAM

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data present on the input balls when an in-

ternal clock edge is suspended will be ignored; any data present on the DQ balls re-

mains driven; and burst counters are not incremented, as long as the clock is suspen-

ded.

Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-

tion will resume on the subsequent positive clock edge.

Figure 48: Clock Suspend During WRITE Burst

T0

T1

T2

T3

T4

T5

CLK

CKE

Internal

clock

NOP

WRITE

NOP

Command

Address

D_IN

Bank,

Col n

D

IN

Don’t Care

1. For this example, BL = 4 or greater, and DQM is LOW.

Note:

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75

512Mb: x4, x8, x16 SDRAM

Clock Suspend

Figure 49: Clock Suspend During READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

CKE

Internal

clock

READ

NOP

Command

Address

DQ

Bank,

Col n

D_OUT

Don’t Care

1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

Note:

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76

512Mb: x4, x8, x16 SDRAM

Clock Suspend

Figure 50: Clock Suspend Mode

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS CKH

t

CKS CKH

t

CMS

CMH

Command

DQM

READ

NOP

WRITE

NOP

t

CMS

CMH

t

AH

AS

Column e

Column m

Address

t

AH

AS

A10

t

AS

AH

BA0, BA1

Bank

t

AC

t

DH

OH

HZ

DS

AC

D

DQ

OUT

IN

t

LZ

Don’t Care

Undefined

1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

Note:

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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77


型号：	MT48LC32M16A2TG-75L:C
厂家：	MICROSS COMPONENTS
描述：	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54 动态存储器光电二极管
文件：	总77页 (文件大小：3584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT48LC32M16A2TG-75L:C [MICROSS]

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