MT4C4256EC-8/883C [MICROSS]
Fast Page DRAM, 256KX4, 80ns, CMOS, CDSO20, CERAMIC, LCC-26/20;
| 型号： | MT4C4256EC-8/883C |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Fast Page DRAM, 256KX4, 80ns, CMOS, CDSO20, CERAMIC, LCC-26/20 动态存储器 CD |
| 文件： | 总12页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
256K x 4DRAM
FAST PAGE MODE
AVAILABLE AS MILITARY
SPECIFICATION
PIN ASSIGNMENT (Top View)
•
•
SMD 5962-90617
MIL-STD-883
20-Pin DIP
20-Pin LCC
(D-8)
FEATURES
•
•
Industry standard pinout and timing
All inputs, outputs and clocks are fully TTL
compatible
DQ1
DQ2
WE
RAS
NC
A0
1
2
3
4
5
6
7
8
9
20 Vss
19 DQ4
18 DQ3
17 CAS
16 OE
15 A8
14 A7
13 A6
12 A5
11 A4
DQ1
DQ2
WE
1
26
25
24
23
22
Vss
2
3
4
5
DQ4
DQ3
CAS
OE
RAS
NC
•
•
•
•
Single +5V±10% power supply
Low power, 5mW standby; 175mW active, typical
Optional FAST PAGE MODE access cycle
Refresh modes: RAS-ONLY, CAS-BEFORE-RAS and
HIDDEN
512-cycle refresh distributed across 8ms
Specifications guaranteed over full military
temperature range (-55°C to +125°C)
A0
A1
9
18
17
16
15
14
A8
A7
A6
A5
A4
A1
10
11
12
13
•
•
A2
A2
A3
A3
Vcc
Vcc 10
OPTIONS
MARKING
•
Timing
80ns access
100ns access
120ns access
- 8
-10
-12
•
Packages
Ceramic DIP (300 mil)
Ceramic LCC
C
EC
No. 103
No. 202
outputs are routed through four leads using common I/ O,
and information direction is controlled by WE and OE.
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row address (A0-A8) defined page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RAS followed by a column address strobed-
in by CAS. CAS may be toggled-in by holding RAS LOW
and strobing-in different column addresses, thus executing
faster memory cycles. Returning RAS HIGH terminates the
FAST PAGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also,the chip is preconditioned for the next cycle during the
RAS high time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle
GENERAL DESCRIPTION
The MT4C4256 883C is a randomly accessed solid-state
memory containing 1,048,576 bits organized in a 262,144 x4
configuration. During READ or WRITE cycles, each 4-bit
word is uniquely addressed through the 18 address bits
which are entered 9 bits (A0-A8) at a time. RAS is used to
latch the first 9 bits and CAS the latter 9 bits. A READ or
WRITE cycle is selected with the WE input. A logic HIGH
on WE dictates READ mode while a logic LOW on WE
dictates WRITE mode.
During a WRITEcycle, data in (D)is latched by the falling
edge ofWE or CAS, whichever occurs last. If WE goes LOW
prior to CAS going LOW, the output pins (Qs) remain open
(High-Z) until the next CAS cycle. If WE goes LOW after
data reaches the outputs (Qs), the outputs are activated and
retain the selected cells’ data as long as CAS remains LOW
(regardless of WE or RAS). This late WE pulse results in a
READ-WRITE cycle. The four data inputs and four data
(READ, WRITE,
/R?A/S-ONLY, /C?A/S-BEFORE-/R?A/S, or
HIDDEN refresh) so that all 512 combinations of
/R/A/S
addresses (A0-A8) are executed at least every 8ms, regard-
less of sequence.
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-47
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
4
DATA IN
BUFFER
WE
CAS
DQ1
DQ2
DQ3
DQ4
*EARLY-WRITE
DETECTION CIRCUIT
4
DATA OUT
BUFFER
4
NO. 2 CLOCK
GENERATOR
OE
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
9
Vcc
9
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
Vss
512
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
512 x 4
REFRESH
COUNTER
9
ROW
ADDRESS
BUFFERS (9)
MEMORY
ARRAY
512
9
9
NO. 1 CLOCK
GENERATOR
RAS
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
TRUTH TABLE
ADDRESSES
DATA IN/OUT
DQ1-DQ4
t
t
FUNCTION
RAS
CAS
H>X
L
WE
X
OE
X
R
C
Standby
H
X
X
High-Z
READ
L
H
L
ROW
ROW
ROW
ROW
n/a
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
Data Out
EARLY-WRITE
READ-WRITE
FAST-PAGE-MODE
READ
L
L
L
X
Data In
L
L
H>L
H
L>H
L
Data Out, Data In
Data Out
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L
H>L
H>L
H>L
H>L
H>L
H>L
H
L
H
L
Data Out
FAST-PAGE-MODE
EARLY-WRITE
FAST-PAGE-MODE
READ-WRITE
RAS-ONLY REFRESH
HIDDEN
L
L
X
ROW
n/a
Data In
L
L
X
Data In
L
L
H>L
H>L
X
L>H
L>H
X
ROW
n/a
Data Out, Data In
Data Out, Data In
High-Z
L
ROW
ROW
ROW
X
READ
L>H>L
L>H>L
H>L
L
H
L
COL
COL
X
Data Out
REFRESH
WRITE
L
L
X
Data In
CAS-BEFORE-RAS REFRESH
L
X
X
High-Z
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-48
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to VSS .............. -1.5V to +7.0V
Storage Temperature Range ....................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Lead Temperature (Soldering 5 Seconds) .................. 270°C
Junction Temperature (T ) ......................................... +175°C
J
Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL PERFORMANCE CHARACTERISTICS
(Notes: 1, 6, 7) (-55°C ≤ T ≤ +125°C; VCC = 5V ±10%)
C
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
Supply Voltage
VCC
VIH
VIL
4.5
2.4
-.5
5.5
VCC+.5
0.8
V
V
V
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
INPUT LEAKAGE CURRENT
Any Input (0V ≤ VIN ≤ 6.5V),
All other pins not under test = 0V
II
-5
5
5
µA
OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V ≤ VOUT ≤ 6.5V)
IOZ
-5
µA
OUTPUT LEVELS
VOH
2.4
V
Output High Voltage (IOUT = -5mA)
Output Low Voltage (IOUT = 4.2mA)
VOL
0.4
V
MAX
-10 -12 UNITS NOTES
PARAMETER/CONDITION
SYMBOL
-8
STANDBY CURRENT: (TTL)
ICC1
3
3
3
mA
(/R/A/
ICC2
ICC3
ICC4
ICC5
ICC6
1
1
1
mA
(/R/A/
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(/R/A/S, CAS, Address Cycling: RC = RC (MIN))
70
50
70
70
60
40
60
60
50
30
50
50
mA
mA
mA
mA
3, 4
3, 4
3
t
t
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(/R/A/S = VIL, CAS, Address Cycling: PC = PC (MIN))
t
t
REFRESH CURRENT: RAS-ONLY
Average power supply current
(/R/A/S Cycling, CAS = VIH: RC = RC (MIN))
t
t
REFRESH CURRENT: CAS-BEFORE-RAS
Average power supply current
(/R/A/S, CAS, Address Cycling: RC = RC (MIN))
3, 5
t
t
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-49
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
CAPACITANCE
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
Input Capacitance: (A0-A8), D
Input Capacitance: RAS, CAS, WE, OE
Input/Output Capacitance: (DQ1-DQ4)
CI1
CI2
CO
7
7
8
pF
pF
pF
2
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ T ≤ +125°C; VCC = 5V ±10%)
C
AC CHARACTERISTICS
-8
-10
-12
PARAMETER
SYM
tRC
tRWC
tPC
MIN
150
195
45
MAX
MIN
180
235
55
MAX
MIN
210
275
65
MAX
UNITS
ns
NOTES
Random READ or WRITE cycle time
READ-WRITE cycle time
ns
FAST-PAGE-MODE READ or WRITE
cycle time
ns
FAST-PAGE-MODE READ-WRITE
cycle time
tPRWC
90
110
130
ns
Access time from RAS
tRAC
tCAC
tOE
80
20
100
25
25
120
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
23
Access time from CAS
Output Enable
20
Access time from column address
Access time from CAS precharge
tAA
40
50
50
60
60
tCPA
tRAS
tRASP
tRSH
tRP
tCAS
tCSH
tCPN
40
R
A
/
80
80
20
60
20
80
10
10
20
5
100,000
100,000
100
100
25
70
25
100
12
12
25
5
100,000
100,000
120
120
30
80
30
120
15
15
25
10
0
100,000
100,000
/R/A/
RAS hold time
/R/A/
C
A
/
100,000
60
100,000
75
100,000
90
CAS hold time
S precharge time
C
A
/
16
17
/C/A/
S precharge time (FAST PAGE MODE) tCP
R
A
/
tRCD
tCRP
tASR
tRAH
tRAD
/C/A/
Row address setup time
Row address hold time
0
0
10
15
15
20
15
20
RAS to column
40
50
60
18
address delay time
Column address setup time
Column address hold time
tASC
tCAH
tAR
0
0
0
ns
ns
ns
15
60
20
70
20
80
Column address hold time
(referenced to RAS)
Column address to
tRAL
40
50
60
ns
/R/A/S lead time
Read command setup time
tRCS
tRCH
0
0
0
0
0
0
ns
ns
Read command hold time
(referenced to CAS)
19
19
Read command hold time
(referenced to RAS)
tRRH
tCLZ
0
0
0
0
0
0
ns
ns
CAS to output in Low-Z
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-50
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ T ≤ +125°C; Vcc = 5V ±10%)
C
AC CHARACTERISTICS
PARAMETER
-8
-10
-12
SYM
tOFF
tOD
MIN
MAX
20
MIN
MAX
20
MIN
MAX
25
UNITS
ns
NOTES
20, 26
26
Output buffer turn-off delay
Output disable
0
0
0
20
20
25
ns
W
E command setup time
tWCS
tWCH
tWCR
0
0
0
ns
21
Write command hold time
15
60
20
70
25
80
ns
Write command hold time
(referenced to RAS)
ns
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWP
tRWL
tCWL
tDS
tDH
tDHR
15
20
20
0
15
25
25
0
20
30
30
0
ns
ns
ns
ns
ns
ns
22
22
Data-in hold time
15
60
20
70
25
80
Data-in hold time
(referenced to RAS)
RAS to WE delay time
tRWD
tAWD
105
65
125
75
150
90
ns
ns
21
21
Column address
to WE delay time
CAS to WE delay time
tCWD
tT
tREF
tRPC
tCSR
45
3
50
3
60
3
ns
ns
ms
ns
ns
21
Transition time (rise or fall)
Refresh period (512 cycles)
RAS to CAS precharge time
50
8
50
8
50
8
0
0
0
C
A
/
10
10
10
5
5
(/C/A/
tCHR
tOEH
tORD
15
20
0
20
20
0
25
25
0
ns
ns
ns
(/C/A/
OE hold time from WE during
READ-MODIFY-WRITE cycle
25
24
OE setup prior to RAS during
HIDDEN REFRESH cycle
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-51
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
NOTES
t
1. All voltages referenced to VSS.
(MAX) is specified as a reference point only; if RAD
t
2. This parameter is sampled. VCC = 5V ±10%,f = 1 MHz.
3. ICC is dependent on cycle rates.
4. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
is greater than the specified RAD (MAX) limit, then
t
access time is controlled exclusively by AA.
t
t
19. Either RCH or RRH must be satisfied for a READ
cycle.
20. OFF (MAX) defines the time at which the output
t
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55°C ≤ TC ≤ +125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by any eight RAS cycles before proper
device operation is assured. The eight RAS cycle
achieves the open circuit condition, and is not
referenced to VOH or VOL.
t
t
t
t
21. WCS, RWD, AWD and CWD are not restrictive
t
operating parameters. WCS applies to EARLY-
t
t
t
WRITE cycles. RWD, AWD and CWD apply to
t
t
READ-MODIFY-WRITE cycles. If WCS ≥ WCS
(MIN), the cycle is an EARLY-WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If RWD ≥ RWD (MIN), AWD ≥
AWD (MIN) and CWD ≥ CWD (MIN), the cycle is a
t
wake-up should be repeated any time the REF
t
t
t
refresh requirement is exceeded.
t
t
t
t
8. AC characteristics assume T = 5ns. This parameter is
not measured.
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE-WRITE (OE
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data outputs (DQs) are High-Z.
12. If CAS = VIL, data outputs (DQs) may contain data
from the last valid READ cycle.
t
t
t
t
controlled) cycle. WCS, RWD, CWD and AWD are
not applicable in a LATE-WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY-WRITE cycles and WE leading edge in
LATE-WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE =
HIGH.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
t
t
t
14. Assumes that RCD < RCD (MAX). If RCD is greater
than the maximum recommended value shown in this
t
t
table, RAC will increase by the amount that RCD
exceeds the value shown.
25. LATE-WRITE and READ-MODIFY-WRITE cycles
t
t
must have both OD and OEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
t
t
15. Assumes that RCD ≥ RCD (MAX).
16. If CAS is LOW at the falling edge of RAS, DQs will be
maintained from the previous cycle. To initiate a new
cycle and clear the data out buffer, CAS must be
t
remains LOW and OE is taken back LOW after OEH
t
pulsed HIGH for CPN.
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
t
17. Operation within the RCD (MAX) limit ensures that
t
t
t
t
RAC (MAX) can be met. RCD (MAX) is specified as
26. The DQs open during READ cycles once OD or OFF
occur. If CAS goes HIGH first, OE becomes a “don’t
care.” If OE goes HIGH and CAS stays LOW, OE is
not a “don’t care;” and the DQs will provide the
previously read data if OE is taken back LOW (while
CAS remains LOW).
t
a reference point only; if RCD is greater than the
t
specified RCD (MAX) limit, then access time is
t
controlled exclusively by CAC.
t
18. Operation within the RAD (MAX) limit ensures that
t
t
t
RAC (MIN) and CAC (MIN) can be met. RAD
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-52
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE
t
RC
t
t
t
RAS
RP
V
V
IH
IL
RAS
t
t
t
CSH
RSH
CAS
RRH
t
t
RCD
CRP
V
V
IH
IL
CAS
t
AR
t
t
t
t
RAD
RAH
RAL
CAH
t
t
ASC
ASR
V
V
IH
IL
ROW
ROW
ADDR
WE
COLUMN
t
t
RCS
RCH
V
V
IH
IL
t
t
t
t
AA
RAC
CAC
CLZ
t
OFF
V
V
IOH
IOL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
EARLY-WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
CAS
t
CSH
t
RSH
t
t
t
CRP
RCD
CAS
V
V
IH
IL
t
AR
t
t
t
t
RAD
RAH
RAL
CAH
t
t
ASC
ASR
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
V
V
IH
IL
WE
t
t
DHR
DH
t
DS
V
V
IOH
IOL
DQ
OE
VALID DATA
V
IH
V
IL
DON’T CARE
UNDEFINED
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-53
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
t
RWC
t
t
RAS
RP
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
t
CAS
CRP
ASR
RCD
V
V
IH
IL
CAS
t
AR
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASC
RCS
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
AWD
V
V
IH
IL
WE
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
IOH
IOL
VALID D
VALID D
DQ
OE
OPEN
OPEN
V
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
FAST-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS
t
t
t
t
RSH
CAS
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CPN
V
V
IH
IL
CAS
t
AR
t
t
t
RAL
RAD
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
t
COLUMN
t
ROW
t
RCS
t
RCS
RRH
t
t
RCS
RCH
t
RCH
RCH
V
V
IH
IL
WE
t
t
t
t
t
t
t
t
t
AA
AA
AA
RAC
CAC
CPA
CAC
CPA
CAC
t
t
OFF
OFF
t
OFF
t
t
t
CLZ
CLZ
CLZ
V
IOH
IOL
VALID
DATA
VALID
DATA
VALID
DATA
t
OD
DQ
OE
OPEN
OPEN
V
t
t
t
t
t
OE
OD
OE
OD
OE
V
V
IH
IL
DON’T CARE
UNDEFINED
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-54
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS
CAS
t
t
t
t
t
CSH
PC
CP
RSH
CAS
t
t
t
t
t
t
CRP
RCD
CAS
CAS
CP
CPN
V
V
IH
IL
t
AR
t
t
t
RAD
RAL
t
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
V
V
IH
IL
WE
t
t
t
t
WCR
DHR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
IOH
IOL
DQ
OE
VALID DATA
VALID DATA
VALID DATA
V
V
V
IH
IL
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
t
t
RASP
RP
V
IH
IL
RAS
CAS
V
t
t
t
t
t
CSH
*
PC
PRWC
RSH
CAS
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CPN
V
V
IH
IL
t
AR
t
t
t
RAL
RAD
RAH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
RCS
t
t
t
CWL
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
AWD
AWD
AWD
CWD
t
t
CWD
CWD
V
V
IH
IL
WE
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
DQ
OE
OPEN
OPEN
D
D
D
D
D
D
t
t
t
OD
OD
OD
t
t
t
t
OE
OE
OE
OEH
V
V
IH
IL
DON’T CARE
UNDEFINED
t
* PC = LATE-WRITE cycle
t
PRWC = FAST READ-MODIFY-WRITE cycle
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-55
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
RAS-ONLY REFRESH CYCLE
(ADDR = A0-A8; WE = DON’T CARE)
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
CAS
t
t
RPC
CRP
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
DQ
ROW
ROW
V
OH
OL
OPEN
V
CAS-BEFORE-RAS REFRESH CYCLE
(A0-A8, WE and OE = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS
t
t
RPC
CPN
t
t
t
RPC
t
t
CSR
CHR
CSR
CHR
V
V
IH
IL
CAS
DQ
V
V
OH
OL
OPEN
HIDDEN REFRESH CYCLE 24
(WE = HIGH, OE = LOW)
(READ)
(REFRESH)
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS
t
t
t
t
CRP
RCD
RSH
CHR
V
V
IH
IL
CAS
t
t
AR
t
t
RAD
RAL
t
t
t
ASR
RAH
ASC
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
t
t
t
t
AA
RAC
CAC
CLZ
t
OFF
V
IOH
IOL
DQ
OE
OPEN
VALID DATA
OPEN
V
t
t
t
OD
OE
ORD
V
V
IH
IL
DON’T CARE
UNDEFINED
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-56
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883 TEST REQUIREMENTS
(per Method 5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
*
PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-57
MT4C4256 883C
256K x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
MT4C4256 883C
REV. 3/97
DS000014
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-58
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