MT5C1005C-15L/883C [MICROSS]
Standard SRAM, 256KX4, 15ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28;
| 型号： | MT5C1005C-15L/883C |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Standard SRAM, 256KX4, 15ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28 CD 静态存储器 |
| 文件： | 总8页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
SRAM
256K x 4 SRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
PIN ASSIGNMENT (Top View)
•
MIL-STD-883
28-Pin DIP
(400 MIL)
32-Pin LCC
32-Pin SOJ
FEATURES
•
•
•
•
High speed: 15, 20, 25, 35 and 45ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
A7
A8
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A7
A8
A9
A10
A11
A12
A13
A14
A15
1
2
3
4
5
6
7
8
9
28 Vcc
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
20 NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
•
•
•
Single +5V (±10%) power supply
Easy memory expansion with CE and OE options
All inputs and outputs are TTL compatible
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
OPTIONS
MARKING
A16 10 19 DQ4
A17 11 18 DQ3
CE 12 17 DQ2
OE 13 16 DQ1
Vss 14 15 WE
•
Timing
OE
Vss
15ns access (Contact factory)
20ns access
-15
-20
25ns access
-25
35ns access
-35
45ns access
55ns access
70ns access
-45
-55*
-70*
32-Pin LCC
32-Pin Flat Pack
•
Packages
A7
A8
A9
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
4
3 2 1 32 31 30
Ceramic DIP (400 mil)
Ceramic Flat Pack
Ceramic LCC
Ceramic SOJ
Ceramic Quad LCC (Contact factory)
C
F
No. 109
No. 303
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A2
A
A10
1
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
A4
A
A3
A
A11
2
A12
3
A134
A1
A
A3
A1
A0
N
A145
10
N156
11
NC
N
EC No. 207
DCJ No. 501
ECW No. 206
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
NC
A
A167
9
12
NC
N
A17
10
11
12
13
14
15
16
13
DQ4
CE
14 1516 17 18 19 20
OE
Vss
•
•
2V data retention, low power standby
Radiation Tolerant (Epi)
L
E
*Electrical characteristics identical to those provided for the 45ns
access devices.
GENERAL DESCRIPTION
write enable ( WE) and CE inputs are both LOW. Reading
is accomplished when WE remains HIGH while CE and
OE go LOW. The devices offer a reduced power standby
mode when disabled.This allows system designs to achieve
low standby power requirements.
The Austin Semiconductor SRAM family employs high-
speed, low-power CMOS designs using a four transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon tech-
nology.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (ISBC2) over the stan-
dard version.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE) and output en-
able (OE) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system
design. Writing to these devices is accomplished when
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-57
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL BLOCK DIAGRAM
Vcc
GND
A
A
A
A
A
A
A
A
A
DQ4
1,048,576-BIT
MEMORY ARRAY
DQ1
CE
(LSB)
OE
WE
COLUMN DECODER
POWER
DOWN
(LSB)
A
A
A
A
A
A
A
A
A
TRUTH TABLE
MODE
OE
CE
WE
X
DQ
POWER
STANDBY
READ
X
L
H
L
L
L
HIGH-Z STANDBY
H
Q
HIGH-Z
D
ACTIVE
ACTIVE
ACTIVE
READ
H
X
H
WRITE
L
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-58
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Voltage on Any Input or DQ Relative to Vss .. -.5V to Vcc+.5V
Voltage on VCC Supply Relative to Vss ............ -.5V to +7V
Storage Temperature ................................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ......................................... ±20
Lead Temperature (soldering 10 seconds) .............. +260°C
Junction Temperature ................................................ +175°C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C ≤ T ≤ 125°C; Vcc = 5.0V ± 10%)
C
DESCRIPTION
CONDITIONS
SYMBOL
VIH
MIN
2.2
-0.5
-5
MAX
VCC+0.5
0.8
UNITS
V
NOTES
1
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
VIL
V
1, 2
0V ≤ VIN ≤ VCC
ILI
5
µA
Output Leakage Current
Output(s) Disabled
ILO
-5
5
µA
0V ≤ VOUT ≤ VCC
Output High Voltage
Output Low Voltage
IOH = -4.0mA
IOL = 8.0mA
VOH
VOL
2.4
V
V
1
1
0.4
MAX
-35
DESCRIPTION
CONDITIONS
SYMBOL -15
-20
-25
-45
UNITS
NOTES
Power Supply
Current: Operating
CE ≤ VIL; VCC = MAX
f = MAX = 1/ RC (MIN)
t
ICC
170 155 140 125 115
mA
3
Output Open
Power Supply
Current: Standby
CE ≥ VIH; VCC = MAX
f = MAX = 1/ RC (MIN)
t
ISBT1
65
25
50
25
45
25
40
25
35
25
mA
mA
Output Open
CE ≥ VIH, All Other Inputs
≤ VIL or ≥ VIH, VCC = MAX
f = 0 Hz
ISBT2
CE ≥ VCC -0.2V; VCC = MAX
VIL ≤ VSS +0.2V
VIH ≥ VCC -0.2V; f = 0 Hz
ISBC2
ISBC2
10
5
10
5
10
5
10
5
10
5
mA
mA
“L” Version Only
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
10
8
UNITS
pF
NOTES
Input Capacitance (A0-A2, A12-A15)
Output Capacitance (DQ1-DQ4)
Input Capacitance (All Other Inputs)
T
= 25°C, f = 1MHz
CI
CO
CI
4
4
4
A
VCC = 5V
pF
8
pF
MT5C1005 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000005
1-59
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55°C ≤ T ≤ 125°C; VCC = 5V ± 10%)
C
-15
-20
-25
-35
-45
DESCRIPTION
SYM
MIN MAX MIN
MAX MIN
MAX MIN
MAX MIN
MAX UNITS NOTES
READ Cycle
READ cycle time
tRC
tAA
15
20
25
35
45
ns
Address access time
15
15
20
20
3
25
25
3
35
35
3
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable access time
tACE
tOH
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
3
3
3
3
tLZCE
tHZCE
tPU
3
3
3
4, 6, 7
4, 6, 7
4
6
8
10
15
15
0
0
0
0
0
0
0
tPD
15
6
20
7
25
8
35
12
0
45
12
4
tAOE
tLZOE
4, 6, 7
0
0
Output disable to output in High-Z tHZOE
5
7
9
12
12
4, 6, 7
WRITE Cycle
WRITE cycle time
tWC
tCW
tAW
15
12
12
0
20
15
15
0
25
17
17
0
35
20
20
0
45
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to end of write
Address valid to end of write
Address setup time
tAS
Address hold from end of write
WRITE pulse width
tAH
1
1
1
1
1
tWP
12
7
15
8
17
10
0
20
13
0
20
13
0
Data setup time
tDS
Data hold time
tDH
0
0
Write disable to output in Low-Z
Write Enable to output in High-Z
tLZWE
tHZWE
3
3
3
3
3
4, 6, 7
4, 6, 7
0
7
0
9
0
10
0
13
0
13
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-60
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
+5V
+5V
AC TEST CONDITIONS
480
480
Input pulse levels ...................................... Vss to 3V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
Q
Q
30 pF
5 pF
255
255
Fig. 1 OUTPUT LOAD
EQUIVALENT
Fig. 2 OUTPUT LOAD
EQUIVALENT
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns.
7. At any given temperature and voltage condition,
t
t
t
t
HZCE is less than LZCE and HZWE is less than
t
t
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
LZWE, and LZOE is less than HZOE.
8. WE is HIGH for READ cycle.
1
9. Device is continuously selected. Chip enable and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
unloaded, and f = ————— Hz
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. LZCE, LZOE, LZWE HZCE, HZOE and HZWE
are specified with CL = 5 pF as in Fig. 2. Transition is
measured ± 200mV typical from steady state voltage,
allowing for actual tester RC time constant.
11. tRC = READ cycle time.
12. Chip enable (CE) and write enable (WE) can initiate
and terminate a WRITE cycle.
t
t
t
, t
t
t
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
TYP
MAX
—
UNITS
V
NOTES
VCC for Retention Data
Data Retention Current
VDR
2
CE ≥ (VCC - 0.2V) VCC = 2V
VIN ≥ (VCC - 0.2V)
ICCDR
1.0
mA
or ≤ 0.2V
VCC = 3V
2.0
—
mA
ns
t
Chip Deselect to Data
Retention Time
CDR
0
4
t
t
Operation Recovery Time
R
RC
ns
4, 11
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
4.5V
V
>2V
Vcc
DR
t
t
R
CDR
V
V
DR
IH
IL
CE
V
DON’T CARE
UNDEFINED
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-61
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE NO. 18, 9
t
RC
ADDR
VALID
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
Q
READ CYCLE NO. 2 7, 8, 10
t
RC
CE
OE
t
AOE
t
t
t
LZOE
HZOE
t
ACE
HZCE
t
LZCE
HIGH-Z
DATA VALID
DQ
Icc
t
t
PD
PU
DON’T CARE
UNDEFINED
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-62
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
12
WRITE CYCLE NO. 1
(Chip Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
AH
AS
CW
CE
t
WP
WE
t
t
DH
DS
D
Q
DATA VALID
HIGH-Z
7, 12
WRITE CYCLE NO. 2
(Write Enable Controlled)
t
WC
ADDR
t
AW
t
t
AH
CW
CE
t
t
AS
WP
WE
t
t
DH
DS
DATA VALID
D
Q
HIGH-Z
DON’T CARE
UNDEFINED
NOTE: Output enable (OE) is inactive (HIGH).
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-63
MT5C1005 883C
256K x 4 SRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883 TEST REQUIREMENTS
(per Method 5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
*
PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
MT5C1005 883C
REV. 11/97
DS000005
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-64
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